Analog Devices ADuC812 e Datasheet

MicroConverter®, Multichannel

a

FEATURES
Analog I/O

8-Channel, High Accuracy 12-Bit ADC
On-Chip, 100 ppm/C Voltage Reference
High Speed 200 kSPS
DMA Controller for High Speed ADC-to-RAM Capture
2 12-Bit Voltage Output DACs
On-Chip Temperature Sensor Function

Memory

8K Bytes On-Chip Flash/EE Program Memory
640 Bytes On-Chip Flash/EE Data Memory
256 Bytes On-Chip Data RAM
16M Bytes External Data Address Space
64K Bytes External Program Address Space

8051 Compatible Core

12 MHz Nominal Operation (16 MHz Max)
3 16-Bit Timer/Counters
High Current Drive Capability—Port 3
9 Interrupt Sources, 2 Priority Levels

Power

Specified for 3 V and 5 V Operation
Normal, Idle, and Power-Down Modes

On-Chip Peripherals

UART and SPI
2-Wire (400 kHz I2C® Compatible) Serial I/O
Watchdog Timer

Power Supply Monitor

®

Serial I/O

12-Bit ADC with Embedded Flash MCU

ADuC812

APPLICATIONS
Intelligent Sensors Calibration and Conditioning
Battery-Powered Systems (Portable PCs, Instruments,

Monitors)
Transient Capture Systems
DAS and Communications Systems
Control Loop Monitors (Optical Networks/Base Stations)

GENERAL DESCRIPTION

The ADuC812 is a fully integrated 12-bit data acquisition system
incorporating a high performance self-calibrating multichannel
ADC, dual DAC, and programmable 8-bit MCU (8051 instruc­tion set compatible) on a single chip.

The programmable 8051 compatible core is supported by 8K
bytes Flash/EE program memory, 640 bytes Flash/EE data
memory, and 256 bytes data SRAM on-chip.

Additional MCU support functions include Watchdog Timer,
Power Supply Monitor, and ADC DMA functions. Thirty-two
programmable I/O lines, I
UART Serial Port I/O are provided for multiprocessor interfaces
and I/O expansion.

Normal, idle, and power-down operating modes for both the
MCU core and analog converters allow flexible power manage­ment schemes suited to low power applications. The part is
specified for 3 V and 5 V operation over the industrial tem­perature range and is available in a 52-lead, plastic quad
flatpack package, and in a 56-lead, chip scale package.

2

C compatible SPI and Standard

FUNCTIONAL BLOCK DIAGRAM

AIN0 (P1.0)–AIN7 (P1.7)

V

REF

C

REF

AIN

MUX

2.5V
REF

BUF

P0.0–P0.7

T/H

TEMP

SENSOR

DD

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

ADuC812

AGNDAV

P1.0–P1.7

CALIBRATION

8051 BASED

MICROCONTROLLER CORE

8K  8 PROGRAM

FLASH EEPROM

640  8 USER

FLASH EEPROM

256  8 USER

DGNDDV

DD

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

RxD

(P3.0)

P3.0–P3.7

TxD

(P3.1)

DAC0

DAC1

TIMER/COUNTERS

2-WIRE

SERIAL I/O

SCLOCK

BUF

BUF

3  16-BIT

MUX

MOSI/

SDATA

SPI

MISO
(P3.3)

P2.0–P2.7

ADC

CONTROL

AND

LOGIC

RAM

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

DAC

CONTROL

MICROCONTROLLER

POWER SUPPLY

MONITOR

WATCHDOG

TIMER

UART

OSC

XTAL2XTAL1

DAC0

DAC1

T0 (P3.4)

T1 (P3.5)
T2 (P1.0)
T2EX (P1.1)

INT0 (P3.2)
INT1 (P3.3)

ALE

PSEN
EA

RESET

ADuC812

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ADC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Integral Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Full-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal to (Noise + Distortion) Ratio . . . . . . . . . . . . . . . . . . . . 8

Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DAC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Voltage Output Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . 8

Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . . . . . 8

ARCHITECTURE, MAIN FEATURES . . . . . . . . . . . . . . . . . . 9

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OVERVIEW OF MCU-RELATED SFRs . . . . . . . . . . . . . . . . . 10

Accumulator SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

B SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stack Pointer SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Status Word SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power Control SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . 11

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . 12

General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Typical Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADCCON1—(ADC Control SFR #1) . . . . . . . . . . . . . . . . . 13

ADCCON2—(ADC Control SFR #2) . . . . . . . . . . . . . . . . . 14

ADCCON3—(ADC Control SFR #3) . . . . . . . . . . . . . . . . . 14

Driving the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage Reference Connections . . . . . . . . . . . . . . . . . . . . . . . 16

Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ADC DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DMA Mode Configuration Example . . . . . . . . . . . . . . . . . . . 17

Micro Operation during ADC DMA Mode . . . . . . . . . . . . . . 17

Offset and Gain Calibration Coefficients . . . . . . . . . . . . . . . . 17

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

NONVOLATILE FLASH MEMORY . . . . . . . . . . . . . . . . . . . 18

Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Flash/EE Memory and the ADuC812 . . . . . . . . . . . . . . . . . . 18

ADuC812 Flash/EE Memory Reliability . . . . . . . . . . . . . . . . 18

Using the Flash/EE Program Memory . . . . . . . . . . . . . . . . . . 19

Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . . . . 19

ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . . . . 20

Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using the Flash/EE Memory Interface . . . . . . . . . . . . . . . . . . 20

Erase-All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

USER INTERFACE TO OTHER ON-CHIP

ADuC812 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Using the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . 24

SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . 25

MISO (Master In, Slave Out Data I/O Pin) . . . . . . . . . . . . . . 25

MOSI (Master Out, Slave In Pin) . . . . . . . . . . . . . . . . . . . . . 26

SCLOCK (Serial Clock I/O Pin) . . . . . . . . . . . . . . . . . . . . . . 26

SS (Slave Select Input Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Interface—Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Interface—Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2

C COMPATIBLE INTERFACE . . . . . . . . . . . . . . . . . . . . . . 28

I

8051 COMPATIBLE ON-CHIP PERIPHERALS . . . . . . . . . . 29

Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Timer/Counters 0 and 1 Data Registers . . . . . . . . . . . . . . . . . 31

TH0 and TL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TH1 and TL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TIMER/COUNTERS 0 AND 1 OPERATING MODES . . . . . 32

Mode 0 (13-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . 32

Mode 1 (16-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . 32

Mode 2 (8-Bit Timer/Counter with Auto Reload) . . . . . . . . . 32

Mode 3 (Two 8-Bit Timer/Counters) . . . . . . . . . . . . . . . . . . 32

Timer/Counter 2 Data Registers . . . . . . . . . . . . . . . . . . . . . . 33

TH2 and TL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

RCAP2H and RCAP2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timer/Counter Operation Modes . . . . . . . . . . . . . . . . . . . . . 34

16-Bit Autoreload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

16-Bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

UART SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 0 (8-Bit Shift Register Mode) . . . . . . . . . . . . . . . . . . . 36

Mode 1 (8-Bit UART, Variable Baud Rate) . . . . . . . . . . . . . . 36

Mode 2 (9-Bit UART with Fixed Baud Rate) . . . . . . . . . . . . 36

Mode 3 (9-Bit UART with Variable Baud Rate) . . . . . . . . . . 36

UART Serial Port Baud Rate Generation . . . . . . . . . . . . . . . 36

Timer 1 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . 37

Timer 2 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . 37

INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ADuC812 HARDWARE DESIGN CONSIDERATIONS . . . . 40

Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Grounding and Board Layout Recommendations . . . . . . . . . 43

OTHER HARDWARE CONSIDERATIONS . . . . . . . . . . . . . 44

In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . . . 44

Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . . . 44

Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . . . . . 45

Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . . . 45

QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . . . . 45

Download—In-Circuit Serial Downloader . . . . . . . . . . . . . . . 45

DeBug—In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . 45

ADSIM—Windows Simulator . . . . . . . . . . . . . . . . . . . . . . . . 45

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 46

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

–2–

REV. E

ADuC812

1, 2

SPECIFICATIONS

f

= 200 kHz, DAC V

SAMPLE

Load to AGND; RL = 2 k, CL = 100 pF. All specifications TA = T

OUT

(AVDD = DVDD = 3.0 V or 5.0 V  10%, REFIN/REF

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

DC ACCURACY

3, 4

Resolution 12 12 Bits
Integral Nonlinearity ±1/2 ±1/2 LSB typ f

±1.5 ±1.5 LSB max f
±1.5 ±1.5 LSB typ f

Differential Nonlinearity ±1 ±1 LSB typ f

CALIBRATED ENDPOINT ERRORS

5, 6

Offset Error ±5 ±5 LSB max

±1 ±1 LSB typ
Offset Error Match 1 1 LSB typ
Gain Error ±6 ±6 LSB max

±1 ±1 LSB typ
Gain Error Match 1.5 1.5 LSB typ

USER SYSTEM CALIBRATION

7

Offset Calibration Range ±5 ±5 % of V
Gain Calibration Range ±2.5 ±2.5 % of V

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

8

70 70 dB typ
Total Harmonic Distortion (THD) –78 –78 dB typ
Peak Harmonic or Spurious Noise –78 –78 dB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Leakage Current ±1 ±1 µA max

Input Capacitance

TEMPERATURE SENSOR

9

10

±0.1 ±0.1 µA typ

20 20 pF max

Voltage Output at 25°C 600 600 mV typ Can vary significantly (> ±20%)
Voltage TC –3.0 –3.0 mV/°C typ from device to device

DAC CHANNEL SPECIFICATIONS

DC ACCURACY

11

Resolution 12 12 Bits
Relative Accuracy ±3 ±3 LSB typ
Differential Nonlinearity ±0.5 ±1 LSB typ Guaranteed 12-Bit Monotonic
Offset Error ±60 ±60 mV max

±15 ±15 mV typ

Full-Scale Error ±30 ±30 mV max

±10 ±10 mV typ

Full-Scale Mismatch ±0.5 ±0.5 % typ % of Full-Scale on DAC1

ANALOG OUTPUTS

Voltage Range_0 0 to V
Voltage Range_1 0 to V

REF

DD

0 to V
0 to V

REF

DD

Resistive Load 10 10 kΩ typ
Capacitive Load 100 100 pF typ
Output Impedance 0.5 0.5 Ω typ
I

SINK

50 50 µA typ

= 2.5 V Internal Reference, MCLKIN = 11.0592 MHz,

OUT

to T

MIN

, unless otherwise noted.)

MAX

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 100 kHz
= 100 kHz
= 200 kHz
= 100 kHz. Guaranteed No

Missing Codes at 5 V

typ

REF

typ

REF

= 10 kHz Sine Wave

IN

f

= 100 kHz

SAMPLE

V

V typ
V typ

REV. E

–3–

ADuC812
SPECIFICATIONS

1, 2

(continued)

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

DAC AC CHARACTERISTICS

Voltage Output Settling Time 15 15 µs typ Full-Scale Settling Time to

within 1/2 LSB of Final Value

Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range

9

2.3/V

DD

2.3/V

DD

V min/max
Input Impedance 150 150 kΩ typ
REF

Output Voltage 2.5 ± 2.5% 2.5 ± 2.5% V min/max Initial Tolerance @ 25°C

OUT

2.5 2.5 V typ

REF

FLASH/EE MEMORY PERFORMANCE

CHARACTERISTICS

Tempco 100 100 ppm/°C typ

OUT

12, 13

Endurance 10,000 Cycles min

50,000 50,000 Cycles typ

Data Retention 10 Years min

WATCHDOG TIMER

CHARACTERISTICS

Oscillator Frequency 64 64 kHz typ

POWER SUPPLY MONITOR

CHARACTERISTICS

Power Supply Trip Point Accuracy ±2.5 ±2.5 % of Selected

Nominal Trip

Point Voltage

max

±1.0 ±1.0% of Selected

Nominal Trip

Point Voltage

typ

DIGITAL INPUTS

Input High Voltage (V
XTAL1 Input High Voltage (V
Input Low Voltage (V
Input Leakage Current (Port 0, EA) ±10 ±10 µA max V

) 2.4 2.4 V min

INH

) 0.8 0.8 V max

INL

) Only 4 V min

INH

±1 ±1 µA typ VIN = 0 V or V

= 0 V or V

IN

DD

DD

Logic 1 Input Current

(All Digital Inputs) ±10 ±10 µA max V

±1 ±1 µA typ VIN = V

IN

= V

DD

DD

Logic 0 Input Current (Port 1, 2, 3) –80 –40 µA max

–40 –20 µA typ V

Logic 1-0 Transition Current (Port 1, 2, 3) –700 –500 µA max V

–400 –200 µA typ V

= 450 mV

IL

= 2 V

IL

= 2 V

IL

Input Capacitance 10 10 pF typ

–4–

REV. E

ADuC812

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

DIGITAL OUTPUTS

Output High Voltage (VOH) 2.4 2.4 V min VDD = 4.5 V to 5.5 V

= 80 µA

I

SOURCE

4.0 2.6 V typ V

Output Low Voltage (VOL)

ALE, PSEN, Ports 0 and 2 0.4 0.4 V max I

0.2 0.2 V typ I

Port 3 0.4 0.4 V max I

0.2 0.2 V typ I

Floating State Leakage Current ±10 ±10 µA max

±1 ±1 µA typ

Floating State Output Capacitance 10 10 pF typ

POWER REQUIREMENTS

IDD Normal Mode

17

14, 15, 16

43 25 mA max MCLKIN = 16 MHz
32 16 mA typ MCLKIN = 16 MHz
26 12 mA typ MCLKIN = 12 MHz
83 mA typ MCLKIN = 1 MHz

Idle Mode 25 10 mA max MCLKIN = 16 MHz

I

DD

18 6 mA typ MCLKIN = 16 MHz
15 6 mA typ MCLKIN = 12 MHz
72 mA typ MCLKIN = 1 MHz
30 15 µA max

Power-Down Mode

I

DD

18

55 µA typ

NOTES

1

Specifications apply after calibration.

2

Temperature range –40°C to +85°C.

3

Linearity is guaranteed during normal MicroConverter core operation.

4

Linearity may degrade when programming or erasing the 640 byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.

5

Measured in production at VDD = 5 V after Software Calibration Routine at 25°C only.

6

User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.

7

The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.

8

SNR calculation includes distortion and noise components.

9

Specification is not production tested, but is supported by characterization data at initial product release.

10

The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result.

11

DAC linearity is calculated using:

Reduced code range of 48 to 4095, 0 to V
Reduced code range of 48 to 3995, 0 to VDD range
DAC output load = 10 kΩ and 50 pF.

12

Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance).

13

Endurance Cycling is evaluated under the following conditions:

Mode = Byte Programming, Page Erase Cycling
Cycle Pattern = 00H to FFH
Erase Time = 20 ms
Program Time = 100 µs

14

IDD at other MCLKIN frequencies is typically given by:

Normal Mode (VDD = 5 V): IDD = (1.6 nAs × MCLKIN) + 6 mA
Normal Mode (VDD = 3 V): IDD = (0.8 nAs × MCLKIN) + 3 mA
Idle Mode (VDD = 5 V): IDD = (0.75 nAs × MCLKIN) + 6 mA
Idle Mode (VDD = 3 V): IDD = (0.25 nAs × MCLKIN) + 3 mA
where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.

15

IDD currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.

16

IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.

17

Analog IDD = 2 mA (typ) in normal operation (internal V

18

EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.

Typical specifications are not production tested, but are supported by characterization data at initial product release.

Timing Specifications—See Pages 46–55.

Specifications subject to change without notice.
Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.

REF

range

, ADC, and DAC peripherals powered on).

REF

= 2.7 V to 3.3 V

DD

= 20 µA

I

SOURCE

= 1.6 mA

SINK

= 1.6 mA

SINK

= 8 mA

SINK

= 8 mA

SINK

REV. E

–5–

ADuC812

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V

DV

DD

Digital Input Voltage to DGND . . . –0.3 V to DV
Digital Output Voltage to DGND . . –0.3 V to DV

to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

REF

Analog Inputs to AGND . . . . . . . . . . –0.3 V to AV

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range Industrial (B Version)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

PIN CONFIGURATIONS

52-Lead MQFP

DD

P1.0/ADC0/T2

P1.1/ADC1/T2EX

P1.2/ADC2

P1.3/ADC3

AV

AGND

C

REF

V

REF

DAC0
DAC1

P1.4/ADC4

P1.5/ADC5/SS

P1.6/ADC6

P0.6/AD6

P0.7/AD7

52 5 1 50 49 48 43 42 41 4047 46 45 44

1

PIN 1

2

IDENTIFIER

3

4

5

DD

6

7

8

9

10

11

12

13

14 1 5 16 17 18 19 20 21 22 23 24 25 26

RESET

P1.7/ADC7

DV

P0.4/AD4

P0.5/AD5

ADuC812

(Not to Scale)

P3.1/TxD

P3.0/RxD

DGND

TOP VIEW

P3.2/INT0

P3.3/INT1/MISO

P0.2/AD2

P0.3/AD3

DD

DV

DGND

P0.1/AD1

P3.4/T0

ALE

P0.0/AD0

P3.6/WR

P3.5/T1/CONVST

PSEN

P3.7/RD

EA

39

38

37

36

35

34

33

32

31

30

29

28

27

SCLOCK

P2.7/A15/A23
P2.6/A14/A22

P2.5/A13/A21

P2.4/A12/A20

DGND

DV

DD

XTAL2

XTAL1

P2.3/A11/A19

P2.2/A10/A18

P2.1/A9/A17

P2.0/A8/A16

SDATA/MOSI

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

56-Lead LFCSP

P1.0/ADC0/T2

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

DVDDDGND

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

EA

43

44

45

46

47

48

49

50

51

52

53

54

55

P1.1/ADC1/T2EX

P1.2/ADC2

P1.3/ADC3

AV

AV

AGND

AGND

AGND

C

REF

V

REF

DAC0

DAC1

P1.4/ADC4

P1.5/ADC5/SS

56

1

PIN 1

INDENTIFIER

2

3

4

DD

5

DD

6

7

8

9

10

11

12

13
14

151617

P1.6/ADC6

P1.7/ADC7

ADuC812

1819202122

RESET

P3.1/TXD

P3.0/RXD

TOP VIEW

(Not to Scale)

DD

DV

P3.2/INT0

P3.3/INT1/MISO

23

DGND

24

P3.4/T0

25

262728

P3.6/WR

P3.5/T1/CONVST

P3.7/RD

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SCLOCK

P2.7/A15/A23

P2.6/A14/A22

P2.5/A13/A21

P2.4/A12/A20

DGND

DGND

DV

DD

XTAL2

XTAL1

P2.3/A11/A19

P2.2/A10/A18

P2.1/A9/A17

P2.0/A8/A16

SDATA/ MOSI

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADuC812BS –40°C to +85°C 52-Lead Metric Quad Flat Package S-52
ADuC812BS –40°C to +85°C 56-Lead Lead Frame Chip Scale Package CP-56
EVAL-ADuC812QS QuickStart Development System
EVAL-ADuC812QSP QuickStart Development System Plus

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. E

ADuC812

PIN FUNCTION DESCRIPTIONS

Mnemonic Type Function

DV

DD

AV

DD

C

REF

V

REF

AGND G Analog Ground. Ground reference point for the analog circuitry.
P1.0–P1.7 I Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode. To configure

ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a

T2EX I Digital Input. Capture/Reload trigger for Counter 2; also functions as an Up/Down control input for

SS I Slave Select Input for the SPI Interface.
SDATA I/O User selectable, I
SCLOCK I/O Serial Clock Pin for I
MOSI I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface.
MISO I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface.
DAC0 O Voltage Output from DAC0.
DAC1 O Voltage Output from DAC1.
RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the

P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

RxD I/O Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port
TxD O Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port

INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, INT0 can be programmed to one of two

INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, INT1 can be programmed to one of two

T0 I Timer/Counter 0 Input.
T1 I Timer/Counter 1 Input.

CONVST I Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled.

WR OWrite Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD ORead Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2 O Output of the Inverting Oscillator Amplifier.
XTAL1 I Input to the Inverting Oscillator Amplifier and to the Internal Clock Generator Circuits.
DGND G Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15) pulled high by the internal pull-up resistors; in that state they can be used as inputs. As inputs, Port 2
(A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the

PDigital Positive Supply Voltage, 3 V or 5 V Nominal.
PAnalog Positive Supply Voltage, 3 V or 5 V Nominal.
IDecoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.
I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the ADC. The nominal internal reference voltage is 2.5 V, which appears at the pin.
This pin can be overdriven by an external reference.

any of these Port Pins as a digital input, write a 0 to the port bit. Port 1 pins are multifunctional and share
the following functionality.

1 to 0 transition of the T2 input.

Counter 2.

2

C Compatible or SPI Data Input/Output Pin.

2

C Compatible or SPI Serial Interface Clock.

device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described
in the Power-On Reset Operation section.

pulled high by the internal pull-up resistors; in that state they can be used as inputs. As inputs, Port 3 pins
being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions that are described below.

priority levels. This pin can also be used as a gate control input to Timer 0.

priority levels. This pin can also be used as a gate control input to Timer 1.

A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion.

high order address bytes during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.

REV. E

–7–

ADuC812

PIN FUNCTION DESCRIPTIONS (continued)

Mnemonic Type Function

PSEN OProgram Store Enable, Logic Output. This output is a control signal that enables the external program

memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.

ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit

address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.

EA IExternal Access Enable, Logic Input. When held high, this input enables the device to fetch code from

internal program memory locations 0000H to 1FFFH. When held low, this input enables the device to fetch
all instructions from external program memory.

P0.7–P0.0 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in
(A0–A7) that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data

bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups
when emitting 1s.

TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000)
to (0000 ...001) from the ideal, i.e., +1/2 LSB.

Full-Scale Error

This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fun­damental. Noise is the rms sum of all nonfundamental signals up
to half the sampling frequency (f

/2), excluding dc. The ratio is

S

dependent upon the number of quantization levels in the digiti­zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.

DAC SPECIFICATIONS
Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.

–8–

REV. E

ADuC812

ARCHITECTURE, MAIN FEATURES

The ADuC812 is a highly integrated, true 12-bit data acquisi-

system. At its core, the ADuC812 incorporates a high

tion
perfor

mance 8-bit (8052 compatible) MCU with on-chip
reprogrammable nonvolatile Flash program memory control­ling a multichannel (eight input channels) 12-bit ADC.

The chip incorporates all secondary functions to fully support
the programmable data acquisition core. These secondary
functions include User Flash Memory, Watchdog Timer
(WDT), Power Supply Monitor (PSM), and various industry­standard parallel and serial interfaces.

PROGRAM MEMORY SPACE

READ ONLY

FFFFH

EXTERNAL
PROGRAM

MEMORY

SPACE

2000H

9FH

00H

UPPER

LOWER

(PAGE 159)

640 BYTES

FLASH/EE DATA

MEMORY

ACCESSED

INDIRECTLY

VIA SFR

CONTROL REGISTERS

(PAGE 0)

DATA MEMORY

FFH

ACCESSIBLE

80H
7FH

00H

ADDRESSING

ACCESSIBLE

ADDRESSING

128

128

EA = 1

INTERNAL

8K BYTE

FLASH/EE

PROGRAM

MEMORY

INTERNAL

SPACE

BY

INDIRECT

ONLY

BY

DIRECT

AND

INDIRECT

1FFFH

0000H

DATA MEMORY SPACE

READ/WRITE

SPECIAL

FUNCTION

REGISTERS

ACCESSIBLE

BY DIRECT

ADDRESSING

ONLY

EA = 0

EXTERNAL

PROGRAM

MEMORY

SPACE

FFFFFFH

FFH

80H

000000H

EXTERNAL

DATA

MEMORY

SPACE
(24-BIT

ADDRESS

SPACE)

7FH

2FH

BANKS

SELECTED

VIA

BITS IN PSW

20H

11

18H

10

10H

01

08H

00

00H

BIT ADDRESSABLE SPACE
(BIT ADDRESSES 0FH–7FH)

1FH

17H

4 BANKS OF 8 REGISTERS

0FH

07H

RESET VALUE OF
STACK POINTER

R0–R7

Figure 2. Lower 128 Bytes of Internal RAM

MEMORY ORGANIZATION

As with all 8052 compatible devices, the ADuC812 has separate
address spaces for program and data memory as shown in Fig­ure 1. Also as shown in Figure 1, an additional 640 bytes of
User Data Flash EEPROM are available to the user. The User
Data Flash Memory area is accessed indirectly via a group of
control registers mapped in the Special Function Register (SFR)
area in the Data Memory Space.

The SFR space is mapped in the upper 128 bytes of internal data
memory space. The SFR area is accessed by direct addressing
only and provides an interface between the CPU and all on-chip
peripherals. A block diagram showing the programming model
of the ADuC812 via the SFR area is shown in Figure 3.

8K BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051

COMPATIBLE

CORE

128-BYTE

SPECIAL
FUNCTION
REGISTER

AREA

640-BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

AUTOCALIBRATING

8-CHANNEL

HIGH SPEED

12-BIT ADC

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

2  12-BIT DACs

SERIAL I/O

PARALLEL I/O

WDT
PSM

Figure 3. Programming Model

Figure 1. Program and Data Memory Maps

The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of
bit addressable memory space at bit addresses 00H through 7FH.

REV. E

–9–

ADuC812

OVERVIEW OF MCU-RELATED SFRs
Accumulator SFR

ACC is the Accumulator register and is used for math opera­tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the Accumulator as A.

B SFR

The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratch pad register.

Stack Pointer SFR

The SP register is the stack pointer and is used to hold an internal
RAM address that is called the “top of the stack.” The SP register
is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip RAM,
the SP register is initialized to 07H after a reset. This causes the
stack to begin at location 08H.

Data Pointer

The Data Pointer is made up of three 8-bit registers: DPP (page
byte), DPH (high byte), and DPL (low byte). These are used to
provide memory addresses for internal and external code access
and external data access. It may be manipulated as a 16-bit
register (DPTR = DPH, DPL), although INC DPTR instructions
will automatically carry over to DPP, or as three independent
8-bit registers (DPP, DPH, and DPL).

Program Status Word SFR

The PSW register is the Program Status Word that contains
several bits reflecting the current status of the CPU as detailed
in Table I.

SFR Address D0H
Power-On Default Value 00H
Bit Addressable Yes

Power Control SFR

The Power Control (PCON) register contains bits for power
saving options and general-purpose status flags as shown in
Table II.

SFR Address 87H
Power-On Default Value 00H
Bit Addressable No

DOMSDPIRESDPOTNIFFOELA1FG0FGDPLDI

Table II. PCON SFR Bit Designations

Bit Name Description

7 SMOD Double UART Baud Rate
6 ——— Reserved
5 ——— Reserved
4 ALEOFF Disable ALE Output
3 GF1 General-Purpose Flag Bit
2 GF0 General-Purpose Flag Bit
1PDPower-Down Mode Enable
0 IDL Idle Mode Enable

YCCA0F1SR0SRVO1FP

Table I. PSW SFR Bit Designations

Bit Name Description

7CYCarry Flag
6ACAuxiliary Carry Flag
5F0General-Purpose Flag
4 RS1 Register Bank Select Bits
3 RS0 RS1 RS0 Selected Bank

000
011
102

113
2OVOverflow Flag
1F1General-Purpose Flag
0P Parity Bit

–10–

REV. E

ADuC812

SPECIAL FUNCTION REGISTERS

All registers except the program counter and the four general-purpose register banks reside in the special function register (SFR) area.
The SFR registers include control, configuration, and data registers that provide an interface between the CPU and other on-chip
peripherals.

Figure 4 shows a full SFR memory map and SFR contents on reset. Unoccupied SFR locations are shown dark shaded (NOT USED).
Unoccupied locations in the SFR address space are not implemented, i.e., no register exists at this location. If an unoccupied
location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded (RESERVED)
and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by
addressable SFRs are those whose address ends in 0H or 8H.

1

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

SPR1

FFH 0

FEH 0

FDH 0

FCH 0

FBH 0

FAH

0

F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H F1H 0 F0H 0

MDO

MDE

EEH 0

DMA

DEH 0

EXF2

CEH 0

PRE1

C6H 0

PADC

BEH 0

MCO

EDH 0 ECH 0

CCONV

DDH 0

RCLK

CDH 0

PRE0

C5H 0 C4H 0

PT2

BDH 0PSBCH 0

EFH 0

E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H E1H 0 E0H 0

ADCI

DFH 0

CY

D7H 0ACD6H 0F0D5H 0

TF2

CFH 0

PRE2

C7H 0

PSI

BFH 0

RD

B7H 1WRB6H 1T1B5H 1T0B4H 1

EA

EADC

AEH

00

SM1

9EH 0

TR1

8EH 0

ET2

ADHESACH 0

SM2

9DH 0

TF0

8DH 0

AFH

0

A7H A6H A5H 1 A4H 1 A3H 1 A2H A1H 1 A0H 1

11

SM0

9FH 0

97H 1 96H 1 95H 1 94H 1 93H 1 92H

TF1

8FH 0

87H 1 86H 1 85H 1 84H 1 83H 1 82H 81H 1 80H 1

I2CM

MDI I2CRS I2CTX I2CI

EBH 0 EAH E9H 0 E8H 0

SCONV

CS3

DCH 0

DBH 0

RS1

RS0

D4H 0

D3H 0OVD2HFID1H 0PD0H 0

TCLK

EXEN2

CCH 0

CBH 0

WDR1

C3H 0

PT1

BBH 0

INT1

B3H 1

ET1

ABH 0

REN

TB8

9CH 0

9BH 0

TR0

IE1

8CH 0

8BH 0

0

0

0

CS2

0

DAH

0

TR2

0

CAH

WDR2

0

C2H

PX1

0

BAH

INT0

B2H

1

EX1

AAH

0

1

RB8

9AHTI99H 0RI98H 0

0

1

IT1

8AH

0

1

SPR0

F9H 0

F8H 0

CS1

CS0

D9H 0

D8H 0

CNT2

CAP2

C9H 0

C8H 0

WDS

WDE

C1H 0

C0H 0

PT0

PX0

B9H 0

B8H 0

TxD

RxD

B1H 1

B0H 1

ET0

EX0

A9H 0

A8H 0

T2EX

91H 1T290H 1

IE0

89H 0

IT0

88H 0

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

SPICON

F8H 00H

F0H 00H

I2CCON

E8H 00H

ACC

E0H 00H

ADCCON2

D8H 00H

PSW

D0H 00H

T2CON

C8H 00H

WDCON

C0H 00H

B8H 00H

B0H FFH

A8H 00H

A0H FFH

SCON

98H 00H

P1

90H FFH

TCON

88H 00H

80H FFHSP81H 07H

DAC0L

F9H 00H

1

ADCOFSL

B

F1H 00H

1

1

1

ADCDATAL

D9H 00H

1

1

RESERVED

1

1

IP

ECON

B9H 00H

1

P3

1

IE

A9H 00H

1

P2

1

SBUF

99H 00H

1, 3

1

TMOD

89H 00H

1

P0

IE2

DAC0H

FAH 00H

2

ADCOFSH

F2H 20H

ADC DATAH

DAH 00H

DMAL

D2H 00H

RCAP2L

CAH 00H

ETIM1

BAH 52H

I2CDAT

9AH 00H

TL0

8AH 00H

DPL

82H 00H

DAC1L

FBH 00H

2

ADCGAINL

F3H 00H

DMAH

D3H 00H

RCAP2H

CBH 00H

NOT USEDNOT USEDNOT USED

ETIM2

BBH 04H

I2CADD

9BH 55H

TL1

8BH 00H

DPH

83H 00H

DAC1H

FCH 00H

2

ADCGAINH

F4H 00H

DMAP

D4H 00H

TL2

CCH 00H

ETIM3

C4H C9H

EDATA1

BCH 00H

TH0

8CH 00H

DPP

84H 00H

DACCON

FDH

2

ADCCON3

F5H 00H

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVED

CDH 00H

EDATA2

BDH 00H

NOT USEDNOT USEDNOT USEDNOT USED

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

NOT USEDNOT USED

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

8DH 00H

“1”

RESERVED NOT USED

04H

RESERVED

RESERVED

RESERVED

TH2

RESERVED

C6H 00H

BEH 00H

TH1

i.e., the bit

RESERVED

RESERVED

EDARL

EDATA3

NOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USED

NOT USED

NOT USED

NOT USED

NOT USED

NOT USED

RESERVEDRESERVED

ADCCON1

SPIDAT

F7H 00H

EFH 20H

RESERVED

PSMCON

DFH DEH

RESERVEDRESERVEDRESERVED

RESERVED

RESERVEDRESERVED

EDATA4

BFH 00H

NOT USED

NOT USED

NOT USED

NOT USED

NOT USED

NOT USED

PCON

87H 00H

SFR MAP KEY:

MNEMONIC

SFR ADDRESS

DEFAULT VALUE

SFR NOTES

1

SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.

2

CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.

3

THE PRIMARY FUNCTION OF PORT 1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS

ON THESE PORT PINS, WRITE A “0” TO THE CORRESPONDING PORT 1 SFR BIT.

THESE BITS ARE CONTAINED IN THIS BYTE.

IE0

89H 0

IT0

88H 0

TCON

88H 00H

MNEMONIC

DEFAULT VALUE

SFR ADDRESS

Figure 4. Special Function Register Locations and Reset Values

REV. E

–11–

ADuC812

ADC CIRCUIT INFORMATION
General Overview

The ADC conversion block incorporates a fast, 8-channel,
12-bit, single-supply ADC. This block provides the user with
multichannel mux, track-and-hold, on-chip reference, calibra­tion features, and ADC. All components in this block are easily
configured via a 3-register SFR interface.

The ADC consists of a conventional successive-approximation
converter based around a capacitor DAC. The converter accepts
an analog input range of 0 V to V

. A high precision, low drift

REF

and factory calibrated 2.5 V reference is provided on-chip. The
internal reference may be overdriven via the external V
This external reference can be in the range 2.3 V to AV

REF

DD

pin.
.

Single step or continuous conversion modes can be initiated in
software or alternatively by applying a convert signal to an external
pin. Timer 2 can also be configured to generate a repetitive trigger
for ADC conversions. The ADC may be configured to operate
in a DMA mode whereby the ADC block continuously converts
and captures samples to an external RAM space without any
interaction from the MCU core. This automatic capture facility
can extend through a 16 MByte external Data Memory space.

The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal offset and gain calibration registers.
A software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
user’s target system.

A voltage output from an on-chip band gap reference propor­tional to absolute temperature can also be routed through the
front end ADC multiplexer (effectively a ninth ADC channel
input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to V

. For this

REF

range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when

= 2.5 V. The ideal input/output transfer characteristic for

V

REF

the 0 to V

range is shown in Figure 5.

REF

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000
1LSB

0V

1LSB =

FS

4096

VOLTAGE INPUT

+FS
–1LSB

Figure 5. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1–3 SFRs (shown on the
following page), the ADC will convert the analog input and
provide an ADC 12-bit result word in the ADCDATAH/L SFRs.
The top four bits of the ADCDATAH SFR will be written
with the channel selection bits to identify the channel result.
The format of the ADC 12-bit result word is shown in Figure 6.

ADCDATAH SFR

CH–ID

TOP 4 BITS

HIGH 4 BITS OF
ADC RESULT WORD

ADCDATAL SFR

–12–

LOW 8 BITS OF THE
ADC RESULT WORD

Figure 6. ADC Result Format

REV. E

ADuC812

ADCCON1—(ADC Control SFR #1)

The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as
detailed below.

SFR Address EFH
SFR Power-On Default Value 20H

1DM0DM1KC0KC1QA0QAC2TCXE

Table III. ADCCON1 SFR Bit Designations

Bit Name Description

ADCCON1.7 MD1 The mode bits (MD1, MD0) select the active operating mode of the ADC as follows:
ADCCON1.6 MD0 MD1 MD0 Active Mode

00ADC powered down
01ADC normal mode
10ADC powered down if not executing a conversion cycle
11ADC standby if not executing a conversion cycle
Note: In power-down mode the ADC V
powered down, thus minimizing current consumption.

ADCCON1.5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the
ADCCON1.4 CK0 ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected

as follows:
CK1 CK0 MCLK Divider
001
012
104
118

circuits are maintained on, whereas all ADC peripherals are

REF

ADCCON1.3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold
ADCCON1.2 AQ0 amplifier to acquire the input signal, and are selected as follows:

AQ1 AQ0 #ADC Clks
001
012
104
118

ADCCON1.1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as

the ADC convert start trigger input. ADC conversions are initiated on the second Timer 2 overflow.

ADCCON1.0 EXC The external trigger enable bit (EXC) is set by the user to allow the external CONVST pin to be

used as the active low convert start input. This input should be an active low pulse (minimum
pulsewidth >100 ns) at the required sample rate.

REV. E

–13–

ADuC812

ADCCON2—(ADC Control SFR #2)

The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.

SFR Address D8H
SFR Power-On Default Value 00H

ICDAAMDVNOCCVNOCS3SC2SC1SC0SC

Table IV. ADCCON2 SFR Bit Designations

L

ocation Name Description

ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the

end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt
Service Routine.

ADCCON2.6 DMA The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode operation.

A more detailed description of this mode is given in the ADC DMA Mode section.

ADCCON2.5 CCONV The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode

of conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previous
conversion has completed.

ADCCON2.4 SCONV The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is

automatically reset to “0” on completion of the single conversion cycle.

ADCCON2.3 CS3 The channel selection bits (CS3–0) allow the user to program the ADC channel selection under
ADCCON2.2 CS2 software control. When a conversion is initiated, the channel converted will be the one pointed to by
ADCCON2.1 CS1 these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
ADCCON2.0 CS0 written to the external memory.

CS3 CS2 CS1 CS0 CH#
00000

00011
00102
00113
01004
01015
01106
01117
1000Temp Sensor
1111DMA STOP
All other combinations reserved.

ADCCON3—(ADC Control SFR #3)

The ADCCON3 register gives user software an indication of ADC busy status.

SFR Address F5H
SFR Power-On Default Value 00H

YSUBDVSRDVSRDVSRDVSRDVSRDVSRDVSR

Table V. ADCCON3 SFR Bit Designations

Bit Location Bit Status Description

ADCCON3.7 BUSY The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion

or calibration cycle. BUSY is automatically cleared by the core at the end of conversion or calibration.

ADCCON3.6 RSVD ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as “0” and should only
ADCCON3.5 RSVD be written as “0” by user software.
ADCCON3.4 RSVD
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 RSVD
ADCCON3.0 RSVD

–14–

REV. E

ADuC812

Driving the ADC

The ADC incorporates a successive approximation (SAR) archi­tecture involving a charge-sampled input stage. Figure 7 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 7. During the sampling phase
(with SW1 and SW2 in the “track” position), a charge propor­tional to the voltage on the analog input is developed across the
input sampling capacitor. During the conversion phase (with
both switches in the “hold” position), the capacitor DAC is
adjusted via internal SAR logic until the voltage on node A is zero,
indicating that the sampled charge on the input capacitor is
balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched
out as the result of the ADC conversion. Control of the SAR,
and timing of acquisition and sampling modes, is handled
automatically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.

ADC0

ADC7

TRACK

AGND

200

HOLD

TEMPERATURE

SENSOR

SW1

2pF

NODE A

SW2

HOLDTRACK

ADuC812

CAPACITOR

DAC

COMPARATOR

Figure 7. Internal ADC Structure

Note that whenever a new input channel is selected, a residual
charge from the 2 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches click
into “hold” mode. Delays can be inserted in software (between
channel selection and conversion request) to account for input
stage settling, but a hardware solution will alleviate this burden
from the software design task and will ultimately result in a
cleaner system implementation. One hardware solution would
be to choose a very fast settling op amp to drive each analog
input. Such an op amp would need to settle fully from a small
signal transient in less than 300 ns to guarantee adequate settling
under all software configurations. A better solution, recommended
for use with any amplifier, is shown in Figure 8.

Though at first glance the circuit in Figure 8 may look like a
simple antialiasing filter, it actually serves no such purpose since
its corner frequency is well above the Nyquist frequency, even at
a 200 kHz sample rate. Though the R/C does help to reject some
incoming high frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met. It
does so by providing a capacitive bank from which the 2 pF

ADuC812

51

0.01F

1

ADC0

Figure 8. Buffering Analog Inputs

sampling capacitor can draw its charge. Since the 0.01 µF capacitor
in Figure 8 is more than 4096 times the size of the 2 pF sampling
capacitor, its voltage will not change by more than one count
(1/4096) of the 12-bit transfer function when the 2 pF charge
from a previous channel is dumped onto it. A larger capacitor
can be used if desired, but not a larger resistor (for reasons
described below).

The Schottky diodes in Figure 8 may be necessary to limit the
voltage applied to the analog input pin as per the Absolute Maxi­mum Ratings. They are not necessary if the op amp is powered
from the same supply as the ADuC812 since in that case, the
op amp is unable to generate voltages above V

or below ground.

DD

An op amp is necessary unless the signal source is very low imped­ance to begin with. DC leakage currents at the ADuC812’s analog
inputs can cause measurable dc errors with external source imped­ances of as little as 100 Ω. To ensure accurate ADC operation,
keep the total source impedance at each analog input less than
61 Ω. The table below illustrates examples of how source
impedance can affect dc accuracy.

Source Error from 1 A Error from 10 A
Impedance Leakage Current Leakage Current

61 Ω 61 µV = 0.1 LSB 610 µV = 1 LSB
610 Ω 610 µV = 1 LSB 61 mV = 10 LSB

Although Figure 8 shows the op amp operating at a gain of 1,
you can configure it for any gain needed. Also, you can use an
instrumentation amplifier in its place to condition differential
signals. Use any modern amplifier that is capable of delivering
the signal (0 to V

) with minimal saturation. Some single-supply,

REF

rail-to-rail op amps that are useful for this purpose include, but
are not limited to, the ones given in Table VI. Check Analog
Devices literature (CD ROM data book, and so on) for details
about these and other op amps and instrumentation amps.

Table VI. Some Single-Supply Op Amps

Op Amp Model Characteristics

OP181/OP281/OP481 Micropower
OP191/OP291/OP491 I/O Good up to VDD, Low Cost
OP196/OP296/OP496 I/O to V

, Micropower, Low Cost

DD

OP183/OP283 High Gain-Bandwidth Product
OP162/OP262/OP462 High GBP, Micro Package
AD820/AD822/AD824 FET Input, Low Cost
AD823 FET Input, High GBP

Keep in mind that the ADC’s transfer function is 0 V to V

REF

,
and any signal range lost to amplifier saturation near ground will
impact dynamic range. Though the op amps in Table VI are
capable of delivering output signals very closely approaching
ground, no amplifier can deliver signals all the way to ground when
powered by a single supply. Therefore, if a negative supply is
available, consider using it to power the front end amplifiers.

REV. E

–15–

ADuC812

However, be sure to include the Schottky diodes shown in
Figure 8 (or at least the lower of the two diodes) to protect the
analog input from undervoltage conditions. To summarize this
section, use the circuit of Figure 8 to drive the analog input pins
of the ADuC812.

Voltage Reference Connections

The on-chip 2.5 V band gap voltage reference can be used as
the reference source for the ADC and DACs. To ensure the
accuracy of the voltage reference, decouple both the V
the C

pin to ground with 0.1 µF ceramic chip capacitors as

REF

pin and

REF

shown in Figure 9.

ADuC812

BUFFER

0.1F

0.1F

V

REF

C

REF

51

BUFFER

Figure 9. Decoupling V

2.5V

BAND GAP

REFERENCE

and C

REF

REF

The internal voltage reference can also be tapped directly from
the V

pin, if desired, to drive external circuitry. However, a

REF

buffer must be used to ensure that no current is drawn from the

pin itself. The voltage on the C

V

REF

pin is that of an internal

REF

node within the buffer block, and its voltage is critical to ADC
and DAC accuracy. Do not connect anything to this pin except
the capacitor, and be sure to keep trace-lengths short on the

capacitor, decoupling the node straight to the underlying

C

REF

ground plane.

The ADuC812 powers up with its internal voltage reference in the
“off” state. The voltage reference turns on automatically whenever
the ADC or either DAC gets enabled in software. Once enabled,
the voltage reference requires approximately 65 ms to power up
and settle to its specified value. Be sure that your software allows
this time to elapse before initiating any conversions. If an external
voltage reference is preferred, connect it to the V

pin as shown

REF

in Figure 10 to overdrive the internal reference.

To ensure accurate ADC operation, the voltage applied to V

REF

must be between 2.3 V and AVDD. In situations where analog
input signals are proportional to the power supply (such as some
strain gage applications), it may be desirable to connect the

pin directly to AVDD. In such a configuration, the user

V

REF

must also connect the C

pin directly to AVDD to circumvent

REF

internal buffer headroom limitations. This allows the ADC
input transfer function to span the full range of 0 V to AV

DD

accurately.

Operation of the ADC or DACs with a reference voltage below

2.3 V, however, may incur loss of accuracy resulting in missing
codes or nonmonotonicity. For that reason, do not use a reference
voltage less than 2.3 V.

ADuC812

V

DD

EXTERNAL

VOLTA G E

REFERENCE

0.1F

0.1F

51

V

REF

C

REF

BUFFER

2.5V

BAND GAP

REFERENCE

Figure 10. Using an External Voltage Reference

Configuring the ADC

The three SFRs (ADCCON1, ADCCON2, ADCCON3) con­figure the ADC. In nearly all cases, an acquisition time of one
ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide
plenty of time for the ADuC812 to acquire its signal before
switching the internal track-and-hold amplifier into hold mode.
The only exception would be a high source impedance analog
input, but these should be buffered first anyway since source
impedances of greater than 610 Ω can cause dc errors as well.

The ADuC812’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz and
4 MHz, and optimum performance is obtained with ADC clock
between 400 kHz and 3 MHz. Frequencies within this range can
be achieved with master clock frequencies from 400 kHz to well
above 16 MHz with the four ADC clock divide ratios to choose
from. For example, with a 12 MHz master clock, set the ADC
clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by
setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1,
ADCCON1.4 = 0).

The total ADC conversion time is 15 ADC clocks, plus one
ADC clock for synchronization, plus the selected acquisition
time (1, 2, 3, or 4 ADC clocks). For the example above, with a
one clock acquisition time, total conversion time is 17 ADC clocks
(or 5.67 µs for a 3 MHz ADC clock).

In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is the inverse of the
total conversion time described above. In the example above, the
continuous conversion mode sample rate would be 176.5 kHz.

ADC DMA Mode

The on-chip ADC has been designed to run at a maximum
conversion speed of 5 µs (200 kHz sampling rate). When con­verting at this rate, the ADuC812 MicroConverter has 5 µs to
read the ADC result and store the result in memory for further
postprocessing, otherwise the next ADC sample could be lost.
In an interrupt driven routine, the MicroConverter would also
have to jump to the ADC Interrupt Service routine, which will
also increase the time required to store the ADC results. In
applications where the ADuC812 cannot sustain the interrupt
rate, an ADC DMA mode is provided.

To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set.
This allows the ADC results to be written directly to a 16 MByte
external static memory SRAM (mapped into data memory space)

–16–

REV. E

ADuC812

without any interaction from the ADuC812 core. This mode
allows the ADuC812 to capture a contiguous sample stream at
full ADC update rates (200 kHz).

DMA Mode Configuration Example

To set the ADuC812 into DMA mode, a number of steps must
be followed.

1. The ADC must be powered down by setting MD1 and MD0
to 0 in ADCCON1.

2. The DMA Address pointer must be set to the start address of
where the ADC results are to be written. This is done by
writing to the DMA mode Address Pointers DMAL, DMAH,
and DMAP. DMAL must be written to first, followed by
DMAH, and then DMAP.

3. The external memory must be preconfigured. This consists of
writing the required ADC channel IDs into the top four bits of
every second memory location in the external SRAM, starting
at the first address specified by the DMA address pointer. As the
ADC DMA mode operates independently of the ADuC812
core, it is necessary to provide it with a stop command. This is
done by duplicating the last channel ID to be converted, fol­lowed by “1111” into the next channel selection field. Figure 11
shows a typical preconfiguration of external memory.

00000AH

000000H

1111

0011

0011

1000

0101

0010

STOP COMMAND

REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION

CONVERT ADC CH#3

CONVERT TEMP SENSOR

CONVERT ADC CH#5

CONVERT ADC CH#2

Figure 11. Typical DMA External Memory Preconfiguration

4. The DMA is initiated by writing to the ADC SFRs in the
following sequence.

a. ADCCON2 is written to enable the DMA mode, i.e.,

MOV ADCCON2, #40H; DMA mode enabled.

b. ADCCON1 is written to configure the conversion time and

power-up of the ADC. It can also enable Timer 2 driven
conversions or External Triggered conversions if required.

c. ADC conversions are initiated by starting single/continuous

conversions, starting Timer 2 running for Timer 2 conver­sions, or by receiving an external trigger.

When the DMA conversions are completed, the ADC interrupt
bit ADCI is set by hardware and the external SRAM contains the
new ADC conversion results as shown in Figure 12. It should be
noted that no result is written to the last two memory locations.

When the DMA mode logic is active, it is responsible for storing
the ADC results away from both the user and ADuC812 core
logic. As it writes the results of the ADC conversions to external
memory, it takes over the external memory interface from the core.
Thus, any core instructions that access the external memory
while DMA mode is enabled will not gain access to it. The core
will execute the instructions and they will take the same time to
execute, but they will not gain access to the external memory.

00000AH

000000H

1111

0011

0011

1000

0101

0010

STOP COMMAND

NO CONVERSION
RESULT WRITTEN HERE

CONVERSION RESULT
FOR ADC CH#3

CONVERSION RESULT
FOR TEMP SENSOR

CONVERSION RESULT
FOR ADC CH#5

CONVERSION RESULT
FOR ADC CH#2

Figure 12. Typical External Memory Configuration Post
ADC DMA Operation

The DMA logic operates from the ADC clock and uses

pipelining
to perform the ADC conversions and access the external memory
at the same time. The time it takes to perform one ADC conver­sion is called a DMA cycle. The actions performed by the logic
during a typical DMA cycle are shown in Figure 13.

CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE

WRITE ADC RESULT

CONVERTED DURING

PREVIOUS DMA CYCLE

DMA CYCLE

READ CHANNEL ID

TO BE CONVERTED DURING

NEXT DMA CYCLE

Figure 13. DMA Cycle

From the previous diagram, it can be seen that during one DMA
cycle the following actions are performed by the DMA logic.

1. An ADC conversion is performed on the channel whose ID

was read during the previous cycle.

2. The 12-bit result and the channel ID of the conversion per-

formed in the previous cycle are written to the external memory.

3. The ID of the next channel to be converted is read from

external memory.

For the previous example, the complete flow of events is shown
in Figure 13. Because the DMA logic uses pipelining, it takes
three cycles before the first correct result is written out.

Micro Operation during ADC DMA Mode

During ADC DMA mode, the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, it should be noted that MCU core
accesses to Ports 0 and 2 (which are being used by the DMA
controller) are gated OFF during ADC DMA mode of operation.
This means that even though the instruction that accesses the
external Ports 0 or 2 will appear to execute, no data will be seen
at these external ports as a result.

The MicroConverter core can be configured with an interrupt
to be triggered by the DMA controller when it has finished
filling the requested block of RAM with ADC results, allowing
the service routine for this interrupt to postprocess data without
any real-time timing constraints.

Offset and Gain Calibration Coefficients

The ADuC812 has two ADC calibration coefficients, one for offset
calibration and one for gain calibration. Both the offset and gain
calibration coefficients are 14-bit words, located in the Special
Function Register (SFR) area. The offset calibration coefficient
is divided into ADCOFSH (six bits) and ADCOFSL (eight bits),

REV. E

–17–

ADuC812

and the gain calibration coefficient is divided into ADCGAINH
(six bits) and ADCGAINL (eight bits). The offset calibration
coefficient compensates for dc offset errors in both the ADC and
the input signal.

Increasing the offset coefficient compensates for positive offset,
and effectively pushes the ADC transfer function DOWN. De­creasing the offset coefficient compensates for negative offset,
and effectively pushes the ADC transfer function UP. The
maximum offset that can be compensated is typically ±5% of

, which equates to typically ±125 mV with a 2.5 V reference.

V

REF

Similarly, the gain calibration coefficient compensates for dc gain
errors in both the ADC and the input signal.

Increasing the gain coefficient compensates for a smaller analog
input signal range and scales the ADC transfer function UP,
effectively increasing the slope of the transfer function. Decreasing
the gain coefficient compensates for a larger analog input signal
range and scales the ADC transfer function DOWN, effectively
decreasing the slope of the transfer function. The maximum analog
input signal range for which the gain coefficient can compensate
is 1.025 ⫻ V

, and the minimum input range is 0.975 ⫻ V

REF

REF

,

which equates to ±2.5% of the reference voltage.

Calibration

Each ADuC812 is calibrated in the factory prior to shipping, and
the offset and gain calibration coefficients are stored in a hidden
area of FLASH/EE memory. Each time the ADuC812 powers up,
an internal power-on configuration routine copies these coefficients
into the offset and gain calibration registers in the SFR area.

The MicroConverter ADC accuracy may vary from system
to system due to board layout, grounding, clock speed, and so
on. To get the best ADC accuracy in your system, perform
the software calibration routine described in Application Note
uC005, available from the MicroConverter homepage at
www.analog.com/microconverter.

NONVOLATILE FLASH MEMORY
Flash Memory Overview

The ADuC812 incorporates Flash memory technology on-chip
to provide the user with a nonvolatile, in-circuit reprogrammable
code and data memory space.

Flash/EE memory is a relatively new type of nonvolatile memory
technology based on a single transistor cell architecture.

This technology is basically an outgrowth of EPROM technology
and was developed in the late 1980s. Flash/EE memory takes the
flexible in-circuit reprogrammable features of EEPROM and
combines them with the space efficient/density features of EPROM
(see Figure 14).

Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be imple­mented to achieve the space efficiencies or memory densities
required by a given design.

Like EEPROM, Flash memory can be programmed in-system
at a byte level, although it must first be erased in page blocks.
Thus, Flash memory is often and more correctly referred to as
Flash/EE memory.

EPROM

TECHNOLOGY

SPACE EFFICIENT/

DENSITY

FLASH/EE MEMORY

TECHNOLOGY

EEPROM

TECHNOLOGY

IN-CIRCUIT

REPROGRAMMABLE

Figure 14. Flash Memory Development

Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit programma­bility, high density, and low cost. Incorporated in the ADuC812,
Flash/EE memory technology allows the user to update program
code space in-circuit without replacing one-time programmable
(OTP) devices at remote operating nodes.

Flash/EE Memory and the ADuC812

The ADuC812 provides two arrays of Flash/EE memory for user
applications. 8K bytes of Flash/EE program space are provided
on-chip to facilitate code execution without any external discrete
ROM device requirements. The program memory can be pro­grammed using conventional third party memory programmers.
This array can also be programmed in-circuit, using the serial
download mode provided.

A 640 byte Flash/EE data memory space is also provided on-chip
as a general-purpose nonvolatile scratchpad area. User access to
this area is via a group of six SFRs.

ADuC812 Flash/EE Memory Reliability

The Flash/EE program and data memory arrays on the ADuC812
are fully qualified for two key Flash/EE memory characteristics:
Flash/EE Memory Cycling Endurance and Flash/EE Memory
Data Retention.

Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent
sequential events:

a. Initial Page Erase Sequence
b. Read/Verify Sequence
c. Byte Program Sequence
d. Second Read/Verify Sequence

In reliability qualification, every byte in the program and data
Flash/EE memory is cycled from 00H to FFH until the first fail is
recorded, signifying the endurance limit of the on-chip Flash/EE
memory.

As indicated in the Specification tables, the ADuC812 Flash/EE
Memory Endurance qualification has been carried out in accor­dance with JEDEC Specification A117 over the industrial
temperature ranges of –40°C, +25°C, and +85°C. The results
allow the specification of a minimum endurance figure over supply
and temperature of 10,000 cycles, with an endurance figure of
50,000 cycles being typical of operation at 25°C.

Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the ADuC812 has been
qualified in accordance with the formal JEDEC Retention Lifetime
Specification (A117) at a specific junction temperature (T

= 55°C).

J

As part of this qualification procedure, the Flash/EE memory is
cycled to its specified endurance limit described above, before data
retention is characterized. This means that the Flash/EE memory
is guaranteed to retain its data for its full specified retention
lifetime every time the Flash/EE memory is reprogrammed.

–18–

REV. E