Analog Devices ADuC812 User Manual

MicroConverter®, Multichannel

FEATURES ANALOG I/O

8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/C Voltage Reference High-Speed 200 kSPS DMA Controller for High-Speed ADC-to-RAM Capture Two 12-Bit Voltage Output DACs On-Chip Temperature Sensor Function

MEMORY

8K Bytes On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory 256 Bytes On-Chip Data RAM 16M Bytes External Data Address Space 64K Bytes External Program Address Space

8051-COMPATIBLE CORE

12 MHz Nominal Operation (16 MHz Max) Three 16-Bit Timer/Counters High Current Drive Capability—Port 3 Nine Interrupt Sources, Two Priority Levels

POWER

Specified for 3 V and 5 V Operation Normal, Idle, and Power-Down Modes

ON-CHIP PERIPHERALS

UART Serial I/O 2-Wire (I Watchdog Timer Power Supply Monitor

2C®

-Compatible) and SPI® Serial I/O

12-Bit ADC with Embedded FLASH MCU

ADuC812

APPLICATIONS Intelligent Sensors Calibration and Conditioning Battery Powered Systems (Portable PCs, Instruments,

Monitors) Transient Capture Systems DAS and Communications Systems Control Loop Monitors (Optical Networks/Base Stations)

GENERAL DESCRIPTION

The ADuC812 is a fully integrated 12-bit data acquisition system incorporating a high performance self calibrating multichannel ADC, dual DAC and programmable 8-bit MCU (8051 instruction set compatible) on a single chip.

The programmable 8051-compatible core is supported by 8K bytes Flash/EE program memory, 640 bytes Flash/EE data memory and 256 bytes data SRAM on-chip.

Additional MCU support functions include Watchdog Timer, Power Supply Monitor and ADC DMA functions. 32 Programmable I/O lines, I Serial Port I/O are provided for multiprocessor interfaces and I/O expansion.

Normal, idle, and power-down operating modes for both the MCU core and analog converters allow for flexible power management schemes suited to low power applications. The part is specified for 3 V and 5 V operation over the industrial temperature range and is available in a 52-lead, plastic quad flatpack package.

C-compatible, SPI and Standard UART

FUNCTIONAL BLOCK DIAGRAM

AIN0 (P1.0)–AIN7 (P1.7)

REF

MicroConverter is a registered trademark of Analog Devices, Inc. I2C is a registered trademark of Philips Corporation. SPI is a registered trademark of Motorola Inc.

AIN

MUX

2.5V REF

BUF

T/H

TEMP

SENSOR

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

ADuC812

AGNDAV

CALIBRATION

8051 BASED

MICROCONTROLLER CORE

8K  8 PROGRAM

FLASH EEPROM

640  8 USER

FLASH EEPROM

256  8 USER

DGNDDV

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

P3.0–P3.7P2.0–P2.7P1.0–P1.7P0.0–P0.7

3  16-BIT

TIMER/COUNTERS

2-WIRE

SERIAL I/O

SCLOCK

SDATA

BUF

MUX

MOSI/

SPI

MISO (P3.3)

TxD

(P3.1)

DAC0

DAC1

ADC

CONTROL

AND

LOGIC

RAM

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

DAC

CONTROL

MICROCONTROLLER

POWER SUPPLY

MONITOR

WATCHDOG

TIMER

UART

OSC

RxD

XTAL2XTAL1

(P3.0)

DAC0

DAC1

T0 (P3.4)

T1 (P3.5) T2 (P1.0) T2EX (P1.1)

INT0 (P3.2) INT1 (P3.3)

ALE

PSEN EA

RESET

ADuC812

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DISCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ADC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Integral Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Full-Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal to (Noise + Distortion) Ratio . . . . . . . . . . . . . . . . . . . . 8

Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DAC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Relative Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Voltage Output Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . 8

Digital-to-Analog Glitch Impulse . . . . . . . . . . . . . . . . . . . . . . . 8

ARCHITECTURE, MAIN FEATURES . . . . . . . . . . . . . . . . . . 9

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OVERVIEW OF MCU-RELATED SFRs . . . . . . . . . . . . . . . . . 10

Accumulator SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

B SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stack Pointer SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Status Word SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power Control SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . 11

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . 12

General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Typical Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ADCCON1 – (ADC Control SFR #1) . . . . . . . . . . . . . . . . . 13

ADCCON2 – (ADC Control SFR #2) . . . . . . . . . . . . . . . . . 14

ADCCON3 – (ADC Control SFR #3) . . . . . . . . . . . . . . . . . 14

Driving the A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage Reference Connections . . . . . . . . . . . . . . . . . . . . . . . 16

Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ADC DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Micro Operation during ADC DMA Mode . . . . . . . . . . . . . . 17

The Offset and Gain Calibration Coefficients . . . . . . . . . . . . 17

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

NONVOLATILE FLASH MEMORY . . . . . . . . . . . . . . . . . . . 18

Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Flash/EE Memory and the ADuC812 . . . . . . . . . . . . . . . . . . 18

ADuC812 Flash/EE Memory Reliability . . . . . . . . . . . . . . . . 18

Using the Flash/EE Program Memory . . . . . . . . . . . . . . . . . . 19

Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . . . . 19

ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . . . . 20

Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using the Flash/EE Memory Interface . . . . . . . . . . . . . . . . . . 20

Erase-All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

USER INTERFACE TO OTHER ON-CHIP

ADuC812 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Using the D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . 25

SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . 26

MISO (Master In, Slave Out Data I/O Pin), Pin #19 . . . . . . 26

MOSI (Master Out, Slave In Pin), Pin #27 . . . . . . . . . . . . . . 26

SCLOCK (Serial Clock I/O Pin), Pin #26 . . . . . . . . . . . . . . . 26

SS (Slave Select Input Pin), Pin #12 . . . . . . . . . . . . . . . . . . . 26

Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Interface—Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Interface—Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

C-COMPATIBLE INTERFACE . . . . . . . . . . . . . . . . . . . . . .28

8051-COMPATIBLE ON-CHIP PERIPHERALS . . . . . . . . . .29

Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Timer/Counter 0 and 1 Data Registers . . . . . . . . . . . . . . . .31

TH0 and TL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TH1 and TL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TIMER/COUNTER 0 AND 1 OPERATING MODES . . . . . . 32

Mode 0 (13-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . 32

Mode 1 (16-Bit Timer/Counter) . . . . . . . . . . . . . . . . . . . . . . 32

Mode 2 (8-Bit Timer/Counter with Auto Reload) . . . . . . . . . 32

Mode 3 (Two 8-Bit Timer/Counters) . . . . . . . . . . . . . . . . . . 32

Timer/Counter 2 Data Registers . . . . . . . . . . . . . . . . . . . . . .33

TH2 and TL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

RCAP2H and RCAP2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Timer /Counter Operation Modes . . . . . . . . . . . . . . . . . . . . . 34

16-Bit Autoreload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

16-Bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

UART SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mode 0: 8-Bit Shift Register Mode . . . . . . . . . . . . . . . . . . . .36

Mode 1: 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . .36

Mode 2: 9-Bit UART with Fixed Baud Rate . . . . . . . . . . . . . 36

Mode 3: 9-Bit UART with Variable Baud Rate . . . . . . . . . . .36

UART Serial Port Baud Rate Generation . . . . . . . . . . . . . . .36

Timer 1 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . 37

Timer 2 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . . . . 37

INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ADuC812 HARDWARE DESIGN CONSIDERATIONS . . . . 40

Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . .40

Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Grounding and Board Layout Recommendations . . . . . . . . .43

OTHER HARDWARE CONSIDERATIONS . . . . . . . . . . . . .44

In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . . . 44

Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . . . 44

Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . . . . . 45

Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . . . 45

QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . . . .45

Download—In-Circuit Serial Downloader . . . . . . . . . . . . . . . 45

DeBug—In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . 45

ADSIM—Windows Simulator . . . . . . . . . . . . . . . . . . . . . . . . 45

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 46

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

–2–

REV. B

ADuC812

SPECIFICATIONS

= 200 kHz, DAC V

SAMPLE

Load to AGND; RL = 2 k, CL = 100 pF. All specifications TA = T

OUT

1, 2

(AVDD = DVDD = 3.0 V or 5.0 V 10%, REFIN/REF

= 2.5 V Internal Reference, MCLKIN = 11.0592 MHz,

OUT

to T

MIN

, unless otherwise noted.)

MAX

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

DC ACCURACY

3, 4

Resolution 12 12 Bits Integral Nonlinearity ± 1/2 ± 1/2 LSB typ f

± 1.5 LSB max f ± 1.5 ±1.5 LSB typ f

Differential Nonlinearity ± 1 ± 1 LSB typ f

= 100 kHz

SAMPLE

= 100 kHz

SAMPLE

= 200 kHz

SAMPLE

= 100 kHz. Guaranteed No

SAMPLE

Missing Codes at 5 V

CALIBRATED ENDPOINT ERRORS

5, 6

Offset Error ± 5LSB max

± 1 ± 2 LSB typ Offset Error Match 1 1 LSB typ Gain Error ± 6LSB max

± 1 ± 2 LSB typ Gain Error Match 1.5 1.5 LSB typ

USER SYSTEM CALIBRATION

Offset Calibration Range ± 5 ±5 % of V Gain Calibration Range ± 2.5 ±2.5 % of V

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

typ

REF

typ

REF

= 10 kHz Sine Wave

= 100 kHz

70 70 dB typ

SAMPLE

Total Harmonic Distortion (THD) –78 –78 dB typ Peak Harmonic or Spurious Noise –78 –78 dB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts

Leakage Current ± 10 µA max

Input Capacitance

TEMPERATURE SENSOR

± 1 ± 1 µA typ

20 20 pF max

Voltage Output at 25°C 600 600 mV typ Can vary significantly (> ±20%) Voltage TC –3.0 –3.0 mV/°C typ from device to device

DAC CHANNEL SPECIFICATIONS

DC ACCURACY

Resolution 12 12 Bits Relative Accuracy ± 3 ± 3 LSB typ Differential Nonlinearity ±0.5 ±1 LSB typ Guaranteed 12-Bit Monotonic Offset Error ±60 mV max

± 25 ± 25 mV typ

Full-Scale Error ± 30 mV max

± 10 ± 10 mV typ

Full-Scale Mismatch ± 0.5 ±0.5 % typ % of Full-Scale on DAC1

ANALOG OUTPUTS

Voltage Range_0 0 to V Voltage Range_1 0 to V

REF

0 to V 0 to V

REF

V typ

V typ Resistive Load 10 10 kΩ typ Capacitive Load 100 100 pF typ Output Impedance 0.5 0.5 Ω typ I

SINK

50 50 µA typ

REV. B

–3–

1, 2

ADuC812–SPECIFICATIONS

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

DAC AC CHARACTERISTICS

Voltage Output Settling Time 15 15 µs typ Full-Scale Settling Time to

Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry

REFERENCE INPUT/OUTPUT

Input Voltage Range

REF

Input Impedance 150 150 kΩ typ REF

REF

Output Voltage 2.5 ±2.5% V min/max Initial Tolerance @ 25°C

OUT

Tempco 100 100 ppm/°C typ

OUT

FLASH/EE MEMORY PERFORMANCE

CHARACTERISTICS

Endurance 10,000 Cycles min

Data Retention 10 Years min

WATCHDOG TIMER

CHARACTERISTICS

Oscillator Frequency 64 64 kHz typ

POWER SUPPLY MONITOR

CHARACTERISTICS

Power Supply Trip Point Accuracy ±2.5 % of Selected

DIGITAL INPUTS

Input High Voltage (V XTAL1 Input High Voltage (V Input Low Voltage (V Input Leakage Current (Port 0, EA) ± 10 µA max V

Logic 1 Input Current

(All Digital Inputs) ± 10 µA max V

Logic 0 Input Current (Port 1, 2, 3) –80 µA max

Logic 1-0 Transition Current (Port 1, 2, 3) –700 µA max V

Input Capacitance 10 10 pF typ

2.3/V

2.5 2.5 V typ

12, 13

50,000 50,000 Cycles typ

± 1.0 ±1.0 % of Selected

) 2.4 V min

INH

) 0.8 V max

INL

) Only 4 V min

INH

± 1 ± 1 µA typ VIN = 0 V or V

± 1 ± 1 µA typ VIN = V

–40 –40 µA typ V

–400 –400 µA typ V

(continued)

2.3/V

V min/max

Nominal Trip Point Voltage max

Nominal Trip Point Voltage typ

Within 1/2 LSB of Final Value

= 0 V or V

= V

= 450 mV

= 2 V

–4–

REV. B

ADuC812

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

DIGITAL OUTPUTS

Output High Voltage (VOH) 2.4 V min VDD = 4.5 V to 5.5 V

4.0 2.6 V typ V I

Output Low Voltage (V

)

ALE, PSEN, Ports 0 and 2 0.4 V max I

0.2 0.2 V typ I

Port 3 0.4 V max I

0.2 0.2 V typ I

Floating State Leakage Current ± 10 µA max

± 5 ± 5 µA typ

Floating State Output Capacitance 10 10 pF typ

POWER REQUIREMENTS

IDD Normal Mode

14, 15, 16

43 mA max MCLKIN = 16 MHz 32 16 mA typ MCLKIN = 16 MHz 26 12 mA typ MCLKIN = 12 MHz 8 3 mA typ MCLKIN = 1 MHz

Idle Mode 25 mA max MCLKIN = 16 MHz

18 17 mA typ MCLKIN = 16 MHz 15 6 mA typ MCLKIN = 12 MHz 7 2 mA typ MCLKIN = 1 MHz 50 50 µA max

Power-Down Mode

55 µA typ

NOTES

Specifications apply after calibration.

Temperature range –40°C to +85°C.

Linearity is guaranteed during normal MicroConverter Core operation.

Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.

Measured in production at VDD = 5 V after Software Calibration Routine at 25°C only.

User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.

The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.

SNR calculation includes distortion and noise components.

Specification is not production tested, but is supported by characterization data at initial product release.

The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result.

DAC linearity is calculated using:

reduced code range of 48 to 4095, 0 to V reduced code range of 48 to 3995, 0 to VDD range DAC output load = 10 kΩ and 50 pF.

Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance).

Endurance Cycling is evaluated under the following conditions:

Mode = Byte Programming, Page Erase Cycling Cycle Pattern = 00Hex to FFHex Erase Time = 20 ms Program Time = 100 µs

IDD at other MCLKIN frequencies is typically given by:

Normal Mode (VDD = 5 V): IDD = (1.6 nAs × MCLKIN) + 6 mA Normal Mode (VDD = 3 V): IDD = (0.8 nAs × MCLKIN) + 3 mA Idle Mode (VDD = 5 V): IDD = (0.75 nAs × MCLKIN) + 6 mA Idle Mode (VDD = 3 V): IDD = (0.25 nAs × MCLKIN) + 3 mA Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.

IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.

IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.

Analog IDD = 2 mA (typ) in normal operation (internal V

EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.

Typical specifications are not production tested, but are supported by characterization data at initial product release.

Specifications subject to change without notice. Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.

REF

range

, ADC and DAC peripherals powered on).

REF

= 80 µA

SOURCE

= 2.7 V to 3.3 V

= 20 µA

SOURCE

= 1.6 mA

SINK

= 1.6 mA

SINK

= 8 mA

SINK

= 8 mA

SINK

REV. B

–5–

ADuC812

52 51 50 49 48 43 42 41 4047 46 45 44

14 15 16 17 18 19 20 21 22 23 24 25 26

PIN 1 IDENTIFIER

TOP VIEW

(Not to Scale)

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

DGND

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

P1.0/ADC0/T2

P1.1/ADC1/T2EX

P1.2/ADC2

P1.3/ADC3

AGND

REF

DAC0 DAC1

P1.4/ADC4

P1.5/ADC5/SS

P1.6/ADC6

P2.7/A15/A23 P2.6/A14/A22

P2.5/A13/A21

P2.4/A12/A20

DGND

XTAL2

XTAL1

P2.3/A11/A19

P2.2/A10/A18

P2.1/A9/A17

P2.0/A8/A16

SDATA/MOSI

P1.7/ADC7

RESET

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1/MISO

DGND

P3.4/T0

P3.5/T1/CONVST

P3.7/RD

SCLOCK

P3.6/WR

ADuC812

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to DGND . . . . . –0.3 V, DV

Digital Output Voltage to DGND . . . . –0.3 V, DV

to AGND . . . . . . . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V

REF

Analog Inputs to AGND . . . . . . . . . . . –0.3 V, AV

+ 0.3 V

Operating Temperature Range Industrial (B Version)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADuC812BS –40°C to +85°C 52-Lead Plastic Quad Flatpack S-52 Eval-ADuC812QS QuickStart Development System

PIN CONFIGURATION

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–6–

REV. B

ADuC812

PIN FUNCTION DESCRIPTIONS

Mnemonic Type Function

REF

AGND G Analog Ground. Ground Reference point for the analog circuitry. P1.0–P1.7 I Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure

ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR. T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to

T2EX I Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for

SS I Slave Select Input for the SPI Interface SDATA I/O User Selectable, I SCLOCK I/O Serial Clock Pin for I MOSI I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface MISO I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface DAC0 O Voltage Output from DAC0 DAC1 O Voltage Output from DAC1 RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the

P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

RxD I/O Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port TxD O Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port

INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two

INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two

T0 I Timer/Counter 0 Input T1 I Timer/Counter 1 Input

CONVST I Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled.

WR O Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory. RD O Read Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2 O Output of the Inverting Oscillator Amplifier XTAL1 I Input to the inverting oscillator amplifier and input to the internal clock generator circuits. DGND G Digital Ground. Ground reference point for the digital circuitry. P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15) pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2 (A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits

P Digital Positive Supply Voltage, 3 V or 5 V Nominal P Analog Positive Supply Voltage, 3 V or 5 V Nominal I Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND. I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference.

any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share the following functionality.

a 1 to 0 transition of the T2 input.

Counter 2.

C-Compatible or SPI Data Input/Output Pin

C-Compatible or SPI Serial Interface Clock

device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described in the Power-On Reset Operation section of this data sheet.

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also contain various secondary functions which are described below.

priority levels. This pin can also be used as a gate control input to Timer 0.

priority levels. This pin can also be used as a gate control input to Timer 1.

A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.

the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

REV. B

–7–

ADuC812

PIN FUNCTION DESCRIPTION (continued)

Mnemonic Type Function

PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program

memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET.

ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit

address space accesses) of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access.

EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from

internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch all instructions from external program memory.

P0.7–P0.0 I/O Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float and in (A0–A7) that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data

bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s.

TERMINOLOGY

ADC SPECIFICATIONS Integral Nonlinearity

This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Full-Scale Error

This is the deviation of the last code transition from the ideal AIN voltage (Full Scale – 1.5 LSB) after the offset error has been adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise +distortion) ratio for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental.

DAC SPECIFICATIONS Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV sec.

–8–

REV. B

ADuC812

128-BYTE

SPECIAL FUNCTION REGISTER

AREA

8K BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051

COMPATIBLE

CORE

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

2  12-BIT DACs

SERIAL I/O

PARALLEL I/O

WDT PSM

AUTO-CALIBRATING

8-CHANNEL

HIGH SPEED

12-BIT ADC

640-BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

ARCHITECTURE, MAIN FEATURES

The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- performance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory controlling a multichannel (8-input channels), 12-bit ADC.

The chip incorporates all secondary functions to fully support the programmable data acquisition core. These secondary functions include User Flash Memory, Watchdog Timer (WDT), Power Supply Monitor (PSM) and various industrystandard parallel and serial interfaces.

PROGRAM MEMORY SPACE

READ ONLY

FFFFH

EXTERNAL PROGRAM

MEMORY

SPACE

2000H

9FH

00H

(PAGE 159)

640 BYTES

FLASH/EE DATA

MEMORY

ACCESSED

INDIRECTLY

VIA SFR

CONTROL REGISTERS

(PAGE 0)

EA = 1

INTERNAL

8K BYTE FLASH/EE PROGRAM

MEMORY

1FFFH

0000H

DATA MEMORY SPACE

READ/WRITE

EA = 0 EXTERNAL PROGRAM

MEMORY

SPACE

FFFFFFH

7FH

2FH

BANKS

SELECTED

VIA

BITS IN PSW

20H

18H

10H

08H

00H

BIT-ADDRESSABLE SPACE (BIT ADDRESSES 0FH–7FH)

1FH

17H

4 BANKS OF 8 REGISTERS

0FH

07H

RESET VALUE OF STACK POINTER

R0–R7

Figure 2. Lower 128 Bytes of Internal RAM

MEMORY ORGANIZATION

As with all 8052-compatible devices, the ADuC812 has separate address spaces for Program and Data memory as shown in Figure 1. Also as shown in Figure 1, an additional 640 Bytes of User Data Flash EEPROM are available to the user. The User Data Flash Memory area is accessed indirectly via a group of control registers mapped in the Special Function Register (SFR) area in the Data Memory Space.

The SFR space is mapped in the upper 128 bytes of internal data memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC812 via the SFR area is shown in Figure 3.

The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next

bit addressable memory space at bit addresses 00H through 7FH.

16 bytes (128 bits) above the register banks form a block of

REV. B

INTERNAL

DATA MEMORY

SPACE

FFH

ACCESSIBLE

80H 7FH

00H

INDIRECT

ADDRESSING

ONLY

ACCESSIBLE

DIRECT

AND

INDIRECT

ADDRESSING

UPPER

128

LOWER

128

Figure 1. Program and Data Memory Maps

SPECIAL

FUNCTION

REGISTERS

ACCESSIBLE

BY DIRECT

ADDRESSING

ONLY

FFH

80H

000000H

EXTERNAL

DATA

MEMORY

SPACE (24-BIT

ADDRESS

SPACE)

Figure 3. Programming Model

–9–

ADuC812

OVERVIEW OF MCU-RELATED SFRs Accumulator SFR

ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A.

B SFR

The B register is used with the ACC for multiplication and division operations. For other instructions it can be treated as a general-purpose scratchpad register.

Stack Pointer SFR

The SP register is the stack pointer and is used to hold an internal RAM address that is called the “top of the stack.” The SP register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP register is initialized to 07H after a reset. This causes the stack to begin at location 08H.

Data Pointer

The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL).

Program Status Word SFR

The PSW register is the Program Status Word which contains several bits reflecting the current status of the CPU as detailed in Table I.

SFR Address D0H Power ON Default Value 00H Bit Addressable Yes

Power Control SFR

The Power Control (PCON) register contains bits for powersaving options and general-purpose status flags as shown in Table II.

SFR Address 87H Power ON Default Value 00H Bit Addressable No

DOMSDPIRESDPOTNIFFOELA1FG0FGDPLDI

Table II. PCON SFR Bit Designations

Bit Name Description

7 SMOD Double UART Baud Rate 6 ——— Reserved 5 ——— Reserved 4 ALEOFF Disable ALE Output 3 GF1 General-Purpose Flag Bit 2 GF0 General-Purpose Flag Bit 1 PD Power-Down Mode Enable 0 IDL Idle Mode Enable

YCCA0F1SR0SRVO1FP

Table I. PSW SFR Bit Designations

Bit Name Description

7 CY Carry Flag 6 AC Auxiliary Carry Flag 5 F0 General-Purpose Flag 4 RS1 Register Bank Select Bits 3 RS0 RS1 RS0 Selected Bank

000 011 102

113 2 OV Overflow Flag 1 F1 General-Purpose Flag 0 P Parity Bit

–10–

REV. B

ADuC812

SPECIAL FUNCTION REGISTERS

All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other onchip peripherals.

Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figure below (NOT USED). Unoccupied locations in the SFR address space are not implemented i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on chip testing are shown lighter shaded below (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted

'1'

in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H.

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

SPR1

FFH 0

FEH 0

FDH 0

FCH 0

FBH 0

FAH

F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H F1H 0 F0H 0

MDO

MDE

MCO

MDI

EFH 0

EEH 0

EDH 0

E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H E1H 0 E0H 0

ADCI

DMA

DEH 0

EXF2

CEH 0

PRE1

C6H 0

PADC

BEH 0

CCONV

DDH 0

RCLK

CDH 0

PRE0

C5H 0 C4H 0

PT2

BDH 0PSBCH 0

DFH 0

D7H 0ACD6H 0F0D5H 0

TF2

CFH 0

PRE2

C7H 0

PSI

BFH 0

B7H 1WRB6H 1T1B5H 1T0B4H 1

EADC

AEH

SM1

9EH 0

TR1

8EH 0

ET2

ADHESACH 0

SM2

9DH 0

TF0

8DH 0

AFH

000

A7H A6H A5H 1 A4H 1 A3H 1 A2H A1H 1 A0H 1

SM0

9FH 0

97H 1 96H 1 95H 1 94H 1 93H 1 92H

TF1

8FH 0

87H 1 86H 1 85H 1 84H 1 83H 1 82H 81H 1 80H 1

I2CM

ECH 0

EBH 0

SCONV

DCH 0

D4H 0

CCH 0

CS3

DBH 0

RS1

RS0

D3H 0OVD2HFID1H 0PD0H 0

TCLK

EXEN2

CBH 0

WDR1

C3H 0

PT1

BBH 0

INT1

B3H 1

ET1

ABH 0

REN

TR0

TB8

9BH 0

IE1

8BH 0

9CH 0

8CH 0

I2CRS

EAH

CS2

DAH

TR2

CAH

WDR2

C2H

PX1

BAH

INT0

B2H

EX1

AAH

RB8

9AHTI99H 0RI98H 0

IT1

8AH

SPR0

F9H 0

F8H 0

I2CTX

I2CI

E9H 0

E8H 0

CS1

CS0

D9H 0

D8H 0

CNT2

CAP2

C9H 0

C8H 0

WDS

WDE

C1H 0

C0H 0

PT0

PX0

B9H 0

B8H 0

TxD

RxD

B1H 1

B0H 1

ET0

EX0

A9H 0

A8H 0

T2EX

91H 1T290H 1

IE0

89H 0

IT0

88H 0

BITS

SPICON

F8H 00H

F0H 00H

I2CCON

E8H 00H

ACC

E0H 00H

ADCCON2

D8H 00H

PSW

D0H 00H

T2CON

C8H 00H

WDCON

C0H 00H

B8H 00H

B0H FFH

A8H 00H

A0H FFH

SCON

98H 00H

90H FFH

TCON

88H 00H

80H FFHSP81H 07H

1, 2

F9H 00H

ADCOFSL

F1H 00H

ADCDATAL

D9H 00H

RESERVED

B9H 00H

A9H 00H

99H 00H

89H 00H

DAC0L

ECON

IE2

SBUF

TMOD

DAC0H

FAH 00H

ADCOFSH

F2H 20H

ADCDATAH

DAH 00H

DMAL

D2H 00H

RCAP2L

CAH 00H

ETIM1

BAH 52H

I2CDAT

9AH 00H

TL0

8AH 00H

DPL

82H 00H

DAC1L

FBH 00H

ADCGAINL

F3H 00H

DMAH

D3H 00H

RCAP2H

CBH 00H

NOT USEDNOT USEDNOT USED

ETIM2

BBH 04H

I2CADD

9BH 55H

TL1

8BH 00H

DPH

83H 00H

DAC1H

FCH 00H

ADCGAINH

F4H 00H

DMAP

D4H 00H

TL2

CCH 00H

ETIM3

C4H C9H

EDATA1

BCH 00H

TH0

8CH 00H

DPP

84H 00H

DACCON

FDH 04H

ADCCON3

F5H 00H

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVED

TH2

CDH 00H

EDATA2

BDH 00H

NOT USEDNOT USEDNOT USEDNOT USED

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

NOT USEDNOT USED

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

TH1

8DH 00H

RESERVED NOT USED

RESERVED

EDARL

C6H 00H

EDATA3

BEH 00H

NOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USED

NOT USED

RESERVEDRESERVED

SPIDAT

F7H 00H

ADCCON1

EFH 20H

RESERVED

PSMCON

DFH DEH

RESERVEDRESERVEDRESERVED

RESERVED

RESERVEDRESERVED

EDATA4

BFH 00H

NOT USED

PCON

87H 00H

SFR MAP KEY:

MNEMONIC

SFR ADDRESS

DEFAULT VALUE

SFR NOTES:

SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.

THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE

PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT.

CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.

THESE BITS ARE CONTAINED IN THIS BYTE.

IE0

89H 0

IT0

88H 0

TCON

88H 00H

MNEMONIC

DEFAULT VALUE

SFR ADDRESS

Figure 4. Special Function Register Locations and Reset Values

REV. B

–11–

ADuC812

ADC CIRCUIT INFORMATION General Overview

The ADC conversion block incorporates a fast, 8-channel, 12-bit, single supply A/D converter. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features and A/D converter. All components in this block are easily configured via a 3-register SFR interface.

The A/D converter consists of a conventional successiveapproximation converter based around a capacitor DAC. The converter accepts an analog input range of 0 to +V

REF

. A high precision, low drift and factory calibrated 2.5 V reference is provided on-chip. The internal reference may be overdriven via the external V range 2.3 V to AV

pin. This external reference can be in the

REF

Single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to the an external pin. Timer 2 can also be configured to generate a repetitive trigger for ADC conversions. The ADC may be configured to operate in a DMA Mode whereby the ADC block continuously converts and captures samples to an external RAM space without any interaction from the MCU core. This automatic capture facility can extend through a 16 MByte external Data Memory space.

The ADuC812 is shipped with factory programmed calibration coefficients which are automatically downloaded to the ADC on power-up ensuring optimum ADC performance. The ADC core contains internal Offset and Gain calibration registers. A software calibration routine is provided to allow the user to overwrite the factory programmed calibration coefficients if required, thus minimizing the impact of endpoint errors in the user’s target system.

A voltage output from an On-Chip bandgap reference proportional to absolute temperature can also be routed through the front end ADC multiplexor (effectively a 9th ADC channel input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to V

. For this

REF

range, the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when

= 2.5 V. The ideal input/output transfer characteristic for

REF

the 0 to V

range is shown in Figure 5.

REF

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000 1LSB

1LSB =

4096

VOLTAGE INPUT

+FS –1LSB

Figure 5. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1-3 SFRs (shown on the following page) the ADC will convert the analog input and provide an ADC 12-bit result word in the ADCDATAH/L SFRs. The top 4 bits of the ADCDATAH SFR will be written with the channel selection bits so as to identify the channel result. The format of the ADC 12 bit result word is shown in Figure 6.

ADCDATAH SFR

CH–ID

TOP 4 BITS

HIGH 4 BITS OF ADC RESULT WORD

ADCDATAL SFR

–12–

LOW 8 BITS OF THE ADC RESULT WORD

Figure 6. ADC Result Format

REV. B

ADuC812

ADCCON1 – (ADC Control SFR #1)

The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below.

SFR Address: EFH SFR Power-On Default Value: 20H

1DM0DM1KC0KC1QA0QAC2TCXE

Table III. ADCCON1 SFR Bit Designations

Bit Name Description

ADCCON1.7 MD1 The mode bits (MD1, MD0) select the active operating mode of the ADC ADCCON1.6 MD0 as follows:

MD1 MD0 Active Mode

0 0 ADC powered down. 0 1 ADC normal mode 1 0 ADC powered down if not executing a conversion cycle. 1 1 ADC standby if not executing a conversion cycle. Note: In powered down mode the ADC V ADC peripherals are powered down thus minimizing current consumption.

ADCCON1.5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the ADCCON1.4 CK0 ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected

as follows:

CK1 CK0 MCLK Divider

001 012 104 118

circuits are maintained on, whereas in power-down mode all

REF

ADCCON1.3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track/hold amplifier ADCCON1.2 AQ0 to acquire the input signal and are selected as follows:

AQ1 AQ0 #ADC Clks

001 012 104 118

ADCCON1.1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 over flow bit be used as

the ADC convert start trigger input.

ADCCON1.0 EXC The external trigger enable bit (EXC) is set by the user to allow the external Pin 23 (CONVST) to be

used as the active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the required sample rate.

REV. B

–13–

ADuC812

ADCCON2 – (ADC Control SFR #2)

The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.

SFR Address: D8H SFR Power On Default Value: 00H

ICDAAMDVNOCCVNOCS3SC2SC1SC0SC

Table IV. ADCCON2 SFR Bit Designations

ocation Name Description

ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the

end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt Service Routine.

ADCCON2.6 DMA The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-

tion. A more detailed description of this mode is given in the ADC DMA Mode section.

ADCCON2.5 CCONV The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of

conversion. In this mode the ADC starts converting based on the timing and channel configuration already set up in the ADCCON SFRs, the ADC automatically starts another conversion once a previous conversion has completed.

ADCCON2.4 SCONV The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is

automatically reset to “0” on completion of the single conversion cycle.

ADCCON2.3 CS3 The channel selection bits (CS3-0) allow the user to program the ADC channel selection under ADCCON2.2 CS2 software control. When a conversion is initiated the channel converted will be that pointed to by ADCCON2.1 CS1 these channel selection bits. In DMA mode the channel selection is derived from the channel ID ADCCON2.0 CS0 written to the external memory.

CS3 CS2 CS1 CS0 CH#

00000 00011 00102 00113 01004 01015 01106 01117 1000Temp Sensor 1111DMA STOP All other combinations reserved

ADCCON3 – (ADC Control SFR #3)

The ADCCON3 register gives user software an indication of ADC busy status.

SFR Address: F5H SFR Power On Default Value: 00H

YSUBDVSRDVSRDVSRDVSRDVSRDVSRDVSR

Table V. ADCCON3 SFR Bit Designations

Bit Bit Location Status Description

ADCCON3.7 BUSY The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or

calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.

ADCCON3.6 RSVD ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as zero and should only ADCCON3.5 RSVD be written as zero by user software. ADCCON3.4 RSVD ADCCON3.3 RSVD ADCCON3.2 RSVD ADCCON3.1 RSVD ADCCON3.0 RSVD

–14–

REV. B

ADuC812

Driving the A/D Converter

The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position) a charge proportional to the voltage on the analog input is developed across the input sampling capacitor. During the conversion phase (with both switches in the “hold” position) the capacitor DAC is adjusted via internal SAR logic until the voltage on node A is zero indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor DAC. The digital value finally contained in the SAR is then latched out as the result of the ADC conversion. Control of the SAR, and timing of acquisition and sampling modes, is handled automatically by built-in ADC control logic. Acquisition and conversion times are also fully configurable under user control.

AIN0

AIN7

AGND

200

TRACK

HOLD

TEMPERATURE

SENSOR

SW1

2pF

NODE A

SW2

HOLDTRACK

ADuC812

CAPACITOR

DAC

COMPARATOR

Figure 7. Internal ADC Structure

Note that whenever a new input channel is selected, a residual charge from the 2 pF sampling capacitor places a transient on the newly selected input. The signal source must be capable of recovering from this transient before the sampling switches click into “hold” mode. Delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. One hardware solution would be to choose a very fast settling op amp to drive each analog input. Such an op amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. A better solution, recommended for use with any amplifier, is shown in Figure 8.

Though at first glance the circuit in Figure 8 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the Nyquist frequency, even at a 200 kHz sample rate. Though the R/C does helps to reject some incoming high-frequency noise, its primary function is to ensure that the transient demands of the ADC input stage are met. It

ADuC812

51

0.01F

AIN0

Figure 8. Buffering Analog Inputs

does so by providing a capacitive bank from which the 2 pF sampling capacitor can draw its charge. Since the 0.01 µF capacitor in Figure 8 is more than 4096 times the size of the 2 pF sampling capacitor, its voltage will not change by more than one count (1/4096) of the 12-bit transfer function when the 2 pF charge from a previous channel is dumped onto it. A larger capacitor can be used if desired, but not a larger resistor (for reasons described below).

The Schottky diodes in Figure 8 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. They are not necessary if the op amp is powered from the same supply as the ADuC812 since in that case the op amp is unable to generate voltages above

or below ground. An op amp of some kind is necessary

unless the signal source is very low impedance to begin with. DC leakage currents at the ADuC812’s analog inputs can cause measurable dc errors with external source impedances as little as 100 Ω or so. To ensure accurate ADC operation, keep the total source impedance at each analog input less than 61 Ω. The table below illustrates examples of how source impedance can affect dc accuracy.

Source Error from 1 µA Error from 10 µA Impedance Leakage Current Leakage Current 61 Ω 61 µV = 0.1 LSB 610 µV = 1 LSB 610 Ω 610 µV = 1 LSB 6.1 mV = 10 LSB

Although Figure 8 shows the op amp operating at a gain of 1, you can of course configure it for any gain needed. Also, you can just as easily use an instrumentation amplifier in its place to condition differential signals. Use any modern amplifier that is capable of delivering the signal (0 to V

) with minimal satura-

REF

tion. Some single-supply rail-to-rail op amps that are useful for this purpose include, but are certainly not limited to, the ones given in Table VI. Check Analog Devices literature (CD ROM data book, etc.) for details on these and other op amps and instrumentation amps.

Table VI. Some Single-Supply Op Amps

Op Amp Model Characteristics

OP181/OP281/OP481 Micropower OP191/OP291/OP491 I/O Good up to VDD, Low Cost OP196/OP296/OP496 I/O to V

, Micropower, Low Cost

OP183/OP283 High Gain-Bandwidth Product OP162/OP262/OP462 High GBP, Micro Package AD820/AD822/AD824 FET Input, Low Cost AD823 FET Input, High GBP

Keep in mind that the ADC’s transfer function is 0 to V

REF

, and any signal range lost to amplifier saturation near ground will impact dynamic range. Though the op amps in Table VI are capable of delivering output signals very closely approaching

REV. B

–15–

ADuC812

ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front-end amplifiers. If you do, however, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 8 to drive the analog input pins of the ADuC812.

Voltage Reference Connections

The on-chip 2.5 V bandgap voltage reference can be used as the reference source for the ADC and DACs. In order to ensure the accuracy of the voltage reference you must decouple both the V

pin and the C

REF

pin to ground with 0.1 µF ceramic

REF

chip capacitors as shown in Figure 9.

ADuC812

BUFFER

0.1F

REF

51

BUFFER

Figure 9. Decoupling V

2.5V

BANDGAP

REFERENCE

and C

REF

The internal voltage reference can also be tapped directly from the V

pin, if desired, to drive external circuitry. However, a

REF

buffer must be used in this case to ensure that no current is drawn from the V

pin itself. The voltage on the C

REF

pin is that of an internal node within the buffer block, and its voltage is critical to ADC and DAC accuracy. Do not connect anything to this pin except the capacitor, and be sure to keep tracelengths short on the C

capacitor, decoupling the node

REF

straight to the underlying ground plane.

The ADuC812 powers up with its internal voltage reference in the “off” state. The voltage reference turns on automatically whenever the ADC or either DAC gets enabled in software. Once enabled, the voltage reference requires approximately 65 ms to power up and settle to its specified value. Be sure that your software allows this time to elapse before initiating any conversions. If an external voltage reference is preferred, simply connect it to the V

pin as shown in Figure 10 to overdrive

REF

the internal reference.

To ensure accurate ADC operation, the voltage applied to V

REF

must be between 2.3 V and AVDD. In situations where analog input signals are proportional to the power supply (such as some strain-gage applications) it can be desirable to connect the V

REF

pin directly to AVDD. In such a configuration you must also connect the C

pin directly to AVDD to circumvent internal

REF

buffer headroom limitations. This allows the ADC input transfer function to accurately span the full range 0 to AV

Operation of the ADC or DACs with a reference voltage below

2.3 V, however, may incur loss of accuracy eventually resulting in missing codes or nonmonotonicity. For that reason, do not use a reference voltage less than 2.3 V.

ADuC812

EXTERNAL

VOLTAGE

REFERENCE

0.1F

51

REF

BUFFER

2.5V

BANDGAP

REFERENCE

Figure 10. Using an External Voltage Reference

Configuring the ADC

The three SFRs (ADCCON1, ADCCON2, ADCCON3) configure the ADC. In nearly all cases, an acquisition time of 1 ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide plenty of time for the ADuC812 to acquire its signal before switching the internal track and hold amplifier in to hold mode. The only exception would be a high source impedance analog input, but these should be buffered first anyway since source impedances of greater than 610 Ω can cause dc errors as well.

The ADuC812’s successive approximation ADC is driven by a divided down version of the master clock. To ensure adequate ADC operation, this ADC clock must be between 400 kHz and 4 MHz, and optimum performance is obtained with ADC clock between 400 kHz and 3 MHz. Frequencies within this range can easily be achieved with master clock frequencies from 400 kHz to well above 16 MHz with the four ADC clock divide ratios to choose from. For example, with a 12 MHz master clock, set the ADC clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1, ADCCON1.4 = 0).

The total ADC conversion time is 15 ADC clocks, plus 1 ADC clock for synchronization, plus the selected acquisition time (1, 2, 3, or 4 ADC clocks). For the example above, with a 1 clock acquisition time, total conversion time is 17 ADC clocks (or

5.67 µs for a 3 MHz ADC clock).

In continuous conversion mode, a new conversion begins each time the previous one finishes. The sample rate is then simply the inverse of the total conversion time described above. In the example above, the continuous conversion mode sample rate would be 176.5 kHz.

ADC DMA Mode

The on-chip ADC has been designed to run at a maximum conversion speed of 5 µs (200 kHz sampling rate). When con- verting at this rate the ADuC812 micro has 5 µs to read the ADC result and store the result in memory for further post processing all within 5 µs otherwise the next ADC sample could be lost. In an interrupt driven routine the micro would also have to jump to the ADC Interrupt Service routine which will also increase the time required to store the ADC results. In applications where the ADuC812 cannot sustain the interrupt rate, an ADC DMA mode is provided.

To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set. This allows the ADC results to be written directly to a 16 MByte external static memory SRAM (mapped into data memory space) without any interaction from the ADuC812

–16–

REV. B

ADuC812

core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz).

A typical DMA Mode configuration example.

To set the ADuC812 into DMA mode a number of steps must be followed.

1. The ADC must be powered down. This is done by ensuring MD1 and MD0 are both set to 0 in ADCCON1.

2. The DMA Address pointer must be set to the start address of where the ADC Results are to be written. This is done by writing to the DMA mode Address Pointers DMAL, DMAH, and DMAP. DMAL must be written to first, followed by DMAH and then by DMAP.

3. The external memory must be preconfigured. This consists of writing the required ADC channel IDs into the top four bits of every second memory location in the external SRAM starting at the first address specified by the DMA address pointer. As the ADC DMA mode operates independent from the ADuC812 core it is necessary to provide it with a stop command. This is done by duplicating the last channel ID to be converted followed by “1111” into the next channel selection field. A typical preconfiguration of external memory is as follows.

00000AH

000000H

1111

0011

1000

0101

0010

STOP COMMAND

REPEAT LAST CHANNEL FOR A VALID STOP CONDITION

CONVERT ADC CH#3

CONVERT TEMP SENSOR

CONVERT ADC CH#5

CONVERT ADC CH#2

Figure 11. Typical DMA External Memory Preconfiguration

4. The DMA is initiated by writing to the ADC SFRs in the following sequence.

a. ADCCON2 is written to enable the DMA mode. i.e.,

MOV ADCCON2, #40H; DMA Mode enabled

b. ADCCON1 is written to configure the conversion time

and power up of the ADC. It can also enable Timer 2 driven conversions or External Triggered conversions if required.

c. ADC conversions are initiated. This is done by starting

single/continuous conversions, starting Timer 2 running f

or Timer 2 conversions or by receiving an external trigger.

When the DMA conversions are completed, the ADC interrupt bit ADCI is set by hardware and the external SRAM contains the new ADC conversion results as shown below. It should be noted that no result is written to the last two memory locations.

When the DMA mode logic is active it takes the responsibility of storing the ADC results away from both the user and ADuC812 core logic. As it writes the results of the ADC conversions to external memory, it takes over the external memory interface from the core. Thus, any core instructions which access the external memory while DMA mode is enabled will not get access to it. The core will execute the instructions and they will take the same time to execute but they will not gain access to the external memory.

REV. B

–17–

00000AH

000000H

1111

0011

1000

0101

0010

STOP COMMAND

NO CONVERSION RESULT WRITTEN HERE

CONVERSION RESULT FOR ADC CH#3

CONVERSION RESULT FOR TEMP SENSOR

CONVERSION RESULT FOR ADC CH#5

CONVERSION RESULT FOR ADC CH#2

Figure 12. Typical External Memory Configuration Post ADC DMA Operation

The DMA logic operates from the ADC clock and uses pipe-lining to perform the ADC conversions and access the external memory at the same time. The time it takes to perform one ADC conversion is called a DMA cycle. The actions performed by the logic during a typical DMA cycle are shown in the following diagram.

CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE

WRITE ADC RESULT

CONVERTED DURING

PREVIOUS DMA CYCLE

DMA CYCLE

READ CHANNEL ID

TO BE CONVERTED DURING

NEXT DMA CYCLE

Figure 13. DMA Cycle

From the previous diagram, it can bee seen that during one DMA cycle the following actions are performed by the DMA logic.

1. An ADC conversion is performed on the channel whose ID was read during the previous cycle.

2. The 12-bit result and the channel ID of the conversion performed in the previous cycle is written to the external memory.

3. The ID of the next channel to be converted is read from external memory.

For the previous example the complete flow of events is shown in Figure 13. Because the DMA logic uses pipe-lining, it takes three cycles before the first correct result is written out.

Micro Operation during ADC DMA Mode

During ADC DMA mode the MicroConverter core is free to continue code execution, including general housekeeping and communication tasks. However, it should be noted that MCU core accesses to Ports 0 and 2 (which of course are being used by the DMA controller) are gated “OFF” during ADC DMA mode of operation. This means that even though the instruction that accesses the external Ports 0 or 2 will appear to execute, no data will be seen at these external Ports as a result.

The MicroConverter core can be configured with an interrupt to be triggered by the DMA controller when it had finished filling the requested block of RAM with ADC results, allowing the service routine for this interrupt to post process data without any real-time timing constraints.

The Offset and Gain Calibration Coefficients

The ADuC812 has two ADC calibration coefficients, one for offset calibration and one for gain calibration. Both the offset and gain calibration coefficients are 14-bit words, located in the Special Function Register (SFR) area. The offset calibration coefficient is divided into ADCOFSH (6 bits) and ADCOFSL (8 bits) and

ADuC812

the gain calibration coefficient is divided into ADCGAINH (6 bits) and ADCGAINL (8 bits).The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal.

Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC Transfer Function DOWN. Decreasing the offset coefficient compensates for negative offset, and effectively pushes the ADC Transfer Function UP. The maximum offset that can be compensated is typically ±5% of V

, which equates to typically ±125 mV with a 2.5 V reference.

REF

Similarly, the gain calibration coefficient compensates for dc gain errors in both the ADC and the input signal.

Increasing the gain coefficient compensates for a smaller analog input signal range and scales the ADC Transfer Function UP, effectively increasing the slope of the transfer function. Decreasing the gain coefficient, compensates for a larger analog input signal range and scales the ADC Transfer Function DOWN, effectively decreasing the slope of the transfer function. The maximum analog input signal range for which the gain coefficient can compensate is 1.025 × V range is 0.975 × V

which equates to typically ±2.5% of the

REF

and the minimum input

REF

reference voltage.

Calibration

Each ADuC812 is calibrated in the factory prior to shipping and the offset and gain calibration coefficients are stored in a hidden area of FLASH/EE memory. Each time the ADuC812 powers up, an internal power-on configuration routine, copies these coefficients into the offset and gain calibration registers in the SFR area.

The MicroConverter ADC accuracy may vary from system to system due to board layout, grounding, clock speed, etc. To get the best ADC accuracy in your system, you should perform the software calibration routine described in the technical note uC005 available from the MicroConverter home page (www.analog.com/microconverter).

NONVOLATILE FLASH MEMORY Flash Memory Overview

The ADuC812 incorporates Flash memory technology on-chip to provide the user with a nonvolatile, in-circuit reprogrammable, code and data memory space.

Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture.

This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and combines them with the space efficient/density features of EPROM (see Figure 14).

Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be implemented to achieve the space efficiencies or memory densities required by a given design.

Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer towards the ideal memory device that includes nonvolatility, in-circuit programmability, high density and low cost. Incorporated in the ADuC812, Flash/EE memory technology allows the user to

–18–

EPROM

TECHNOLOGY

SPACE EFFICIENT/

DENSITY

FLASH/EE MEMORY

TECHNOLOGY

EEPROM

TECHNOLOGY

IN-CIRCUIT

REPROGRAMMABLE

Figure 14. Flash Memory Development

update program code space in-circuit without the need to replace one-time programmable (OTP) devices at remote operating nodes.

Flash/EE Memory and the ADuC812

The ADuC812 provides two arrays of Flash/EE memory for user applications. 8K bytes of Flash/EE Program space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed using conventional third party memory programmers. This array can also be programmed in-circuit, using the serial download mode provided.

A 640-Byte Flash/EE Data Memory space is also provided on-chip. This may be used by the user as a general purpose nonvolatile scratchpad area. User access to this area is via a group of six SFRs.

ADuC812 Flash/EE Memory Reliability

The Flash/EE Program and Data Memory arrays on the ADuC812 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as:

a. Initial Page Erase Sequence b. Read/Verify Sequence A single Flash/EE c. Byte Program Sequence Memory d. Second Read/Verify Sequence Endurance Cycle

In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00 hex to FFhex until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory.

As indicated in the specification pages of this data sheet, the ADuC812 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, and +85°C. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles, with an endurance figure of 50,000 cycles being typical of operation at 25°C.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC812 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (T

= 55°C). As part of this qualification procedure, the Flash/EE

memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed.

REV. B

ADuC812

Using the Flash/EE Program Memory

This 8K Byte Flash/EE Program Memory array is mapped into the lower 8K bytes of the 64K bytes program space addressable by the ADuC812 and will be used to hold user code in typical applications.

The program memory array can be programmed in one of two modes, namely:

Serial Downloading (In-Circuit Programming)

As part of its embedded download/debug kernel, the ADuC812 facilitates serial code download via the standard UART serial port. Serial download mode is automatically entered on power-up if the external pin, PSEN, is pulled low through an external resistor as shown in Figure 15. Once in this mode, the user can download code to the program memory array while the device is sited in its target application hardware. A PC serial download executable is provided as part of the ADuC812 QuickStart development system.

The Serial Download protocol is detailed in a MicroConverter Applications Note uC004 available from the ADI MicroConverter Website at www.analog.com/micronverter.

PULL PSEN LOW DURING RESET TO CONFIGURE THE ADuC812 FOR

ADuC812

PSEN

1k

SERIAL DOWNLOAD MODE

sing the Flash/EE Data Memory

The user Flash/EE data memory array consists of 640 bytes that are configured into 160 (Page 00H to Page 9FH), 4-byte pages as shown in Figure 16.

BYTE 1 BYTE 2 BYTE 3 BYTE 4

9FH

BYTE 1 BYTE 2 BYTE 3 BYTE 4

00H

Figure 16. User Flash/EE Memory Configuration

As with other ADuC812 user-peripherals circuits, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1-4) are used to hold the 4-byte page being accessed. EADRL is used to hold the 8-bit address of the page being accessed. Finally, ECON is an 8-bit control register that may be written with one of five Flash/EE memory access commands to trigger various read, write, erase and verify functions. These register can be summarized as follows:

ECON: SFR Address: B9H

Function: Controls access to 640 Bytes

Flash/EE Data Space.

Default: 00H

EADRL: SFR Address: C6H

Function: Holds the Flash/EE Data

Page Address. 0 through 9F Hex

Default: 00H

EDATA 1–4:

SFR Address: BCH to BFH respectively Function: Holds Flash/EE Data

memory page write or page read data bytes.

Default : EDATA1–4 –> 00H

A block diagram of the SFR registered interface to the Data Flash/EE Memory array is shown in Figure 17.

Figure 15. Flash/EE Memory Serial Download Mode Programming

Parallel Programming

The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. In this mode Ports P0, P1 and P2 operate as the external data and address bus interface, ALE operates as the Write Enable strobe and Port P3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming.

The high voltage (12 V) supply required for Flash programming is generated using on-chip charge pumps to supply the high voltage program lines.

The complete parallel programming specification is available on the MicroConverter home page at www.analog.com/

microconverter.

REV. B

–19–

FUNCTION:

HOLDS THE 8-BIT PAGE ADDRESS POINTER

9FH

EADRL

00H

FUNCTION:

HOLDS COMMAND WORD

BYTE 2

BYTE 1

BYTE 1 BYTE 2 BYTE 3 BYTE 4

INTERPRETER LOGIC

BYTE 3

ECON COMMAND

ECON

FUNCTION: HOLDS THE 4-BYTE PAGE WORD

BYTE 4

EDATA1 (BYTE 1)

EDATA2 (BYTE 2)

EDATA3 (BYTE 3)

EDATA4 (BYTE 4)

FUNCTION: INTERPRETS THE FLASH

COMMAND WORD

Figure 17. User Flash/EE Memory Control and Configuration

ADuC812

ECON—Flash/EE Memory Control SFR

This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, program and erase cycles as detailed in Table VII:

Table VII. ECON–Flash/EE Memory Control Register Command Modes

Command Byte Command Mode

01H READ COMMAND

Results in four bytes being read into EDATA 1–4 from memory page address contained in EADRL.

02H PROGRAM COMMAND

Results in four bytes (EDATA 1–4) being written to memory page address in EADRL. This write command assumes the designated “write” page has been pre-erased.

03H RESERVED FOR INTERNAL USE

03H should not be written to the ECON SFR.

04H VERIFY COMMAND

Allows the user to verify if data in EDATA 1–4 is contained in page address designated by EADRL.

A subsequent read of the ECON SFR will result in a “zero” being read if the verification is valid, a nonzero value will be read to indicate an invalid verification.

05H ERASE COMMAND

Results in an erase of the 4-byte page designated in EADRL.

06H ERASE-ALL COMMAND

Results in erase of the full Flash/EE data memory 160-page (640 bytes) array.

07H to FFH RESERVED COMMANDS

Commands reserved for future use.

Flash/EE Memory Timing

The typical program/erase times for the Flash/EE Data Memory are:

Erase Full Array (640 Bytes) – 20 ms Erase Single Page (4 Bytes) – 20 ms Program Page (4 Bytes) – 250 µs Read Page (4 Bytes) – Within Single Instruction Cycle

Flash/EE erase and program timing is derived from the master clock. When using a master clock frequency of 11.0592 MHz it is not necessary to write to the ETIM registers at all. However, when operating at other master clock frequencies (f

CLK

), you must change the values of ETIM1 and ETIM2 to avoid degrading data Flash/EE endurance and retention. ETIM1 and ETIM2 form a 16-bit word, ETIM2 being the high byte and ETIM1 the low byte. The value of this 16-bit word must be set as follows to ensure optimum data Flash/EE endurance and retention.

ETIM2, ETIM1 = 100 µs × f

CLK

ETIM3 should always remain at its default value of 201 dec/C9 hex.

Using the Flash/EE Memory Interface

As with all Flash/EE memory architectures, the array can be programmed in system at a byte level, although it must be erased first, the erasure being performed in page blocks (4-byte pages in this case).

A typical access to the Flash/EE array will involve setting up the page address to be accessed in the EADRL SFR, configuring the EDATA1-4 with data to be programmed to the array (the EDATA SFRs will not be written for read accesses) and finally writing the ECON command word which initiates one of the six modes shown in Table VII. It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC812 is idled until the requested Program/Read or Erase mode is completed.

In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine cycle MOV instruction (to write to the ECON SFR), the next instruction will not be executed until the Flash/EE operation is complete (250 µs or 20 ms later). This means that the core will not respond to Interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like Counter/Timers continue to count and time as configured throughout

will

this pseudo-

idle period.

Erase-All

Although the 640-byte User Flash/EE array is shipped from the factory pre-erased, i.e., Byte locations set to FFH, it is nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADuC812. An “ERASE-ALL” command consists of writing “06H” to the ECON SFR, which initiates an erase of all 640 byte locations in the Flash/EE array. This command coded in 8051 assembly would appear as:

MOV ECON, #06H ; Erase all Command

; 20 ms Duration

Program a Byte

In general terms, a byte in the Flash/EE array can only be programmed if it has previously been erased. To be more specific, a byte can only be programmed if it already holds the value FFH. Because of the Flash/EE architecture, this erasure must happen at a page level; therefore, a minimum of four bytes (1 page) will be erased when an erase command is initiated. A more specific example of the Program-Byte process is shown below. In this example the user writes F3H into the second byte on Page 03H of the Flash/EE Data Memory space while preserving the other three bytes already in this page. As the user is only required to modify one of the page bytes, the full page must be first read so that this page can then be erased without the existing data being lost. This example, coded in 8051 assembly, would appear as:

MOV EADRL, #03H ; Set Page Address Pointer MOV ECON, #01H ; Read Page MOV EDATA2, #0F3H ; Write New Byte MOV ECON, #05H ; Erase Page MOV ECON, #02H ; Write Page (Program

Flash/EE)

–20–

REV. B

ADuC812

USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS

The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given.

DAC

The ADuC812 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to

(the internal bandgap 2.5 V reference) and 0 V to AVDD.

REF

EDOM1GNR0GNR1RLC0RLCCNYS1DP0DP

Table VIII. DACCON SFR Bit Designations

Each can operate in 12-bit or 8-bit mode. Both DACs share a control DAC0H/L.

It should be noted that in 12-bit asynchronous mode, the DAC voltage output will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as DACH first, followed by DACL.

DACCON DAC Control Register

SFR Address FDH Power-On Default Value 04H Bit Addressable No

Bit Name Description

7 MODE The DAC MODE bit sets the overriding operating mode for both DACs.

Set to “1” = 8-Bit Mode (Write 8 Bits to DACxL SFR). Set to “0”= 12-Bit Mode.

6 RNG1 DAC1 Range Select Bit.

Set to “1” = DAC1 Range 0–V Set to “0” = DAC1 Range 0–V

REF

5 RNG0 DAC0 Range Select Bit.

Set to “1” = DAC0 Range 0–V Set to “0” = DAC0 Range 0–V

DD.

REF.

4 CLR1 DAC1 Clear Bit.

Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal.

3 CLR0 DAC0 Clear Bit.

Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal.

2 SYNC DAC0/1 Update Synchronization Bit.

When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both DACs will then update simultaneously when the SYNC bit is set to “1.”

1 PD1 DAC1 Power-Down Bit.

Set to “1” = Power-On DAC1. Set to “0” = Power-Off DAC1.

0 PD0 DAC0 Power-Down Bit.

Set to “1” = Power-On DAC0. Set to “0” = Power-Off DAC0.

DACxH/L DAC Data Registers

Function DAC Data Registers, written by user to update the DAC output. SFR Address DAC0L (DAC0 Data Low Byte) –>F9H; DAC1L (DAC1 Data Low Byte)->FBH

DAC0H (DAC0 Data High Byte) –>FAH; DAC1H(DAC1 Data High Byte)->FCH Power-On Default Value 00H –>All four Registers Bit Addressable No –>All four Registers

The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits.

REV. B

–21–

FFF HEX000 HEX

– 50mV

– 100mV

100mV

50mV

0mV

ADuC812

Using the D/A Converter

The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.

REF

Figure 18. Resistor String DAC Functional Equivalent

As illustrated in Figure 18, the reference source for each DAC is user selectable in software. It can be either AV 0-to-AV

mode, the DAC output transfer function spans from

0 V to the voltage at the AV DAC output transfer function spans from 0 V to the internal V

or if an external reference is applied the voltage at the V

REF

pin. The DAC output buffer amplifier features a true rail-to-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both

and ground. Moreover, the DAC’s linearity specification

(when driving a 10 kΩ resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48, and, in 0-to-AV tion near ground and V

mode only, codes 3995 to 4095. Linearity degrada-

is caused by saturation of the output

amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 19. The dotted line in Figure 19 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 19 represents a transfer function in 0-to-V mode only. In 0-to-V

mode (with V

REF

nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end

in this case, not VDD), showing no signs of endpoint lin-

REF

earity errors.

ADuC812

OUTPUT BUFFER

HIGH-Z

DISABLE

(FROM MCU)

pin. In 0-to-V

REF

or V

mode, the

REF

< VDD) the lower

REF.

REF

Figure 19. Endpoint Nonlinearities Due to Amplifier Saturation

The endpoint nonlinearities conceptually illustrated in Figure 19 get worse as a function of output loading. Most of the ADuC812’s data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 19 become larger. With larger current demands, this can significantly limit output voltage swing. Figure 20 and Figure 21 illustrate this behavior. It should be noted that the upper trace in each of these figures is only valid for an output range selection of 0-to-AV

. In 0-to-V

mode, DAC

REF

loading will not cause high-side voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. For example, if AV

= 3 V and V

= 2.5 V, the

REF

high-side voltage will not be affected by loads less than 5 mA. But somewhere around 7 mA the upper curve in Figure 21 drops below 2.5 V (V output will not be capable of reaching V

OUTPUT VOLTAGE – V

0 5 10 15

) indicating that at these higher currents the

REF

DAC LOADED WITH 0FFF HEX

DAC LOADED WITH 0000 HEX

SOURCE/SINK CURRENT – mA

REF

Figure 20. Source and Sink Current Capability with

= VDD = 5 V

REF

–22–

REV. B

ADuC812

OUTPUT VOLTAGE – V

0 5 10 15

SOURCE/SINK CURRENT – mA

Figure 21. Source and Sink Current Capability with

= VDD = 3 V

REF

To drive significant loads with the DAC outputs, external buffering may be required, as illustrated in Figure 22.

ADuC812

the DAC outputs will remain at ground potential whenever the DAC is disabled. However, each DAC output will still spike briefly when you first apply power to the chip, and again when each DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24 respectively.

200s/DIV

AVDD – 2V/DIV

DAC OUT – 500mv/DIV

Figure 23. DAC Output Spike at Chip Power-Up

5s/DIV, 1V/DIV

Figure 22. Buffering the DAC Outputs

The DAC output buffer also features a high-impedance disable function. In the chip’s default power-on state, both DACs are disabled, and their outputs are in a high-impedance state (or “three-state”) where they remain inactive until enabled in software. This means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each DAC output. Assuming this resistor is in place,

Figure 24. DAC Output Spike at DAC Enable

REV. B

–23–

ADuC812

WATCHDOG TIMER

The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error. The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled, the watchdog circuit will generate a system reset if the user program fails to set the watchdog timer refresh bits (WDR1, WDR2) within a predetermined amount of time (see PRE2–0 bits in WDCON).

2ERP1ERP0ERP—1RDW2RDWSDWEDW

Table IX. WDCON SFR Bit Designations

Bit Name Description

7 PRE2 Watchdog Timer Prescale Bits. 6 PRE1 5 PRE0

PRE2 PRE1 PRE0 Timeout Period (ms) 000 16 001 32 010 64 011 128 100 256 101 512 1 1 0 1024 1 1 1 2048

The watchdog timer itself is a 16-bit counter. The watchdog timeout interval can be adjusted via the PRE2–0 bits in WDCON. Full Control and Status of the watchdog timer function can be controlled via the watchdog timer control SFR (WDCON).

WDCON Watchdog Timer Control Register

SFR Address C0H Power-On Default Value 00H Bit Addressable Yes

4 — Not Used. 3 WDR1 Watchdog timer refresh bits, set sequentially to refresh the watchdog. 2 WDR2 1 WDS Watchdog Status Bit.

Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.

1 WDE Watchdog Enable Bit.

Set by user to enable the watchdog and clear its counters.

Example

To set up the watchdog timer for a timeout period of 2048 ms the following code would be used.

MOV WDCON,#0E0h ;2.048 second

;timeout period

SETB WDE ;enable watchdog timer

In order to prevent the watchdog timer timing out the timer refresh bits need to be set before 2.048 seconds has elapsed.

SETB WDR1 ;refresh watchdog timer..

SETB WDR2 ; ..bits must be set in this

;order

–24–

REV. B

ADuC812

POWER SUPPLY MONITOR

As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AV

and DVDD) on the ADuC812. It

will indicate when either power supply drops below one of five user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AV must be equal to or greater than 2.7 V. The Power Supply Monitor function is controlled via the PSMCON SFR. If enabled via the IE2 SFR, the Power Supply Monitor will interrupt

PSMCON Power Supply Monitor

Control Register

the core using the PSMI bit in the PSMCON SFR. This bit will not be cleared until the failing power supply has returned above the trip point for at least 256 ms. This is to ensure that the power supply has fully settled before the bit is cleared. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures

that normal code execution will not resume until a safe supply level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit.

SFR Address DFH Power-On Default Value DCH Bit Addressable No

—PMCIMSP2PT1PT0PTFSPNEMSP

Table X. PSMCON SFR Bit Designations

Bit Name Description

7 — Not Used. 6 CMP AVDD and DVDD Comparator Bit.

This is a read-only bit and directly reflects the state of the AV Read “1” indicates that both AV Read “0” indicates that either AV

5 PSMI Power Supply Monitor Interrupt Bit.

This bit will be set high by the MicroConverter if CMP is low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMP return (and remain) high, a 256 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. How

ever, if either comparator output is low, it is not possible for the user to clear PSMI. 4 TP2 VDD Trip Point Selection Bits. 3 TP1 2 TP0 These bits select the AV

and DVDD trip-point voltage as follows:

TP2 TP1 TP0 Selected DV

0004.63

0014.37

0103.08

0112.93

1002.63

AVDD/

1 PSF

DVDD fault indicator Read “1” indicates that the AV Read “0” indicates that the DV

0 PSMEN Power Supply Monitor Enable Bit.

Set to

“1”

by the user to enable the Power Supply Monitor Circuit.

Cleared to “0” by the user to disable the Power Supply Monitor Circuit.

and DVDD comparators.

and DVDD supply are above its selected trip point.

or DVDD supply are below its selected trip point.

Trip Point (V)

supply caused the fault condition.

Example

To configure the PSM for a trippoint of 4.37 V, the following code would be used

MOV PSMCON,#005h ;enable PSM with

;4.37V threshold SETB EA ;enable interrupts MOV IE2,#002h ;enable PSM

;interrupt

If the supply voltage falls below this level, the PC would vector to the ISR.

REV. B

–25–

ORG 0043h ;PSM ISR CHECK:MOV A,PSMCON ;PSMCON.5 is the

;PSM interrupt ;bit..

JB ACC.5,CHECK ;..it is cleared

;only when Vdd ;has remained ;above the trip ;point for 256ms ;or more.

RETI ; return only when "all's well"

ADuC812

SERIAL PERIPHERAL INTERFACE

The ADuC812 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins are shared with the I2C interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON below). The SPI Port can be configured for Master or Slave operation and typically consists of four pins, namely:

MISO (Master In, Slave Out Data I/O Pin), Pin #19

The MISO (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin), Pin #27

The MOSI (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.

SCLOCK (Serial Clock I/O Pin), Pin #26

The master serial clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The

SCLOCK pin is configured as an output in master mode and as an input in slave mode. In master mode the bit-rate, polarity and phase of the clock are controlled by the CPOL, CPHA, SPR0 and SPR1 bits in the SPICON SFR (see Table XII). In slave mode the SPICON register will have to be configured with the phase and polarity (CPHA and CPOL) of the expected input clock. In both master and slave mode the data is transmitted on one edge of the SCLOCK signal and sampled on the other. It is important therefore that the CPHA and CPOL are configured the same for the master and slave devices.

SS (Slave Select Input Pin), Pin #12

The Slave Select (SS) input pin is shared with the ADC5 input. In order to configure this pin as a digital input the bit must be cleared, e.g., CLR P1.5.

This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC812 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0 then the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception. In SPI Slave Mode, the logic level on the external SS pin (Pin #13), can be read via the SPR0 bit in the SPICON SFR.

The following SFR registers are used to control the SPI interface.

SPICON SPI Control Register

SFR Address F8H Power-On Default Value OOH Bit Addressable Yes

IPSILOCWEPSMIPSLOPCAHPC1RPS0RPS

Table XI. SPICON SFR Bit Designations

Bit Name Description

7 ISPI SPI Interrupt Bit.

Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR

6 WCOL Write Collision Error Bit.

Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code.

5 SPE SPI Interface Enable Bit.

Set by user to enable the SPI interface. Cleared by user to enable the I

4 SPIM SPI Master/Slave Mode Select Bit.

Set by user to enable Master Mode operation (SCLOCK is an output). Cleared by user to enable Slave Mode operation (SCLOCK is an input).

3 CPOL Clock Polarity Select Bit.

Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low.

2 CPHA Clock Phase Select Bit.

Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data.

C interface.

–26–

REV. B

Table XII. SPICON SFR Bit Designations (continued)

Bit Name Description

1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:

SPR1 SPR0 Selected Bit Rate 00f 01f 10f

OSC

/4 /8 /32

1 1 fosc/64 In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin #12) can be read via the SPR0 bit.

NOTE The CPOL and CPHA bits should both contain the same values for master and slave devices.

SPIDAT SPI Data Register

Function The SPIDAT SFR is written by the

user to transmit data over the SPI interface or read by user code to read data just received by the SPI

interface. SFR Address F7H Power-On Default Value 00H Bit Addressable No

Using the SPI Interface

Depending on the configuration of the bits in the SPICON SFR shown in Table XII, the ADuC812 SPI interface will transmit or receive data in a number of possible modes. Figure 26 shows all possible ADuC812 SPI configurations and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication.

SCLOCK

(CPOL = 1)

SPI Interface—Master Mode

In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC812 needs to assert the SS pin on an external slave device, a Port digital output pin should be used.

In master mode a byte transmission or reception is initiated by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period a data bit is also sampled via MISO.

SCLOCK

(CPOL = 0)

SAMPLE INPUT

DATA OUTPUT

(CPHA = 1)

ISPI FLAG

SAMPLE INPUT

DATA OUTPUT

(CPHA = 0)

ISPI FLAG

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB?

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?

Figure 25. SPI Timing, All Modes

After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT.

SPI Interface—Slave Mode

In slave mode the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication.

Transmission is also initiated by a write to SPIDAT. In slave mode, a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received if CPHA = 1, or when SS returns high if CPHA = 0.

ADuC812

REV. B

–27–

ADuC812

I2C-COMPATIBLE INTERFACE

The ADuC812 supports a 2-wire serial interface mode which is

C compatible. The I2C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON

SDATA (Pin 27) Serial data I/O Pin SCLOCK (Pin 26) Serial Clock

Three SFRs are used to control the I

These are described below:

I2CCON: I

C-compatible interface.

C Control Register

SFR Address E8H Power-On Default Value 00H Bit Addressable Yes

ODMEDMOCMIDMMC2ISRC2IXTC2IIC2I

Table XIII. I2CCON SFR Bit Designations

Bit Name Description

7 MDO I

C Software Master Data Output Bit (MASTER MODE ONLY). This data bit is used to implement a master I bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.

6 MDE I

C Software Master Data Output Enable Bit (MASTER MODE ONLY). Set by user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin as an input (Rx).

5 MCO I

C Software Master Clock Output Bit (MASTER MODE ONLY). This data bit is used to implement a master I this bit will be outputted on the SCLOCK pin.

4 MDI I

C Software Master Data Input Bit (MASTER MODE ONLY). This data bit is used to implement a master I pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) = “0.”

3 I2CM I

2 I2CRS I

1 I2CTX I

C Master/Slave Mode Bit.

Set by user to enable I Cleared by user to enable I

C Reset Bit (SLAVE MODE ONLY).

Set by user to reset the I Cleared by user code for normal I

C Direction Transfer Bit (SLAVE MODE ONLY).

C software master mode.

C hardware slave mode.

C interface.

Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving.

0 I2CI I

C Interrupt Bit (SLAVE MODE ONLY).

Set by the MicroConverter after a byte has been transmitted or received. Cleared by User Software.

previously). An Application Note describing the operation of this interface as implemented is available from the MicroConverter Website at www.analog.com/microconverter. This interface can be configured as a Software Master or Hardware Slave, and uses two pins in the interface.

C transmitter interface in software. Data written to this

C transmitter interface in software. Data written to

C receiver interface in software. Data on the SDATA

C operation.

I2CADD I2C Address Register

Function Holds the I2C peripheral address

for the part. It may be overwritten by user code. Technical Note µC001

www.analog.com/microconverter

at describes the format of the I2C

standard 7-bit address in detail. SFR Address 9BH Power-On Default Value 55H Bit Addressable No

I2CDAT I2C Data Register

Function The I2CDAT SFR is written by

the user to transmit data over

C interface or read by user

the I code to read data just received by

C interface. User software

the I should only access I2CDAT once per interrupt cycle.

SFR Address 9AH Power-On Default Value 00H Bit Addressable No

–28–

REV. B

ADuC812

8051-COMPATIBLE ON-CHIP PERIPHERALS

This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are fully 8051-compatible and are controlled via standard 8051 SFR bit definitions.

Parallel I/O Ports 0–3

The ADuC812 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Port 0 is an 8-bit open drain bidirectional I/O port that is directly controlled via the P0 SFR (SFR address = 80 hex). Port 0 pins that have 1s written to them via the Port 0 SFR will be configured as open drain and will therefore float. In that state, Port 0 pins can be used as high impedance inputs. An external pull-up resistor will be required on Port 0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s.

Port 1 is also an 8-bit port directly controlled via the P1 SFR (SFR address = 90 hex). Port 1 ia an input only port. Port 1 digital output capability is not supported on this device. Port 1 pins can be configured as digital inputs or analog inputs.

By (power-on) default these pins are configured as Analog Inputs, i.e., “1” written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a “0” to these port bits to configure the corresponding pin as a high impedance digital input.

These pins also have various secondary functions described in Table XIV.

Table XIV. Port 1, Alternate Pin Functions

Pin Alternate Function

P1.0 T2 (Timer/Counter 2 External Input) P1.1 T2EX (Timer/Counter 2 Capture/Reload Trigger) P1.5 SS (Slave Select for the SPI interface)

Port 2 is a bidirectional port with internal pull-up resistors directly controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and, in that state, they can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space.

Port 3 is a bidirectional port with internal pull-ups directly controlled via the P3 SFR (SFR address = B0 hex). Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state they can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-ups. Port 3 pins also have various secondary functions described in Table XV.

Table XV. Port 3, Alternate Pin Functions

Pin Alternate Function

P3.0 RXD (UART Input Pin)

(or Serial Data I/O in Mode 0)

P3.1 TXD (UART Output Pin)

(or Serial Clock Output in Mode 0)

P3.2 INT0 (External Interrupt 0) P3.3 INT1 (External Interrupt 1) P3.4 T0 (Timer/Counter 0 External Input) P3.5 T1 (Timer/Counter 1 External Input) P3.6 WR (External Data Memory Write Strobe) P3.7 RD (External Data Memory Read Strobe)

The alternate functions of P1.0, P1.1, P1.5 and Port 3 pins can only be activated if the corresponding bit latch in the P1 and P3 SFRs contains a 1. Otherwise, the port pin is stuck at 0.

Timers/Counters

The ADuC812 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each Timer/Counter consists of two 8-bit registers THx and TLx (x = 0, 1 and 2). All three can be configured to operate either as timers or event counters.

In “Timer” function, the TLx register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency.

In “Counter” function, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin, T0, T1, or T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle.

REV. B

–29–

ADuC812

User configuration and control of all Timer operating modes is achieved via three SFRs, namely:

TMOD, TCON: Control and configuration for

Timers 0 and 1. T2CON: Control and configuration for

Timer 2.

etaGT/C1M0MetaGT/C1M0M

Table XVI. TMOD SFR Bit Designations

Bit Name Description

7 Gate Timer 1 Gating Control.

Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable timer 1 whenever TR1 control bit is set.

6 C/T Timer 1 Timer or Counter Select Bit.

Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock).

5 M1 Timer 1 Mode Select Bit 1 (Used with M0 Bit). 4 M0 Timer 1 Mode Select Bit 0.

M1 M0 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be

reloaded into TL1 each time it overflows.

1 1 Timer/Counter 1 Stopped.

3 Gate Timer 0 Gating Control.

Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set.

2 C/T Timer 0 Timer or Counter Select Bit.

Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock).

1 M1 Timer 0 Mode Select Bit 1. 0 M0 Timer 0 Mode Select Bit 0.

M1 M0 0 0 TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no

prescaler

1 0 8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to

be reloaded into TL0 each time it overflows.

1 1 TL0 is an 8-bit timer/counter controlled by the standard timer 0 control

bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.

TMOD Timer/Counter 0 and 1 Mode

SFR Address 89H Power-On Default Value 00H Bit Addressable No

–30–

REV. B

TCON: Timer/Counter 0 and 1 Control Register

SFR Address 88H Power-On Default Value 00H Bit Addressable Yes

ADuC812

1FT1RT0FT0RT1EI

NOTE

These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.

Table XVII. TCON SFR Bit Designations

1TI

0EI

0TI

Bit Name Description

7 TF1 Timer 1 Overflow Flag.

Set by hardware on a timer/counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.

6 TR1 Timer 1 Run Control Bit.

Set by user to turn on timer/counter 1. Cleared by user to turn off timer/counter 1.

5 TF0 Timer 0 Overflow Flag.

Set by hardware on a timer/counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine.

4 TR0 Timer 0 Run Control Bit.

Set by user to turn on timer/counter 0. Cleared by user to turn off timer/counter 0.

3 IE1 External Interrupt 1 (INT1) Flag.

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state. Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.

2 IT1 External Interrupt 1 (IE1) Trigger Type.

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level).

1 IE0 External Interrupt 0 (INT0) Flag.

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.

0 IT0 External Interrupt 0 (IE0) Trigger Type.

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level).

Timer/Counter 0 and 1 Data Registers

Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration.

TH0 and TL0

Timer 0 high byte and low byte. SFR Address = 8CH, 8AH respectively.

TH1 and TL1

Timer 1 high byte and low byte. SFR Address = 8DH, 8BH respectively.

REV. B

–31–

ADuC812

TIMER/COUNTER 0 AND 1 OPERATING MODES

The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1.

Mode 0 (13-Bit Timer/Counter)

Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 26 shows mode 0 operation.

CORE

CLK

P3.4/T0

GATE

P3.2/INT0

12

TR0

C/T = 0

C/T = 1

(5 BITS)

CONTROL

TL0

TH0

(8 BITS)

TF0

INTERRUPT

Figure 26. Timer/Counter 0, Mode 0

In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag TF0. The overflow flag, TF0, can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulsewidth measurements. TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all eight bits of TH0 and the lower five bits of TL0. The upper three bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.

Mode 1 (16-Bit Timer/Counter)

Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 27.

CORE

P3.4/T0

CLK

12

TR0

C/T = 0

C/T = 1

(8 BITS)

CONTROL

TL0

TH0

(8 BITS)

TF0

INTERRUPT

Mode 2 (8-Bit Timer/Counter with Auto Reload)

Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 28. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.

CORE

CLK

P3.4/T0

GATE

P3.2/INT0

12

TR0

C/T = 0

C/T = 1

CONTROL

TL0

(8 BITS)

RELOAD

TH0

(8 BITS)

TF0

INTERRUPT

Figure 28. Timer/Counter 0, Mode 2

Mode 3 (Two 8-Bit Timer/Counters)

Mode 3 has different effects on timer 0 and timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 29. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter.

When timer 0 is in Mode 3, timer 1 can be turned on and off by switching it out of, and into, its own Mode 3, or can still be used by the serial interface as a Baud Rate Generator. In fact, it can be used, in any application not requiring an interrupt from timer 1 itself.

CORE

CLK

P3.4/T0

GATE

P3.2/INT0

12

TR0

C/T = 0

C/T = 1

CORE

CLK/12

CONTROL

TL0

(8 BITS)

TF0

INTERRUPT

GATE

P3.2/INT0

Figure 27. Timer/Counter 0, Mode 1

–32–

CORE

CLK/12

TR1

CONTROL

TH0

(8 BITS)

TF1

Figure 29. Timer/Counter 0, Mode 3

INTERRUPT

REV. B

T2CON Timer/Counter 2 Control Register

SFR Address C8H Power-On Default Value 00H Bit Addressable Yes

2FT2FXEKLCRKLCT2NEXE2RT2TNC2PAC

Table XVIII. T2CON SFR Bit Designations

Bit Name Description

7 TF2 Timer 2 Overflow Flag.

Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software.

6 EXF2 Timer 2 External Flag.

Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software.

5 RCLK Receive Clock Enable Bit.

Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the receive clock.

4 TCLK Transmit Clock Enable Bit.

Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the transmit clock.

3 EXEN2 Timer 2 External Enable Flag.

Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX.

2 TR2 Timer 2 Start/Stop Control Bit.

Set by user to start timer 2. Cleared by user to stop timer 2.

1 CNT2 Timer 2 Timer or Counter Function Select Bit.

Set by user to select counter function (input from external T2 pin). Cleared by user to select timer function (input from on-chip core clock).

0 CAP2 Timer 2 Capture/Reload Select Bit.

Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX

when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.

ADuC812

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers.

TH2 and TL2

Timer 2, data high byte and low byte. SFR Address = CDH, CCH respectively.

RCAP2H and RCAP2L

Timer 2, Capture/Reload byte and low byte. SFR Address = CBH, CAH respectively.

REV. B

–33–

ADuC812

Timer/Counter Operation Modes

The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XIX.

Table XIX. TIMECON SFR Bit Designations

RCLK (or) TCLK CAP2 TR2 MODE

0 0 1 16-Bit Autoreload 0 1 1 16-Bit Capture 1 X 1 Baud Rate X X 0 OFF

16-Bit Autoreload Mode

In “Autoreload” mode, there are two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The Autoreload mode is illustrated in Figure 30 below.

CORE

T2EX

CLK

TRANSITION

DETECTOR

C/T2 = 0

C/T2 = 1

CONTROL

TR2

RELOAD

TL2

(8-BITS)

RCAP2L RCAP2H

16-Bit Capture Mode

In the “Capture” mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. The Capture Mode is illustrated in Figure 31.

The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1.

In either case if Timer 2 is being used to generate the baud rate, the TF2 interrupt flag will not occur. Hence Timer 2 interrupts will not occur so they do not have to be disabled. In this mode the EXF2 flag, however, can still cause interrupts and this can be used as a third external interrupt.

Baud rate generation will be described as part of the UART serial port operation in the following pages.

TH2

(8-BITS)

TF2

EXF2

TIMER INTERRUPT

CORE

T2EX

CLK

TRANSITION

DETECTOR

CONTROL

EXEN2

Figure 30. Timer/Counter 2, 16-Bit Autoreload Mode

C/T2 = 0

C/T2 = 1

CONTROL

TR2

CAPTURE

CONTROL

EXEN2

TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

TF2

EXF2

Figure 31. Timer/Counter 2, 16-Bit Capture Mode

–34–

TIMER INTERRUPT

REV. B

ADuC812

UART SERIAL INTERFACE

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via Pins RXD(P3.0) and

SCON UART Serial Port Control

SFR Address 98H Power-On Default Value 00H Bit Addressable Yes

0MS1MS2MSNER8BT8BRITIR

Table XX. SCON SFR Bit Designations

Bit Name Description

7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the Serial Port operating mode as follows:

SM0 SM1 Selected Operating Mode 0 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 0 1 Mode 1: 8-bit UART, variable baud rate 1 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or

(Core_Clk/32)

1 1 Mode 3: 9-bit UART, variable baud rate

5 SM2 Multiprocessor Communication Enable Bit.

Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received.

4 REN Serial Port Receive Enable Bit.

Set by user software to enable serial port reception. Cleared by user software to disable serial port reception.

3 TB8 Serial Port Transmit (Bit 9).

The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.

2 RB8 Serial port Receiver Bit 9.

The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is latched into RB8.

1 TI Serial Port Transmit Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software.

0 RI Serial Port Receive Interrupt Flag.

Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software.

TXD(P3.1) while the SFR interface to the UART is comprised of SBUF and SCON, as described below.

SBUF

The serial port receive and transmit registers are both accessed through the SBUF SFR (SFR address = 99 hex). Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register.

REV. B

–35–

ADuC812

Mode 0: 8-Bit Shift Register Mode

Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RXD line. The eight bits are transmitted with the least-significant bit (LSB) first, as shown in Figure 32.

MACHINE

CYCLE 8

S6S5S4S3S2S1S6S5S4S4S3S2S1S6S5S4S3S2S1

CORE

CLK

ALE

RXD

(DATA OUT)

TXD

(SHIFT

CLOCK)

MACHINE

CYCLE 1

DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7

MACHINE

CYCLE 2

MACHINE

CYCLE 7

Figure 32. UART Serial Port Transmission, Mode 0

Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared the data is clocked into the RXD line and the clock pulses are output from the TXD line.

Mode 1: 8-Bit UART, Variable Baud Rate

Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore 10 bits are transmitted on TXD or received on RXD. The baud rate is set by the Timer 1 or Timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception).

Transmission is initiated by writing to SBUF. The “write to SBUF” signal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. The data is output bit by bit until the stop bit appears on TXD and the transmit interrupt flag (TI) is automatically set as shown in Figure 33.

STOP BIT

SET INTERRUPT

TXD

(SCON.1)

START BIT

D0 D1 D2 D3 D4 D5 D6 D7

I.E., READY FOR MORE DATA

Figure 33. UART Serial Port Transmission, Mode 0

Reception is initiated when a 1-to-0 transition is detected on RXD. Assuming a valid start bit was detected, character reception continues. The start bit is skipped and the eight data bits are clocked into the serial port shift register. When all eight bits have been clocked in, the following events occur: The eight bits in the receive shift register are latched into SBUF The ninth bit (Stop bit) is clocked into RB8 in SCON. The Receiver interrupt flag (RI) is set if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0, and Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set.

Mode 2: 9-Bit UART with Fixed Baud Rate

Mode 2 is selected by setting SM0 and clearing SM1. In this mode the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by default, although by setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit and a stop bit (1). The ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required.

To transmit, the eight data bits must be written into SBUF. The ninth bit must be written to TB8 in SCON. When transmission is initiated the eight data bits (from SBUF) are loaded onto the transmit shift register (LSB first). The contents of TB8 are loaded into the ninth bit position of the transmit shift register. The transmission will start at the next valid baud rate clock. The TI flag is set as soon as the stop bit appears on TXD.

Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RXD (LSB first) and loaded onto the receive shift register. When all eight bits have been clocked in, the following events occur:

The eight bits in the receive shift register are latched into SBUF.

The ninth data bit is latched into RB8 in SCON.

The Receiver interrupt flag (RI) is set.

This will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated:

RI = 0, and Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set.

Mode 3: 9-Bit UART with Variable Baud Rate

Mode 3 is selected by setting both SM0 and SM1. In this mode the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The operation of the 9-bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

UART Serial Port Baud Rate Generation

Mode 0 Baud Rate Generation

The baud rate in Mode 0 is fixed:

Mode 0 Baud Rate = (Core Clock Frequency/12)

Mode 2 Baud Rate Generation

The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core clock. If SMOD = 1, the baud rate is 1/32 of the core clock:

Mode 2 Baud Rate = (2

SMOD

/64) × (Core Clock Frequency)

Mode 1 and 3 Baud Rate Generation

The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or both (one for transmit and the other for receive).

–36–

REV. B

ADuC812

Timer 1 Generated Baud Rates

When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows:

Modes 1 and 3 Baud Rate =

SMOD

/32) × (Timer 1 Overflow Rate)

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation, in the Autoreload mode (high nibble of TMOD = 0010 Binary). In that case, the baud rate is given by the formula:

Modes 1 and 3 Baud Rate =

SMOD

/32) × (Core Clock/(12 × [256-TH1]))

Table XXI shows some commonly-used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz. Generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications.

Table XXI. Commonly-Used Baud Rates, Timer 1

Ideal Core SMOD TH1-Reload Actual % Baud CLK Value Value Baud Error

9600 12 1 –7 (F9h) 8929 7 19200 11.0592 1 –3 (FDh) 19200 0 9600 11.0592 0 –3 (FDh) 9600 0 2400 11.0592 0 –12(F4h) 2400 0

Timer 2 Generated Baud Rates

Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload mode a wider range of baud rates is possible using Timer 2.

Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate)

Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Hence, it increments six times faster than Timer 1, and therefore baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible.

Timer 2 is selected as the baud rate generator by setting the TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 34.

In this case, the baud rate is given by the formula:

Modes 1 and 3 Baud Rate -

(Core Clk)/(32 × [65536 – (RCAP2H, RCAP2L)])

Table XXII shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz.

Table XXII. Commonly Used Baud Rates, Timer 2

Ideal Core RCAP2H RCAP2L Actual % Baud CLK Value Value Baud Error

19200 12 –1 (FFh) –20 (ECh) 19661 2.4 9600 12 –1 (FFh) –41 (D7h) 9591 0.1 2400 12 –1 (FFh) –164 (5Ch) 2398 0.1 1200 12 –2 (FEh) –72 (B8h) 1199 0.1 19200 11.0592 –1 (FFh) –18 (EEh) 19200 0 9600 11.0592 –1 (FFh) –36 (DCh) 9600 0 2400 11.0592 –1 (FFh) –144(70h) 2400 0 1200 11.0592 –2 (FFh) –32 (E0h) 1200 0

REV. B

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.

CORE

CLK

NOTE: AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT

T2EX

TRANSITION

DETECTOR

C/T2 = 0

C/T2 = 1

CONTROL

EXEN2

Figure 34. Timer 2, UART Baud Rates

TR2

TL2

(8-BITS)

RCAP2L RCAP2H

EXF

TH2

(8-BITS)

TIMER 2 INTERRUPT

–37–

TIMER 2

OVERFLOW

RELOAD

OVERFLOW

TIMER 1

SMOD

RCLK

CLOCK

TCLK

CLOCK

ADuC812

INTERRUPT SYSTEM

The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs.

IE: Interrupt Enable Register. IP: Interrupt Priority Register. IE2: Secondary Interrupt Enable Register.

IE: Interrupt Enable Register

SFR Address A8H Power-On Default Value 00H Bit Addressable Yes

AECDAE2TESE1TE1XE0TE0XE

Table XXIII. IE SFR Bit Designations

Bit Name Description

7 EA Written by User to Enable “1” or Disable “0” All Interrupt Sources 6 EADC Written by User to Enable “1” or Disable “0” ADC Interrupt 5 ET2 Written by User to Enable “1” or Disable “0” Timer 2 Interrupt 4 ES Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt 3 ET1 Written by User to Enable “1” or Disable “0” Timer 1 Interrupt 2 EX1 Written by User to Enable “1” or Disable “0” External Interrupt 1 1 ET0 Written by User to Enable “1” or Disable “0” Timer 0 Interrupt 0 EX0 Written by User to Enable “1” or Disable “0” External Interrupt 0

IP: Interrupt Priority Register

SFR Address B8H Power-On Default Value 00H Bit Addressable Yes

ISPCDAP2TPSP1TP1XP0TP0XP

Table XXIV. IP SFR Bit Designations

Bit Name Description

7 PSI Written by User to Select SPI/I2C Priority (“1” = High; “0” = Low) 6 PADC Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low) 5 PT2 Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low) 4 PS Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low) 3 PT1 Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low) 2 PX1 Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low) 1 PT0 Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low) 0 PX0 Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low)

–38–

REV. B

ADuC812

IE2: Secondary Interrupt Enable Register

SFR Address A9H Power-On Default Value 00H Bit Addressable No

—————— IMSPEISE

Table XXV. IE2 SFR Bit Designations

Bit Name Description

7 — Reserved for Future Use. 6 — Reserved for Future Use. 5 — Reserved for Future Use. 4 — Reserved for Future Use. 3 — Reserved for Future Use. 2 — Reserved for Future Use. 1 EPSMI Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt. 0 ESI Written by User to Enable “1” or Disable “0” SPI/I2C Serial Port Interrupt.

Interrupt Priority

The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed as shown in Table XXVI.

Table XXVI. Priority within an Interrupt Level

Source Priority Description

PSMI 1 (Highest) Power Supply Monitor Interrupt IE0 2 External Interrupt 0 ADCI 3 ADC Interrupt TF0 4 Timer/Counter 0 Interrupt IE1 5 External Interrupt 1 TF1 6 Timer/Counter 1 Interrupt I2CI + ISPI 7 I RI + TI 8 Serial Interrupt TF2 + EXF2 9 (Lowest) Timer/Counter 2 Interrupt

C/SPI Interrupt

Interrupt Vectors

When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt Vector Addresses are shown in the Table XXVII.

Table XXVII. Interrupt Vector Addresses

Source Vector Address

IE0 0003 Hex TF0 000B Hex IE1 0013 Hex TF1 001B Hex RI + TI 0023 Hex TF2 + EXF2 002B Hex ADCI 0033 Hex I2CI + ISPI 003B Hex PSMI 0043 Hex

REV. B

–39–

ADuC812

ADuC812 HARDWARE DESIGN CONSIDERATIONS

This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC812 into any hardware system.

Clock Oscillator

The clock source for the ADuC812 can come either from an external source or from the internal clock oscillator. To use the internal clock oscillator connect a parallel resonant crystal between Pins 32 and 33, and connect a capacitor from each pin to ground as shown below.

XTAL1

XTAL2

ADuC812

TO INTERNAL TIMING CIRCUITS

Figure 35. External Parallel Resonant Crystal Connections

ADuC812

TO INTERNAL TIMING CIRCUITS

EXTERNAL

CLOCK

SOURCE

XTAL1

XTAL2

Figure 36. Connecting an External Clock Source

Whether using the internal oscillator or an external clock source, the ADuC812’s specified operational clock speed range is 300 kHz to 16 MHz. The core itself is static, and will function all the way down to dc. But at clock speeds slower that 400 kHz the ADC will no longer function correctly. Therefore to ensure specified operation, use a clock frequency of at least 400 kHz and no more than 16 MHz.

External Memory Interface

In addition to its internal program and data memories, the ADuC812 can access up to 64K bytes of external program memory (ROM/PROM/etc.) and up to 16M bytes of external data memory (SRAM).

To select from which code space (internal or external program memory) to begin executing instructions, tie the EA (external access) pin high or low, respectively. When EA is high (pulled up to V

), user program execution will start at address 0 of the

internal 8K bytes Flash/EE code space. When EA is low (tied to ground) user program execution will start at address 0 of the external code space. In either case, addresses above 1FFF hex (8K) are mapped to the external space.

Note that a second very important function of the EA pin is described in the Single Pin Emulation Mode section of this data sheet.

External program memory (if used) must be connected to the ADuC812 as illustrated in Figure 37. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. During the time that the low byte of the program counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2) emits the high byte of the program counter (PCH), then PSEN strobes the EPROM and the code byte is read into the ADuC812.

ADuC812

ALE

PSEN

LATCH

EPROM

D0–D7 (INSTRUCTION)

A0–A7

A8–A15

Figure 37. External Program Memory Interface

Note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64K bytes. External program execution sacrifices two of the 8-bit ports (P0 and P2) to the function of addressing the program memory. While executing from external program memory, Ports 0 and 2 can be used simultaneously for read/write access to external data memory, but not for general-purpose I/O.

Though both external program memory and external data memory are accessed by some of the same pins, the two are completely independent of each other from a software point of view. For example, the chip can read/write external data memory while executing from external program memory.

Figure 38 shows a hardware configuration for accessing up to 64K bytes of external RAM. This interface is standard to any 8051-compatible MCU.

ADuC812

LATCH

ALE

D0–D7 (DATA)

A0–A7

SRAM

A8–A15

Figure 38. External Data Memory Interface (64 K Address Space)

–40–

REV. B

ADuC812

If access to more than 64K bytes of RAM is desired, a feature unique to the ADuC812 allows addressing up to 16M bytes of external RAM simply by adding an additional latch as illustrated in Figure 39.

ADuC812

LATCH

ALE

LATCH

SRAM

D0–D7 (DATA)

A0–A7

A8–A15

A16–A23

Figure 39. External Data Memory Interface (16 M Bytes Address Space)

In either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL) as an address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC812 (write operation) or the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the SRAM, and the 8051 standard of 64K byte external data memory access is maintained.

Detailed timing diagrams of external program and data memory read and write access can be found in the timing specification sections of this data sheet.

Power-On Reset Operation

External POR (power-on reset) circuitry must be implemented to drive the RESET pin of the ADuC812. The circuit must hold the RESET pin asserted (high) whenever the power supply

) is below 2.5 V. Furthermore, VDD must remain above

(DV

2.5 V for at least 10 ms before the RESET signal is deasserted (low) by which time the power supply must have reached at least a 2.7 V level. The external POR circuit must be operational down to 1.2 V or less. The timing diagram of Figure 40 illustrates this functionality under three separate events: power-up, brownout, and power-down. Notice that when RESET is asserted (high) it tracks the voltage on DV

. These recommendations

must be adhered to through the manufacturing flow of your ADuC812-based system as well as during its normal power-on operation. Failure to adhere to these recommendations can result in permanent damage to device functionality.

2.5V MIN

RESET

1.2V MAX

10ms

MIN

1.2V MAX10ms

Figure 40. External POR Timing

The best way to implement an external POR function to meet the above requirements involves the use of a dedicated POR chip, such as the ADM809/ADM810 SOT-23 packaged PORs from Analog Devices. Recommended connection diagrams for both active-high ADM810 and active-low ADM809 PORs are shown in Figure 41 and Figure 42, respectively.

POWER SUPPLY

(ACTIVE HIGH)

POR

RESET

ADuC812

Figure 41. External Active High POR Circuit

Some active-low POR chips, such as the ADM809 can be used with a manual push-button as an additional reset source as illustrated by the dashed line connection in Figure 42.

POWER SUPPLY

1k

OPTIONAL MANUAL RESET P

POR

(ACTIVE LOW)

H-BUTTON

ADuC812

RESET

Figure 42. External Active Low POR Circuit

Power Supplies

The ADuC812’s operational power supply voltage range is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or ±10% of the nominal 5 V level, the chip will function equally well at any power supply level between 2.7 V and 5.5 V.

Separate analog and digital power supply pins (AV

and DV

respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system DV you can power AV

and DVDD from two separate supplies if

line. However, though

desired, you must ensure that they remain within ±0.3 V of one another at all times in order to avoid damaging the chip (as per the Absolute Maximum Ratings section of this data sheet). Therefore it is recommended that unless AV

and DVDD are connected

directly together, you connect back-to-back Schottky diodes between them as shown in Figure 43.

DIGITAL SUPPLY

10F

–

0.1F

DGND

ADuC812

ANALOG SUPPLY

10F

AGND

0.1F

–

REV. B

Figure 43. External Dual-Supply Connections

–41–

ADuC812

As an alternative to providing two separate power supplies, the user can help keep AV and/or ferrite bead between it and DV

separately to ground. An example of this configuration is

quiet by placing a small series resistor

, and then decoupling

shown in Figure 44. With this configuration other analog circuitry (such as op amps, voltage reference, etc.) can be powered from the AV include back-to-back Schottky diodes between AV

supply line as well. Thne user will still want to

and DV

in order to protect from power-up and power-down transient conditions that could separate the two supply voltages momentarily.

DIGITAL SUPPLY

–

0.1F

10F

BEAD

DGND

ADuC812

1.6V

AGND

10F

0.1F

Figure 44. External Single-Supply Connections

Notice that in both Figure 43 and Figure 44, a large value (10 µF) reservoir capacitor sits on DV sits on AV located at each V

. Also, local small-value (0.1 µF) capacitors are

pin of the chip. As per standard design prac-

and a separate 10 µF capacitor

tice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each AV

pin with trace lengths as

short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noted that, at all times, the analog and digital ground pins on the ADuC812 must be referenced to the same system ground reference point.

Power Consumption

The currents consumed by the various sections of the ADuC812 are shown in Table XXVIII. The “CORE” values given represent the current drawn by DVDD, while the rest (“ADC,” “DAC,” “voltage ref”) are pulled by the AVDD pin and can be disabled in software when not in use. The other on-chip peripherals (watchdog timer, power supply monitor, etc.) consume negligible current and are therefore lumped in with the “CORE” operating current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order to determine the total current needed at the ADuC812’s supply pins. Also, current drawn from the DVDD supply will increase by approximately 10 mA during Flash/EE erase and program cycles.

Table XXVIII. Typical IDD of Core and Peripherals

VDD = 5 V VDD = 3 V

Core:

(Normal Mode) (1.6 nAs × MCLK) +

(0.8 nAs × MCLK) +

6 mA 3 mA

Core:

(Idle Mode)

(0.75 nAs × MCLK) +

(0.25 nAs × MCLK) +

5 mA 3 mA ADC: 1.3 mA 1.0 mA DAC (Each): 250 µA 200 µA Voltage Ref: 200 µA 150 µA

Since operating DV

current is primarily a function of clock

speed, the expressions for “CORE” supply current in Table XXVIII are given as functions of M Plug in a value for M

in hertz to determine the current con-

CLK

, the oscillator frequency.

CLK

sumed by the core at that oscillator frequency. Since the ADC and DACs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. The internal voltage reference is automatically enabled whenever either the ADC or at least one DAC is enabled. And again, do not forget to include current sourced by I/O pins, serial port pins, DAC outputs, etc., plus the additional current drawn during Flash/EE erase and program cycles.

A software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. Below are brief descriptions of power-down and idle modes.

In idle mode, the oscillator continues to run, but is gated off to the core only. The on-chip peripherals continue to receive the clock, and remain functional. Port pins and DAC output pins retain their states in this mode. The chip will recover from idle mode upon receiving any enabled interrupt, or on receiving a hardware reset.

In full power-down mode, the on-chip oscillator stops, and all on-chip peripherals are shut down. Port pins retain their logic levels in this mode, but the DAC output goes to a high-impedance state (three-state). The chip will only recover from power-down mode upon receiving a hardware reset or when power is cycled. During full power-down mode, the ADuC812 consumes a total of approximately 5 µA.

–42–

REV. B

ADuC812

Grounding and Board Layout Recommendations

As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC812-based designs in order to achieve optimum performance from the ADCs and DAC.

Although the ADuC812 has separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC812, as illustrated in the simplified example of Figure 45a. In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply for example), they cannot be connected again near the ADuC812 since a ground loop would result. In these cases, tie the ADuC812’s AGND and DGND pins all to the analog ground plane, as illustrated in Figure 45b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC812 can then be placed between the digital and analog sections, as illustrated in Figure 45c.

PLACE ANALOG

COMPONENTS HERE

In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 45b with DV return currents from DV

to flow through AGND. Also, try to

since that would force

avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 45c. Whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground.

If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC812’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC812 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high-speed signals from coupling capacitively into the ADuC812 and affecting the accuracy of ADC conversions.

PLACE DIGITAL

COMPONENTS HERE

PLACE ANALOG

COMPONENTS

HERE

PLACE ANALOG

COMPONENTS

HERE

GND

PLACE DIGITAL

COMPONENTS

PLACE DIGITAL

COMPONENTS

Figure 45. System Grounding Schemes

DGNDAGND

HERE

DGNDAGND

HERE

REV. B

–43–

ADuC812

ANALOG INPUT

OUTPUT

REF

DAC OUTPUT

51

DOWNLOAD/DEBUG

ENABLE JUMPER

(NORMALLY OPEN)

RxD

ADuC812

TxD

ADC0

AGND

REF

DAC0

DAC1

ADC7

RESET

DGND

DVDDDGND

1k

PSEN

DGND

XTAL2

XTAL1

2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN)

11.0592MHz

DVDD

ADM810

GND

RST

C1+

V+

C1–

C2+

C2–

V–

T2OUT

R2IN

ADM202

T1OUT

R1OUT

R2OUT

GND

R1IN

T1IN

T2IN

Figure 46. Typical System Configuration

OTHER HARDWARE CONSIDERATIONS

To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to download, debug, and emulation modes.

In-Circuit Serial Download Access

Nearly all ADuC812 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC812’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 46 with a simple ADM202-based circuit. If users would rather not design an RS-232 chip onto a board, refer to the application note “uC006–A 4-Wire UART-to-PC Interface”* for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADuC812.

In addition to the basic UART connections, users will also need a way to trigger the chip into download mode. This is accomplished via a 1 kΩ pull-down resistor that can be jumpered onto

*Application Note uC006 is available at www.analog.com/microconverter

9-PIN D-SUB

FEMALE

NOT CONNECTED IN THIS EXAMPLE

the PSEN pin, as shown in Figure 46. To get the ADuC812 into download mode, simply connect this jumper and powercycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. With the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or RESET is toggled.

Note that PSEN is normally an output (as described in the External Memory Interface section) and it is sampled as an input only on the falling edge of RESET (i.e., at power-up or upon an external manual reset). Note also that if any external circuitry unintentionally pulls PSEN low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. To prevent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself.

Embedded Serial Port Debugger

From a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described above. In fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways.

–44–

REV. B

Note that the serial port debugger is fully contained on the ADuC812 device, (unlike “ROM monitor” type debuggers) and therefore no external memory is needed to enable in-system debug sessions.

Single-Pin Emulation Mode

Also built into the ADuC812 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC812 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier. To enable single-pin emulation mode, however, users will need to pull the EA pin high through a 1 kΩ resistor as shown in Figure 46. The emulator will then connect to the 2-pin header also shown in Figure 46. To be compatible with the standard connector that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), use a 2-pin 0.1-inch pitch “Friction Lock” header from Molex (www.molex.com) such as their part number 22-27-2021. Be sure to observe the polarity of this header. As represented in Figure 46, when the Friction Lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top).

Enhanced-Hooks Emulation Mode

ADuC812 also supports enhanced-hooks emulation mode. An enhanced-hooks-based emulator is available from Metalink Corporation (www.metaice.com). No special hardware support for these emulators needs to be designed onto the board since these are “pod-style” emulators where users must replace the chip on their board with a header device that the emulator pod plugs into. The only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure.

Typical System Configuration

A typical ADuC812 configuration is shown in Figure 46. It summarizes some of the hardware considerations discussed in the previous paragraphs.

QUICKSTART DEVELOPMENT SYSTEM

The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC812. The system consists of the following PC-based (Windows-compatible) hardware and software development tools.

Hardware: ADuC812 Evaluation Board, Plug-In

Power Supply and Serial Port Cable

Code Development: 8051 Assembler

Code Functionality: Windows Based Simulator

In-Circuit Code Download: Serial Downloader

In-Circuit Debugger: Serial Port Debugger

Miscellaneous Other: CD-ROM Documentation and

Two Additional Prototype Devices

Figure 47 shows the typical components of a QuickStart Development System. A brief description of some of the software tools components in the QuickStart Development System is given below.

ADuC812

Figure 47. Components of the QuickStart Development System

Figure 48. Typical Debug Session

Download—In-Circuit Serial Downloader

The Serial Downloader is a Windows application that allows the user to serially download an assembled program (Intel Hex format file) to the on-chip program FLASH memory via the serial COM1 port on a standard PC. An Application Note (uC004) detailing this serial download protocol is available from www.analog.com/microconverter.

DeBug—In-Circuit Debugger

The Debugger is a Windows application that allows the user to debug code execution on silicon using the MicroConverter UART serial port. The debugger provides access to all on-chip peripherals during a typical debug session as well as single-step and break-point code execution control.

ADSIM—Windows Simulator

The Simulator is a Windows application that fully simulates all the MicroConverter functionality including ADC and DAC peripherals. The simulator provides an easy-to-use, intuitive, interface to the MicroConverter functionality and integrates many standard debug features; including multiple breakpoints, single stepping; and code execution trace capability. This tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform.

The QuickStart development tool-suite software is freely available at the Analog Devices MicroConverter Website www.analog.com/microconverter.

REV. B

–45–

ADuC812

1, 2, 3

TIMING SPECIFICATIONS

(AVDD = DVDD = 3.0 V or 5.0 V  10%. All specifications TA = T

12 MHz Variable Clock

Parameter Min Typ Max Min Typ Max Unit Figure

CLOCK INPUT (External Clock Driven XTAL1)

CKL

CKH

CKR

CKF

CYC

NOTES

AC inputs during testing are driven at DVDD– 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1 and VIL max for a Logic 0.

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

for Port0, ALE, PSEN outputs = 100 pF; C

LOAD

ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.

XTAL1 Period 83.33 62.5 1000 ns 50 XTAL1 Width Low 20 20 ns 50 XTAL1 Width High 20 20 ns 50 XTAL1 Rise Time 20 20 ns 50 XTAL1 Fall Time 20 20 ns 50 ADuC812 Machine Cycle Time 1 12t

for all other outputs = 80 pF unless otherwise noted.

LOAD

MIN

to T

unless otherwise noted.)

MAX

µs

DVDD – 0.5V

0.45V

CKH

CKL

CKR

Figure 49. XTAL 1 Input

+ 0.9V

0.2V

TEST POINTS

– 0.1V

0.2V

LOAD

+ 0.1V

– 0.1V

Figure 50. Timing Waveform Characteristics

TIMING

REFERENCE

POINTS

CKF

– 0.1V

LOAD

– 0.1V

LOAD

–46–

REV. B

ADuC812

12 MHz Variable Clock

Parameter Min Max Min Max Unit Figure

EXTERNAL PROGRAM MEMORY

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

PHAX

ALE Pulsewidth 127 2tCK–40 ns 52 Address Valid to ALE Low 43 tCK–40 ns 52 Address Hold after ALE Low 53 tCK–30 ns 52 ALE Low to Valid Instruction In 234 4tCK– 100 ns 52 ALE Low to PSEN Low 53 tCK–30 ns 52

PSEN Pulsewidth 205 3tCK–45 ns 52 PSEN Low to Valid Instruction In 145 3tCK– 105 ns 52

Input Instruction Hold after PSEN 00 ns52 Input Instruction Float after PSEN 59 tCK–25 ns 52 Address to Valid Instruction In 312 5tCK– 105 ns 52 PSEN Low to Address Float 25 25 ns 52 Address Hold after PSEN High 0 0 ns 52

MCLK

LHLL

ALE (O)

PSEN (O)

PORT 0 (I/O)

PORT 2 (O)

AVLLtLLPL

LLAX

PCL (OUT)

AVIV

PLAZ

PCH

PLPH

t t

LLIV

PLIV

PXIX

INSTRUCTION

(IN)

Figure 51. External Program Memory Read Cycle

PXIZ

PHAX

REV. B

–47–

ADuC812

12 MHz Variable Clock

Parameter Min Max Min Max Unit Figure

EXTERNAL DATA MEMORY READ CYCLE

RLRH

AVLL

LLAX

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

RLAZ

WHLH

RD Pulsewidth 400 6tCK– 100 ns 53 Address Valid after ALE Low 43 tCK–40 ns 53 Address Hold after ALE Low 48 tCK–35 ns 53 RD Low to Valid Data In 252 5tCK– 165 ns 53 Data and Address Hold after RD 00 ns53 Data Float after RD 97 2tCK–70 ns 53 ALE Low to Valid Data In 517 8tCK– 150 ns 53 Address to Valid Data In 585 9tCK– 165 ns 53 ALE Low to RD or WR Low 200 300 3tCK–50 3tCK+50 ns 53 Address Valid to RD or WR Low 203 4tCK– 130 ns 53

RD Low to Address Float 0 0 ns 53 RD or WR High to ALE High 43 123 tCK–40 6tCK– 100 ns 53

MCLK

ALE (O)

WHLH

PSEN (O)

RD (O)

PORT 0 (I/O)

PORT 2 (O)

LLDV

LLWL

AVWL

AVLL

LLAX

A0–A7 (OUT) DATA (IN)

AVDV

A16–A23 A8–A15

RLAZ

RLDV

RLRH

RHDX

Figure 52. External Data Memory Read Cycle

RHDZ

–48–

REV. B

ADuC812

12 MHz Variable Clock

Parameter Min Max Min Max Unit Figure

EXTERNAL DATA MEMORY WRITE CYCLE

WLWH

AVLL

LLAX

LLWL

AVWL

QVWX

QVWH

WHQX

WHLH

WR Pulsewidth 400 6tCK– 100 ns 54 Address Valid after ALE Low 43 tCK–40 ns 54 Address Hold after ALE Low 48 tCK–35 ns 54 ALE Low to RD or WR Low 200 300 3tCK–50 3tCK+50 ns 54 Address Valid to RD or WR Low 203 4tCK– 130 ns 54 Data Valid to WR Transition 33 tCK–50 ns 54 Data Setup Before WR 433 7tCK– 150 ns 54 Data and Address Hold after WR 33 tCK–50 ns 54 RD or WR High to ALE High 43 123 tCK–40 6tCK– 100 ns 54

MCLK

ALE (O)

WHLH

PSEN (O)

WR (O)

PORT 2 (O)

QVWX

WLWH

QVWH

AVLL

LLWL

AVWL

LLAX

A0–A7 DATA

A16–A23 A8–A15

Figure 53. External Data Memory Write Cycle

WHQX

REV. B

–49–

ADuC812

12 MHz Variable Clock

Parameter Min Typ Max Min Typ Max Unit Figure

UART TIMING (Shift Register Mode)

XLXL

QVXH

DVXH

XHDX

XHQX

Serial Port Clock Cycle Time 1.0 12t

µs55 Output Data Setup to Clock 700 10tCK – 133 ns 55 Input Data Setup to Clock 300 2tCK + 133 ns 55 Input Data Hold after Clock 0 0 ns 55 Output Data Hold after Clock 50 2tCK – 117 ns 55

ALE (O)

XLXL

(OUTPUT CLOCK)

(OUTPUT DATA)

TxD

RxD

(INPUT DATA)

DVXH

QVXH

XHQX

XHDX

MSB BIT6 BIT1

MSB BIT6 BIT1 LSB

Figure 54. UART Timing in Shift Register Mode

LSB

SET RI

SET TI

–50–

REV. B

ADuC812

Parameter Min Max Unit Figure

C-COMPATIBLE INTERFACE TIMING

SHD

DSU

DHD

RSU

PSU

BUF

SUP

NOTE

Input filtering on both the SCLOCK and SDATA inputs suppress noise spikes which are less than 50 ns.

SDATA (I/O)

SCLOCK Low Pulsewidth 4.7 µs56 SCLOCK High Pulsewidth 4.0 µs56 Start Condition Hold Time 0.6 µs56 Data Setup Time 100 ns 56 Data Hold Time 0 0.9 µs56 Setup Time for Repeated Start 0.6 µs56 Stop Condition Setup Time 0.6 µs56 Bus Free Time between a STOP Condition and a START Condition 1.3 µs56 Rise Time of Both SCLOCK and SDATA 300 ns 56 Fall Time of Both SCLOCK and SDATA 300 ns 56 Pulsewidth of Spike Suppressed 50 ns 56

BUF

MSB

SUP

LSB ACK MSB

SCLK (I)

PSU

STOP

CONDITION

START

CONDITION

DSU

DHD

SHD

1 2-7 8 9 1

DSU

SUP

Figure 55. I2C-Compatible Interface Timing

RSU

DHD

S(R)

REPEATED

START

REV. B

–51–

ADuC812

Parameter Min Typ Max Unit Figure

SPI MASTER MODE TIMING (CPHA = 1)

DAV

DSU

DHD

SCLOCK Low Pulsewidth 330 ns 57 SCLOCK High Pulsewidth 330 ns 57 Data Output Valid after SCLOCK Edge 50 ns 57 Data Input Setup Time before SCLOCK Edge 100 ns 57 Data Input Hold Time after SCLOCK Edge 100 ns 57 Data Output Fall Time 10 25 ns 57 Data Output Rise Time 10 25 ns 57 SCLOCK Rise Time 10 25 ns 57 SCLOCK Fall Time 10 25 ns 57

SCLOCK

(CPOL=0)

MSB BIT 6 – 1

LSB

SCLOCK

(CPOL=1)

MOSI

DAV

MISO

MSB IN

DHD

DSU

BIT 6 – 1

Figure 56. SPI Master Mode Timing (CPHA = 1)

LSB IN

–52–

REV. B

ADuC812

Parameter Min Typ Max Unit Figure

SPI MASTER MODE TIMING (CPHA = 0)

DAV

DOSU

DSU

DHD

SCLOCK Low Pulsewidth 330 ns 58 SCLOCK High Pulsewidth 330 ns 58 Data Output Valid after SCLOCK Edge 50 ns 58 Data Output Setup before SCLOCK Edge 150 ns 58 Data Input Setup Time before SCLOCK Edge 100 ns 58 Data Input Hold Time after SCLOCK Edge 100 ns 58 Data Output Fall Time 10 25 ns 58 Data Output Rise Time 10 25 ns 58 SCLOCK Rise Time 10 25 ns 58 SCLOCK Fall Time 10 25 ns 58

SCLOCK

(CPOL=0)

DAV

SCLOCK

(CPOL=1)

DOSU

MOSI

MISO

MSB BIT 6 – 1 LSB

MSB IN

DSU tDHD

BIT 6 – 1

Figure 57. SPI Master Mode Timing (CPHA = 0)

LSB IN

REV. B

–53–

ADuC812

Parameter Min Typ Max Unit Figure

SPI SLAVE MODE TIMING (CPHA = 1)

DAV

DSU

DHD

SFS

SS to SCLOCK Edge 0 ns 59 SCLOCK Low Pulsewidth 330 ns 59 SCLOCK High Pulsewidth 330 ns 59 Data Output Valid after SCLOCK Edge 50 ns 59 Data Input Setup Time before SCLOCK Edge 100 ns 59 Data Input Hold Time after SCLOCK Edge 100 ns 59 Data Output Fall Time 10 25 ns 59 Data Output Rise Time 10 25 ns 59 SCLOCK Rise Time 10 25 ns 59 SCLOCK Fall Time 10 25 ns 59 SS High after SCLOCK Edge 0 ns 59

SFS

SCLOCK

(CPOL=0)

SCLOCK

(CPOL=1)

MISO

MOSI

DAV

MSB IN

DSU tDHD

MSB

BIT 6 – 1

Figure 58. SPI Slave Mode Timing (CPHA = 1)

LSB

LSB IN

–54–

REV. B

ADuC812

Parameter Min Typ Max Unit Figure

SPI SLAVE MODE TIMING (CPHA = 0)

DAV

DSU

DHD

DOSS

SFS

SS to SCLOCK Edge 0 ns 60 SCLOCK Low Pulsewidth 330 ns 60 SCLOCK High Pulsewidth 330 ns 60 Data Output Valid after SCLOCK Edge 50 ns 60 Data Input Setup Time before SCLOCK Edge 100 ns 60 Data Input Hold Time after SCLOCK Edge 100 ns 60 Data Output Fall Time 10 25 ns 60 Data Output Rise Time 10 25 ns 60 SCLOCK Rise Time 10 25 ns 60 SCLOCK Fall Time 10 25 ns 60 Data Output Valid after SS Edge 20 ns 60 SS High after SCLOCK Edge ns 60

SCLOCK

(CPOL=0)

SCLOCK

(CPOL=1)

MISO

MOSI

DOSS

DSU tDHD

MSB BIT 6 – 1 LSB

MSB IN

DAV

BIT 6 – 1

LSB IN

Figure 59. SPI Slave Mode Timing (CPHA = 0)

SFS

REV. B

–55–

ADuC812

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Lead Plastic Quad Flatpack

(S-52)

0.037 (0.95)

0.026 (0.65)

SEATING

PLANE

0.012 (0.30)

0.006 (0.15)

0.008 (0.20)

0.006 (0.15)

0.094 (2.39)

0.084 (2.13)

0.082 (2.09)

0.078 (1.97)

0.557 (14.15)

0.537 (13.65)

PIN 1

0.025 (0.65) BSC

TOP VIEW

(PINS DOWN)

0.014 (0.35)

0.010 (0.25)

4052

2713

0.398 (10.11)

0.390 (9.91)

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Entire Data Sheet has been revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All

C00208–0–10/01(B)

–56–

PRINTED IN U.S.A.

REV. B

Analog Devices ADuC812 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

PIN FUNCTION DESCRIPTIONS

TERMINOLOGY

Differential Nonlinearity

Offset Error

Full-Scale Error

Signal to (Noise + Distortion) Ratio

Total Harmonic Distortion

Voltage Output Settling Time

Digital-to-Analog Glitch Impulse

ARCHITECTURE, MAIN FEATURES

MEMORY ORGANIZATION

B SFR

Stack Pointer SFR

Data Pointer

Program Status Word SFR

Power Control SFR

SPECIAL FUNCTION REGISTERS

ADC Transfer Function

Typical Operation

Driving the A/D Converter

Voltage Reference Connections

Configuring the ADC

ADC DMA Mode

The Offset and Gain Calibration Coefficients

Calibration

Flash/EE Memory and the ADuC812

ADuC812 Flash/EE Memory Reliability

Using the Flash/EE Program Memory

Serial Downloading (In-Circuit Programming)

Parallel Programming

Flash/EE Memory Timing

Using the Flash/EE Memory Interface

Erase-All

Program a Byte

USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS

Using the D/A Converter

WATCHDOG TIMER

POWER SUPPLY MONITOR

SERIAL PERIPHERAL INTERFACE

MISO (Master In, Slave Out Data I/O Pin), Pin #19

MOSI (Master Out, Slave In Pin), Pin #27

SCLOCK (Serial Clock I/O Pin), Pin #26

SS (Slave Select Input Pin), Pin #12

Using the SPI Interface

SPI Interface—Master Mode

SPI Interface—Slave Mode

8051-COMPATIBLE ON-CHIP PERIPHERALS

Parallel I/O Ports 0–3

Timers/Counters

Timer/Counter 0 and 1 Data Registers

TH0 and TL0

TH1 and TL1

TIMER/COUNTER 0 AND 1 OPERATING MODES

Mode 0 (13-Bit Timer/Counter)

Mode 1 (16-Bit Timer/Counter)

Mode 2 (8-Bit Timer/Counter with Auto Reload)

Mode 3 (Two 8-Bit Timer/Counters)

Timer/Counter 2 Data Registers

TH2 and TL2

RCAP2H and RCAP2L

Timer/Counter Operation Modes

16-Bit Autoreload Mode

16-Bit Capture Mode

UART SERIAL INTERFACE

Mode 0: 8-Bit Shift Register Mode

Mode 1: 8-Bit UART, Variable Baud Rate

Mode 2: 9-Bit UART with Fixed Baud Rate

Mode 3: 9-Bit UART with Variable Baud Rate

UART Serial Port Baud Rate Generation

Timer 1 Generated Baud Rates

Timer 2 Generated Baud Rates

INTERRUPT SYSTEM