Analog Devices ADUC812 Datasheet

MicroConverter™, Multichannel

a

FEATURES
ANALOG I/O

8-Channel, High Accuracy 12-Bit ADC
On-Chip, 40 ppm/C Voltage Reference
High Speed 200 kSPS
DMA Controller for High Speed ADC-to-RAM Capture
Two 12-Bit Voltage Output DACs
On-Chip Temperature Sensor Function

MEMORY

8K Bytes On-Chip Flash/EE Program Memory
640 Bytes On-Chip Flash/EE Data Memory
On-Chip Charge Pump (No Ext. V
256 Bytes On-Chip Data RAM
16M Bytes External Data Address Space
64K Bytes External Program Address Space

8051-COMPATIBLE CORE

12 MHz Nominal Operation (16 MHz Max)
Three 16-Bit Timer/Counters
32 Programmable I/O lines
High Current Drive Capability—Port 3
Nine Interrupt Sources, Two Priority Levels

POWER

Specified for 3 V and 5 V Operation
Normal, Idle and Power-Down Modes

ON-CHIP PERIPHERALS

UART Serial I/O
2-Wire (I

2C®

-Compatible) and SPI® Serial I/O
Watchdog Timer
Power Supply Monitor

AIN0 (P1.0)

AIN

AIN7 (P1.7)

V

REF

C

REF

MUX

2.5V
REF

BUF

T/H

TEMP

SENSOR

Requirements)

PP

FUNCTIONAL BLOCK DIAGRAM

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

12-Bit ADC with Embedded FLASH MCU

ADuC812

APPLICATIONS
Intelligent Sensors (IEEE 1451.2-Compatible)
Battery Powered Systems (Portable PCs, Instruments,

Monitors)
Transient Capture Systems
DAS and Communications Systems

GENERAL DESCRIPTION

The ADuC812 is a fully integrated 12-bit data acquisition
system incorporating a high performance self-calibrating
multichannel ADC, two 12-bit DACs and programmable 8-bit
(8051-compatible) MCU on a single chip.

The programmable 8051-compatible core is supported by
8K bytes Flash/EE program memory, 640 bytes Flash/EE data
memory and 256 bytes data SRAM on-chip.

Additional MCU support functions include Watchdog Timer,

ADC

CONTROL

AND

CALIBRATION

LOGIC

8051-COMPATIBLE

MICROCONTROLLER

8K BYTES FLASH/EE
PROGRAM MEMORY

640 BYTES FLASH/EE

DATA MEMORY

256  8 USER

RAM

Power Supply Monitor and ADC DMA functions. 32 Program­mable I/O lines, I
Serial Port I/O are provided for multiprocessor interfaces and
I/O expansion.

Normal, idle and power-down operating modes for both the
MCU core and analog converters allow for flexible power man­agement schemes suited to low power applications. The part is
specified for 3 V and 5 V operation over the industrial tempera­ture range and is available in a 52-lead, plastic quad flatpack
package.

DAC

CONTROL

MICROCONTROLLER

POWER SUPPLY

MONITOR

WATCHDOG

TIMER

ON-CHIP SERIAL

DOWN LOADER

OSC

2

C-compatible, SPI and Standard UART

P3.0 P3.7P2.0 P2.7P1.0 P1.7P0.0 P0.7

ADuC812

BUF

BUF

3  16-BIT

TIMER/COUNTERS

2-WIRE

MUX

SPI

DAC0

DAC1

T0 (P3.4)

T1 (P3.5)
T2 (P1.0)
T2EX (P1.1)

INT0 (P3.2)
INT1 (P3.3)

ALE

PSEN
EA

RESET

UART

12-BIT

DAC0

12-BIT

DAC1

SERIAL I/O

AGNDAV

DD

I2C is a registered trademark of Philips Corporation.
MicroConverter is a trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.

DGNDDV

DD

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

XTAL

1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(P3.0)

2

(P3.1)

SCLOCK

MOSI/

SDATA

MISO
(P3.3)

RxD

TxD

XTAL

1, 2

ADuC812–SPECIFICATIONS

MCLKIN = 16.0 MHz, DAC V

Load to AGND; RL = 10 k, CL = 100 pF. All specifications TA = T

OUT

(AVDD = DVDD = +3.0 V or +5.0 V  10%, V

to T

MIN

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Units Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

DC ACCURACY

3, 4

Resolution 12 12 Bits
Integral Nonlinearity ± 1/2 ± 1/2 LSB typ f

± 1.5 LSB max f
± 1.5 ±1.5 LSB typ f

Differential Nonlinearity ± 1 ± 1 LSB typ f

CALIBRATED ENDPOINT ERRORS

5, 6

Offset Error ± 5LSB max

± 1 ± 2 LSB typ
Offset Error Match 1 1 LSB typ
Gain Error ± 6LSB max

± 1 ± 2 LSB typ
Gain Error Match 1.5 1.5 LSB typ

USER SYSTEM CALIBRATION

Offset Calibration Range ± 5 ±5 % of V
Gain Calibration Range ± 2.5 ±2.5 % of V

7

typ

REF

typ

REF

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

8

70 70 dB typ
Total Harmonic Distortion (THD) –78 –78 dB typ
Peak Harmonic or Spurious Noise –78 –78 dB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

Volts

Leakage Current ± 10 µA max

± 1+1 µA typ
Input Capacitance 20 20 pF max

TEMPERATURE SENSOR

9

Voltage Output at +25°C 600 600 mV typ Measured On-Chip via a Typical
Voltage TC –3.0 –3.0 mV/°C typ ± 0.5 LSB (610 µV) Accurate ADC

DAC CHANNEL SPECIFICATIONS

DC ACCURACY

10

Resolution 12 12 Bits
Relative Accuracy ± 3 ± 3 LSB typ
Differential Nonlinearity ±0.5 ±1 LSB typ Guaranteed 12-Bit Monotonic
Offset Error ± 50 mV max

± 25 ± 25 mV typ

Full-Scale Error ± 25 mV max

± 10 ± 10 mV typ

Full-Scale Mismatch ± 0.5 ± 0.5 % typ % of Full-Scale on DAC1

ANALOG OUTPUTS

Voltage Range_0 0 to V
Voltage Range_1 0 to V

REF

DD

0 to V
0 to V

REF

DD

V typ

V typ
Resistive Load 10 10 kΩ typ
Capacitive Load 100 100 pF typ
Output Impedance 0.5 0.5 Ω typ
I

SINK

50 50 µA typ

= 2.5 V Internal Reference,

REF

, unless otherwise noted.)

MAX

= 100 kHz

SAMPLE

= 100 kHz

SAMPLE

= 200 kHz

SAMPLE

= 100 kHz. Guaranteed No

SAMPLE

Missing Codes at 5 V

= 10 kHz Sine Wave

IN

f

= 100 kHz

SAMPLE

–2–

REV. 0

ADuC812

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Units Test Conditions/Comments

DAC AC CHARACTERISTICS

Voltage Output Settling Time 15 15 µs typ Full-Scale Settling Time to

Within 1/2 LSB of Final Value

Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range 2.3/V

DD

Input Impedance 150 150 kΩ typ
REF

Output Voltage 2.45/2.55 V min/max

OUT

2.5 2.5 V typ

REF

FLASH/EE MEMORY PERFORMANCE

CHARACTERISTICS

Tempco 40 40 ppm/°C typ

OUT

11, 12

Endurance 10,000 Cycles min

50,000 50,000 Cycles typ

Data Retention 10 Years min

WATCHDOG TIMER

CHARACTERISTICS

Oscillator Frequency 64 64 kHz typ

POWER SUPPLY MONITOR

CHARACTERISTICS

Power Supply Trip Point Accuracy ± 2.5 % of Selected

± 1.0 ±1.0 % of Selected

DIGITAL INPUTS

Input High Voltage (V
Input Low Voltage (V

) 2.4 V min

INH

) 0.8 V max

INL

Input Leakage Current (Port 0, EA) ± 10 µA max V

± 1 ± 1 µA typ VIN = 0 V or V

Logic 1 Input Current

(All Digital Inputs) ± 10 µA max V

± 1 ± 1 µA typ VIN = V

Logic 0 Input Current (Port 1, 2, 3) –80 µA max

–40 –40 µA typ V

Logic 1-0 Transition Current (Port 1, 2, 3) –700 µA max V

–400 –400 µA typ V

Input Capacitance 10 10 pF typ

2.3/V

DD

V min/max

Nominal Trip
Point Voltage
max

Nominal Trip
Point Voltage
typ

= 0 V or V

IN

= V

IN

DD

DD

= 450 mV

IL

= 2 V

IL

= 2 V

IL

DD

DD

REV. 0 –3–

ADuC812–SPECIFICATIONS

1, 2

ADuC812BS

Parameter VDD = 5 V VDD = 3 V Units Test Conditions/Comments

DIGITAL OUTPUTS

Output High Voltage (VOH) 2.4 V min VDD = 4.5 V to 5.5 V

= 80 µA

I

4.0 2.6 V typ V

Output Low Voltage (V

OL

)

ALE, PSEN, Ports 0 and 2 0.4 V max I

0.2 0.2 V typ I

Port 3 0.4 V max I

0.2 0.2 V typ I

Floating State Leakage Current ± 10 µA max

± 5 ± 5 µA typ

Floating State Output Capacitance 10 10 pF typ

POWER REQUIREMENTS

IDD Normal Mode

16

13, 14, 15

42 mA max MCLKIN = 16 MHz
32 16 mA typ MCLKIN = 16 MHz
26 12 mA typ MCLKIN = 12 MHz
8 3 mA typ MCLKIN = 1 MHz

Idle Mode 25 mA max MCLKIN = 16 MHz

I

DD

18 17 mA typ MCLKIN = 16 MHz
15 6 mA typ MCLKIN = 12 MHz
7 2 mA typ MCLKIN = 1 MHz
50 50 µA max

Power-Down Mode

I

DD

17

55 µA typ

NOTES

1

Specifications apply after calibration.

2

Temperature range –40°C to +85°C.

3

Linearity is guaranteed during normal MicroConverter Core operation.

4

Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.

5

Measured in production at VDD = 5 V after Software Calibration Routine at +25°C only.

6

User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.

7

The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.

8

SNR calculation includes distortion and noise components.

9

The temperature sensor will give a measure of the die temperature directly, air temperature can be inferred from this result.

10

DAC linearity is calculated using:

reduced code range of 48 to 4095, 0 to V
reduced code range of 48 to 3995, 0 to VDD range
DAC output load = 10 kΩ and 50 pF.

11

Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification A103 (Data Retention) and JEDEC Draft Specification All7 (Endurance).

12

Endurance Cycling is evaluated under the following conditions:

Mode = Byte Programming, Page Erase Cycling
Cycle Pattern = 00Hex to FFHex
Erase Time = 20 ms
Program Time = 100 µs

13

IDD at other MCLKIN frequencies is typically given by:

Normal Mode (VDD = 5 V): IDD = (1.6 × MCLKIN) + 6
Normal Mode (VDD = 3 V): IDD = (0.8 × MCLKIN) + 3
Idle Mode (VDD = 5 V): IDD = (0.75 × MCLKIN) + 6
Idle Mode (VDD = 3 V): IDD = (0.25 × MCLKIN) + 3
Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.

14

IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.

15

IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.

16

Analog IDD = 2 mA (typ) in normal operation (internal V

17

EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.

Typical specifications are not production tested, but are supported by characterization data at initial product release.

Specifications subject to change without notice.

Please refer to User Guide, Quick Reference Guide, Application Notes and Silicon Errata Sheet at www.analog.com/microconverter for additional information.

REF

range

, ADC and DAC peripherals powered on).

REF

SOURCE

= 2.7 V to 3.3 V

DD

= 20 µA

I

SOURCE

= 1.6 mA

SINK

= 1.6 mA

SINK

= 8 mA

SINK

= 8 mA

SINK

–4–

REV. 0

ADuC812

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DV

to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V

DD

Digital Input Voltage to DGND . . . . . –0.3 V, DV

Digital Output Voltage to DGND . . . . –0.3 V, DV

V

to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V

REF

Analog Inputs to AGND . . . . . . . . . . . . –0.3 V, AV

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

P1.0/ADC0/T2

P1.1/ADC1/T2EX

P1.2/ADC2

P1.3/ADC3

AV

AGND

C

REF

V

REF

DAC0
DAC1

P1.4/ADC4

P1.5/ADC5/SS

P1.6/ADC6

PIN CONFIGURATION

DD

P0.5/AD5

P0.6/AD6

P0.7/AD7

52 51 50 49 48 43 42 41 4047 46 45 44

1

PIN 1
IDENTIFIER

2

3

4

5

DD

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

RESET

P1.7/ADC7

DV

P0.4/AD4

(Not to Scale)

P3.1/TxD

P3.0/RxD

DGND

ADuC812

TOP VIEW

P3.2/INT0

P3.3/INT1/MISO

P0.2/AD2

P0.3/AD3

DD

DV

DGND

P0.0/AD0

P0.1/AD1

P3.4/T0

P3.5/T1/CONVST

ALE

P3.6/WR

PSEN

P3.7/RD

EA

SCLOCK

39

P2.7/A15/A23

38

P2.6/A14/A22

37

P2.5/A13/A21

36

P2.4/A12/A20

35

DGND

34

DV

DD

33

XTAL2 (OUTPUT)

32

XTAL1 (INPUT)

31

P2.3/A11/A19

30

P2.2/A10/A18

29

P2.1/A9/A17

28

P2.0/A8/A16

27

SDATA/MOSI

Temperature Package Package

Model Range Description Option

ADuC812BS –40°C to +85°C 52-Lead Plastic Quad Flatpack S-52

QuickStart™ Development System

Eval-ADuC812QS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

ADuC812

PIN FUNCTION DESCRIPTIONS

Mnemonic Type Function

DV

DD

AV

DD

C

REF

V

REF

AGND G Analog Ground. Ground Reference point for the analog circuitry.
P1.0–P1.7 I Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure

ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to

T2EX I Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for

SS I Slave Select input for the SPI interface.
SDATA I/O User selectable, I
SCLOCK I/O Serial Clock pin for I
MOSI I/O SPI Master Output/Slave Input Data I/O pin for SPI interface.
MISO I/O Master Input/Slave Output Data I/O pin for SPI Serial Interface.
DAC0 O Voltage Output from DAC0.
DAC1 O Voltage Output from DAC1.
RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the

P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

RxD I/O Receiver Data Input (asynchronous) or Data Input/ Output (synchronous) of serial (UART) port.
TxD O Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.

INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two

INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two

T0 I Timer/Counter 0 Input.
T1 I Timer/Counter 1 Input.

CONVST I Active low Convert Start Logic input for the ADC block when the external Convert start function is en-

WR O Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD O Read Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2 O Output of the inverting oscillator amplifier.
XTAL1 I Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
DGND G Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15) pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2
(A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits

PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program

P Digital Positive Supply Voltage, +3 V or +5 V nominal.
P Analog Positive Supply Voltage, +3 V or +5 V nominal.
I Decoupling pin for on-chip reference. Connect 0.1 µF between this pin and AGND.
I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this
appears at the pin (once the ADC or DAC peripherals are enabled). This pin can be overdriven by an exter­nal reference.

any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.

a 1 to 0 transition of the T2 input.

Counter 2.

2

C-Compatible Input/Output pin or SPI Data Input/Output pin.

2

C-Compatible or SPI serial interface clock.

device.

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions which are described below.

priority levels. This pin can also be used as a gate control input to Timer 0.

priority levels. This pin can also be used as a gate control input to Timer 1.

abled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.

the high order address bytes during fetches from external program memory and middle and high order
address bytes during accesses to the external 24-bit external data memory space.

memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.

–6–

REV. 0

ADuC812

Mnemonic Type Function

ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and middle byte for 24-bit

address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.

EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from

internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch
all instructions from external program memory.

P0.7–P0.0 I/O Port 0 is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in that
(A0–A7) state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus

during accesses to external program or data memory. In this application it uses strong internal pull-ups
when emitting 1s.

TERMINOLOGY

ADC SPECIFICATIONS
Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition and full scale, a point
1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Full-Scale Error

This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan­tization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.

DAC SPECIFICATIONS
Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maxi­mum deviation from a straight line passing through the end­points of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital to Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.

REV. 0

–7–

ADuC812

ADuC812 ARCHITECTURE, MAIN FEATURES

The ADuC812 is a highly integrated high accuracy 12-bit data
acquisition system. At its core, the ADuC812 incorporates a high
performance 8-bit (8051-Compatible) MCU with on-chip repro­grammable nonvolatile Flash/EE program memory controlling a
multichannel (8-input channels), 12-bit ADC.

The chip incorporates all secondary functions to fully support the
programmable data acquisition core. These secondary functions
include User Flash/EE Data Memory, Watchdog Timer (WDT),
Power Supply Monitor (PSM) and various industry-standard
parallel and serial interfaces.

ADuC812 MEMORY ORGANIZATION

As with all 8051-compatible devices, the ADuC812 has separate
address spaces for Program and Data memory as shown in Fig­ure 1. Also as shown in Figure 1, an additional 640 Bytes of
Flash/EE Data Memory are available to the user. The Flash/EE
Data Memory area is accessed indirectly via a group of control
registers mapped in the Special Function Register (SFR) area.

PROGRAM MEMORY SPACE

READ ONLY

FFFFFFH

EXTERNAL

PROGRAM

MEMORY

SPACE

The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of bit
addressable memory space at bit addresses 00H through 7FH.

The SFR space is mapped in the upper 128 bytes of internal
data memory space. The SFR area is accessed by direct address­ing only and provides an interface between the CPU and all on­chip peripherals. A block diagram showing the programming
model of the ADuC812 via the SFR area is shown in Figure 3.

7FH

BANKS

SELECTED

VIA

BITS IN PSW

30H

20H

11

18H

10

10H

01

08H

00

00H

2FH

BIT-ADDRESSABLE SPACE

(BIT ADDRESSES 0–7FH)

1FH

17H

4 BANKS OF 8 REGISTERS

0FH

07H

RESET VALUE OF
STACK POINTER

R0–R7

2000H

1FFFH

EXTERNAL
PROGRAM

MEMORY

0000H

DATA MEMORY SPACE

READ/WRITE

SPECIAL

FUNCTION

REGISTERS

ACCESSIBLE

BY DIRECT

ADDRESSING

ONLY

FFH

80H

EA = 0

SPACE

FFFFFFH

000000H

EXTERNAL

DATA

MEMORY

SPACE
(24-BIT

ADDRESS

SPACE)

9FH

00H

UPPER

LOWER

(PAGE 159)

640 BYTES

FLASH/EE DATA

MEMORY

ACCESSED

INDIRECTLY

VIA SFR

CONTROL REGISTERS

(PAGE 0)

DATA MEMORY

FFH

ACCESSIBLE

80H
7FH

00H

ADDRESSING

ADDRESSING

128

128

EA = 1

INTERNAL

8K BYTE

FLASH/EE

PROGRAM

MEMORY

INTERNAL

SPACE

BY

INDIRECT

ONLY

ACCESSIBLE

BY

DIRECT

AND

INDIRECT

Figure 1. ADuC812 Program and Data Memory Maps

Figure 2. Lower 128 Bytes of Internal RAM

8K BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051-

COMPATIBLE

CORE

128-BYTE

SPECIAL
FUNCTION
REGISTER

AREA

640-BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

SELF-CALIBRATING

8-CHANNEL

HIGH SPEED

12-BIT ADC

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

2  12-BIT DACs

SERIAL I/O

PARALLEL I/O

WDT
PSM

Figure 3. ADuC812 Programming Model

ADC CIRCUIT INFORMATION
General Overview

The ADC conversion block incorporates a 5 µs, 8-channel,
12-bit, single supply A/D converter. This block provides the
user with multichannel mux, track/hold, on-chip reference,
calibration features and A/D converter. All components in this
block are easily configured via a 3-register SFR interface.

The A/D converter consists of a conventional successive­approximation converter based around a capacitor DAC. The
converter accepts an analog input range of 0 to +V

. A high

REF

precision, low drift and factory calibrated 2.5 V reference is

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ADuC812

provided on-chip. The internal reference may be overdriven via
the external V
range 2.3 V to AV

pin. This external reference can be in the

REF

.

DD

Single step or continuous conversion modes can be initiated in
software or, alternatively, by applying a convert signal to an
external Pin 25 (CONVST). Timer 2 can also be configured
to generate a repetitive trigger for ADC conversions. The ADC
may be configured to operate in a DMA Mode whereby the
ADC block continuously converts and captures samples to an
external RAM space without any interaction from the MCU
core. This automatic capture facility can extend through a
16 MByte external Data Memory space.

The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal Offset and Gain calibration registers, a
software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
users target system.

A voltage output from an on-chip temperature sensor propor­tional to absolute temperature can also be routed through the
front-end ADC multiplexor (effectively a 9th ADC channel
input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to V

. For this

REF

range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when

= 2.5 V. The ideal input/output transfer characteristic for

V

REF

the 0 to V

range is shown in Figure 4.

REF

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000
1LSB

0V

1LSB =

FS

4096

VOLTAGE INPUT

+FS
–1LSB

Figure 4. ADuC812 ADC Transfer Function

SFR Interface to ADC Block

The ADC operation is fully controlled via three SFRs, namely:

ADCCON1 – (ADC Control SFR #1)

The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.

SFR Address: EFH
SFR Power-On Default Value: 20H
Bit Addressable: NO

MD1 MD0 CK1 CK0 AQ1 AQ0 T2C EXC

Table I. ADCCON1 SFR Bit Designations

Bit Bit
Location Mnemonic Description

ADCCON1.7 MD1 The mode bits (MD1, MD0)
ADCCON1.6 MD0 select the active operating mode

of the ADC as follows:

MD1 MD0 Active Mode

0 0 ADC powered down.
0 1 ADC normal mode
1 0 ADC powered down

if not executing a
conversion cycle.

1 1 ADC standby if not

executing a conver­sion cycle.

ADCCON1.5 CK1 The ADC clock divide bits (CK1,
ADCCON1.4 CK0 CK0) select the divide ratio for

the master clock used to generate
the ADC clock. An ADC con­version will require 16 ADC
clocks in addition to the selected
number of acquisition clocks (see
AQ0/AQ1 below). The divider
ratio is selected as follows:

CK1 CK0 MCLK Divider

001
012
104
118

ADCCON1.3 AQ1 The ADC acquisition select bits
ADCCON1.2 AQ0 (AQ1, AQ0) select the time avail-

able for the input track/hold
amplifier to acquire the input
signal and is selected as follows:

AQ1 AQ0 #ADC Clks

001
012
103
114

Note: for analog input source
impedances of <8 kΩ, the default
AQ0/AQ1 selection of 00, i.e., 1
Acquisition Clock will suffice. For
source impedances greater than
this, it is recommended that you
increase the acquisition clock
selection to 2, 3 or 4 clocks.

ADCCON1.1 T2C The Timer 2 conversion bit (T2C)

is set to enable the Timer 2 over­flow bit to be used as the ADC
convert start trigger input.

ADCCON1.0 EXC The external trigger enable bit

(EXC) is set to allow the external
Pin 23 (CONVST) to be used as
the active low convert start input.
This input should be an active low
pulse (100 ns minimum pulsewidth)
at the required sample rate.

Note: In standby mode the ADC V
powered down mode all ADC peripherals are powered down thus minimizing
current consumption. Typical ADC current consumption is 1.6 mA at VDD = 5 V.

circuits are maintained on, while in

REF

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–9–

ADuC812

ADCCON2 – (ADC Control SFR #2)

The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.

SFR Address: D8H
SFR Power On Default Value: 00H
Bit Addressable: YES

ADCI DMA CCONV SCONV CS3 CS2 CS1 CS0

Table II. ADCCON2 SFR Bit Designations

Bit Bit
Location Mnemonic Description

ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is

set by hardware at the end of a
single ADC conversion cycle or at
the end of a DMA block conver­sion. ADCI is cleared by hardware
when the PC vectors to the ADC
Interrupt Service Routine.

ADCCON2.6 DMA The DMA mode enable bit (DMA)

is set by the user to initiate a pre­configured ADC DMA mode opera­tion. A more detailed description of
this mode is given below.

ADCCON2.5 CCONV The continuous conversion bit

(CCONV) is set by the user to
initiate the ADC into a continuous
mode of conversion. In this mode
the ADC starts converting based on
the timing and channel configura­tion already set up in the ADCCON
SFRs, the ADC automatically starts
an other conversion once a previous
conversion cycle has completed.

ADCCON2.4 SCONV The single conversion bit

(SCONV) is set by the user to
initiate a single conversion cycle.
The SCONV bit is automatically
reset to “0” on completion of the

single conversion cycle.
ADCCON2.3 CS3 The channel selection bits (CS3-0)
ADCCON2.2 CS2 allow the user to program the
ADCCON2.1 CS1 ADC channel selection under
ADCCON2.0 CS0 software control. Once a conver-

sion is initiated the channel

converted will be that pointed to

by these channel selection bits. In

DMA mode the channel selection

is derived from the channel ID

written to the external memory.

CS3 CS2 CS1 CS0 CH#

00000

00011

00102

00113

01004

01015

01106

01117

1000Temp Sensor

1 X X X Other

Combinations

1111DMA STOP

ADCCON3 – (ADC Control SFR #3)

The ADCCON3 register gives user software an indication of
ADC busy status.

SFR Address: F5H
SFR Power On Default Value: 00H
Bit Addressable: NO

BUSY RSVD RSVD RSVD CTYP CAL1 CAL0 CALST

Table III. ADCCON3 SFR Bit Designations

Bit Bit
Location Mnemonic Description

ADCCON3.7 BUSY The ADC busy status bit (BUSY)

is a read-only status bit that is set
during a valid ADC conversion or
calibration cycle. Busy is auto­matically cleared by the core at the
end of conversion or calibration.

ADCCON3.6 RSVD ADCCON3.0–3.6 are reserved
ADCCON3.5 RSVD (RSVD) for internal use. These
ADCCON3.4 RSVD bits will read as zero and should
ADCCON3.3 RSVD only be written as zero by user
ADCCON3.2 RSVD software.
ADCCON3.1 RSVD
ADCCON3.0 RSVD

ADC Internal Reference

If the internal reference is being used, both the V

REF

and C

REF

pins should be decoupled with 100 nF capacitors to AGND.
These decoupling capacitors should be placed very close to the
V

REF

and C

pins. For specified performance, it is recom-

REF

mended that when using an external reference, this reference
should be between 2.3 V and the analog supply AV

DD

.

If the internal reference is required for use external to the
MicroConverter, it should be buffered at the V

pin and a

REF

100 nF capacitor should be connected from this pin to AGND.

The internal 2.5 V is factory calibrated to an absolute accuracy
of 2.5 V ±50 mV. It should also be noted that the internal V

REF

will remain powered down until either of the DACs or the ADC
peripheral blocks are powered on by their respective enable bits.

Calibration

The ADC block also has four associated calibration SFRs.
These SFR’s drive calibration logic ensuring optimum perfor­mance from the 12-bit ADC at all times. As part of the power­on reset configuration, these SFRs are configured automatically
and transparently from factory programmed calibration con­stants. In many applications use of factory programmed calibra­tion constants will suffice; however, these calibration SFRs may
be overwritten by user code to further compensate for system­dependent offset and gain errors.

Calibration Overview

The ADC block incorporates calibration hardware that ensures
optimum performance from the ADC at all times. The calibra­tion modes are exercised as part of the ADuC812 internal factory
final test routines. The factory calibration results are stored in
Flash memory and are automatically downloaded on any power­on-reset event to initialize the ADC calibration registers. In

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