ANALOG DEVICES ADuC7129 Service Manual

Precision Analog Microcontroller

C

www.BDTIC.com/ADI

FEATURES

Analog I/O

Multichannel, 12-bit, 1 MSPS ADC

Up to 14 analog-to-digital converter (ADC) channels Fully differential and single-ended modes 0 to V

10-bit digital-to-analog converter (DAC)

32-bit 21 MHz direct digital synthesis (DDS) Current-to-voltage (I/V) conversion Integrated second-order low-pass filter (LPF) DDS input to DAC

100 Ω line driver On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator

Microcontroller

ARM7TDMI core, 16-/32-bit RISC architecture JTAG port supports code download and debug External watch crystal/clock source

41.78 MHz PLL with 8-way programmable divider

Optional trimmed on-chip oscillator

Memory

126 kB Flash/EE memory, 8 kB SRAM

analog input range

REF

ARM7TDMI MCU with 12-Bit ADC and DDS DAC

ADuC7128/ADuC7129

In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability

On-chip peripherals

2× UART, 2× I Up to 40-pin GPIO port 5× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor 16-bit PWM generator Quadrature encoder Programmable logic array (PLA)

Power

Specified for 3 V operation Active mode

11 mA (@ 5.22 MHz) 45 mA (@ 41.78 MHz)

Packages and temperature range

64-lead 9 mm × 9 mm LFCSP package, −40°C to 125°C 64-lead LQFP, −40°C to +125°C 80-lead LQFP, −40°C to +125°C

Tools

Low cost QuickStart development system Full third-party support

2

C and SPI serial I/O

FUNCTIONAL BLOCK DIAGRAM

REF

DD

GND

AGND

AV

IOGND

IOVDDIOGND

IOVDDDGND

ADC0

CMP0 CMP1

MP

V

RST

XCLKI

XCLKO

XCLK

OUT

REF

MUX

+ –

POR

OSC/PLL

PSM

SENSOR

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

12-BIT SAR

T/H

ADC 1MSPS

TEMP

BAND GAP

REFERENCE

5 GEN PURPOSE

CONTROLL ER

JTAG PLA SPI

JTAG P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.3

WITH ADDIT IONAL PERIPHERALS

TIMERS

WAKE-UP/

RTC TIMER

INTERRUPT

DDS

ARM7TDMI-BASED M CU

2 kBYTES

62 kBYTES

FLASH/EE

(31k ×

16 BITS)

2

C

I

DD

LV

10-BIT

IOUT DAC

I/V

LPF

DD

DACGND

DACV

VDAC

OUT

LD1TX

LD2TX

ADuC7129

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6

S1

S2

06020-001

64 kBYTES

FLASH/EE

(32k ×

16 BITS)

UART0 UART1

8192 BYTES

SRAM

(2k ×

32 BITS)

GPIO

CONTROL

PWM

QUAD

ENCODER

Figure 1.

ADuC7128/ADuC7129

www.BDTIC.com/ADI

REVISION HISTORY

4/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

GENERAL DESCRIPTION

The ADuC7128/ADuC7129 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating a high performance, multichannel analog-to-digital converter (ADC), DDS with line driver, 16-/32-bit MCU, and Flash/EE memory on a single chip.

The ADC consists of up to 14 single-ended inputs. The ADC ca

n operate in single-ended or differential input modes. The ADC input voltage is 0 to V temperature sensor, and voltage comparator complete the ADC peripheral set.

The ADuC7128/ADuC7129 integrate a differential line driver

utput. This line driver transmits a sine wave whose values are

o calculated by an on-chip DDS or a voltage output determined by the DACDAT MMR.

The devices operate from an on-chip oscillator and PLL, generating a

n internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated.

. Low drift band gap reference,

REF

The microcontroller core is an ARM7TDMI®, 16-/32-bit r

educed instruction set computer (RISC), offering up to 41 MIPS peak performance. There are 126 kB of nonvolatile Flash/EE provided on-chip, as well as 8 kB of SRAM. The ARM7TDMI core views all memory and registers as a single linear array.

On-chip factory firmware supports in-circuit serial download v

ia the UART serial interface port, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family.

The parts operate from 3.0 V to 3.6 V and are specified over an

dustrial temperature range of −40°C to +125°C. When operating

in at 41.78 MHz, the power dissipation is 135 mW. The line driver output, if enabled, consumes an additional 30 mW.

Rev. 0 | Page 3 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = IOVDD = 3.0 V to 3.6 V, V otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2

ADC Power-Up Time 5 s DC Accuracy

1, 2

Resolution 12 Bits Integral Nonlinearity

3

±0.7 ±1.5 LSB 2.5 V internal reference −40°C to +85°C

±2.0 LSB 1.0 V external reference

Differential Nonlinearity

3

±0.6 LSB 1.0 V external reference DC Code Distribution 1 LSB ADC input is a dc voltage

ENDPOINT ERRORS

4

Offset Error ±5 LSB Offset Error Match ±1 LSB Gain Error ±5 LSB Gain Error Match ±1 LSB

DYNAMIC PERFORMANCE FIN = 10 kHz sine wave, f

Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −80 dB Crosstalk Between Channel 12 and

Channel 13

ANALOG INPUT

Input Voltage Ranges

Differential Mode

5

Single-Ended Mode 0 to V Leakage Current ±15 µA 85°C to 125°C only ±1 ±3 µA −40°C to +85°C Input Capacitance 20 pF During ADC acquisition

ON-CHIP VOLTAGE REFERENCE 0.47 µF from V

Output Voltage 2.5 V Accuracy ±2.5 mV Measured at TA = 25°C Reference Drop When DAC Enabled 9 mV Reference drop when DAC enabled Reference Temperature Coefficient ±40 ppm/°C Power Supply Rejection Ratio 80 dB Output Impedance 40 Ω Internal V

EXTERNAL REFERENCE INPUT

Power-On Time 1 ms

REF

6

Input Voltage Range 0.625 AVDD V Input Impedance 38 kΩ

DAC CHANNEL SPECIFICATIONS

VDAC Output RL = 5 kΩ, CL = 100 pF

Voltage Swing

I/V Output Resistance 7 Ω V mode selected Low-Pass Filter 3 dB Point 1 MHz 2-pole at 1.5 MHz and 2 MHz Resolution 10 Bits

= 2.5 V internal reference, f

REF

±0.7 ±2.0 LSB 2.5 V internal reference 85°C to 125°C only

±0.5 +1/−0.9 LSB 2.5 V internal reference

69 dB

−60 dB

V

(0.33 × V

0.2 × V

1.33

REF

) ×

±

= 41.78 MHz. All specifications TA = T

CORE

± V

/2 V

CM

REF

V

REF

V

is the internal 2.5 V reference

REF

MAX

to AGND

REF

to T

SAMPLE

, unless

MIN

= 1 MSPS

Rev. 0 | Page 4 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

Relative Accuracy ±2 LSB Differential Nonlinearity, +VE 0.35 LSB Differential Nonlinearity, −VE −0.15 LSB Offset Error −190 mV Gain Error +150 mV Voltage Output Settling Time

to 0.1%

Line Driver Output

Total Harmonic Distortion −52 dB PLM operating at 691.2 kHz Output Voltage Swing ±1.768 V rms

COMMON MODE

AC Mode 1.65 V

DC Mode 1.5 V

DIFFERENTIAL INPUT IMPEDANCE 11 13 kΩ Line driver buffer disabled

Leakage Current LD1TX, LD2TX 7 A Line driver buffer disabled

Short-Circuit Current ±50 mA No protection diodes, max allowable current Line Driver Tx Power-Up Time 20 µs

COMPARATOR

Input Offset Voltage ±15 mV Input Bias Current 1 µA Input Voltage Range AGND AVDD − 1.2 V Input Capacitance 7 pF Hysteresis

3, 5

Response Time 1 µs

TEMPERATURE SENSOR

Voltage Output at 25°C 780 mV Voltage Temperature Coefficient −1.3 mV/°C

Accuracy ±3 °C POWER SUPPLY MONITOR (PSM) IOV

Trip Point Selection 2.79 V Two selectable trip points

DD

3.07 V

Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage GLITCH IMMUNITY ON RST PIN

WATCHD OG T IME R ( WDT )

3

Timeout Period 0 ms

512 sec FLASH/EE MEMORY

7, 8

Endurance 10,000 Cycles

Data Retention 20 Years TJ = 85°C DIGITAL INPUTS All digital inputs, including XCLKI and XCLKO

Logic 1 Input Current (Leakage

Current)

Logic 0 Input Current (Leakage

Current)

−80 +125 µA V

Input Capacitance 15 pF

5 s

As measured into a range of specified loads (see Figure 2) at LD1TX and LD2TX, unless other

wise noted

Each output has a common mode of 0.5 V × AV and swings 0.5 V × V V

is the internal 2.5 V reference

REF

Each output has a common mode of 0.5 V × V and swings 0.6 V × V

is the internal 2.5 V reference

V

REF

2 15 mV

Hysteresis can be turned on or off via the

YST bit in the CMPCON register

CMPH Response time can be modified via the CMPRES

bits in the CMPC

50 µs

±0.2 ±1 µA V

−40 −65 A V

= VDD or V

INH

= 0 V, except TDI

INL

= 0 V, TDI Only

INL

REF

ON register

= 5 V

INH

above and below this;

DD

REF

Rev. 0 | Page 5 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

V

, Input Low Voltage 0.8 V

INL

V

, Input High Voltage 2.0 V

INH

Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs)

VT+ 1.65 V VT− 1.2 V VT+ − VT− 0.75 V

LOGIC OUTPUTS

VOH, Output High Voltage IOVDD −

VOL, Output Low Voltage 0.4 V I

CRYSTAL INPUTS XCLKI and XCLKO

V

, Input Low Voltage 1.1 V Logic inputs, XCLKI only

INL

V

, Input High Voltage 1.7 V Logic inputs, XCLKI only

INH

XCLKI, Input Capacitance 20 pF XCLKO, Output Capacitance 20 pF

MCU CLOCK RATE (PLL)

326.4 kHz (32.768 kHz x 1275)/128

41.77920 MHz (32.768 kHz x 1275)/1 INTERNAL OSCILLATOR 32.768 kHz

Tolerance ±3 % −40°C to 85°C ±4 % 85°C to 125°C only

STARTUP TIME Core clock = 41.78 MHz

At Power-On 70 ms From Sleep Mode 1.6 ms From Stop Mode 1.6 ms

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns

POWER REQUIREMENTS

Power Supply Voltage Range

IOVDD, AVDD, and DACVDD (Supply

LVDD (Regulator Output from Chip) 2.5 2.6 2.7 V

Power Supply Current

Normal Mode 15 19 mA 5.22 MHz clock

42 49 mA 41.78 MHz clock Additional Line Driver Tx Supply

Pause Mode 37 mA 41.78 MHz clock Sleep Mode 0.3 3.6 mA External crystal or internal OSC ON

1

All ADC channel specifications are guaranteed during normal MicroConverter core operation.

2

Apply to all ADC input channels.

3

Not production tested; supported by design and/or characterization of data on production release.

4

Measured using an external AD845 op amp as an input buffer stage, as shown in Figure 42. Based on external ADC system components.

5

The input signal can be centered on any dc common-mode voltage (VCM), as long as this value is within the ADC voltage input range specified.

6

When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0.

7

Endurance is qualified as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C.

8

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.

9

Test carried out with a maximum of eight I/Os set to a low output level.

10

Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode = 3.6 V supply, pause mode = 3.6 V

supply, sleep mode = 3.6 V supply.

11

IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.

3

9

Voltage to Chip)

Current

10, 11

All logic inputs, including XCLKI and XCLKO

V I

SOURCE

= 1.6 mA

400 mV

= 1.6 mA

SINK

Eight programmable core clock selections within this r

ange

3.0 3.6 V

30 mA 691 kHz, maximum load (see Figure 2)

Rev. 0 | Page 6 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Line Driver Load

100nF

LD1TX

94

57

27.5µH

8.9µH

06020-002

118

100nF

94

LD2TX

LD1TX

LD2TX

Figure 2. Line Driver Load Minimum (Top) and Maximum (Bottom)

Rev. 0 | Page 7 of 92

ADuC7128/ADuC7129

A

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

Table 2. External Memory Write Cycle

Parameter Min Typ Max Unit

CLK UCLK t

MS_AFTER_CLKH

t

ADDR_AFTER_CLKH

t

AE_H_AFTER_MS

tAE (XMxPAR[14:12] + 1) × CLK t

HOLD_ADDR_AFTER_AE_L

t

HOLD_ADDR_BEFORE_WR_L

t

WR_L_AFTER_AE_L

t

DATA_AFTER_WR_L

tWR (XMxPAR[7:4] + 1) × CLK t

WR_H_AFTER_CLKH

t

HOLD_DATA_AFTER_WR_H

t

BEN_AFTER_AE_L

t

RELEASE_MS_AFTER_WR_H

/D[15:0] FFFF 9ABC 5678 9ABE 1234

0 4 ns

4 8 ns

½ CLK

½ CLK + (!XMxPAR[10]) × CLK

(!XMxPAR[8]) × CLK ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK 8 12 ns

0 4 ns

(!XMxPAR[8]) × CLK

½ CLK

(!XMxPAR[8] + 1) × CLK

CLK

t

MS_AFTER_CLKH

MS

t

WR_L_AFTER_AE_L

t

WR

t

WR_H_AFTER_CLKH

t

HOLD_DATA_AFTER_W R_H

t

DATA_AFTER_WR_L

t

BEN_AFTER_AE_L

Figure 3. External Memory Write Cycle

t

RELEASE_MS_AFTER_WR_H

AE

WS

RS

BLE

BHE

A16

t

AE_H_AFTER_MS

t

HOLD_ADDR_AFTER_AE _L

t

HOLD_ADDR_BEFO RE_WR_L

t

ADDR_AFTER_CLKH

t

AE

06020-065

Rev. 0 | Page 8 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Table 3. External Memory Read Cycle

Parameter Min Typ Max Unit

CLK 1/MD Clock ns typ × (CDPOWCON[2:0] + 1) t

MS_AFTER_CLKH

t

ADDR_AFTER_CLKH

t

AE_H_AFTER_MS

tAE (XMxPAR[14:12] + 1) × CLK t

HOLD_ADDR_AFTER_AE_L

t

RD_L_AFTER_AE_L

t

RD_H_AFTER_CLKH

tRD (XMxPAR[3:0] + 1) × CLK t

DATA_BEFORE_RD_H

t

DATA_AFTER_RD_H

t

RELEASE_WS_AFTER_RD_H

4 8 ns

4 16 ns

½ CLK

½ CLK + (! XMxPAR[10] ) × CLK

½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK

0 4 ns

16 ns

8 + (! XMxPAR[9]) × CLK

1 × CLK

0ns 50ns 100ns 150ns 200ns 250n s 300ns 350ns 400ns

CLK

ECLK

t

GP0

WS

RS

A/D[15:0 ]

BLE

BHE

XA16

AE

FFFF 2348 XXXX CDEF XX 234A XX 89AB

MS_AFTER_CLKH

t

AE_H_AFTER_M S

t

ADDR_AFTER_CLKH

SAMPLE_ADDR_0

t

AE

t

RD_L_AFTER_AE _L

t

RD

t

HOLD_ADDR_AF TER_AE_L

t

RD_H_AFTER_CLK H

t

DATA_BEFORE_RD_H

t

DATA_AFTER_RD_ H

SAMPLE_ADDR_1

SAMPLE_DATA_HSAMPLE_DATA_L

t

RELEASE_WS_ AFTER_RD_H

Figure 4. External Memory Read Cycle

6020-067

Rev. 0 | Page 9 of 92

ADuC7128/ADuC7129

S

www.BDTIC.com/ADI

I2C® Timing Specifications

2

Table 4. IP

Parameter Description Slave Min Slave Max Master Typ Unit

tL SCLOCK low pulse width1 200 1360 ns tH SCLOCK high pulse width1 100 1140 ns t

SHD

t

DSU

t

DHD

t

RSU

t

PSU

t

BUF

tR Rise time for both SCLOCK and SDATA 100 300 200 ns tF Fall time for both SCLOCK and SDATA 60 300 20 ns t

SUP

1

t

HCLK

P

C Timing in Fast Mode (400 kHz)

Start condition hold time 300 251,350 ns Data setup time 100 740 ns

Data hold time 0 400 ns Setup time for repeated start 100 12.51350 ns Stop condition setup time 100 400 ns Bus-free time between a stop condition and a start condition 1.3 μs

Pulse width of spike suppressed 50 ns

depends on the clock divider or CD bits in the PLLCON MMR, t

t

BUF

DATA (I/O )

SCLOCK (I)

t

PSU

PS

STOP

CONDITION

START

CONDITION

t

DSU

MSB LSB ACK MSB

t

SHD

HCLK

t

DHD

Figure 5. I

= t

/2CD.

UCLK

t

SUP

t

DSU

t

H

t

L

2

P

C-Compatible Interface Timing

t

R

t

DHD

t

RSU

t

SUP

S(R)

REPEATED

START

F

t

R

1982–71

t

F

6020-003

Rev. 0 | Page 10 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

SPI Timing Specifications

Table 5. SPI Master Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit

tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

Data output valid after SCLOCK edge 2 × t

DAV

t

Data input setup time before SCLOCK edge

DSU

t

Data input hold time after SCLOCK edge

DHD

tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns

1

t

depends on the clock divider or CD bits in the PLLCON MMR, t

HCLK

2

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

1

2

= t

HCLK

(SPIDIV + 1) × t (SPIDIV + 1) × t

2

1 × t

ns

UCLK

2 × t

ns

UCLK

/2CD.

UCLK

ns

HCLK

ns

HCLK

+ 2 × t

ns

UCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MOSI MSB BIT 6 TO BIT 1 LSB

MISO MSB IN BIT 6 TO BIT 1 LSB IN

t

SH

t

DAV

t

DSU

t

DHD

t

SL

t

DF

t

DR

t

SR

t

SF

6020-004

Figure 6. SPI Master Mode Timing (PHASE Mode = 1)

Rev. 0 | Page 11 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Table 6. SPI Master Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit

tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

Data output valid after SCLOCK edge 2 × t

DAV

t

Data output setup before SCLOCK edge 75 ns

DOSU

t

Data input setup time before SCLOCK edge

DSU

t

Data input hold time after SCLOCK edge

DHD

tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns

1

t

depends on the clock divider or CD bits in the PLLCON MMR, t

HCLK

2

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MOSI MSB BIT 6 TO BIT 1 LSB

t

DOSU

1

2

= t

HCLK

t

SH

t

DAV

t

DF

/2CD.

UCLK

t

SL

t

DR

(SPIDIV + 1) × t (SPIDIV + 1) × t

1 × t

ns

UCLK

2 × t

ns

UCLK

t

SR

ns

HCLK

ns

HCLK

+ 2 × t

HCLK

t

SF

ns

UCLK

MISO MSB IN BIT 6 TO BIT 1 LSB IN

t

DSU

t

DHD

Figure 7. SPI Master Mode Timing (PHASE Mode = 0)

06020-005

Rev. 0 | Page 12 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Table 7. SPI Slave Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit

tCS CS to SCLOCK edge tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

Data output valid after SCLOCK edge 2 × t

DAV

t

Data input setup time before SCLOCK edge11 × t

DSU

t

Data input hold time after SCLOCK edge

DHD

tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns t

CS high after SCLOCK edge 0 ns

SFS

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

2

t

depends on the clock divider or CD bits in the PLLCON MMR, t

HCLK

CS

1

2

= t

HCLK

2 × t

ns

UCLK

(SPIDIV + 1) × t (SPIDIV + 1) × t

ns

/2CD.

UCLK

2 × t

ns

UCLK

1

UCLK

ns

HCLK

ns

HCLK

+ 2 × t

ns

UCLK

t

CS

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MISO MSB BIT 6 TO BIT 1 LSB

MOSI MSB IN BIT 6 TO BIT 1 LSB IN

t

SH

t

DAV

t

DSU

t

DHD

Figure 8. SPI Slave Mode Tim

t

SL

t

DF

t

DR

t

ing (PHASE Mode = 1)

t

SFS

SR

t

SF

06020-006

Rev. 0 | Page 13 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Table 8. SPI Slave Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit

tCS CS to SCLOCK edge tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

Data output valid after SCLOCK edge 2 × t

DAV

t

Data input setup time before SCLOCK edge

DSU

t

Data input hold time after SCLOCK edge

DHD

tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLOCK rise time 5 12.5 ns tSF SCLOCK fall time 5 12.5 ns t

Data output valid after CS edge 25 ns

DOCS

t

CS high after SCLOCK edge 0 ns

SFS

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

2

t

depends on the clock divider or CD bits in the PLLCON MMR, t

HCLK

CS

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MISO

t

DOCS

1

2

1

= t

HCLK

t

CS

t

SH

t

DF

MSB BIT 6 TO BIT 1 LSB

t

DAV

2 × t

ns

UCLK

(SPIDIV + 1) × t (SPIDIV + 1) × t

1

1 × t

ns

UCLK

2 × t

ns

UCLK

/2CD.

UCLK

SL

t

DR

ns

HCLK

ns

HCLK

+ 2 × t

HCLK

t

SFS

t

SR

t

SF

ns

UCLK

MOSI

MSB IN BIT 6 TO BIT 1 LSB IN

t

DSU

t

DHD

Figure 9. SPI Slave Mode Tim

ing (PHASE Mode = 0)

Rev. 0 | Page 14 of 92

06020-007

ADuC7128/ADuC7129

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

DVDD = IOVDD, AGND = REFGND = DACGND = GND T

= 25°C, unless otherwise noted.

A

Table 9.

Parameter Rating

AVDD to DVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V IOVDD to IOGND, AVDD to AGND −0.3 V to +6 V Digital Input Voltage to IOGND −0.3 V to IOVDD + 0.3 V Digital Output Voltage to IOGND −0.3 V to IOVDD + 0.3 V V

to AGND −0.3 V to AVDD + 0.3 V

REF

Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Output to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range

Industrial –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C

θJA Thermal Impedance

64-Lead LFCSP 24°C/W

64-Lead LQFP 47°C/W

80-Lead LQFP 38°C/W Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec) 240°C

RoHS Compliant Assemblies

(20 sec to 40 sec)

260°C

REF

.

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one

e.

tim

ESD CAUTION

Rev. 0 | Page 15 of 92

ADuC7128/ADuC7129

C

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TRIP

DD

REF

AVDDAGND

DACGND

V

P4.5

P4.4

P4.3/PWM

P4.2

P1.0/SPM0

ADC4

ADC3/CMP1

ADC2/CMP0

ADC1

ADC0

646362616059585756555453525150

DACV

P1.1/SPM1

49

VDAC

ADC10

GND

ADCNEG

ADC12/LD1TX ADC13/LD2TX

P4.6/SPM10 P4.7/SPM11

P0.0/BM/CMP

P0.6/T1/MRST

ADC5

OUT

ADC9

REF

AV

AGND

TMS

TDI

OUT

DD

10 11 12 13 14 15 16

PIN 1

1

INDICATO R

2 3 4 5 6 7 8 9

171819202122232425262728293031

TCK

TDO

IOGND

ADuC7128

TOP VIEW

(Not to Scale)

DDLVDD

IOV

DGND

P3.0/PWM1

RST

/TRST

BUSY

P3.1/PWM2

P3.2/PWM3

P3.3/PWM4

P3.4/PWM5

P3.5/PWM6

P0.3/AD

48

P1.2/SPM2

47

P1.3/SPM3

46

P1.4/SPM4

45

P1.5/SPM5

44

P4.1/S2

43

P4.0/S1

42

IOV

DD

41

IOGND

40

P1.6/SPM6

39

P1.7/SPM7

38

DGND

37

PV

DD

36

XCLKI

35

XCLKO

34

P0.7/SPM8/ECLK/XCLK

33

P2.0/SPM9

32

BUSY

P0.4/IRQ 0/CONVST

P0.5/IRQ1/ADC

6020-063

Figure 10. ADuC7128 Pin Configuration

Table 10. ADuC7128 Pin Function Descriptions

Pin No.

Mnemonic Type

1

Description

1 ADC5 I Single-Ended or Differential Analog Input 5/Line Driver Input. 2 VDAC

O Output from DAC Buffer.

OUT

3 ADC9 I Single-Ended or Differential Analog Input 9. 4 ADC10 I Single-Ended or Differential Analog Input 10. 5 GND

S

REF

Ground Voltage Reference for the ADC. For optimal per

formance, the analog power supply

should be separated from IOGND and DGND.

6 ADCNEG I

Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be

onnected to the ground of the signal to convert. This bias point must be between

c

0 V and 1 V. 7, 58 AVDD S Analog Power. 8 ADC12/LD1TX I/O Single-Ended or Differential Analog Input 12/DAC Differential Negative Output. 9 ADC13/LD2TX I/O Single-Ended or Differential Analog Input 13/DAC Differential Positive Output. 10, 57 AGND S Analog Ground. Ground reference point for the analog circuitry. 11 TMS I JTAG Test Port Input, Test Mode Select. Debug and download access. 12 TDI I JTAG Test Port Input, Test Data In. Debug and download access. 13 P4.6/SPM10 I/O General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10. 14 P4.7/SPM11 I/O General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11. 15

P0.0/BM

/CMP

OUT

I/O

General-Purpose Input and Output Port 0.0/Boot Mode. The ADuC7128 enters download

mode if BM

is low at reset and executes code if BM is pulled high at reset through a 1 kΩ

resistor/voltage comparator output. 16

P0.6/T1/MRST

O General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output.

17 TCK I JTAG Test Port Input, Test Clock. Debug and download access. 18 TDO O JTAG Test Port Output, Test Data Out. Debug and download access. 19, 41 IOGND S Ground for GPIO. Typically connected to DGND. 20, 42 IOVDD S 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

Rev. 0 | Page 16 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Pin No. Mnemonic Type

21 LVDD S

22 DGND S Ground for Core Logic. 23 P3.0/PWM1 I/O General-Purpose Input and Output Port 3.0/PWM1 Output. 24 P3.1/PWM2 I/O General-Purpose Input and Output Port 3.1/PWM2 Output. 25 P3.2/PWM3 I/O General-Purpose Input and Output Port 3.2/PWM3 Output. 26 P3.3/PWM4 I/O General-Purpose Input and Output Port 3.3/PWM4 Output. 27

28 29 P3.4/PWM5 I/O General-Purpose Input and Output Port 3.4/PWM5 Output.

30 P3.5/PWM6 I/O General-Purpose Input and Output Port 3.5/PWM6 Output. 31

32 P0.5/IRQ1/ADC

33 P2.0/SPM9 I/O General-Purpose Input and Output Port 2.0/Serial Port Mux Pin 9. 34 P0.7/SPM8/ECLK/XCLK I/O

35 XCLKO O Output from the Crystal Oscillator Inverter. 36 XCLKI I Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 37 PVDD S

38 DGND S Ground for PLL. 39 P1.7/SPM7 I/O General-Purpose Input and Output Port 1.7/Serial Port Mux Pin 7. 40 P1.6/SPM6 I/O General-Purpose Input and Output Port 1.6/Serial Port Mux Pin 6. 43 P4.0/S1 I/O General-Purpose Input and Output Port 4.0/Quadrature Input 1. 44 P4.1/S2 I/O General-Purpose Input and Output Port 4.1/Quadrature Input 2. 45 P1.5/SPM5 I/O General-Purpose Input and Output Port 1.5/Serial Port Mux Pin 5. 46 P1.4/SPM4 I/O General-Purpose Input and Output Port 1.4/Serial Port Mux Pin 4. 47 P1.3/SPM3 I/O General-Purpose Input and Output Port 1.3/Serial Port Mux Pin 3. 48 P1.2/SPM2 I/O General-Purpose Input and Output Port 1.2/Serial Port Mux Pin 2. 49 P1.1/SPM1 I/O General-Purpose Input and Output Port 1.1/Serial Port Mux Pin 1. 50 P1.0/SPM0 I/O General-Purpose Input and Output Port 1.0/Serial Port Mux Pin 0. 51 P4.2 I/O General-Purpose Input and Output Port 4.2. 52 P4.3/ PWM 53 P4.4 I/O General-Purpose Input and Output Port 4.4. 54 P4.5 I/O General-Purpose Input and Output Port 4.5. 55 V

56 DACGND S Ground for the DAC. Typically connected to AGND. 59 DACVDD S

60 ADC0 I Single-Ended or Differential Analog Input 0. 61 ADC1 I Single-Ended or Differential Analog Input 1. 62 ADC2/CMP0 I Single-Ended or Differential Analog Input 2/Comparator Positive Input. 63 ADC3/CMP1 I Single-Ended or Differential Analog Input 3/Comparator Negative Input. 64 ADC4 I Single-Ended or Differential Analog Input 4.

1

I = input, O = output, S = supply.

P0.3/ADC

RST

P0.4/IRQ0/CONVST

I/O

REF

/TRST

BUSY

I/O

BUSY

I/O General-Purpose Input and Output Port 4.3/PWM Safety Cutoff.

TRIP

1

Description

2.5 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 µF capacitor to DGND

I/O

I Reset Input (Active Low).

I/O

General-Purpose Input and Output Port 3.3/ADC Debug and download access.

General-Purpose Input and Output Port 0.5/External I Conversion Input Signal for ADC.

General-Purpose Input and Output Port 0.6/External Interrupt Request 1, Active High/ADC Signal.

General-Purpose Input and Output Port 0.7/Serial P Clock Signal/Input to the Internal Clock Generator Circuits.

2.5 V PLL Supply. Must be connected to a 0.1 µF

2.5 V LDO output.

2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the nternal reference.

i

Power Supply for the DAC. This must be supplied with 2.5 output.

.

Si gna l/J TAG Tes t Po r t Input, Test Reset.

BUSY

nterrupt Request 0, Active High/Start

ort Mux Pin 8/Output for the External

capacitor to DGND. Should be connected to

V. This can be connected to the LDO

BUSY

Rev. 0 | Page 17 of 92

ADuC7128/ADuC7129

K

C

www.BDTIC.com/ADI

/AD11

TRIP

DD

ADC3/CMP179ADC2/CMP078ADC177ADC076ADC1175DACV

80

74

AV

73

DD

AV

AGND71AGND70DACGND69V

72

REF

REFGND67IOGND66P4.5/AD1365P4.4/AD1264P4.3/PWM

68

P4.2/AD1062P1.0/SPM061P1.1/SPM1

63

VDAC

ADC12/LD1TX ADC13/LD2TX

TDI/P0.1/BLE

P4.6/SPM10/AD14 P4.7/SPM11/AD15

P0.0/BM/CMP

P0.6/T1/MRST

ADC4 ADC5 ADC6 ADC7

/ADC8

OUT

ADC9

ADC10

GND

ADCNEG

AV

AGND

P2.3/AE

/MS0

OUT

REF

TMS

39

BUSY

P0.5/IRQ1/ADC

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

P2.0/SPM9

P1.2/SPM2 P1.3/SPM3 P1.4/SPM4 P1.5/SPM5 P4.1/S2/AD9 P4.0/S1/AD8 IOV

DD

IOGND P1.6/SPM6 P1.7/SPM7 P2.2/RS P2.1/WS P2.7/MS3 P3.7/AD7 P3.6/AD6 DGND PV

DD

XCLKI XCLKO P0.7/SPM8/ECLK/XCL

6020-064

1

PIN 1

2 3

4 5 6 7

8

9 10

DD

11 12 13 14 15 16 17 18 19 20

21

22

23

24

25

DD

TCK

TDO/P0.2/BHE

DD

LV

IOV

IOGND

26

27

DGND

ADuC7129

TOP VIEW

(Not to Scale)

P3.0/PWM1/AD028P3.1/PWM2/AD129P3.2/PWM3/AD230P3.3/PWM4/AD3

31

32

P2.4/MS0

35

33

P2.5/MS134P2.6/MS2

/TRST/A16

BUSY

P0.3/AD

38

36

RST

P3.4/PWM5/AD437P3.5/PWM6/AD5

P0.4/IRQ0/CONVST/MS1

Figure 11. ADuC7129 Pin Configuration

Table 11. ADuC7129 Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1 ADC4 I Single-Ended or Differential Analog Input 4. 2 ADC5 I Single-Ended or Differential Analog Input 5. 3 ADC6 I Single-Ended or Differential Analog Input 6. 4 ADC7 I Single-Ended or Differential Analog Input 7. 5 VDAC

/ADC8 I Output from DAC Buffer/Single-Ended or Differential Analog Input 8.

OUT

6 ADC9 I Single-Ended or Differential Analog Input 9. 7 ADC10 I Single-Ended or Differential Analog Input 10. 8 GND

S

REF

Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND.

9 ADCNEG I

Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between

0 V and 1 V. 10, 73, 74 AVDD S 3.3 V Analog Supply. 11 ADC12/LD1TX I/O Single-Ended or Differential Analog Input 12/DAC Differential Negative Output. 12 ADC13/LD2TX I/O Single-Ended or Differential Analog Input 13/DAC Differential Positive Output. 13 AGND S Analog Ground. Ground reference point for the analog circuitry. 14 TMS I JTAG Test Port Input, Test Mode Select. Debug and download access. 15

TDI/P0.1/BLE

I/0

JTAG Test Port Input, Test Data In. Debug and download access/general-purpose input and

output Port 0.1/External Memory BLE

.

16 P2.3/AE I/O General-Purpose Input and Output Port 2.3/AE Output.

Rev. 0 | Page 18 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Pin No. Mnemonic Type

17 P4.6/SPM10/AD14 I/O General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10/External Memory AD14. 18 P4.7/SPM11/AD15 I/O General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11/External Memory AD15. 19

20 21 TCK I JTAG Test Port Input, Test Clock. Debug and download access. 22

23, 53, 67 IOGND S Ground for GPIO. Typically connected to DGND. 24, 54 IOVDD S 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 25 LVDD S

26 DGND S Ground for Core Logic. 27 P3.0/PWM1/AD0 I/O General-Purpose Input and Output Port 3.0/PWM1 Output/External Memory AD0. 28 P3.1/PWM2/AD1 I/O General-Purpose Input and Output Port 3.1/PWM2 Output/External Memory AD1. 29 P3.2/PWM3/AD2 I/O General-Purpose Input and Output Port 3.2/PWM3 Output/External Memory AD2. 30 P3.3/PWM4/AD3 I/O General-Purpose Input and Output Port 3.3/PWM4 Output//External Memory AD3. 31 P2.4/MS0 I/O General-Purpose Input and Output Port 2.4/Memory Select 0. 32

33 P2.5/MS1 I/O General-Purpose Input and Output Port 2.5/Memory Select 1. 34 P2.6/MS2 I/O General-Purpose Input and Output Port 2.6/Memory Select 2. 35 36 P3.4/PWM5/AD4 I/O General-Purpose Input and Output Port 3.4/PWM5 Output/External Memory AD4. 37 P3.5/PWM6/AD5 I/O General-Purpose Input and Output Port 3.5/PWM6 Output/External Memory AD5. 38

39 P0.5/IRQ1/ADC

40 P2.0/SPM9 I/O General-Purpose Input and Output Port 2.0/Serial Port Mux Pin 9. 41 P0.7/SPM8/ECLK/XCLK I/O

42 XCLKO O Output from the Crystal Oscillator Inverter. 43 XCLKI I Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 44 PVDD S

45 DGND S Ground for PLL. 46 P3.6/AD6 I/O General-Purpose Input and Output Port 3.6/External Memory AD6. 47 P3.7/AD7 I/O General-Purpose Input and Output Port 3.7/External Memory AD7. 48 P2.7/MS3 I/O General-Purpose Input and Output Port 2.7/Memory Select 3. 49

50 51 P1.7/SPM7 I/O General-Purpose Input and Output Port 1.7/Serial Port Mux Pin 7. 52 P1.6/SPM6 I/O General-Purpose Input and Output Port 1.6/Serial Port Mux Pin 6. 55 P4.0/S1/AD8 I/O General-Purpose Input and Output Port 4.0/Quadrature Input 1/External Memory AD8. 56 P4.1/S2/AD9 I/O General-Purpose Input and Output Port 4.1/Quadrature Input 2/External Memory AD9. 57 P1.5/SPM5 I/O General-Purpose Input and Output Port 1.5/Serial Port Mux Pin 5. 58 P1.4/SPM4 I/O General-Purpose Input and Output Port 1.4/Serial Port Mux Pin 4. 59 P1.3/SPM3 I/O General-Purpose Input and Output Port 1.3/Serial Port Mux Pin 3. 60 P1.2/SPM2 I/O General-Purpose Input and Output Port 1.2/Serial Port Mux Pin 2. 61 P1.1/SPM1 I/O General-Purpose Input and Output Port 1.1/Serial Port Mux Pin 1. 62 P1.0/SPM0 I/O General-Purpose Input and Output Port 1.0/Serial Port Mux Pin 0.

P0.0/BM

P0.6/T1/MRST

TDO/P0.2/BHE

P0.3/ADC

RST

P0.4/IRQ0/CONVST

P2.1/WS P2.2/RS

/CMP

OUT

/TRST/A16

BUSY

/MS0

/MS1

I/O

BUSY

1

Description

I/O

O General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/External Memory AE.

O

I/O

I Reset Input (Active Low).

I/O

I/O General-Purpose Input and Output Port 2.1/Memory Write Select. I/O General-Purpose Input and Output Port 2.1/Memory Read Select.

General-Purpose Input and Output Port 0.0 /Boot Mode. The ADuC7129 enters download mode if BM resistor/voltage comparator output/external memory MS0.

JTAG Test Port Output, Test Data Out. Debug and download access/general-purpose input and output Port 0.2/External Memory BHE

2.5 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 μF capacitor to DGND.

General-Purpose Input and Output Port 3.3/ADC Debug and download access/External Memory A16.

General-Purpose Input and Output Port 0.5/External Interrupt Request 0, Active High/Start Conversion Input Signal for ADC/External Memory MS1.

General-Purpose Input and Output Port 0.6/External Interrupt Request 1, Active High/ADC

General-Purpose Input and Output Port 0.7/Serial Port Mux Pin 8/Output for the External Clock Signal/Input to the Internal Clock Generator Circuits.

2.5 V PLL Supply. Must be connected to a 0.1 μF capacitor to DGND. Should be connected to 2.5 V LDO output.

is low at reset and executes code if BM is pulled high at reset through a 1 kΩ

.

Si gna l/J TAG Tes t Po r t Input, Test Reset.

BUSY

Signal.

BUSY

Rev. 0 | Page 19 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

Pin No. Mnemonic Type

63 P4.2/AD10 I/O General-Purpose Input and Output Port 4.2/External Memory AD10. 64 P4.3/PWM 65 P4.4/AD12 I/O General-Purpose Input and Output Port 4.4/External Memory AD12. 66 P4.5/AD13 I/O General-Purpose Input and Output Port 4.5/External Memory AD13. 68 REFGND S Ground for V 69 V

70 DACGND S Ground for the DAC. Typically connected to AGND. 71, 72 AGND S Analog Ground. 75 DACVDD S

76 ADC11 I Single-Ended or Differential Analog Input 11. 77 ADC0 I Single-Ended or Differential Analog Input 0. 78 ADC1 I Single-Ended or Differential Analog Input 1. 79 ADC2/CMP0 I Single-Ended or Differential Analog Input 2/Comparator Positive Input. 80 ADC3/CMP1 I Single-Ended or Differential Analog Input 3/Comparator Negative Input.

1

I = input, O = output, S = supply.

I/O

REF

/AD11 I/O General-Purpose Input and Output Port 4.3/PWM Safety Cutoff/External Memory AD11.

TRIP

1

Description

. Typically connected to DGND.

REF

2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the

internal reference.

Power Supply for the DAC. This must be supplied with 2.5 V. It can be connected to the LDO

output.

Rev. 0 | Page 20 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

f

= 774kSPS

S

0.8

0.6

0.4

0.2

0

(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 20001000 3000 4000

Figure 12. Typical INL Error, f

1.0

f

=1MSPS

S

0.8

0.6

0.4

0.2

0

(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 20001000 3000 4000

Figure 13. Typical INL Error, f

1.0

0.9

0.8

0.7

0.6

0.5

(LSB)

0.4

0.3

0.2

0.1

0

1.0 1.5 2. 0 2.5 3.0

Figure 14. Typical Worst Case INL Error vs. V

ADC CODE S

= 774 kSPS

S

ADC CODES

= 1 MSPS

S

WCP

EXTERNAL RE FERENCE (V )

REF

WCN

, fS = 774 kSPS

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

06020-008

06020-009

(LSB)

06020-010

1.0

f

= 774kSPS

S

0.8

0.6

0.4

0.2

0

(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 20001000 3000 4000

Figure 15. Typical DNL Error, f

1.0

f

= 1MSPS

S

0.8

0.6

0.4

0.2

0

(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 20001000 3000 4000

Figure 16. Typical DNL Error, f

0

–0.1

–0.2

–0.3

–0.4

–0.5

(LSB)

–0.6

–0.7

–0.8

–0.9

–1.0

1.0 1.5 2. 0 2.5 3.0

ADC CODE S

= 774 kSPS

S

ADC CODES

= 1 MSPS

S

WCN

EXTERNAL RE FERENCE (V )

Figure 17. Typical Worst Case DNL Error vs. V

WCP

, fS = 774 kSPS

REF

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

06020-011

06020-012

(LSB)

06020-013

Rev. 0 | Page 21 of 92

ADuC7128/ADuC7129

–

www.BDTIC.com/ADI

9000

8000

7000

6000

5000

4000

FREQUENCY

3000

2000

1000

0

1161 1162 1163

BIN

Figure 18. Code Histogram Plot

0

–20

–40

–60

–80

(dB)

–100

–120

–140

–160

0100

FREQUENCY (kHz)

Figure 19. Dynamic Performance, f

20

0

–20

–40

–60

(dB)

–80

–100

–120

–140

–160

0110050 200

FREQUENCY (kHz)

Figure 20. Dynamic Performance, f

f

= 774kSPS,

S

SNR = 69.3dB, THD = –80. 8dB, PHSN = –83.4dB

= 774 kSPS

S

f

=1MSPS,

S

SNR = 70.4dB, THD = –77. 2dB, PHSN = –78.9dB

50

= 1 MSPS

S

06020-014

200

06020-015

06020-016

75

70

65

60

55

SNR (dB)

50

45

40

1.01.52.02.53.0

SNR

THD

EXTERNAL REFERENCE (V)

Figure 21. Typical Dynamic Performance vs. V

1500

1450

1400

1350

1300

1250

CODE

1200

1150

1100

1050

1000

–50 0 50 100

TEMPERATURE (°C)

76

–78

–80

–82

–84

–86

–88

REF

150

Figure 22. On-Chip Temperature Sensor Voltage Output vs. Temperature

39.8

39.7

39.6

39.5

39.4

(mA)

39.3

39.2

39.1

39.0

38.9 –40 25 8501

TEMPERATURE (°C)

25

Figure 23. Current Consumption vs. Temperature @ CD = 0

THD (dB)

06020-017

06020-018

06020-019

Rev. 0 | Page 22 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

12.05

12.00

11.95

11.90

11.85

11.80

(mA)

11.75

11.70

11.65

11.60

11.55 –40 25 8501

TEMPERATURE (°C)

Figure 24. Current Consumption vs. Temperature @ CD = 3

7.85

7.80

7.75

7.70

7.65

(mA)

7.60

7.55

7.50

7.45

7.40 –40 25 8501

TEMPERATURE (°C)

Figure 25. Current Consumption vs. Temperature @ CD = 7

25

06020-020

25

06020-021

300

250

200

150

(µA)

100

50

0

–40 125

25 85

TEMPERATURE (°C)

Figure 26. Current Consumption vs. Temperature in Sleep Mode

37.4

37.2

37.0

36.8

(mA)

36.6

36.4

36.2

62.25 250. 00 500.00125.00 1000.00 SAMPLING FREQUENCY (kSPS)

Figure 27. Current Consumption vs. ADC Speed

06020-022

06020-023

Rev. 0 | Page 23 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

TERMINOLOGY

ADC SPECIFICATIONS

Integral Nonlinearity

The maximum deviation of any code from a straight line

ssing through the endpoints of the ADC transfer function.

pa The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB ch

ange between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) f

Gain Error

The deviation of the last code transition from the ideal AIN v

oltage (full scale − 1.5 LSB) after the offset error has been

adjusted out.

Signal to (Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the o

utput of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.

rom the ideal, that is, +½ LSB.

/2), excluding

S

The theoretical signal to (noise + distortion) ratio for an ideal N-

bit converter with a sine wave input is given by

Signal to (No

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

The ratio of the rms sum of the harmonics to the fundamental.

ise + Distortion) = (6.02 N + 1.76) dB

DAC SPECIFICATIONS

Relative Accuracy

Otherwise known as endpoint linearity, relative accuracy is

easure of the maximum deviation from a straight line passing

a m through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error.

Voltage Output Settling Time

The amount of time it takes for the output to settle to within a

B level for a full-scale input change.

1 LS

Rev. 0 | Page 24 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits.

The ARM7TDMI is an ARM7 core with the following four add

itional features:

, support for the Thumb® (16-bit) instruction set

• T

• D,

support for debug

• M

, support for long multiplications

• I, in

cludes the embedded ICE module to support

embedded system debugging

THUMB MODE (T)

An ARM® instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, called the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications.

However, the Thumb mode has two limitations:

umb code typically requires more instructions for the

• Th

same job. As a result, ARM code is usually best for maximizing the performance of the time-critical code.

• The Th

See the ARM7TDMI user guide for details on the core

rchitecture, the programming model, and both the ARM

a and Thumb instruction sets.

umb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. This result is achieved in fewer cycles than required on a standard ARM7 core.

EMBEDDEDICE (I)

EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor ha

lts and enters debug state. Once in a debug state, the processor registers can be inspected, as well as the Flash/EE, the SRAM, and the memory mapped registers.

EXCEPTIONS

ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are

• N

ormal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events.

• F

ast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ.

• Me

• A

• S

Typically, the programmer defines interrupt as IRQ, but for hig programmer can define interrupt as FIQ.

mory abort.

ttempted execution of an undefined instruction.

oftware interrupt instruction (SWI). This can be used to

make a call to an operating system.

her priority interrupt, that is, faster response time, the

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers.

When writing user-level programs, 15 general-purpose, 32-bit

egisters (R0 to R14), the program counter (R15), and the current

r program status register (CPSR) are usable. The remaining registers are used only for system-level programming and exception handling.

When an exception occurs, some of the standard registers are

eplaced with registers specific to the exception mode. All

r exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in

Figure 28. The fast interrupt mode has more registers (R8 to

R

12) for fast interrupt processing. Interrupt processing can begin without the need to save or restore these registers and, thus, saves critical time in the interrupt handling process.

More information relative to the programmer’s model and the ARM7TDMI co ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd.:

DI0029G, ARM7TDMI Technical Reference Manual

• D

DI-0100, ARM Architecture Reference Manual

re architecture can be found in the following

Rev. 0 | Page 25 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15 (PC)

CPSR

USER MODE

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

SPSR_FIQ

FIQ

MODE

R13_SVC

R14_SVC

SPSR_SVC

SVC

MODE

Figure 28. Register Organ

R13_ABT

R14_ABT

SPSR_ABT

USABLE IN USER MODE

SYSTEM MODES ONLY

R13_IRQ

R14_IRQ

SPSR_IRQ

ABORT

MODE

ization

IRQ

R13_UND

R14_UND

SPSR_UND

UNDEFINED

MODE

INTERRUPT LATENCY

The worst case latency for an FIQ consists of the following:

• The lo

• The t

ngest time the request can take to pass through the

synchronizer

ime for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers, including the PC

ime for the data abort entry

ime for FIQ entry

At the end of this time, the ARM7TDMI executes the instruction a

t Address 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 µs in a system using a continuous 41.78 MHz processor clock.

The maximum IRQ latency calculation is similar, but it must a

llow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode, where the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles.

t consists of the shortest time the request can take through the

I synchronizer plus the time to enter the exception mode.

Note that the ARM7TDMI always runs in ARM (32-bit) mode

hen in privileged modes, that is, when executing interrupt

6020-024

w service routines.

Rev. 0 | Page 26 of 92

ADuC7128/ADuC7129

www.BDTIC.com/ADI

MEMORY ORGANIZATION

The ADuC7128/ADuC7129 incorporate three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 29.

Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section.

0xFFFFFFFF

0xFFFF0000

0x0009F800

0x00080000

0x00041FFF

0x00040000

0x0001FFFF

0x00000000

Figure 29. Physical Memory Map

MMRs

RESERVED

FLASH/EE

RESERVED

SRAM

RESERVED

REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM)

06020-025

MEMORY ACCESS

The ARM7 core sees memory as a linear array of 232 byte locations where the different blocks of memory are mapped as outlined in Figure 29.

The ADuC7128/ADuC7129 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.

BIT 31

BYTE 2

BYTE 3

. . .

B 7 3

BYTE 1

.

A

Figure 30. Little Endian Format

6 2

32 BITS

9 5 1

BYTE 0

. . .

8 4 0

BIT 0

0xFFFFFFFF

0x00000004 0x00000000

06020-026

FLASH/EE MEMORY

The 128 kB of Flash/EE is organized as two banks of 32 k × 16 bits. In the first block, 31 k × 16 bits are user space and 1 k × 16 bits is reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes.

The second 64 kB block is organized in a similar manner. It is arranged in 32 k × 16 bits. All of this is available as user space.

The 126 kB of Flash/EE is available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and FLASH/EE section).

SRAM

The 8 kB of SRAM are available to the user, organized as 2 k × 32 bits, that is, 2 k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section).

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 31 are unoccupied or reserved locations and should not be accessed by user software. See Table 12 through Table 31 for a full MMR memory map.

The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripherals. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7128/ADuC7129 are on the APB except the Flash/EE memory and the GPIOs.

Rev. 0 | Page 27 of 92

ADuC7128/ADuC7129

F

0

www.BDTIC.com/ADI

xFFFF06BC

0xFFFF 0690

0xFFFF 0688

0xFFFF 0670

0xFFFF 0544

0xFFFF 0500

0xFFFF04A8

0xFFFF 0480

0xFFFF 0448

0xFFFF 0440

0xFFFF 0434

0xFFFF 0400

0xFFFF 0394

0xFFFF 0380

0xFFFF 0370

0xFFFF 0360

0xFFFF 0350

0xFFFF 0340

0xFFFF 0334

0xFFFF 0320

0xFFFF 0318

0xFFFF 0300

0xFFFF 0240

0xFFFF 0200

0xFFFF 0110

0xFFFF 0000

DDS

DAC

ADC

BANDGAP

REFERENCE

POWER SUPPLY

MONITOR

PLL AND

OSCILLATOR

CONTROL

GENERAL PURP OSE

TIMER 4

WATCHDOG

TIMER

WAKEUP

TIMER

GENERAL PURP OSE

TIMER

TIMER 0

REMAP AND

SYSTEM CONTROL

INTERRUPT

CONTROLL ER

Figure 31. Memory Mapped

0xFFFFFFF

0xFFFF0FBC

0xFFFF0F80

0xFFFF0F18

0xFFFF0F00

0xFFFF0EA8

0xFFFF0E80

0xFFFF0E28

0xFFFF0E00

0xFFFF0D70

0xFFFF0D00

0xFFFF0C30

0xFFFF0C00

0xFFFF 0B54

0xFFFF 0B00

0xFFFF0A14

0xFFFF0A00

0xFFFF 0948

0xFFFF0900

0xFFFF 0848

0xFFFF 0800

0xFFFF076C

0xFFFF 0740

0xFFFF072C

0xFFFF0700

Registers

PWM

QEN

FLASH CONT ROL

INTERFACE 1

FLASH CONT ROL

INTERFACE 0

GPIO

EXTERNAL MEMORY

PLA

SPI

2

C1

I

I2C0

UART1

UART0

6020-027

COMPLETE MMR LISTING

Note that the Access Type column corresponds to the access time reading or writing an MMR. It depends on the AMBA bus used to access the peripheral. The processor has two AMBA buses: the AHB (advanced high performance bus) used for system modules and the APB (advanced peripheral bus) used for lower performance peripherals.

Table 12. IRQ Base Address = 0xFFFF0000