ANALOG DEVICES ADuC7128, ADuC7129 Service Manual

Precision Analog Microcontroller

ARM7TDMI MCU with 12-Bit ADC and DDS DAC

ADuC7128/ADuC7129

Rev. 0

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Silicon Anomaly

This anomaly list describes the known bugs, anomalies and workarounds for the ADuC7128/ADuC7129 MicroConverter®. The
anomalies listed apply to all ADuC7128/ADuC7129 packaged material branded as follows:

First Line ADuC7128 or ADuC7129
Second Line BCPZ126

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.

ADuC7128/ADuC7129 FUNCTIONALITY ISSUES

Silicon
Revision
Identifier

All silicon branded

Kernel
Revision
Identifier Chip Marking

ADuC7128 BCPZ126 or
ADuC7129 BCPZ126

Silicon
Status Anomaly Sheet No. of Reported Anomalies

Release Rev. 0 2

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ADuC7128/ADuC7129 Silicon Anomaly

if the FIFO of the slave is empty, the slave should NACK the request from the

©2011 Analog Devices, Inc. All rights reserved. Trademarks and

FUNCTIONALITY ISSUES

Table 1. ADC Conversion Start Mode [er001]

Background

Issue

Workaround
Related Issues

Table 2. I2C® Slave Not Releasing the Bus [er002]

Background

Issue

Workaround

Related Issues

SECTION 1. ADuC7128/ADuC7129 FUNCTIONALITY ISSUES

Reference Number Description Status

er001 ADC conversion start mode Open
er002 I2C slave not releasing the bus Open

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ADCCON[2:0] allow the user to select one of the following seven ADC conversion start modes of operation:

• External Pin

• Timer1 overflow.

• Timer0 overflow.

• Single software conversion.

• Continuous software conversion.

CONVST

triggered ADC conversion.

• PLA triggered ADC conversion.

•

PWM triggered ADC conversion.

The active low, external pin (P0.4) triggered conversion is always active, even if it is not selected via ADCCON[2:0].
This is the case if the function of P0.4 is configured as a
example, MS1, PLAO[1], or GPIO. This means that if a falling edge is seen on P0.4 and ADCCON[7] is enabled, a single
ADC conversion is triggered. If an ADC conversion cycle is already in progress, this conversion stops, and a new ADC
conversion cycle begins in response to a falling edge on P0.4.

Pending.
ADCCON[7], the ADC enable conversion mode bit, is fully functional, allowing the user to disable any of the active

ADC conversion modes except continuous conversion (see the ADuC7128/ADuC7129 data sheet).

During a read from the master to the slave,
master. Then, it should release the bus, allowing the master to generate a stop condition.

Following the generation of a NACK, the ADuC7128/ADuC7129 may not release the bus due to the generation of a
FIFO transmit empty interrupt.

Following the generation of a transmit FIFO empty interrupt, the bus can be released by any of the following:

• Placing valid data in the transmit FIFO.

• Placing dummy data in the transmit FIFO followed by a transmit FIFO flush.

• Resetting the slave interface by disabling/enabling the slave.

None.

CONVST

input or if P0.4 is configured as any other function, for

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S10318-0-11/11(0)

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