ANALOG DEVICES ADuC7124, ADuC7126 Service Manual
Precision Analog Microcontroller, 12-Bit Analog I/O, Large
Memory, ARM7TDMI MCU with Enhanced IRQ Handler
ADuC7124/ADuC7126
Silicon Anomaly
This anomaly list describes the known bugs, anomalies, and workarounds for the ADuC7124/ADuC7126 MicroConverter® Revision B
silicon. The anomalies listed apply to all ADuC7124/ADuC7126 packaged material branded as follows:
First Line ADuC7124 or ADuC7126
Third Line B30
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADuC7124/ADuC7126 FUNCTIONALITY ISSUES
Silicon Revision
Identifier
B 30 All silicon branded
ADuC7124/ADuC7126 PERORMANCE ISSUES
Silicon Revision
Identifier
B 30 All silicon branded
Kernel Revision
Identifier Chip Marking
B30
Kernel Revision
Identifier Chip Marking
B30
Silicon
Status
Released Rev. A 5
Silicon
Status
Released Rev. A 2
Anomaly
Sheet
Anomaly
Sheet
No. of Reported
Anomalies
No. of Reported
Anomalies
Rev. A | Page 1 of 4
ADuC7124/ADuC7126 Silicon Anomaly
Related Issues
None.
FUNCTIONALITY ISSUES
Table 1. ADC Conversion—
Background
ADC conversion can be set as
000. Clearing ADCCON Bit 13 enables
Issue
Workaround
ADC conversion by
Configure
CONV
Related Issues
None.
CONV
Edge Trigger Mode [er001]
START
CONV
falling edge trigger mode by setting ADCCON Bit 13 and with ADCCON[2:0] =
STA RT
CONV
CONV
CONV
when its pulse width is more than 25 ns. This will be fixed in the next revision.
STA RT
through one PLA flip-flop with ULCK as its clock. This ensures that the ADC is triggered by
STA RT
edge trigger mode is not reliable.
STA RT
Table 2. ADC Conversion—PLA Edge Trigger Mode [er002]
Background
The ADC conversion can be set as PLA rising edge trigger mode by setting ADCCON Bit 13 and with ADCCON[2:0] =
101. Clearing ADCCON Bit 13 enables PLA low level trigger mode.
Issue
Workaround
ADC conversion by PLA edge trigger mode is not reliable.
Configure the PLA element output through another PLA flip-flop with ULCK as its clock. This ensures that the ADC is
triggered by the PLA edge when CD is less than 5. This will be fixed in the next revision.
Related Issues
None.
2
Table 3. Disabling I
Background
Issue
C Interface in Slave Mode When a Transfer Is in Progress [er003]
The I2CSEN bit (Bit 0 in the I2CxSCON register) enables/disables the I2C slave interface. The I2CSBUSY bit (Bit 6 in the
I2CxSSTA register) indicates whether the I
2
C slave mode is enabled (I2CxSCON Bit 0 = 1) and a transfer is in progress with the master, do not clear I2CxSCON
If I
Bit 0 to 0 to disable the I
2
C slave interface until the I2C busy bit, I2CSBUSY (Bit 6 of I2CxSSTA), is cleared.
2
C slave interface is busy.
When I2CxSCON Bit 0 is cleared to 0 and I2CSBUSY is still set, the ADuC7124/ADuC7126 may drive the SDAx pins low
indefinitely. When this condition occurs, the ADuC7124/ADuC7126 do not release the SDAx pins unless a hardware reset
condition occurs.
2
Workaround
When disabling I
C slave mode by writing to the I2CSEN bit (Bit 0 in the I2CxSCON register), first set the I2CMEN bit (Bit 0
in the I2CxMCON register) = 1 to enable master mode. Then disable the slave mode by clearing the I2CSEN bit. Finally,
clear the I2CMEN bit.
high level trigger mode.
STA RT
Table 4. Operation of SPI in Slave Mode [er004]
Background
When in SPI slave mode, the ADuC7124/ADuC7126 expect the number of clock pulses from the master to be divisible by
8 when the chip select (CS) pin is low. The internal bit shift counter within the ADuC7124/ADuC7126 is not reset when
the chip select pin is deasserted.
Issue
If the number of clocks from the master is not divisible by 8 when the chip select is active, incorrect data may be
received or transmitted by the ADuC7124/ADuC7126 because the bit shift counter will not be at 0 for future transfers.
The internal bit shift counter for the transmit or receive buffers can only be reset by a hardware, software, or watchdog
reset.
Workaround
Related Issues
Always ensure that the number of SPI clocks is divisible by 8 when the ADuC7124/ADuC7126 chip select is active.
None.
Table 5. Timer0 in Periodic Mode with Internal 32 kHz Clock [er005]
Background
In periodic mode, the internal counter decrements/increments from the value in the load register (T0LD MMR) until
zero/full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by
accessing its value register (T0VAL).
Issue
The first timer interrupt occurs only after a full 16-bit countdown. After the countdown, the T0LD value is copied into
T0VAL as expected.
This issue occurs only when the 32 kHz oscillator is serving as the timer source.
Workaround
Related
None.
None.
Issues
Rev. A | Page 2 of 4
Loading...