Analog Devices ADUC7060QSPZU1, ADuC7060 Datasheet

Low-Power, Precision Analog Microcontroller

,

Dual

Σ-∆ ADCs,

Flash/EE, ARM7TDMI

Preliminary Technical Data

ADuC7060/ADuC7061/ADuC7062

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Analog input/output

Dual (24-bit) ADCs
Single-ended and differential inputs
Programmable ADC output rate (4 Hz to 8 kHz)
Programmable digital filters
Low power operation mode

Primary (24-bit) ADC channel

Up to 5 input channels
PGA (1 to 512) input stage
Selectable input range, ±2.34 mV to ±1.2 V
30 nV rms noise

Auxiliary (24-bit) ADC

Up to 8 buffered input channels
On-chip precision reference (±10 ppm/°C)
Programmable sensor excitation current sources

200 μA to 2 mA current source range

Single 16-bit voltage output DAC

Microcontroller

ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
Multiple clocking options

Memory

32 kB (16 kB × 16) Flash/EE memory
4 kB (1 kB × 32) SRAM

Tools

In-circuit download, JTAG based debug
Low cost, QuickStart development system

Communications interfaces
SPI interface(5 Mbps)

UART serial I/O and I

2

C (master/slave)

On-chip peripherals

4× general-purpose (capture/compare) timers

2× general-purpose (capture/compare) timers
Wakeup timer
Watchdog timer

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type
interrupt on edge or level external pin inputs

16-bit, 6-channel PWM
General-purpose inputs/outputs

Up to 14 GPIO pins that are fully 3.3 V compliant

Power

AVDD/DVDD specified for 2.5 V (+5%)
All inputs/outputs fully 3.3 V compliant
Active mode: 2.6 mA (@1 MHz, both ADCs active)
10 mA (@10 MHz, both ADCs active)

Packages and Temperature range

Fully specified for −40°C to +125°C operation
32-lead LFCSP (5 mm × 5 mm)
48-lead LFCSP
48-lead LQFP

Derivatives: 48-lead LQFP and 48-lead LFCSP, dual ADCs

(ADuC7060); 32-lead LFCSP, dual ADCs (ADuC7061);
32-lead LFCSP, single ADC (ADuC7062)

APPLICATIONS

Industrial automation and process control
Intelligent, precision sensing systems, 4 to 20 mA loop-

based smart sensors

GENERAL DESCRIPTION

The ADuC706x are fully integrated, 8 kSPS, 24-bit data acqui­sition systems incorporating high performance multichannel
sigma-delta (Σ-) analog-to-digital converters (ADCs), 16-bit/
32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip.

The ADCs consists of a 5-channel primary ADC and up to an
8-channel auxiliary ADC. The ADCs operate in single-ended or
differential input modes. A single channel buffered voltage
output DAC is available on-chip. The DAC output range is
programmable to one of two voltage ranges.

The devices operate from an on-chip oscillator and a PLL gene­rating an internal high frequency clock up to 10.24 MHz. The
microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine offering up to 10 MIPS peak performance. 4 kB of
SRAM and 32 kB of nonvolatile Flash/EE memory are provided
on-chip. The ARM7TDMI core views all memory and registers
as a single linear array.

The ADuC7060 contains four timers. Timer 1 is wake-up timer
with the ability to bring the part out of power saving mode.
Timer 2 may be configured as a watchdog timer. A 16-bit PWM
with six output channels is also provided.

The ADuC7060 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt
levels are supported.On-chip factory firmware supports in­circuit serial download via the UART serial interface ports and
nonintrusive emulation via the JTAG interface.

The parts operate from 2.375 V to 2.625 V over an industrial
temperature range of −40°C to +125°C.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 2 of 100

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

Electrical Specifications ............................................................... 4

Timing Specifications .................................................................. 8

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Ter minology .................................................................................... 14

Overview of the ARM7TDMI Core ............................................. 15

Thumb Mode (T) ........................................................................ 15

Multiplier (M) ............................................................................. 15

Embedded ICE (I) ...................................................................... 15

ARM Registers ............................................................................ 15

Interrupt Latency ........................................................................ 16

Memory Organization ............................................................... 16

Flash/EE Control Interface ........................................................ 17

Memory Mapped Registers ....................................................... 20

Complete MMR Listing ............................................................. 21

Reset ............................................................................................. 26

Oscillator, PLL and Power Control .............................................. 27

ADC Circuit information .............................................................. 30

Example Application Circuits ................................................... 49

DAC Peripherals ............................................................................. 50

DAC .............................................................................................. 50

MMR Interface ............................................................................ 50

Nonvolatile Flash/EE Memory ..................................................... 52

Flash/EE Memory Reliability .................................................... 52

Programming .............................................................................. 52

Processor Reference Peripherals ................................................... 53

Interrupt System ......................................................................... 53

IRQ ............................................................................................... 53

Fast Interrupt Request (FIQ) .................................................... 54

Timers .............................................................................................. 60

Timer0.......................................................................................... 61

Timer1 or Wake-Up Timer ....................................................... 63

Timer2 or Watchdog Timer ...................................................... 65

Timer3.......................................................................................... 67

Pulse-Width Modulator (PWM) .................................................. 69

PWM General Overview ........................................................... 69

UART Serial Interface .................................................................... 74

Baud Rate Generation ................................................................ 74

UART Register Definition ......................................................... 74

I2C ..................................................................................................... 79

Serial Clock Generation ............................................................ 80

I2C Bus Addresses ....................................................................... 80

I2C Registers ................................................................................ 80

I2C Common Registers .............................................................. 88

Serial Peripheral Interface ............................................................. 89

MISO (Master In, Slave Out) Pin ............................................. 89

MOSI (Master Out, Slave In) Pin ............................................. 89

SCL (Serial Clock I/O) Pin ........................................................ 89

Slave Select (SS Input) Pin......................................................... 89

Configuring External Pins for SPI Functionality ................... 89

SPI Registers ................................................................................ 90

General-Purpose I/O ..................................................................... 94

GPxCON Registers..................................................................... 94

GPxDAT Registers ..................................................................... 94

GPxSET Registers ....................................................................... 94

GPxCLR Registers ...................................................................... 95

GPxPAR Registers ...................................................................... 95

Hardware Design Considerations ................................................ 96

Power Supplies ............................................................................ 96

Outline Dimensions ....................................................................... 97

Ordering Guide .......................................................................... 98

REVISION HISTORY

6/08—Revision PrA: Preliminary Version

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 3 of 100

FUNCTIONAL BLOCK DIAGRAM

PRECISION ANAL OG PERIPHE RALS

POR

MEMORY

32kB FLASH

4kB RAM

ARM7TDMI

MCU

10MHz

ON-CHIP

OSC (3%)

PLL

4× TIMERS

WDT

W/U TIMER

PWM

GPIO PORT

UART PORT

SPI PORT
I

2

C PORT

VIC
(VECTORED
INTERRUPT

CONTROLL ER)

MUX

MUX

24-BIT

Σ-Δ

ADC

BUF

24-BIT

Σ-Δ ADC

PGA

PRECISION

REFERENCE

TEMP

SENSOR

14-BIT

DAC

RESET

XTAL2

XTAL1

AIN0
AIN1

AIN5

AIN4

AIN3

AIN2

AIN6
AIN7
AIN8
AIN9

IEXC0
IEXC1

DAC

VREF+

VREF–

GND_SW

ADuC7060/
ADuC7061/
ADuC7062

BUF

07079-001

Figure 1.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 4 of 100

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VDD = 2.5 V ± 5%, V

REF+

= 1.2 V, V

REF−

= GND internal reference, f

CORE

= 10.24 MHz driven from external 32.768 kHz watch crystal or on-

chip precision oscillator, all specifications T

A

= −40°C to +125°C, unless otherwise noted.

Table 1. ADuC706x Specifications

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS

Conversion Rate1 Chop off, ADC normal operating mode 50 8000 Hz
Chop on, ADC normal operating mode 4 2600 Hz
Chop on, ADC low power mode 1 650 Hz
Main Channel

No Missing Codes1 Chop off (f

ADC

≤ 1 kHz) 24 Bits

Chop on (f

ADC

≤ 666 Hz) 24 Bits
Integral Nonlinearity2 Gain = 1 ±14 ppm of FSR
Gain = 8 ±25 ppm of FSR
Gain = 64 ±66 ppm of FSR

Offset Error

3, 4

Chop off, offset error is in the order of
the noise for the programmed gain and
update rate following calibration

±4 V

Offset Error

3, 4

Chop on ±0.5 V

Offset Error Drift vs.
Temperature

5

Chop off (with GAIN ≤ 64) 650/PGA_GAIN nV/°C

Offset Error Drift vs.
Temperature

5

Chop on (with GAIN ≤ 64) 10 nV/°C

Full Scale Error

1, 6, 7, 8

Normal mode ±0.5 mV

Full Scale Error

1, 6, 7, 8

Low power mode ±1.0 mV

Gain Drift v Temperature9 5 ppm/°C
PGA Gain Mismatch Error ±0.1 %
Output Noise

1

See Table 29

Power Supply Rejection Chop on, ADC = 1 V, (gain = 1) 80 dB
Chop on, ADC = 7.8 mV, (gain = 128) 113 dB
Chop off, ADC = 1 V, (gain = 1) 80 dB

Aux Channel

No Missing Codes

1

Chop off (f

ADC

≤ 1 kHz) 24 Bits

Chop on (f

ADC

≤ 666 Hz) 24 Bits
Integral Nonlinearity ±20 ppm of FSR
Offset Error

4

Chop off ±15 V

Offset Error

4

Chop on ±0.5 V

Offset Error Drift vs.

Temperature

5

Chop off 200 nV/°C

Offset Error Drift vs.
Temperature

5

Chop on 10 nV/°C

Full-Scale Error

1, 6, 7, 8

Normal mode ±0.5 mV

Full-Scale Error

1, 6, 8

Low power mode ±1.0 mV

Gain Drift vs. Temperature9 3 ppm/°C

Output Noise See Table 27

Power Supply Rejection Chop on, ADC = 1 V 80 dB

Chop off, ADC = 1 V 80 dB

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 5 of 100

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS: ANALOG

INPUT

Internal VREF = 1.2 V

Main Channel

Absolute Input Voltage

Range

Applies to both VIN+ and VIN− 0.1 V

DD

− 0.7 V

Input Voltage Range Gain = 11 1.2 V

Gain = 2

10

600 mV

Gain = 4

10

300 mV
Gain = 8 150 mV
Gain = 16 75 mV
Gain = 32 37.5 mV
Gain = 64 18.75 mV
Gain = 128 9.375 mV

Input Leakage Current

1

ADC0/ADC1 10 nA
ADC2/ADC3/ADC4/ADC5 15 nA
ADC6/ADC7/ADC8/ADC9 15 nA
Input Offset Current

1, 11

0.5 nA

Common-Mode Rejection
DC

1

On ADC ADC = 7.8 mV 95 dB

ADC = 1 V

1

113 dB

Common-Mode Rejection
50/60 Hz

1

50/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz

update rate, chop on
ADC = 7.8 mV, range ± 20 mV 95 dB
ADC = 1 V, range ±1.2 V 90 dB
Normal-Mode Rejection

50/60 Hz

1

On ADC 50/60 Hz ± 1 Hz, 16.6Hz f

ADC

, chop on 75 dB

50/60 Hz ± 1 Hz, 16.6Hz f

ADC

, chop off 67 dB

Aux Channel

Absolute Input Voltage
Range

1

Buffer enabled 0.1 AVDD − 0.1 V

Buffer disabled AGND AVDD
Input Voltage Range Range based reference source 0 − 1.2 V
Input Current 5.5 µA
Common-Mode Rejection

DC

1

On ADC ADC = 7.8 mV 95 dB

ADC = 1 V

1

113 dB

Common-Mode Rejection
50/60 Hz

1

50/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz

update rate, chop on
ADC = 7.8 mV, range ± 20 mV 95 dB
ADC = 1 V, range ± 1.2 V 90 dB
Normal-Mode Rejection

50/60 Hz

1

On ADC 50/60 Hz ± 1 Hz, 16.6 Hz f

ADC

, chop on 75 dB

50/60 Hz ± 1 Hz, 16.6 Hz f

ADC

, chop off 67 dB

VOLTAGE REFERENCE

ADC Precision Reference

Internal VREF 1.2 V
Initial Accuracy

1

Measured at TA = 25°C −0.06 +0.06 %
Reference Temperature

Coefficient

1, 12

−20 ±10 +20 ppm/°C

Power Supply Rejection 70 dB

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 6 of 100

Parameter Test Conditions/Comments Min Typ Max Unit

External Reference Input
Range

13

0.1 AVDD V

V

REF

Divide by 2 Initial Error

1

0.1 %

DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF

Voltage Range 0 − V

REF

V
0 − AVDD V
12-BIT MODE

DC Specifications14

Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity Guaranteed monotonic ±0.2 ±1 LSB
Offset Error 1.2 V internal reference ±2 ±15 mV
Gain Error V

REF

range (reference = 1.2 V) ±1 %
AVDD range ±1 %
Gain Error Mismatch 0.1

% of full
scale on
DAC

16-BIT MODE

DC Specifications15

Resolution 14 Bits
Relative Accuracy For 14-bit resolution ±3 LSB
Differential Nonlinearity Guaranteed monotonic (14 bits) ±0.5 ±1 LSB
Offset Error 1.2 V internal reference ±2 ±15 mV
Gain Error V

REF

range (reference = 1.2 V) ±1 %
AVDD range ±1 %
Gain Error Mismatch 0.1

% of full
scale on
DAC

DAC AC CHARACTERISTICS

Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch

Energy

1 LSB change at major carry (where
maximum number of bits
simultaneously change in the DACxDAT
register)

±20 nV-sec

TEMPERATURE SENSOR16 After user calibration

Accuracy MCU in power down or standby mode ±4 °C
Thermal Impedance 32-lead LFCSP TBD °C/W
48-lead LFCSP TBD °C/W
48-lead LFQFP TBD °C/W

POWER-ON RESET (POR)

POR Trip Level Refers to voltage at VDD pin
Power-on level 2.0 V
Power-down level 2.25 V

RESET Timeout from POR

Maximum supply ramp between 1.8 V
to 2.25 V; after POR trip, VDD must
reach 2.25 V within this time limit

128 ms

EXCITATION CURRENT SOURCES

Output Current Available from each current source 200 1000 A
Initial Tolerance at 25°C ±5 %
Drift 200 ppm/°C
Initial Current matching at

25°C

Matching between both current
sources

±0.5 %

Drift matching 20 ppm/°C
Line Regulation (AVDD) AVDD = 2.5 V ± 5% 0.2 %/V
Output Compliance1 AVDD − 0.7 AGND − 30 mV V

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 7 of 100

Parameter Test Conditions/Comments Min Typ Max Unit

WATCHDOG TIMER (WDT )

Timeout Period

1

32.768 kHz clock, 256 prescale 0.008 512 sec

Timeout Step Size 7.8 ms

FLASH/EE MEMORY

1

Endurance17 10,000 Cycles
Data Retention

18

20 Years

DIGITAL INPUTS All digital inputs except NTRST

Input Leakage Current Input (high) = DVDD ±1 ±10 µA
Input Pull-up Current Input (low) = 0 V 10 20 80 µA
Input Capacitance 10 pF
Input Leakage Current NTRST only: input (low) = 0 V ±1 ±10 µA
Input Pull-Down Current NTRST only: input (high) = DVDD 30 55 100 µA

LOGIC INPUTS

1

All logic inputs
VINL, Input Low Voltage 0.4 V
VINH, Input High Voltage 2.0 V

CRYSTAL OSCILLATOR

1

Logic Inputs, XTAL1 Only

VINL, Input Low Voltage 0.8 V

VINH, Input High Voltage 1.7 V
XTAL1 Capacitance 12 pF
XTAL2 Capacitance 12 pF

ON-CHIP OSCILLATORS

Oscillator 32,768 kHz

Accuracy −3 +3 %

MCU CLOCK RATE

8 programmable core clock selections
within this range (binary divisions 1, 2, 4,
8 . . . 64, 128)

0.160 2.56 10.24 MHz

MCU START-UP TIME

At Power-On Includes kernel power-on execution time 134 ms
After Reset Event Includes kernel power-on execution time 5 ms
From MCU Power-Down
PLL ON

Wakeup from Interrupt 13 s

PLL Off

Wakeup from Interrupt 100 s

Internal PLL Lock Time 1 ms

POWER REQUIREMENTS

Power Supply Voltages

DVDD (±5%) 2.375 2.5 2.625 V
AVDD (±5%) 2.375 2.5 2.625 V

Power Consumption

IDD (MCU Normal Mode)19 MCU clock rate = 10.24 MHz, ADC on 10 TBC mA

MCU clock rate = 1.28 MHz, ADC on,
DAC off

2.8 mA

IDD (MCU Powered Down) 120 175 µA
IDD (Primary ADC)

PGA enabled, normal mode/low power
mode

1.2/0.3 mA

IDD (Aux ADC) Normal mode/low power mode 0.3/0.1 mA

1

These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.

2

Valid for primary ADC gain setting of PGA = 4 to 64.

3

Tested at gain range = 4 after initial offset calibration.

4

Measured with an internal short. A System zero-scale calibration will remove this error.

5

Measured with an internal short.

6

These numbers do not include internal reference temperature drift.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 8 of 100

7

Factory calibrated at gain = 1.

8

System calibration at specific gain range removes the error at this gain range.

9

Measured using external reference.

10

Limited by minimum absolute input voltage range.

11

Valid for a differential input less than 10 mV.

12

Measured using the box method.

13

References up to AVDD are accommodated by setting ADC0CON Bit 12.

14

Reference DAC linearity is calculated using a reduced code range of 171 to 4095.

15

Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535.

16

Die temperature.

17

Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.

18

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.

19

Typical, additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

TIMING SPECIFICATIONS

Data not ready yet.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 9 of 100

ABSOLUTE MAXIMUM RATINGS

TA = −40°C to +125°C, unless otherwise noted

Table 2.

Parameter Rating

AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.3 V
ADC Inputs to AGND −0.3 V to AVDD + +0.3 V
ESD (Human Body Model) Rating

All Pins ±2 kV

Storage Temperature 125°C
Junction Temperature

Transient 150°C
Continuous 130°C

Lead Temperature, Soldering

Reflow (15 sec)

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 10 of 100

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TCK

TDI

TDO

NTRST

DVDD

DGND

P2.1/PWM5/IRQ3

P1.6/PWM4

P1.5/PWM3

P1.4/PWM2

P0.2/IRQ2/PWM0

P0.4/PWM1/IRQ0

XTAL1
P0.3/MOSI/SDA

P0.2/MISO

DVDD

P0.0/SS

P0.1/SCLK/SCL

XTAL2

DGND
ADC9

ADC8

ADC6

ADC7

TMS

P1.0/IRQ1/SIN/T0

P1.1/SOUT

P0.5

P1.3/TRIP

P1.2/SYNC

RESET

P0.6

DVDD

DGND

ADC5/EXT_REF 2IN−

DAC0

ADC4/EXT_REF2I N+

ADC3

ADC2

IEXC1

IEXC0

GND_SW

ADC1

ADC0

VREF+

VREF−

AGND

AVDD

07079-002

13141516171819

2021222324

4847464544434241403938

37

1
2

3

4
5
6

7

8

9
10
11
12

35

36

34
33

32
31
30
29

28
27

26
25

ADuC7060

TOP VIEW

(Not to Scale)

PIN 1
INDICATOR

NOTES

1. NC = NO CONNE CT.

2

. THE LFCSP_VQ HAS AN EXP OSED PADDLE T HAT MUST BE CONNECT ED TO GND.

Figure 2. 48-Lead LQFPand 48-LFCSP Pin Configuration

Table 3. Pin Function Descriptions (48-Lead LQFP and 48-Lead LFCSP)

Pin No. Mnemonic

Typ e

1

Description

1

RESET

I Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin.
2 TMS I JTAG Test Mode Select. Input pin. Used for debug and download.
3 P1.0/IRQ1/SIN/T0 I/O

General-Purpose Input and Output P1/External Interrupt Request 1/Serial Input Pin 0/Timer 0
input. This pin is a multifunction input/output pin offering four functions.

4 P1.1/SOUT I/O

General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function
input/output pin.

5 P1.2/SYNC I/O

General-Purpose Input and General-Purpose Output P1.2/PWM External Sync Input. This is a dual
function input/output pin.

6 P1.3/TRIP I/O

General-Purpose Input and General-Purpose Output P1.3/PWM External Trip Input. This is a dual

function input/output pin.
7 P0.5 I/O General-Purpose Input and General-Purpose Output P0.5.
8 P0.6 I/O General-Purpose Input and General-Purpose Output P0.6.
9 DVDD S Digital Supply Pin.
10 DGND S Digital Ground.
11 DAC0 O DAC Output. Analog output pin.
12 ADC5/EXT_REF2IN− I

Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual

function analog input pin. The ADC5 serves as the analog input for the auxiliary ADC. The

EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel.
13 ADC4/EXT_REF2IN+ I

Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog

Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external

reference positive input for the auxiliary channel.
14 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for the auxiliary ADC.
15 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for the auxiliary ADC.
16 IEXC1 O Programmable Current Source. Analog output pin.
17 IEXC0 O Programmable Current Source. Analog output pin.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 11 of 100

Pin No. Mnemonic

Typ e

1

Description

18 GND_SW I

Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly

to the AGND system ground.
19 ADC1 I Positive Differential Input for Primary ADC. Analog input pin.
20 ADC0 I Negative Differential Input for Primary ADC. Analog input pin.
21 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin.
22 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin.
23 AGND S Analog Ground.
24 AVDD S Analog Supply Pin.
25 ADC6 I Analog Input 6 for Auxiliary ADC. Analog input pin.
26 ADC7 I Analog Input 7 for Auxiliary ADC. Analog input pin.
27 ADC8 I Analog Input 8 for Auxiliary ADC. Analog input pin.
28 ADC9 I Analog Input 9 for Auxiliary ADC. Analog input pin.
29 DGND S Digital Ground.
30 DVDD S Digital Supply Pin.
31

P0.0/SS

I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.0/SPI

slave select pin. Active low
32 P0.1/SCLK/SCL I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.1/ SPI

clock pin/ I

2

C clock pin.

33 P0.2/MISO I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.2/SPI

master input or slave output.
34 P0.3/MOSI/SDA I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.3/ SPI

master output or slave input/I2C data pin.
35 XTAL1 O External Crystal Oscillator Output Pin.
36 XTAL2 I External Crystal Oscillator Input Pin.
37 P0.4/PWM1/IRQ0 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.4/

External Interrupt Request 0/PWM1 output.
38 P2.0/IRQ2/PWM0 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output

P2.0/External Interrupt Request 2/PWM0 output.
39 P1.4/PWM2 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P1.4/PWM2

output.
40 P1.5/PWM3 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P1.5/PWM3

output.
41 P1.6/PWM4 I/O Multifunction I/O Pin. General-Purpose Input and General-Purpose Output P1.6/PWM4 output.
42 P2.1/PWM5/IRQ3 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P2.1/

PWM5 output/External Interrupt Request 3.
43 DGND S Digital Ground.
44 DVDD S Digital Supply Pin.
45 NTRST I JTAG Reset. Input pin used for debug and download only.
46 TDO O JTAG Data Out. Output pin used for debug and download only.
47 TDI I JTAG Data In. Input pin used for debug and download only.
48 TCK I JTAG Clock Pin. Input pin used for debug and download only.

1

I = input, O = output, S = supply.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 12 of 100

PIN 1
INDICATO R

1RESET
2TMS
3P1.0/IRQ1/SIN/T0
4P1.1/SOUT
5DAC0
6ADC5/EXT_REF2IN−
7ADC4/EXT_REF2IN+
8ADC3

24 XT AL2
23 XT AL1
22 P0.3/MOSI/ SDA/ADC9
21 P0.2/MISO/ADC8
20 P0.1/SCLK/SCL /ADC7
19 P0.0/SS/ADC6
18 VREF–
17 VREF+

9

ADC2

10

IEXC

1

11

IEXC0

12

GND_SW

13

ADC1

14

ADC0

15

AGND

16

AVDD

32

TCK

31

TDI

30

TDO

29

NTRST

28

DVDD

27

DGND

26

P

2.0/IRQ2/PWM0

25

P0.4/IRQ0/PWM1

ADuC7061/
ADuC7062

TOP VIEW

(Not to Scale)

07079-003

NOTES

1. NC = NO CONNECT.

2. THE LFCSP_VQ HAS AN E XPOSED PADDLE THAT MUST BE CONNECTED
TO GND.

Figure 3. 32-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions ADuC7061/ADuC7062 32-Lead LFCSP

Pin No. Mnemonic Type1 Description

1

RESET

I Reset Pin. Active Low, input pin. An external 1 kΩ pull-up resistor is recommended with this pin.
2 TMS I JTAG Test Mode Select. Input pin used for debug and download.
3 P1.0/IRQ1/SIN/T0 I/O Multifunction Input/Output Pin:
General-Purpose Input and General-Purpose Output P1.0.
External interrupt Request 1.
Serial Input.
Timer 0 Input.
4 P1.1/SOUT I/O Multifunction Input/Output Pin:
General-Purpose Input and General-Purpose Output P1.1.
Serial Output.
5 DAC0 O DAC Output. Analog output pin.
6 ADC5/EXT_REF2IN− I Multifunction Analog Input Pin:
Single-Ended or Differential Analog Input 5. Analog input for auxiliary ADC.
External Reference Negative Input for the Auxiliary Channel.
7 ADC4/EXT_REF2IN+ I Multifunction Analog Input Pin:
Single-ended or Differential Analog Input 4. Analog input for auxiliary ADC.

External Reference Positive Input for the Auxiliary Channel.
8 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for auxiliary ADC.
9 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for auxiliary ADC.
10 IEXC1 O Programmable Current Source. Analog output pin.
11 IEXC0 O Programmable Current Source. Analog output pin.
12 GND_SW I

Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly

to the AGND system ground.
13 ADC1 I Positive Differential Input for Primary ADC. Analog input pin.
14 ADC0 I Negative Differential Input for Primary ADC. Analog input pin.
15 AGND S Analog Ground.
16 AVDD S Analog Supply Pin.
17 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin.
18 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin.
19

P0.0/SS

/ADC6

I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.0/ SPI

Slave Select (active low)/Input to Auxiliary ADC6.
20 P0.1/SCLK/SDA/ADC7 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.1/SPI

clock/ I

2

C clock/ Input to Auxiliary ADC7.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 13 of 100

Pin No. Mnemonic Type1 Description

21 P0.2/MISO/ADC8 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.2/SPI
master input or slave output/Auxiliary ADC8 input.

22 P0.3/MOSI/SDA/ADC9 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.3/SPI

master output or slave input/I2C data pin/Auxiliary ADC ADC9 input.
23 XTAL1 O External Crystal Oscillator Output Pin.
24 XTAL2 I External Crystal Oscillator Input Pin.
25 P0.4/IRQ0/PWM1 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.4/WM1

output.
26 P2.0/IRQ2/PWM0 I/O

Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output

P2.0/External Interrupt Request 2/PWM0 output.
27 DGND S Digital Ground.
28 DVDD S Digital Supply Pin.
29 NTRST I JTAG Reset. Input pin used for debug and download only.
30 TDO O JTAG Data Out. Output pin used for debug and download only.
31 TDI I JTAG Data In. Input pin used for debug and download only.
32 TCK I JTAG Clock. Input pin used for debug and download only.

1

I = input, O = output, S = supply.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 14 of 100

TERMINOLOGY

Conversion Rate

The conversion rate specifies the rate at which an output result
is available from the ADC, once the ADC has settled.

The sigma-delta (Σ-) conversion techniques used on this part
mean that while the ADC front-end signal is over sampled at a
relatively high sample rate, a subsequent digital filter is used to
decimate the output giving a valid 24-bit data conversion result
at output rates from 1 Hz to 8 kHz.

Note that when software switches from one input to another
(on the same ADC), the digital filter must first be cleared and
then allowed to average a new result. Depending on the con­figuration of the ADC and the type of filter, this can take
multiple conversion cycles.

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point ½ LSB
below the first code transition, and full scale, a point ½ LSB
above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.

No Missing Codes

No missing codes is a measure of the differential nonlinearity
of the ADC. The error is expressed in bits and specifies the
number of codes (ADC results) as 2N bits, where is N = no
missing codes, guaranteed to occur through the full ADC
input range.

Offset Error

Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.

Offset Error Drift

Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSBs per °C.

Gain Error

Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured and the ideal
span between any two points in the transfer function.

Output Noise

The output noise is specified as the standard deviation (or 1 ×
Sigma) of ADC output codes distribution collected when the
ADC input voltage is at a dc voltage. It is expressed as µ rms.
The output, or rms noise, can be used to calculate the effective
resolution of the ADC as defined by the following equation:

Effective Resolution = log2(Full-Scale Range/rms Noise) bits

The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Sigma of the distribution of ADC output codes
collected when the ADC input voltage is at dc. The peak-to­peak noise is, therefore calculated as 6.6 × the rms noise.

The peak-to-peak noise can be used to calculate the ADC
(noise free code) resolution for which there is no code flicker
within a 6.6-Sigma limit as defined by the following equation:

Noise Free Code Resolution = log2(

NoisePeaktoPeak

RangeScaleFull−−−

) bits

Data Sheet Acronyms

ADC analog-to-digital converter
ARM advanced RISC machine
JTAG joint test action group
LSB least significant byte/bit
LVF low voltage flag
MCU microcontroller
MMR memory mapped register
MSB most significant byte/bit
PID protected identifier
POR power-on reset
PSM power supply monitor
rms root mean square

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 15 of 100

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM® Ltd. The ARM7TDMI is a
von Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data can
be 8, 16, or 32 bits and the length of the instruction word is
either 16 bits or 32 bits, depending on the mode in which the
core is operating.

The ARM7TDMI is an ARM7 core with four additional
features, as listed in Table 5.

Table 5. ARM7TDMI

Feature Description

T Support for the Thumb® (16-bit) instruction set
D Support for debug
M Enhanced multiplier
I

Includes the EmbeddedICE™ module to support
embedded system debugging

THUMB MODE (T)

An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set compressed into 16 bits, the
Thumb instruction set. Faster code execution from 16-bit memory
and greater code density is achieved by using the Thumb instruc­tion set, making the ARM7TDMI core particularly suited for
embedded applications.

However, the Thumb mode has three limitations.

• Relative to ARM, the Thumb code usually requires more

instructions to perform that same task. Therefore, ARM
code is best for maximizing the performance of time­critical code in most applications.

• The Thumb instruction set does not include some

instructions that are needed for exception handling, so
ARM code can be required for exception handling.

• When an interrupt occurs, the core vectors to the interrupt

location in memory and executes the code present at that
address. The first command is required to be in ARM code.

MULTIPLIER (M)

The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, and 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.

EMBEDDED ICE (I)

The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers that allow
nonintrusive user code debugging. These registers are con­trolled through the JTAG test port. When a breakpoint or
watchpoint is encountered, the processor halts and enters the
debug state. Once in a debug state, the processor registers can
be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.

ARM7 Exceptions

The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:

Normal interrupt or IRQ. This is provided to service general­purpose interrupt handling of internal and external events.
Note, that the ADuC7060 supports 8 configurable priority levels
for all IRQ sources.

Fast interrupt or FIQ. This is provided to service data transfer
or a communication channel with low latency.
FIQ has priority over IRQ. Note, that the ADuC7060 supports 8
configurable priority levels for all FIQ sources.

Memory abort (prefetch and data).

Attempted execution of an undefined instruction.

Software interrupts (SWI) instruction that can be used to make
a call to an operating system.

Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define
interrupts as the FIQ type.

The priority of these exceptions and vector address are listed in
Tabl e 6.

Table 6. Exception Priorities and Vector Addresses

Priority Exception Address

1 Hardware Reset 0x00
2 Memory Abort (Data) 0x10
3 FIQ 0x1C
4 IRQ 0x18
5 Memory Abort (Prefetch) 0x0C
6 Software Interrupt1 0x08
6 Undefined Instruction1 0x04

1

A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive.

The list of exceptions in Table 6 are located from 0x00 to 0x1C,
with a reserved location at 0x14.

ARM REGISTERS

The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.

The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. When programming using high level languages,

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 16 of 100

such as C, it is necessary to ensure that the stack does not
overflow. This is dependent on the performance of the compiler
that is used.

When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 4. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.

More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.

USABLE IN US ER MODE

SYSTEM MODES ONLY

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R13_UND

R14_UND

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15 (PC)

R13_IRQ

R14_IRQ

R13_ABT

R14_ABT

R13_SVC

R14_SVC

SPSR_FIQ

CPSR

USER MODE

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

07079-004

Figure 4. Register Organization

INTERRUPT LATENCY

The worst-case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) that loads all the registers including the
PC, plus the time for the data abort entry, plus the time for FIQ
entry. At the end of this time, the ARM7TDMI is executing the
instruction at 0x1C (FIQ interrupt vector address). The
maximum total time is 50 processor cycles, or just over 4.88 s
in a system using a continuous 10.24 MHz processor clock. The
maximum IRQ latency calculation is similar, but must allow for
the fact that FIQ has higher priority and could delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used; some compilers have an option to compile without using
this command. Another option is to run the part in Thumb
mode where this is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.

Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service
routines.

MEMORY ORGANIZATION

The ARM7, a von Neumann architecture MCU core sees
memory as a linear array of 232-byte locations. As shown in
Figure 5, the ADuC7060 maps this into four distinct user areas,
namely: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.

The first 30 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. Any
access, either reading or writing, to an area not defined in the
memory map results in a data abort exception.

Memory Format

The ADuC706x memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address. See Figure 6 for details.

0x00040FFF

0x00040000

0xFFFFFFFF

0xFFFF0000

MMRs

0x00087FFF

0x00080000

FLASH/EE

SRAM

0x00007FFF

0x00000000

REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)

RESERVED

RESERVED

RESERVED

07079-005

Figure 5. ADuC706x Memory Map

BIT 31

BYTE 2

A

6

2

.
.
.

BYTE 3

B

7

3

.
.
.

BYTE 1

9

5

1

.
.
.

BYTE 0

8

4

0

.
.
.

BIT 0

32 BITS

0xFFFFFFFF

0x00000004

0x00000000

7079-006

Figure 6. Little Endian Format

SRAM

The ADuC706x features 4 kB of SRAM, organized as 1024 ×
32 bits, that is, 1024 words located at 0x40000.

The RAM space can be used as data memory as well as volatile
program space.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 17 of 100

ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.

Remap

The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.

By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.

It is possible to logically remap the SRAM to Address 0x00000000
by setting Bit 0 of the SYSMAP0 MMR located at 0xFFFF0220.
To revert Flash/EE to 0x00000000, Bit 0 of REMAP is cleared.

It is sometimes desirable to remap RAM to 0x00000000 to
optimize the interrupt latency of the ADuC706x because code
can run in full 32-bit ARM mode and at maximum core speed.
Note that when an exception occurs, the core defaults to ARM
mode.

Remap Operation

When a reset occurs on the ADuC706x, execution starts
automatically in the factory programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed by
user code. If the ADuC706x is in normal mode, it executes the
power-on configuration routine of the kernel and then jumps to
the reset vector, Address 0x00000000, to execute the user’s reset
exception routine. Because the Flash/EE is mirrored at the
bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.

The remap command must be executed from the absolute
Flash/EE address, and not from the mirrored, remapped
segment of memory, as this may be replaced by SRAM. If a
remap operation is executed while operating code from the
mirrored location, prefetch/data aborts can occur or the user
can observe abnormal program operation.

Any kind of reset logically remaps the Flash/EE memory to the
bottom of the memory array.

REMAP Register

Name: REMAP

Address: 0xFFFF0220

Default value: Updated by the kernel

Access: Read/write access

Function: This 8-bit register allows user code to remap

either RAM or Flash/EE space into the bottom
of the ARM memory space starting at Address
0x00000000.

Table 7. REMAP MMR Bit Designations

Bit Description

7 to 1

Reserved. These bits are reserved and should be written

as 0 by user code.
0 Remap Bit.
Set by the user to remap the SRAM to 0x00000000.

Cleared automatically after reset to remap the Flash/EE

memory to 0x00000000.

FLASH/EE CONTROL INTERFACE

Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section.

FEESTA Register

FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 7.

Name: FEESTA

Address: 0xFFFF0E00

Default value: 0x20

Access: Read

Table 7. FEESTA MMR Bit Designations

Bit Description

15:6 Reserved.
5 Reserved.
4 Reserved.
3

Flash Interrupt Status Bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading FEESTA register.

2

Flash/EE Controller Busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.

1

Command Fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.

0

Command Pass. Set by the MicroConverter® when a
command completes successfully. Cleared
automatically when reading the FEESTA register.

FEEMOD Register

FEEMOD sets the operating mode of the flash control interface.
Table 8 shows FEEMOD MMR bit designations.

Name: FEEMOD

Address: 0xFFFF0804

Default value: 0x0000

Access: Read/write

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 18 of 100

Table 8. FEEMOD MMR Bit Designations

Bit Description

15:9 Reserved.
8 Reserved. Always set this bit to 0.
7:5

Reserved. Always set these bits to 0 except when
writing keys.

4 Flash/EE Interrupt Enable.

Set by user to enable the Flash/EE interrupt. The

interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt.
3 Erase/Write Command Protection.
Set by user to enable the erase and write commands.

Cleared to protect the Flash against erase/write

command.
2:0 Reserved. Always set these bits to 0.

FEECON Register

FEECON is an 8-bit command register. The commands are
described in Table 9.

Name: FEECON
Address: 0xFFFF0808
Default value: 0x0
Access: Read/write

Table 9. Command Codes in FEECON

Code Command Description

0x001 Null Idle State.
0x011 Single Read Load FEEDAT with the 16-bit data. Indexed by FEEADR.
0x021 Single Write

Write FEEDAT at the address pointed by FEEADR. This operation takes 50 μs.

0x031 Erase/Write

Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This
operation takes approximately 24 ms.

0x041 Single Verify

Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The

result of the comparison is returned in FEESTA Bit 1.
0x051 Single Erase Erase the page indexed by FEEADR.
0x061 Mass Erase

Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental

execution, a command sequence is required to execute this instruction. See the

Command Sequence for Executing a Mass Erase section.
0x07 Reserved Reserved.
0x08 Reserved Reserved.
0x09 Reserved Reserved.
0x0A Reserved Reserved.
0x0B Signature

This command results in a 24-bit LFSR based signature been generated and loaded into

FEESIG MMR. This operation takes 16,389 clock cycles.
0x0C Protect

This command can run only once. The value of FEEPRO is saved and removed only with a

mass erase (0x06) or the key.
0x0D Reserved Reserved.
0x0E Reserved Reserved.
0x0F Ping No operation; interrupt generated.

1

The FEECON register always reads 0x07 immediately after execution of any of these commands.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 19 of 100

FEEDAT Register

FEEDAT is a 16-bit data register. This register holds the data
value for flash read and write commands.

Name: FEEDAT
Address: 0xFFFF080C
Default value: 0xXXXX
Access: Read/write

FEEADR Register

FEEADR is a 16-bit address register used for accessing
individual pages of the 32 kB flash block. The valid address
range for a user is: 0x0000 – 0x77FF. this represents the 30 kB
flash user memory space. A read or write access outside this
boundary causes a data abort exception to occur.

Name FEEADR
Address 0xFFFF0810
Default value 0x0000
Access Read/write

FEESIGN Register

The FEESIGN register is a 24-bit MMR. This register is updated
with the 24-bit signature value after the signature command has
been executed. This value is the result of the linear feedback
shift register (LFSR )operation initiated by the signature
command.

Name: FEESIGN
Address: 0xFFFF0818
Default value: 0xFFFFFF
Access: Read

FEEPRO Register

FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 10).

Name: FEEPRO
Address: 0xFFFF081C
Default value: 0x00000000
Access: Read/write

FEEHIDE Register

FEEHIDE MMR provides immediate protection. It does not
require any software key. Note that the protection settings in
FEEHIDE are cleared by a reset (see Table 10).

Name: FEEHIDE
Address: 0xFFFF0820
Default value: 0xFFFFFFFF
Access: Read/write

Table 10. FEEPRO and FEEHIDE MMR Bit Designations

Bit Description

31 Read Protection.

Cleared by user to protect all code. – no JTAG read
accesses for protected pages if this bit is set.
Set by user to allow reading the code via JTAG.

30

Protection for Page 59 (0x00087600 – 0x000877FF. Set
by user to allow writing the Page 59. Cleared to
protect Page 59.

29

Protection for Page 58 (0x00087400 – 0x000875FF. Set
by user to allow writing the Page 58. Cleared to
protect Page 58.

28:0

Write Protection for Page 57 to Page 0. Each bit
represents 2 pages. Each page is 512 bytes in size.
Bit0 is protection for Page 0 and Page 1 (0x00080000 –
0x000803FF. Set by the user to allow writing Page 0
and Page 1. Cleared to protect Page 0 and Page 1.
Bit1 is protection for Page 2 and Page 3 (0x00080400 –
0x000807FF. Set by the user to allow writing Page 2
and Page 3. Cleared to protect Page 2 and Page 3.
..
..
Bit27 is protection for Page 54 and Page 55
(0x00087000 – 0x000873FF. Set by the user to allow
writing Page 54 and Page 55. Cleared to protect
Page 54 and Page 55.
Bit28 is protection for Page 56 and Page 57
(0x00087400 – 0x000877FF. Set by the user to allow
writing Page 56 and Page 57. Cleared to protect
Page 56 and Page 57.

Command Sequence for Executing a Mass Erase

FEEDAT = 0x3CFF;
FEEADR = 0x77C3;
FEEMOD = FEEMOD|0x8; //Erase key enable
FEECON = 0x06; //Mass erase command

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 20 of 100

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array, and accessed by indirect
addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in 5 are
unoccupied or reserved locations, and should not be accessed
by user software. Figure 7 shows the full MMR memory map.

The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA busses: advanced high performance bus (AHB)
used for system modules, and advanced peripheral bus (APB)
used for a lower performance peripheral. Access to the AHB is
one cycle, and access to the APB is two cycles. All peripherals
on the ADuC706x are on the APB except the Flash/EE memory,
the GPIOs, and the PWM.

PWM

0xFFFF0FC0

0xFFFFFFF

F

0xFFFF 0F80

FLASH CONTRO L

INTERFACE

0xFFFF0E24

0xFFFF0E00

GPIO

0xFFFF0D50

0xFFFF0D00

SPI

0xFFFF0A14

0xFFFF0A00

I2C

0xFFFF 0948

0xFFFF 0900

UART

0xFFFF 0730

0xFFFF 0700

DAC

0xFFFF 0620

0xFFFF 0600

ADC

0xFFFF 0570

0xFFFF 0500

BANDGAP

REFERENCE

0xFFFF 0490

0xFFFF 048C

SPI/I2C

SELECTION

0xFFFF 0470

0xFFFF 0450

PLL AND OSCI LLATOR

CONTROL

0xFFFF 0420

0xFFFF 0404

GENERAL PURPOS E

TIMER

0xFFFF 0394

0xFFFF 0380

WATCHDOG

TIMER

0xFFFF 0370

0xFFFF 0360

WAKE UP

TIMER

0xFFFF 0350

0xFFFF 0340

GENERAL PURPOS E

TIMER

0xFFFF 0334

0xFFFF 0320

REMAP AND

SYSTEM CONTROL

0xFFFF 0238

0xFFFF 0220

INTERRUPT

CONTROLL ER

0xFFFF 0140

0xFFFF 0000

07079-007

Figure 7. Memory Mapped Registers

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 21 of 100

COMPLETE MMR LISTING

In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.

Table 11. IRQ Address Base = 0xFFFF0000

Address Name Byte

Access
Typ e

Default
Value Description

0x0000 IRQSTA 4 R 0x00000000 Active IRQ Source.
0x0004 IRQSIG 4 R Current State of All IRQ Sources (Enabled and Disabled).
0x0008 IRQEN 4 RW 0x00000000 Enabled IRQ Sources.
0x000C IRQCLR 4 W MMR to Disable IRQ Sources.
0x0010 SWICFG 4 W Software Interrupt Configuration MMR.
0x0014 IRQBASE 4 R/W 0x00000000

Base Address of all Vectors. Points to start of 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.

0x001C IRQVEC 4 R 0x00000000

This register contains the subroutine address for the currently active IRQ
source.

0x0020 IRQP0 4 R/W 0x00000000

Contains the interrupt priority setting for interrupt Source 1 to Source 7.

An interrupt can have a priority setting of 0 to 7. For example:
Bits[7:4] containthe priority level for Interrupt 1.
Bits[11:8] contain the priority level for Interrupt 2.
Bits[31:28] contain the priority level for Interrupt 7.
0x0024 IRQP1 4 R/W 0x00000000

Contains the interrupt priority setting for Interrupt Source 8 to Interrupt

Source 15. For example:
Bits[7:4] contain the priority level for Interrupt 9.
Bits[11:8] contain the priority level for Interrupt 10.
Bits[31:28] contain the priority level for Interrupt 15.
0x0028 IRQP2 4 R/W 0x00000000

Contains the interrupt priority setting for Interrupt Source 16 to Interrupt

Source 19.
0x002C RESERVED 4 R/W 0x00000000 Reserved.
0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting.
0x0034 IRQCONE 4 R/W 0x00000000

Configures the external interrupt sources as either rising edge, falling

edge, or level triggered.
0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge level triggered interrupt source.
0x003C IRQSTAN 4 R/W 0x00000000

This register indicates the priority level of an interrupt that has just

caused an interrupt exception.
0x0100 FIQSTA 4 R 0x00000000 Active FIQ Source.
0x0104 FIQSIG 4 R Current State of All FIQ Sources (Enabled and Disabled).
0x0108 FIQEN 4 RW 0x00000000 Enabled FIQ Sources.
0x010C FIQCLR 4 W MMR to Disable FIQ Sources.
0x011C FIQVEC 4 R 0x00000000 FIQ Interrupt Vector.
0x013C FIQSTAN 4 R 0x00000000

Indicates the priority level of an FIQ that has just caused an FIQ

exception.

Table 12. System Control Address Base = 0xFFFF0200

Address Name Byte

Access
Typ e

Default Value Description

0x0220 REMAP1 1 R/W 0x00 REMAP Control Register. See the Remap Operation section.
0x0230 RSTSTA 1 R/W 0x01 RSTSTA Status MMR. See the Reset section.
0x0234 RSTCLR 1 W 0x00 RSTCLR MMR for clearing RSTSTA register.

1

Updated by kernel.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 22 of 100

Table 13. Timer Address Base = 0xFFFF0300

Address Name Byte

Access
Type Default Value Description

0x0320 T0LD 4 RW 0x00000000 Timer0 Load Register.
0x0324 T0VAL 4 R 0xFFFFFFFF Timer0 Value Register.
0x0328 T0CON 4 RW 0x01000000 Timer0 Control MMR.
0x032C T0CLRI 1 W N/A Timer0 Interrupt Clear Register.
0x0330 T0CAP 4 R 0x00000000 Timer0 Capture Register.
0x0340 T1LD 4 RW 0x00000000 Timer1 Load Register.
0x0344 T1VAL 4 R 0xFFFFFFFF Timer1 Value Register
0x0348 T1CON 2 RW 0x0000 Timer1 Control MMR.
0x034C T1CLRI 1 W N/A Timer1 Interrupt Clear Register
0x0360 T2LD 2 RW 0x0040 Timer2 Load Register.
0x0364 T2VAL 2 R 0x0040 Timer2 Value Register.
0x0368 T2CON 2 RW 0x0100 Timer2 Control MMR.
0x036C T2CLRI 1 W N/A Timer2 Interrupt Clear Register.
0x0380 T3LD 2 RW 0x0000 Timer3 Load Register.
0x0384 T3VAL 2 R 0xFFFF Timer3 Value Register.
0x0388 T3CON 4 RW 0x00000000 Timer3 Control MMR.
0x038C T3CLRI 1 W N/A Timer3 Interrupt Clear Register.
0x0390 T3CAP 2 R 0x0000 Timer3 Capture Register.

Table 14. PLL Base Address = 0xFFFF0400

Address Name Byte

Access
Typ e

Default Value Description

0x0404 POWKEY1 2 W N/A POWCON Prewrite Key
0x0408 POWCON0 1 RW 0x7B Power Control and Core Speed Control Register.
0x040C POWKEY2 4 W N/A POWCON Postwrite Key..
0x0410 PLLKEY1 4 W N/A PLLCON Prewrite Key.
0x0414 PLLCON 1 RW 0x00 PLL Clock Source Selection MMR.
0x0418 PLLKEY2 4 W N/A PLLCON Postwrite Key.
0x0464 GP0KEY1 4 R/W 0x00 GP0CON1 Prewrite Key.
0x0468 GP0CON1 1 R/W 0x00

Configures P0.0, P0.1, P0.2, and P0.3 as analog inputs or digital I/Os. Also
enables SPI or I

2

C mode.

0x046C GP0KEY2 4 R/W 0x00 GP0CON1 Postwrite Key.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 23 of 100

Table 15. ADC Address Base = 0xFFFF0500

Address Name Byte

Access
Type Default Value Description

0x0500 ADCSTA 2 R 0x0000 ADC Status MMR.
0x0504 ADCMSKI 2 R/W 0x0000 ADC Interrupt Source Enable MMR.
0x0508 ADCMDE 2 R/W 0x0003 ADC Mode Register.
0x050C ADC0CON 2 R/W 0x8000 Primary ADC Control MMR.
0x0510 ADC1CON 2 R/W 0x0000 Auxiliary ADC Control MMR.
0x0514 ADCFLT 2 R/W 0x0007 ADC Filter Control MMR.
0x0518 ADCCFG 2 R/W 0x0000 ADC Configuration MMR.
0x051C ADC0DAT 4 R/W 0x00000000 Primary ADC Result MMR.
0x0520 ADC1DAT 4 R/W 0x00000000 Auxiliary ADC Result MMR
0x0524 ADC0OF 2 R/W 0x0000 Primary ADC Offset Calibration Setting.
0x0528 ADC1OF 2 R/W 0x0000 Auxiliary ADC Offset MMR.
0x052C ADC0GN 2 R/W 0x5555 Primary ADC Offset MMR.
0x0530 ADC1GN 2 R/W 0x5555 Auxiliary ADC Offset MMR. See the Gain Calibration section.
0x0534 ADCORCR 2 R/W 0x0001 Primary ADC Result Counter/Reload MMR.
0x0538 ADCORCV 2 R 0x0000 Primary ADC Result Counter MMR.
0x053C ADCOTH 2 R/W 0x0000 Primary ADC 16-bit Comparator Threshold MMR.
0x0540 ADCOTHC 2 R/W 0x0001 Primary ADC 16-bit Comparator Threshold Counter Limit.
0x0544 ADCOTHV 2 R/W 0x0000
0x0548 ADCOACC 4 R/W 0x00000000 Primary ADC Accumulator.
0x054C ADCOATH 4 R/W 0x00000000 Primary ADC 32-Bit Comparator Threshold MMR.
0x0570 IEXCON 1 R/W 0x00 Excitation Current Sources Control Register.

1

Updated by kernel. {Where is this endnote in the table?}

Table 16. DAC Control Address Base = 0xFFFF0600

Address Name Byte

Access
Type Default Value Description

0x0600 DACCON 1 R/W 0x00 DAC Control Register.
0x0604 DAC0DAT 4 R/W 0x00000000 DAC Output Data Register.

Table 17. UART Base Address = 0XFFFF0700

Address Name Byte

Access
Type Default Value Description

0x0700 COMTX 1 W N/A UART Transmit Register.
0x0700 COMRX 1 R 0x00 UART Receive Register.
0x0700 COMDIV0 1 RW 0x00 UART Standard Baud Rate Generator Divisor Value 0.
0x0704 COMIEN0 1 RW 0x00 UART Interrupt Enable MMR 0.
0x0704 COMDIV1 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 1.
0x0708 COMIID0 1 R 0x01 UART Interrupt Identification 0.
0x070C COMCON0 1 RW 0x03 UART Control Register 0.
0x0710 COMCON1 1 RW 0x00 UART Control Register 1.
0x0714 COMSTA0 1 R 0x60 UART Status Register 0.
0X072C COMDIV2 2 RW 0x0000 UART Fractional Divider MMR.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 24 of 100

Table 18. I2C Base Address = 0XFFFF0900

Address Name Byte

Access
Typ e

Default
Value Description

0x0900 I2CMCON 2 R/W 0x0000 I2C master Control register.
0x0904 I2CMSTA 2 R 0x0000 I2C master Status register.
0x0908 I2CMRX 1 R 0x00 I2C master Receive register.
0x090C I2CMTX 1 W 0x00 I2C master Transmit register.
0x0910 I2CMCNT0 2 R/W 0x0000

I

2

C master Read Count register. Write the number of required bytes into this

register prior to reading from a slave device.

0x0914 I2CMCNT1 1 R 0x00

I

2

C master Current Read count register. This register contains the number of

bytes already received during a read from slave sequence.

0x0918 I2CADR0 1 R/W 0x00

Address byte register. Write the required slave address in here prior to
communications.

0x091C I2CADR1 1 R/W 0x00

Address byte register. Write the required slave address in here prior to

communications. Only used in 10-bit mode.
0x0924 I2CDIV 2 R/W 0x1F1F I2C clock control register. Used to configure the SCLK frequency.
0x0928 I2CSCON 2 R/W 0x0000 I2C slave Control register.
0x092C I2CSSTA 2 R/W 0x0000 I2C slave Status register.
0x0930 I2CSRX 1 R/W 0x00 I2C slave Receive register.
0x0934 I2CSTX 1 R/W 0x00 I2C slave Transmit register.
0x0938 I2CALT 1 R/W 0x00 I2C Hardware General Call recognition register.
0x093C I2CID0 1 R/W 0x00 I2C Slave ID0 register. Slave bus ID register
0x0940 I2CID1 1 R/W 0x00 I2C Slave ID1 register. Slave bus ID register
0x0944 I2CID2 1 R/W 0x00 I2C Slave ID2 register. Slave bus ID register
0x0948 I2CID3 1 R/W 0x00 I2C Slave ID3 register. Slave bus ID register
0x094C I2CFSTA 2 R/W 0x0000 I2C FIFO Status register. Used in both master + slave modes

Table 19. SPI Base Address = 0xFFFF0A00

Address Name Byte Access Type Default Value Description

0x0A00 SPISTA 4 R 0x00000000 SPI Status MMR.
0x0A04 SPIRX 1 R 0x00 SPI Receive MMR.
0x0A08 SPITX 1 W SPI Transmit MMR.
0x0A0C SPIDIV 1 RW 0x1B SPI Baud Rate Select MMR.
0x0A10 SPICON 2 RW 0x00 SPI Control MMR.

Table 20. GPIO Base Address = 0xFFFF0D00

Address Name Byte

Access
Type Default Value Description

0x0D00 GP0CON 4 RW 0x00000000 GPIO Port0 Control MMR.
0x0D04 GP1CON 4 RW 0x00000000 GPIO Port1 Control MMR.
0x0D08 GP2CON 4 RW 0x00000000 GPIO Port2 Control MMR.
0x0D20 GP0DAT 4 RW 0x000000EF GPIO Port0 Data Control MMR.
0x0D24 GP0SET 4 W 0x000000EF GPIO Port0 Data Set MMR.
0x0D28 GP0CLR 4 W 0x000000EF GPIO Port0 Data Clear MMR.
0x0D2C GP0PAR 4 W 0x00000000 GPIO Port0 Pull-Up Disable MMR.
0x0D30 GP1DAT 4 RW 0x000000FF GPIO Port1 Data Control MMR.
0x0D34 GP1SET 4 W 0x000000FF GPIO Port1 Data Set MMR.
0x0D38 GP1CLR 4 W 0x000000FF GPIO Port1 Data Clear MMR.
0x0D3C GP1PAR 4 W 0x00000000 GPIO Port1 Pull-Up Disable MMR.
0x0D40 GP2DAT 4 RW 0x000000FF GPIO Port2 Data Control MMR.
0x0D44 GP2SET 4 W 0x000000FF GPIO Port2 Data Set MMR.
0x0D48 GP2CLR 4 W 0x000000FF GPIO Port2 Data Clear MMR.
0x0D4C GP2PAR 4 W 0x00000000 GPIO Port2 Pull-up Disable MMR.

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 25 of 100

Table 21. Flash/EE Base Address = 0xFFFF0E00

Address Name Byte

Access
Type Default Value Description

0x0E00 FEESTA 1 R 0x20 Flash/EE Status MMR.
0x0E04 FEEMOD 1 RW 0x00 Flash/EE Control MMR.
0x0E08 FEECON 1 RW 0x07 Flash/EE Control MMR.
0x0E0C FEEDAT 2 RW 0x0000 Flash/EE Data MMR.
0x0E10 FEEADR 2 RW 0x0000 Flash/EE Address MMR.
0x0E18 FEESIG 3 R 0xFFFFFF Flash/EE LFSR MMR.
0x0E1C FEEPRO 4 RW 0x00000000 Flash/EE Protection MMR.
0x0E20 FEEHID 4 RW 0xFFFFFFFF Flash/EE Protection MMR.

Table 22. PWM Base Address = 0xFFFF0F80

Address Name Byte

Access
Type Default Value Description

0x0F80 PWMCON 2 R/W 0x0000 PWM Control register. See PWM section for full details.
0x0F84 PWM0COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 0 and PWM Output 1.
0x0F88 PWM0COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 0 and PWM Output 1.
0x0F8C PWM0COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 0 and PWM Output 1.
0x0F90 PWM0LEN 2 R/W 0x0000 Frequency Control for PWM outputs 0 and PWM Output 1.
0x0F94 PWM1COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 2 and PWM Output 3.
0x0F98 PWM1COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 2 and PWM Output 3.
0x0F9C PWM1COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 2 and PWM Output 3.
0x0FA0 PWM1LEN 2 R/W 0x0000 Frequency Control for PWM Output 2 and PWM Output 3.
0x0FA4 PWM2COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 4 and PWM Output 5.
0x0FA8 PWM2COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 4 and PWM Output 5.
0x0FAC PWM2COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 4 and PWM Output 5.
0x0FB0 PWM2LEN 2 R/W 0x0000 Frequency Control for PWM Output 4 and PWM Output 5.
0x0FB8 PWMCLRI 2 R/W 0x0000

PWM Interrupt Clear Register. Writing any value to this register clears a
PWM interrupt source.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 26 of 100

RESET

There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.

The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 24.

RSTSTA Register

Name: RSTSTA
Address: 0xFFFF0230
Default value: Depends on type of reset
Access: Read/write access
Function: This 8-bit register indicates the source of the

last reset event and can be written by user code
to initiate a software reset.

RSTCLR Register

Name: RSTCLR
Address: 0xFFFF0234
Access: Write only
Function: This 8-bit write only register clears the

corresponding bit in RSTSTA.

Table 23. RSTSTA/RSTCLR MMR Bit Designations

Bit Description

7 to 4

Not Used. These bits are not used and always
read as 0.

3 External Reset.

Automatically set to 1 when an external reset
occurs.

This bit is cleared by setting the corresponding bit
in RSTCLR.

2 Software Reset.

This bit is set to 1 by user code to generate a soft­ware reset.

This bit is cleared by setting the corresponding bit
in RSTCLR.

1

1 Watchdog Timeout.

Automatically set to 1 when a watchdog timeout

occurs.
Cleared by setting the corresponding bit in RSTCLR.
0 Power-On Reset.
Automatically Set when a power-on-reset occurs.
Cleared by setting the corresponding bit in RSTCLR.

1

If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset.

Table 24. Device Reset Implications

RESET

Reset External
Pins to Default
State

Kernel
Executed

Reset All
External MMRs
(Excluding
RSTSTA)

Peripherals
Reset

Watc hdog
Timer Reset

RAM
Valid

RSTSTA (Status
After Reset
Event)

POR Yes Yes Yes Yes Yes Yes/No RSTSTA[0] = 1
Watchdog Yes Yes Yes Yes No Yes RSTSTA[1] = 1
Software Yes Yes Yes Yes No Yes RSTSTA[2] = 1
External

Pin

Yes Yes Yes Yes No Yes RSTSTA[3] = 1

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 27 of 100

OSCILLATOR, PLL AND POWER CONTROL

Clocking System

Each ADuC7060 integrates a 32.768 kHz ±3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple of the internal
oscillator or an external 32.768 kHz crystal to provide a stable 10.24
MHz clock (UCLK) for the system. To allow power saving, the core
can operate at this frequency, or at binary submultiples of it. The
actual core operating frequency, UCLK/2

CD

, is refered to as HCLK.

The default core clock is the PLL clock divided by 8 (CD = 3) or

1.28 MHz.

PLL

CORE

CD

10.24MHz

32.768kHz

*32.768kHz±3%

HCLK

UCLK

OCLK

WATCHDOG

TIMER

WAKEUP

TIMER

INT. 32kHz

OSCILLATOR

ANALOG

PERIPHERALS

/2

CD

I2C

07079-008

Figure 8. Clocking System

The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.

Power Control System

The core clock frequency is changed by writing to the POWCON0
register. This is a key protected register therefore, registers
POWKEY1 and POWKEY2 must be written to immediately before
and after configuring the POWCON0 register. The following is a
simple example showing how to configure the core clock for

10.24 MHz:

POWKEY1 = 0x1;
POWCON0 = 0x78; //Set core to max CPU

//speed of 10.24 MHz

POWKEY2 = 0xF4;

A choice of operating modes is available on the ADuC7060. Table
below describes what part is powered on in the different modes and
indicates the power-up time.

Table 26 gives some typical values of the total current consumption
(analog + digital supply currents) in the different modes, depending
on the clock divider bits. The ADC is turned off. Note that these
values also include current consumption of the regulator and other
parts on the test board where these values are measured.

Table 25.

POWCON[6:3] Mode Core Peripherals PLL XTAL/T2/T3 IRQ0 to IRQ3 Start-Up/Power-On Time

1111 Active X X X X X
1110 Pause X X X X
1100 Nap X X X
1000 Sleep X X
0000 Stop X

Table 26. Typical Current Consumption at 25°C in mA

POWCON[6:3] Mode CD = 0 CD = 1 CD = 2 CD = 3 CD = 4 CD = 5 CD = 6 CD = 7

1111 Active TBD TBD TBD TBD TBD TBD TBD TBD
1110 Pause TBD TBD TBD TBD TBD TBD TBD TBD
1100 Nap TBD TBD TBD TBD TBD TBD TBD TBD
1000 Sleep TBD TBD TBD TBD TBD TBD TBD TBD
0000 Stop TBD TBD TBD TBD TBD TBD TBD TBD

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 28 of 100

Power and Clock Control Registers

Name: POWKEY1
Address: 0xFFFF0404
Default Value: 0xXXXX
Access: Write
Function: When writing to POWCON0, the value 0x01

must be written to this register in the
instruction immediately before writing to
POWCON0

Name: POWCON0
Address: 0xFFFF0408
Default Value: 0x7B
Access: Read/write
Function: This register controls the clock divide bits

controlling the CPU clock (HCLK)

Table 27. POWCON0 MMR Bit Designations

Bit Name Description

7 Reserved This bit must always be set to 0.
6 XPD

XTAL Power Down.
Cleared by the user to power-down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.

5

PLLPD

PLL Power Down. Timer peripherals power down if driven from the PLL output clock.
Timers driven from an active clock source remain in normal power mode.
This bit is cleared to 0 to power-down the PLL.
The PLL cannot be powered down if either the core or peripherals are enabled:
Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.

4

PPD

Peripherals Power Down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I

2

C and UART serial ports.
Cleared to power-down the peripherals. The peripherals cannot be powered down if the core is enabled:
Bit 3 and Bit 4 must be cleared simultaneously.
Set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer1) can still be active

3

COREPD

Core Power Down. If user code powers down the MCU, include a dummy MCU cycle after the power-down
command is written to POWCON.

Cleared to power-down the ARM core.
Set by default and set by hardware on a wake-up event.

2 to 0 CD[2:0] Core clock depends on CD setting:

[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz

Preliminary Technical Data ADuC7060/ADuC7061/ADuC7062

Rev. PrA | Page 29 of 100

Name: POWKEY2
Address: 0xFFFF040C
Default Value: 0xXXXX
Access: Write
Function: When writing to POWCON0, the value 0xF4 must be written to this register in the instruction immediately

after writing to POWCON0

Name: PLLKEY1
Address: 0xFFFF0410
Default Value: 0xXXXX
Access: Write
Function: When writing to the PLLCON register, the value 0xAA must be written to this register in the instruction

immediately before writing to PLLCON

Name: PLLCON
Address: 0xFFFF0414
Default Value: 0x00
Access: Read/Write
Function: This register selects the clock input to the PLL.

Table 28. PLLCON MMR Bit Designations

Bit Name Description

7 to 2 Reserved These bits must always be set to 0.
1 to 0 OSEL Oscillator Selection bits:

[00] = Internal 32,768 Hz Oscillator
[01] = Internal 32,768 Hz Oscillator
[10] = External Crystal
[11] = Internal 32,768 Hz Oscillator

Name: PLLKEY2
Address: 0xFFFF0418
Default Value: 0xXXXX
Access: Write
Function: When writing to PLLCON, the value 0x55 must be written to this register in the instruction immediately after

writing to PLLCON.

ADuC7060/ADuC7061/ADuC7062 Preliminary Technical Data

Rev. PrA | Page 30 of 100

ADC CIRCUIT INFORMATION

IEXC0

IEXC1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

GND_SW

50Ω

BUF

Σ-Δ

MODULATOR

PROGRAMMABLE

FILTER

Σ-Δ

MODULATOR

PROGRAMMABLE

FILTER

OVERRANGE

INTERFACE

AND CONTROL

CHOP

MUX

CHOP

MUX

AGND

TEMPERATURE

SENSOR

INTEGRATOR

ACCUMULATOR

CONVERSION

COUNTER

COMPARATORS

TO ARM

0.2Hz TO 8kHz

0.5Hz TO 8kHz

DAC

BUF

INTERNAL

REFERENCE

AVDD

EXT_REF2IN+

EXT_REF2IN−

0.2mA TO 1mA

PGA

50µA O/C

DETECT

V

REF–

V

REF+AVDD

AIN0

AIN1

DAC0

07079-009

Figure 9. Analog Block Diagram

The ADuC706x incorporates two independent multichannel
Σ- ADCs. The primary ADC is a 24-bit, 5-channel ADC. The
auxiliary ADC is a 16-bit Σ- ADC, with up to eight input
channels.

The primary ADC input has a mux and a programmable gain
amplifier on its input stage. The mux on the primary channel
can be configured as two fully differential input channels or five
single-ended input channels.

The auxiliary ADC incorporates a buffer on its input stage.
Digital filtering is present on both ADCs which allows

measurement of a wide dynamic range and low frequency
signals such as those in pressure sensor, temperature sensor,
weigh-scale, or strain-gauge type applications.

The ADuC706x auxiliary ADC can be configured as four fully
differential input channels or as eight single-ended input
channels.

Because of internal buffering, the internal channels can convert
signals directly from sensors without the need for external
signal conditioning.