ANALOG DEVICES ADuC7039 Service Manual

Integrated, Precision

Battery Sensor for Automotive Systems

FEATURES

High precision ADC Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from 10 Hz to 1 kHz On-chip 5 ppm/ºC voltage reference Current channel

Fully differential, buffered input Programmable gain ADC input range: −200 mV to +300 mV Digital comparator with current accumulator feature

Voltage channel

Buffered, on-chip attenuator for 12 V battery input

Temperature channel

External and on-chip temperature sensor options

Microcontroller

ARM7TDMI-S core, 16-/32-bit RISC architecture

20.48 MHz PLL On-chip precision oscillator

JTAG port supports code download and debug

ADuC7039

Memory

64 kB Flash/EE memory options, 4-kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN

On-chip peripherals

SAEJ2602/LIN 2.1-compatible slave SPI GPIO port 1 × general-purpose timer Wake-up and watchdog timers On-chip power-on-reset

Power

Operates directly from 12 V battery supply Current consumption 7.5 mA (10 MHz) Low power monitor mode

Package and temperature range

32-pin, 6 mm × 6 mm LFCSP Fully specified for −40°C to +115°C operation

APPLICATIONS

Battery sensing/management for automotive systems

FUNCTIONAL BLOCK DIAGRAM

PRECISION ANAL OG ACQUISITION

IIN+

IIN–

VBAT

VTEMP

GND_SW

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

BUF PGA

RESULT

ACCUMULATOR

MUX

BUF

TEMPERATURE

SENSOR

VDD

REG_AVDD

AGND

REG_DVDD

Σ-Δ ADC

DIGITAL

COMPARATOR

Σ-Δ ADC

PRECISION

REFERENCE

VSS

DGND

16-BIT

IO_VSS

Figure 1.

RTCK TDI TDO NTRST TMS

ADuC7039

LDO POR

20MHz

ARM7TDMI

MCU

1 × TIMER

WDT

W/U TIMER

GPIO_5

GPIO_4

64KB FLASH

LOW POWER

ON-CHIP PLL

GPIO_3/ MOSI

MEMORY

4KB RAM

PRECISION

OSC

GPIO PORT

SPI PORT

LIN

GPIO_2/ MISO

GPIO_1/SCLK

RESET

LIN

GPIO_0/SS

08463-001

ADuC7039

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Specifications ............................................................... 3

Timing Specifications .................................................................. 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Overview of the ARM7TDMI-S Core ..................................... 12

Memory Organization ............................................................... 14

Reset ............................................................................................. 15

Flash/EE Memory ........................................................................... 16

Flash/EE MMR Interface ........................................................... 16

Flash/EE Memory Signature ..................................................... 20

Flash/EE Memory Security ....................................................... 21

Flash/EE Memory Reliability .................................................... 23

ADuC7039 Kernel ...................................................................... 23

Memory Mapped Registers (MMR) ............................................. 25

Complete MMR Listing ............................................................. 26

16-Bit, Sigma-Delta Analog-to-Digital Converters ................... 29

ADC Ground Switch .................................................................. 32

ADC Noise Performance Tables ............................................... 32

ADC MMR Interface ................................................................. 33

ADC Sinc3 Digital Filter Response .......................................... 42

ADC Modes of Operation ......................................................... 43

ADC Configuration ................................................................... 45

I-ADC Diagnostics ..................................................................... 46

REVISION HISTORY

8/10—Rev.A to Rev. B

Changes to Fast Temperature Conversion Mode Section ......... 46

Changes to Bit 4 Description (LINCON[6] Reference) in

Table 62 ............................................................................................ 86

Changes to Part Identification Section ........................................ 87

6/10—Rev. 0 to Rev. A

Added SAEJ2602 to Features Section ............................................ 1

Changes to Table 2 ............................................................................ 9

Power Supply Support Circuits ..................................................... 47

System Clocks ................................................................................. 48

Oscillators Calibration ............................................................... 53

Interrupt System ............................................................................. 58

Timers .............................................................................................. 60

Synchronization of TIMERS Across Asynchronous Clock

Domains ...................................................................................... 60

Programming the Timers .......................................................... 61

Timer0—General-Purpose Timer ........................................... 62

Timer1—Wake-Up Timer ......................................................... 64

Timer2—Watchdog Timer ........................................................ 66

General-Purpose Input/Output .................................................... 68

Serial Peripheral Interface (SPI) ................................................... 73

Master In, Slave Out (MISO) Pin ............................................. 73

Master Out, Slave In (MOSI) Pin ............................................. 73

Serial Clock I/O (SCLK) Pin ..................................................... 73

Slave Select (SS) Pin ................................................................... 73

SPI MMR Interface .................................................................... 73

High Voltage Peripheral Control Interface ................................. 77

Low Voltage Flag (LVF) ............................................................. 80

Handling HV Interface Interrupt and HV Communication 80

LIN (Local Interconnect Network) Interface.............................. 82

LIN Physical Interface ............................................................... 82

LIN Diagnostic ........................................................................... 83

LIN Communication ................................................................. 83

LIN MMRs .................................................................................. 83

Part Identification ........................................................................... 87

Recommended Schematic ............................................................. 89

Outline Dimensions ....................................................................... 90

Ordering Guide .......................................................................... 90

Changes to Bit 2 and Bit 1 Descriptions in Table 34 .................. 39

Changes to System Clocks Section ............................................... 49

Added Syncronization of Timers across Asynchronous Clock

Domains Section, Figure 23, and Figure 24 ................................ 60

Added Programming the Timers Section ................................... 61

Changes to Recommended Schematic Text ................................ 89

3/10—Revision 0: Initial Version

Rev. B | Page 2 of 92

ADuC7039

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VDD = 3.5 V to 18 V, V +115°C, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS

Conversion Rate1 ADC normal operating mode 10 1000 Hz ADC low power mode, chop on 10 650 Hz Current Channel

No Missing Codes1 Valid for all ADC update rates and ADC modes 16 Bits Integral Nonlinearity Offset Error

Offset Error

Offset Error Drift Offset Error Drift Offset Error Drift Total Gain Error Low power mode −1 ±0.2 +1 % Gain Drift PGA Gain Mismatch Error ±0.1 % Output Noise1 10 Hz update rate, gain = 512, chop enabled 100 150 nV rms 1 kHz update rate, gain = 512, ADCFLT = 0x0007 0.6 0.9 µV rms 1 kHz update rate, gain = 32, ADCFLT = 0x0007 0.8 1.2 µV rms 1 kHz update rate, gain = 8, ADCFLT = 0x8101 2.1 4.1 µV rms 1 kHz update rate, gain = 8, ADCFLT = 0x0007 1.6 2.4 µV rms 1 kHz update rate, gain = 4, ADCFLT = 0x0007 2.6 3.9 µV rms ADC low power mode, 250Hz update rate, chop enable,

Voltage Channel8

No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error Offset Error Offset Error Drift4 Chop off ±0.03 LSB/°C Total Gain Error Total Gain Error Gain Drift Output Noise 1 kHz update rate, ADCFLT = 0x0007 180 270 µV rms

Temperature Channel

No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error Offset Error Offset Error Drift1 Chop off 0.03 LSB/°C Total Gain Error Gain Drift1 3 ppm/°C Output Noise1 1 kHz update rate 7.5 11.25 µV rms

1, 2, 3

1, 3

1, 7

±3 ppm/°C

1, 3

1, 7

Includes resistor mismatch drift ±3 ppm/°C

3, 10

1, 3

= 1.2 V internal reference, f

REF

1, 2

±10 ±60 ppm of FSR

Chop off, external short, after user system calibration,

= 20.48 MHz driven from on-chip precision oscillator, all specifications TA = −40°C to

CORE

−10 ±3 +10 LSB

1 LSB = (36.6/gain) µV

Chop on, external short, low power mode,

+250 ±50 −300 nV

MCU powered down

Chop on, external short, after user system calibration

0 3.0 µV

Tested at CD = 0, VDD = 18 V

Chop on, external short, after user system calibration

±0.5 µV

Tested at CD = 0, VDD = 4 V

1, 2, 4

Chop off, gains of 8 to 64, normal mode ±0.03 LSB/°C

1, 4

Chop off, valid for ADC gain of 512 ±30 nV/°C

1, 4

Chop on ±5 nV/°C

1, 3, 5 , 6

Factory calibrated at a gain of 4; normal mode −0.5 ±0.1 +0.5 %

0.6 0.9 µV rms

gain = 512

Chop off, 1 LSB = 439.5 µV, after two point calibration −10 ±1 +10 LSB Chop on, after two point calibration −1 ±0.3 +1 LSB

1, 3, 5, 6

Includes resistor mismatch −0.25 ±0.06 +0.25 %

1, 3, 5, 6

Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 %

1, 9

10 Hz update rate, chop on 60 90 µV rms

Chop off, 1 LSB = 19.84 V (in unipolar mode) −10 ±3 +10 LSB

Chop on −5 +1 +5 LSB

1, 3, 10

VREF = (REG_AVDD, GND_SW)/2 −0.25 ±0.06 +0.25 %

Rev. B | Page 3 of 92

ADuC7039

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS, ANALOG INPUT

Current Channel

Absolute Input Voltage Range1 Applies to both IIN+ and IIN− −200 +300 mV Input Voltage Range Gain = 4 ±300 mV Gain = 8 ±150 mV Gain = 32 ±37.5 mV Gain = 512 ±2.3 mV Input Leakage Current1 −3 +3 nA Input Offset Current

Voltage Channel

Absolute Input Voltage Range1 Voltage ADC specifications are valid in this range 4 18 V Input Voltage Range1 0 to 28.8 V VBAT Input Current VBAT = 18 V 3 5.5 8 µA

Temperature Channel V

Absolute Input Voltage

Range Input Voltage Range1 0 to V VTEMP Input Current1 2.5 100 nA

VOLTAGE REFERENCE

Internal VREF 1.2 V Power-Up Time1 0.5 ms Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 % Temperature Coefficient Long-Term Stability16 100 ppm/1000 hr

ADC DIAGNOSTICS

VREF/136 Accuracy1 At any gain setting 8.4 9.4 mV Voltage Attenuator Current Differential voltage increase on the attenuator when current is on 2.3 3.6 V Source Accuracy1

RESISTIVE ATTENUATOR1

Divider Ratio 24 Resistor Mismatch Drift Included in the voltage channel total gain error ±3 ppm/°C

ADC GROUND SWITCH

Resistor to Ground 15 20 30 kΩ

TEMPERATURE SENSOR17 Uncalibrated

Accuracy MCU in power down or standby mode; TA = −40°C to +85°C −10 ±3 +10 °C MCU in power down or standby mode; TA = −20°C to +60°C −8 ±2 +8 ºC Calibrated − ADC2GN = 0x968A;

POWER-ON RESET (POR)1

POR Trip Level Refers to voltage at the VDD pin 2.85 3.0 3.15 V POR Hysteresis 300 mV Reset Timeout from POR 20 ms

LOW VOLTAGE FLAG(LVF)

LVF Level Refers to voltage at the VDD pin 1.9 2.1 2.3 V

WATCHDOG TIMER (WDT)

Timeout Period1 32 kHz clock, 256 prescale 0.008 524 Seconds Timeout Step Size 7.8 ms

FLASH/EE MEMORY1

Endurance18 10,000 Cycles Data Retention19 20 Years

DIGITAL INPUTS1 All digital inputs except NTRST

Input Leakage Current Input (high) = REG_DVDD ±1 ±10 µA Input Pull-Up Current1 Input (low) = 0 V 10 20 80 µA Input Capacitance1 10 pF Input Leakage Current NTRST only; input (low) = 0 V ±1 ±10 µA Input Pull-Down Current NTRST only; input (high) = REG_DVDD 30 55 100 µA

11, 12

1, 13

0.5 1.5 nA

= (REG_AVDD, GND_SW)/2

REF

100 1300 mV

REF

1, 15

−20 ±5 +20 ppm/°C

−4 ±2 +4 °C

MCU in power down or standby mode

Rev. B | Page 4 of 92

ADuC7039

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS1 All logic inputs

Input Low Voltage (VINL) 0.4 V Input High Voltage (VINH) 2.0 V

ON-CHIP OSCILLATORS

Low Power Oscillator 128 kHz

Accuracy After user calibration at nominal supply and room

temperature; includes drift data from 1000 hr life-test

Precision Oscillator 128 kHz

Accuracy After run time calibration −1 +1 % MCU CLOCK RATE1 10.24 MHz MCU START-UP TIME1

At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down Oscillator running 2 ms Internal PLL Lock Time 1 ms

LIN I/O GENERAL

Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range for which the LIN interface is functional 7 18 V Input Capacitance1 5.5 pF LIN Comparator Response Time1 Using 22 Ω resistor 38 90 µs

LIN DC PARAMETERS

Current limit for driver when LIN bus is in dominant state;

LIN DOM MAX

VBAT = VBAT (maximum)

LIN_PAS_REC

LIN_PAS_DOM

LIN_NO_GND

BUS_NO_BAT

V V V V V

Driver off; 7.0 V < V

Input leakage, V

1, 20

Control unit disconnected from ground, GND = VDD;

VBAT disconnected, VDD = GND, 0 V < V

LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V

LIN_DOM

LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V

LIN_REC

LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V

LIN_CNT

LIN receiver hysteresis voltage 0.175 VDD V

HYS

LIN_DOM_DRV_LOSUP

LIN dominant output voltage; VDD = 7.0 V

0 V < V

< 18 V; VBAT = 12 V

LIN

< 18 V; VDD = V

BUS

= 0 V −1 mA

LIN

− 0.7 V 20 µA

LIN

< 18 V 100 µA

BUS

RL 500 Ω 1.2 V

RL 1000 Ω 0.6 V

LIN_DOM_DRV_HISUP

LIN dominant output voltage; VDD = 18 V RL 500 Ω 2 V RL 1000 Ω 0.8 V

LIN_RECESSIVE

LIN recessive output voltage 0.8 VDD V VBAT Shift20 0 0.115 VDD V GND Shift20 0 0.115 VDD V R

Slave termination resistance 20 30 47 kΩ

SLAVE

SERIAL DIODE

Voltage drop at the serial diode, D

0.4 0.7 1 V

Ser_Int

LIN AC PARAMETERS1 Bus load conditions (CBUS||RBUS):

1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω D1 Duty Cycle 1 0.396 TH TH V D1 = t

= 0.744 × VBAT

REC(MAX)

= 0.581 × VBAT

DOM(MAX)

= 7.0 V … 18 V; t

SUP

BUS_REC(MIN)

= 50 µs

BIT

/(2 × t

)

BIT

D2 Duty Cycle 2 0.581 TH TH V D2 = t

= 0.284 × VBAT

REC(MIN)

= 0.422 × VBAT

DOM(MIN)

= 7.0 V … 18 V; t

SUP

BUS_REC(MAX)

= 50 µs

BIT

/(2 × t

)

BIT

−3 +3 %

40 200 mA

−1 +1 mA

Rev. B | Page 5 of 92

ADuC7039

Parameter Test Conditions/Comments Min Typ Max Unit

1, 20

TH TH V t D3 = t

1, 20

TH TH V t D4 = t

1, 20

Propagation delay of receiver 6 μs

RX_PDR

1, 20

Symmetry of receiver propagation delay rising edge,

RX_SYM

PACKAGE THERMAL SPECIFICATIONS

Thermal Impedance (θJA)21 32-lead CSP, stacked die 32 °C/W

POWER REQUIREMENTS1

Power Supply Voltages VDD (Battery Supply) 3.5 18 V

REG_DVDD, REG_AVDD22 2.45 2.6 2.75 V

Power Consumption IDD (MCU Normal Mode)23 ADC off (20.48 MHz) 10 20 mA ADC off (10.24 MHz) 7.5 16 mA IDD (MCU Powered Down)1 ADC low power mode, measured over an ambient

IDD (MCU Powered Down)1 Precision oscillator turned off, ADC off Average current, measured with wake-up and watchdog

Average current, measured with wake-up and watchdog

IDD (Current ADC) 1.7 mA IDD (Voltage/Temperature ADC) 0.5 mA IDD (Precision Oscillator) 400 μA

Not guaranteed by production test but by design and/or characterization data at production release.

Valid for current ADC gain setting of PGA up to 64.

These numbers include temperature drift.

The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of

the temperature drift characterization data distribution.

Includes internal reference temperature drift.

User system calibration removes this error at a given temperature and at a given gain on the current channel.

The gain drift is included in the total gain error. This typical specification is an indicator of the gain error due to temperature drift. This typical value is the mean of the

temperature drift characterization data distribution.

Voltage channel specifications include resistive attenuator input stage.

RMS noise is referred to voltage attenuator input; for example, at f

input referred noise figures.

Valid after an initial self calibration.

It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach

can also be used to reduce the ADC input range (LSB size).

In ADC low power mode, the input range is fixed at ±2.34375 mV.

Valid for a differential input less than 10 mV.

The absolute value of the voltage of VTEMP and GND_SW must be 100mV minimum, for accurate operation of the T-ADC.

Measured using box method.

The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.

Die temperature.

Endurance is qualified to 10,000 cycles, as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.

Retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.

These numbers are not production tested but are supported by LIN compliance testing.

Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.

Internal regulated supply available at REG_DVDD (I

Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

= 0.778 × VBAT 0.417

REC(MAX)

= 0.616 × VBAT

DOM(MAX)

= 7.0 V ... 18 V

= 96 μs

BIT

/(2 × t

BUS_REC(MIN)

= 0.389 × VBAT 0.590

REC(min)

= 0.251 × VBAT

DOM(min)

= 7.0 V … 18 V

= 96 μs

BIT

BUS_REC(MAX)

)

BIT

/(2 × t

)

BIT

−2 +2 μs

with respect to falling edge (t

RX_SYM

= t

RF_PDR

− t

RX_PDF

)

750 1000 μA

temperature range of T

= −10°C to +40°C, continuous ADC

conversion

95 300 μA

timers clocked from low power oscillator (−40°C to +85°C)

95 175 μA timers clocked from low power oscillator over an ambient temperature range of −10°C to +40°C

= 1 kHz, typical rms noise at the ADC input is 7.5 μV, scaled by the attenuator (24) yields these

ADC

= 5 mA) and REG_AVDD (I

SOURCE

=1 mA).

Rev. B | Page 6 of 92

ADuC7039

TIMING SPECIFICATIONS

LIN Timing Specifications

TRANSMIT

INPUT TO

TRANSMITTING

NODE

(TRANSCEIVER SUPPLY

OF TRANSMIT TING NODE)

SUP

RxD

(OUTPUT O F RECEIVING NODE 1)

RECESSIVE

DOMINANT

REC (MAX)

DOM (MAX)

REC (MIN)

DOM (MI N)

BIT

LIN_DO M (MAX )

LIN_DO M (MI N)

RX_PDF

BIT

LIN_REC ( MIN)

LIN_REC ( MAX)

RX_PDR

BIT

THRESHOLDS OF RECEIVING NO DE 1

THRESHOLDS OF RECEIVING NO DE 2

LIN

BUS

(OUTPUT O F RECEIVING NODE 2)

RxD

RX_PDR

Figure 2. LIN 2.1 Timing Specification

RX_PDF

08463-002

Rev. B | Page 7 of 92

ADuC7039

ABSOLUTE MAXIMUM RATINGS

TA = −40°C to +115°C, unless otherwise noted.

Table 2.

Parameter Rating

AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V VBAT to AGND −22 V to +40 V VDD to VSS −0.3 V to +40 V LIN to IO_VSS −16 V to +40 V LIN Short-Circuit Current1 200 mA Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V ESD (HBM) Rating

HBM-ADI0082 (Based on ANSI/ESD STM5.1-2007); All Pins Except LIN and VBAT

LIN and VBAT ±6 kV IEC61000-4-2 for LIN and VBAT ±7 kV Storage Temperature 150°C Junction Temperature

Transient 150°C

Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C

200 mA can be sustained on the LIN pin for 2 seconds. The active internal

short circuit protection HVCFG[1] = 0 is required to be enabled on this device during LIN operation and is the default operation. This disconnects the LIN pin, if a short circuit event occurs, after the specified maximum period of 90 µs.

2.5 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 92

ADuC7039

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GPIO_5

VSS

IO_VSS

LIN

VBAT

TOP VIEW

IIN+

AGND

IIN–

VDDNCGPIO_4

AGND

REG_AVDD

24 23

GPIO_2/ MISO GPIO_1/ SCLK

GPIO_0/ SS

21 20

DGND

REG_DVDD

8463-003

32313029282726

RESET

1 GPIO_3/MOSI 2

TDO

TCK

TMS

TDI

NTRST

RTCK

NOTES:

1. FOR DETAILS ON NC PINS, SEE T HE PIN FUNCT ION DESCRIPTIO NS TABLE.

2. EPAD IS INTERNALLY CO NNECTED TO DGND.

ADuC7039

4 5

(Not to Scale)

6 7 8REG_AVDD

10111213141516

VTEMP

GND_SW

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

RESET

I Reset Input Pin. Active low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When not in

use, this pin can be left unconnected. For added security and robustness, it is recommended that this pin be strapped via a resistor to REG_DVDD.

2 TDO O

JTAG Test Data Output. This data output pin is one of the standard 6-pin JTAG debug ports on the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an internal, weak, pull-up resistor. This pin can be left unconnected when not in use.

3 TCK I

JTAG Test Clock. This clock input pin is one of the standard 6-pin JTAG debug ports on the part. TCK is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected when not in use.

4 TMS I

JTAG Test Mode Select. This mode select input pin is one of the standard 6-pin JTAG debug ports on the part. TMS is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected when not in use.

5 TDI I

JTAG Test Data Input. This data input pin is one of the standard 6-pin JTAG debug ports on the part. TDI is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected when not in use.

6 NTRST I

JTAG Test Reset. This reset input pin is one of the standard 6-pin JTAG debug ports on the part. NTRST is an input pin only and has an internal, weak, pull-down resistor. This pin can be left unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode.

7 RTCK O

JTAG Return Test Clock. This output pin is used to adjust the JTAG clock speed to the highest possible

rate of the ADuC7039. 8 NC No Connect. This pin is internally connected; therefore, do not externally connect this pin. 9 GND_SW I

Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature

channel and external reference. If this input is not used, connect it directly to the AGND system ground. 10 VTEMP I External Pin for NTC/PTC Temperature Measurement. 11, 14, 15 AGND S Ground Reference for On-Chip Precision Analog Circuits. 12 IIN+ I Positive Differential Input for Current Channel. 13 IIN− I Negative Differential Input for Current Channel. 16, 17 REG_AVDD S

Nominal 2.6 V analog Output from On-Chip Regulator. Pin 16 and Pin 17 must be connected together

to a capacitor to ground. 18, 19 REG_DVDD S

Nominal 2.6 V digital Output from On-Chip Regulator. Pin 18 and Pin 19 must be connected together

to capacitors to ground. 20 DGND S Ground Reference for On-Chip Digital Circuits.

Rev. B | Page 9 of 92

ADuC7039

Pin No. Mnemonic Type1 Description

GPIO_0/SS

22 GPIO_1/SCLK I/O

23 GPIO_2/MISO I/O

24 GPIO_3/MOSI I/O

25 GPIO_4 I/O

26 NC

27 VDD S Battery Power Supply to On-Chip Regulator. 28 VBAT I Battery Voltage Input to Resistor Divider. 29 LIN I/O LIN Serial Interface Input/Output Pin. 30 IO_VSS S Ground Reference for LIN Pin. 31 VSS S Ground Reference. This is the ground reference for the internal voltage regulators. 32 GPIO_5 I/O

EPAD EPAD The exposed pad is internally connected to DGND.

I = input, O = output, S = supply.

I/O General-Purpose Digital I/O 0, or SPI Interface. By default, this pin is configured as an input. The

pin has an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 0. SPI interface, slave select input.

General-Purpose Digital I/O 1 or SPI Interface. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 1. SPI interface, serial clock input.

General-Purpose Digital I/O 2 or SPI Interface. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 2. SPI interface, master input/slave output pin.

General-Purpose Digital I/O 3 or SPI Interface. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 3. SPI interface, master output/slave input pin.

General-Purpose I/O 4. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and when not in use, can be left unconnected.

No Connect. This pin is not internally connected, but is reserved for possible future use. Therefore, do not externally connect this pin.

General-Purpose I/O 5. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and when not in use, can be left unconnected.

Rev. B | Page 10 of 92

ADuC7039

TERMINOLOGY

Conversion Rate

The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC has settled.

The sigma-delta (Σ-) conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output giving a valid 16-bit data conversion result at output rates from 1 Hz to 1 kHz.

Note that when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this can require multiple conversion cycles.

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale.

No Missing Codes

No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2

bits, where N = no missing codes, guaranteed to occur through the full ADC input range.

Offset Error

Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition.

Offset Error Drift

Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSB/°C or nV/°C.

Gain Error

Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function.

Output Noise

The output noise is specified as the standard deviation (or 1 × Σ) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as µV or nV rms. The output, or rms noise, can be used to calculate the effective resolution of the ADC as defined by the following equation:

Effective Resolution = log

(Full-Scale Range/rms Noise) bits

The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-to-peak noise is, therefore, calculated as 6.6 × the rms noise.

The peak-to-peak noise can be used to calculate the ADC (noise free, code) resolution for which there is no code flicker within a 6.6 × Σ limit as defined by the following equation:

Noise Free Code Resolution = log

(Full-Scale Range/Peak-

to-Peak Noise) bits

Table 4. Data Sheet Acronyms

Acronym Definition

ADC Analog-to-digital converter ARM Advanced RISC machine JTAG Joint test action group LIN Local interconnect network LSB Least significant byte/bit MCU Microcontroller MMR Memory mapped register MSB Most significant byte/bit OTP One time programmable PID Protected identifier POR Power-on reset rms Root mean square

Rev. B | Page 11 of 92

ADuC7039

THEORY OF OPERATION

The ADuC7039 is a complete system solution for battery monitoring in 12 V automotive applications. This device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters including battery current, voltage, and temperature over a wide range of operating conditions.

Minimizing external system components, the device is powered directly from the 12 V battery. An on-chip, low dropout regulator generates the supply voltage for two integrated, 16-bit, Σ- ADCs. The ADCs precisely measure battery current, voltage, and temperature to characterize the state of health and charge of the car battery.

A Flash/EE memory-based ARM7™ microcontroller (MCU) is also integrated on-chip. It is used to both preprocess the acquired battery variables and to manage communications from the ADuC7039 to the main electronic control unit (ECU) via a local interconnect network (LIN) interface that is integrated on-chip.

The MCU can be configured to operate in normal or flexible power saving modes of operation.

In its normal operating mode, the MCU is clocked indirectly from an on-chip oscillator via the phase-locked loop (PLL) at a maximum clock rate of 10.24 MHz. In its power saving operating modes, the MCU can be totally powered down, waking up only in response to the wake-up timer, a POR, or a LIN communication event.

The ADC can be configured to operate in a normal (full power) mode of operation, interrupting the MCU after various sample conversion events.

On-chip factory firmware supports in-circuit Flash/EE reprogramming via the LIN or JTAG serial interface ports, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting the ADuC7039.

The ADuC7039 operates directly from the 12 V battery supply and is fully specified over a temperature range of −40°C to +115°C. The ADuC7039 is functional, but with degraded performance, at temperatures from 115°C to 125°C.

OVERVIEW OF THE ARM7TDMI-S CORE

The ARM7 core is a 32-bit, reduced instruction set computer (RISC), developed by ARM® Ltd. The ARM7TDMI-S is a von Neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16, or 32 bits, and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating.

The ARM7TDMI-S is an ARM7 core with four additional features, as listed in Tabl e 5.

Table 5. ARM7TDMI-S

Feature Description

T Support for the Thumb® (16-bit) instruction set D Support for debug M Enhanced multiplier I

Includes the EmbeddedICE™ module to support embedded system debugging

Thumb Mode (T)

An ARM instruction is 32 bits long. The ARM7TDMI-S processor supports a second instruction set compressed into 16 bits, the Thumb instruction set. Faster code execution from 16-bit memory and greater code density can be achieved by using the Thumb instruction set, making the ARM7TDMI-S core particularly suited for embedded applications.

However, the Thumb mode has three limitations.

• Relative to ARM, the Thumb code usually requires more

instructions to perform that same task. Therefore, ARM code is best for maximizing the performance of timecritical code in most applications.

• The Thumb instruction set does not include some

instructions that are needed for exception handling, so ARM code can be required for exception handling.

• When an interrupt occurs, the core vectors to the interrupt

location in memory and executes the code present at that address. The first command is required to be in ARM code.

Multiplier (M)

The ARM7TDMI-S instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result.

EmbeddedICE (I)

The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI-S. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. Once in a debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory mapped registers.

Rev. B | Page 12 of 92

ADuC7039

ARM7 Exceptions

The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows:

• Normal interrupt or IRQ. This is provided to service

general-purpose interrupt handling of internal and external events.

• Fast interrupt or FIQ. This is provided to service data

transfer or a communication channel with low latency. FIQ has priority over IRQ.

• Memory abort (prefetch and data).

• Attempted execution of an undefined instruction.

• Software interrupt (SWI) instruction that can be used

to make a call to an operating system.

Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type.

The priority of these exceptions and the vector addresses are listed in Table 6 .

Table 6. Exception Priorities and Vector Addresses

Priority Exception Address

1 Hardware reset 0x00 2 Memory abort (data) 0x10 3 FIQ 0x1C 4 IRQ 0x18 5 Memory abort (prefetch) 0x0C 6 Software interrupt1 0x08 6 Undefined instruction1 0x04

A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive.

ARM Registers

The ARM7TDMI-S has 16 standard registers. R0 to R12 are used for data manipulation, R13 is the stack pointer, R14 is the link register, and R15 is the program counter that indicates the instruction currently being executed. The link register contains the address from which the user has branched (if the branch and link command was used) or the command during which an exception occurred.

The stack pointer contains the current location of the stack. As a general rule, on an ARM7TDMI-S, the stack starts at the top of the available RAM area and descends using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. On the ADuC7039, the stack begins at 0x00040FFC and descends. When programming using high level languages, such as C, it is necessary to ensure that the stack does not over-flow. This is dependent on the performance of the compiler that is used.

When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the

Rev. B | Page 13 of 92

stack pointer (R13) and the link register (R14) as represented in Figure 4. The FIQ mode has more registers (R8 to R12) supporting faster interrupt processing. With the increased number of noncritical registers, the interrupt can be processed without the need to save or restore these registers, thereby reducing the response time of the interrupt handling process.

More information relative to the programmer’s model and the ARM7TDMI-S core architecture can be found in ARM7TDMI-S technical and ARM architecture manuals available directly from ARM Ltd.

R13_ABT

R14_ABT

ABORT

MODE

USABLE IN USER MODE

SYSTEM MODES ONLY

IRQ

R13_UND

R14_UND

SPSR_UND

UNDEFINED

MODE

R13_IRQ

R14_IRQ

SPSR_IRQ

MODE

R10

R11

R12

R13

R14

R15 (PC)

CPSR

USER MODE

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

SPSR_FIQ

R13_SVC

R14_SVC

SVC

MODE

SPSR_ABT

SPSR_SVC

FIQ

MODE

Figure 4. Register Organization

Interrupt Latency

The worst-case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, and the time for the longest instruction to complete (the longest instruction is an LDM that loads all the registers including the PC), plus the time for the data abort entry and the time for FIQ entry. At the end of this time, the ARM7TDMI-S is executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, or just under 5 s in a system using a continuous 10.24 MHz processor clock. The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode where this is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time the request can take through the synchronizer and the time to enter the exception mode.

Note that the ARM7TDMI-S initially (first instruction) runs in ARM (32-bit) mode when an exception occurs. The user can immediately switch from ARM mode to Thumb mode if required, for example, when executing interrupt service routines.

08463-004

ADuC7039

MEMORY ORGANIZATION

The ARM7, a von Neumann architecture, MCU core sees memory as a linear array of 2 the ADuC7039 maps this into four distinct user areas, namely: a memory area that can be remapped, an SRAM area, a Flash/EE area, and a memory mapped register (MMR) area.

0xFFFF0000

0x00080000

0x00040000

0x00000000

Figure 5. ADuC7039 Memory Map, 64 kB Flash Option

• The first 64 kB of this memory space is used as an area into

which the on-chip Flash/EE or SRAM can be remapped.

• The ADuC7039 features a second 4 kB area at the top of

the memory map used to locate the MMRs, through which all on-chip peripherals are configured and monitored.

• The ADuC7039 features an SRAM size of 4 kB.

• The ADuC7039 features 64 kB of on-chip Flash/EE

memory. However, 62 kB of on-chip Flash/EE memory are available to the user. In addition, 2 kB are reserved for the on-chip kernel.

byte locations. As shown in Figure 5,

RESERVED

0xFFFF0FFF

0x0008FFFF

0x0040FFF

0x0000F7FF

MMRs

RESERVED

FLASH/EE

RESERVED

SRAM

RESERVED

REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM)

8463-005

SRAM

The ADuC7039 features 4 kB of SRAM, organized as 1024 × 32 bits, that is, 1024 words, which is located at 0x40000.

The RAM space can be used as data memory and also as a volatile program space.

ARM code can run directly from SRAM at full clock speed given that the SRAM array is configured as a 32-bit wide memory array. SRAM is read/writeable in 8-, 16-, and 32-bit segments.

Remap

The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020.

By default, after a reset, the Flash/EE memory is logically mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000. This is accomplished by setting Bit 0 of the SYSMAP MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000, Bit 0 of SYSMAP is cleared.

It is sometimes desirable to remap RAM to 0x00000000 to execute code from SRAM while erasing a page of Flash/EE memory.

Remap Operation

When a reset occurs on the ADuC7039, execution starts automatically in the factory programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7039 is in normal mode, it executes the power-on configuration routine of the kernel and then jumps to the reset vector, Address 0x00000000, to execute the user’s reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE.

Any access, either reading or writing, to an area not defined in the memory map results in a data abort exception.

Memory Format

The ADuC7039 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address, and the most significant byte in the highest byte address.

BIT 31

BYTE 3

. . .

BYTE 2

BYTE 1

32 BITS

Figure 6. Little Endian Format

BYTE 0

. . .

BIT 0

0xFFFFFFFF

0x00000004

0x00000000

8463-007

Rev. B | Page 14 of 92

ADuC7039

The remap command must be executed from the absolute Flash/EE address, and not from the mirrored, remapped segment of memory, because this may be replaced by SRAM. If a remap operation is executed while operating code from the mirrored location, prefetch/data aborts can occur, or the user can observe abnormal program operation.

Any kind of reset logically remaps the Flash/EE memory to the bottom of the memory array.

SYSMAP Register

Name: SYSMAP

RSTSTA Register

Name: RSTSTA

Address: 0xFFFF0230

Default Value: N/A

Access: Read/write

Function: This 8-bit register indicates the source of the

last reset event and can also be written by user code to initiate a software reset.

Address: 0xFFFF0220

Default Value: Updated by the kernel

Access: Read/write

Function: This 8-bit register allows user code to remap

either RAM or Flash/EE space into the bottom of the ARM memory space starting at Address 0x00000000.

Table 7. SYSMAP MMR Bit Designations

Bit Description

7 to 1

Reserved. These bits are reserved and should be written as 0 by user code.

0 Remap bit.

This bit is set by the user to remap the SRAM to 0x00000000.

This bit is cleared automatically after reset to remap the Flash/EE memory to 0x00000000.

RESET

There are four kinds of reset: external reset, power-on-reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset event are tabulated in Ta ble 9.

RSTCLR Register

Name: RSTCLR

Address: 0xFFFF0234

Access: Write only

Function: This 8-bit write-only register clears the

corresponding bit in RSTSTA.

Table 8. RSTSTA/RSTCLR MMR Bit Designations

Bit Description

7 to 4 Not used. These bits are not used and always read as 0. 3 External reset. This bit is set by hardware when an external reset occurs. This bit is cleared by setting the corresponding bit in RSTCLR. 2 Software reset. This bit is set by user code to generate a software reset. This bit is cleared by setting the corresponding bit in RSTCLR.1 1 Watchdog timeout. This bit is set by hardware when a watchdog timeout occurs. This bit is cleared by setting the corresponding bit in RSTCLR. 0 Power-on reset. This bit is set by hardware when a power-on-reset occurs. This bit is cleared by setting the corresponding bit in RSTCLR.

If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset.

Table 9. Device Reset Implications

Impact

Reset External

RESET

POR Yes Yes Yes Yes Yes Yes Yes/No2 RSTSTA[0] = 1 Watchdog Yes Yes Yes Yes Yes No Yes RSTSTA[1] = 1 Software Yes Yes Yes Yes Yes No Yes RSTSTA[2] = 1 External Pin Yes Yes Yes Yes Yes No Yes RSTSTA[3] = 1

RAM is not valid in the case of a reset following LIN download.

The impact on RAM is dependent on the HVSTA[2] contents if LVF is enabled. When LVF is enabled using HVCFG[4], RAM has not been corrupted by the POR reset

mechanism if the LVF Status Bit HVSTA[2] is 1. See the Low Voltage Flag (LVF) section for more information.

Pins to Default State

Kernel Executed

Reset All External MMRs (Excluding RSTSTA)

Reset All HV Indirect Registers

Peripherals Reset

Watchdog Timer Reset

RAM Valid1

RSTSTA (Status After Reset Event)

Rev. B | Page 15 of 92

ADuC7039

FLASH/EE MEMORY

The ADuC7039 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space.

Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased, the erase being performed in page blocks. Thus, flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated within the ADuC7039, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes.

The Flash/EE memory is physically located at 0x80000. Upon a hard reset, it logically maps to 0x00000000. The factory default contents of all Flash/EE memory locations is 0xFFFF. Flash/EE can be read in 8-/16-/32-bit segments, and written in segments of 16 bits. The Flash/EE is rated for 10,000 endurance cycles. This rating is based on the number of times that each individual byte is cycled, that is, erased and programmed. Implementing a redundancy scheme in the software ensures a greater than 10,000-cycle endurance.

The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data.

The entire Flash/EE is available to the user as code and nonvolatile data memory. There is no distinction between data and program, because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. The ARM7TDMI-S operates at a fixed 10.24 MHz clock frequency, but the Flash/EE memory controller is operating at 20.48 MHz. This means that the Flash/EE memory controller can transparently fetch the second 16-bit half-word (part of the 32-bit ARM operation code) within a single core clock period.

The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to erase a page. To write a 16-bit word requires 50 s.

It is possible to write to a single, 16-bit location at most twice between erases; that is, it is possible to walk bytes, not bits. If a location is written to more than twice, then it is possible to corrupt the contents of the Flash/EE page.

The Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port.

Serial Downloading (In-Circuit Programming)

The ADuC7039 facilitates code download via the LIN pin. The protocol is documented in the AN-946 Application Note, Flash/EE Memory Programming via LIN (Protocol 6).

JTAG Access

The ADuC7039 features an on-chip JTAG debug port to facilitate code download and debug.

FLASH/EE MMR INTERFACE

Access to, and control of, the Flash/EE memory on the ADuC7039 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as a single block of 64 kB.

Note that if executing from Flash/EE memory, the MCU core is halted until the command is completed. User software must ensure that the Flash/EE controller has completed any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle is completed, the Flash/EE page can be corrupted. User code, LIN, and JTAG programming use the Flash/EE control interface, consisting of the following MMRs:

• FEESTA: read-only register, reflects the status of the

Flash/EE control interface.

• FEEMOD: sets the operating mode of the Flash/EE control

interface.

• FEECON: 8-bit command register. The commands are

interpreted as described in Ta bl e 10 .

• FEEDAT: 16-bit data register.

• FEEADR: 16-bit address register.

• FEESIG: holds the 24-bit code signature as a result of the

signature command being initiated.

• FEEHID: protection MMR. Controls read and write

protection of the Flash/EE memory code space. If previously configured via the FEEPRO register, FEEHID can require a software key to enable access.

• FEEPRO: a buffer of the FEEHID register that stores the

FEEHID value, thus, it automatically downloads to the FEEHID registers on subsequent reset and power-on events.

The following sections provide detailed descriptions of the bit designations for each of the Flash/EE control MMRs.

Rev. B | Page 16 of 92

ADuC7039

FEECON Register

Name: FEECON

Address: 0xFFFF0E08

Default Value: 0x07

Access: Read/write

Function: This 8-bit register is written by user code to control the operating modes of the Flash/EE memory controller.

Table 10. Command Codes in FEECON

Code Command Description

0x001 Reserved Reserved; this command should not be written by user code. 0x011 Single read Load FEEDAT with the 16-bit data indexed by FEEADR. 0x021 Single write Write FEEDAT at the address indexed by FEEADR. This operation takes 50 s. 0x031 Erase write

0x041 Single verify

0x051 Single erase Erase the page indexed by FEEADR. 0x061 Mass erase

0x07 Idle Default command. 0x08 Reserved Reserved; this command should not be written by user code. 0x09 Reserved Reserved; this command should not be written by user code. 0x0A Reserved Reserved; this command should not be written by user code. 0x0B Signature

0x0C Protect

0x0D Reserved Reserved; this command should not be written by user code. 0x0E Reserved Reserved; this command should not be written by user code. 0x0F Ping No operation; interrupt generated.

The FEECON always reads 0x07 immediately after execution of any of these commands.

Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation takes 20 ms.

Compare the contents of the location indexed by FEEADR to the data in FEEDAT. The result of the comparison is returned in FEESTA Bit 1.

Erase 62 kB of user space. The 2 kB kernel is protected. This operation takes 2.48 seconds. To prevent accidental execution, a command sequence is required to execute this instruction; this is described in the Command Sequence for Executing a Mass Erase section.

This command results in a 24-bit, LFSR-based signature being generated and loaded into FEESIG. See the Flash/EE Memory Signature section.

This command can be run one time only. The value of FEEPRO is saved and can be removed only with a mass erase (0x06) or with the software protection key.

Rev. B | Page 17 of 92

ADuC7039

Command Sequence for Executing a Mass Erase

Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation.

1. Ensure FEESTA is cleared.

2. Set Bit 3 in FEEMOD.

3. Write 0xFFC3 in FEEADR.

4. Write 0x3CFF in FEEDAT.

5. Run the mass erase command (0x06) in FEECON.

This sequence is illustrated in the following example:

Int a = FEESTA; // Ensure FEESTA is cleared FEEMOD = 0x08 FEEADR = 0xFFC3 FEEDAT = 0x3CFF FEECON = 0x06; //Mass erase command while (FEESTA & 0x04){} //Wait for command to finish

FEESTA Register

Name: FEESTA

Address: 0xFFFF0E00

Default Value: 0xXXX0

Access: Read only

Function: This 16-bit, read-only register can be read by user code and reflects the current status of the Flash/EE memory controller.

Table 11. FEESTA MMR Bit Designation

Bit Description

15 to 4 Reserved. 3 Flash/EE interrupt status bit.

This bit is cleared automatically when the FEESTA register is read by user code. 2 Flash/EE controller busy. This bit is set automatically when the Flash/EE controller is busy. This bit is cleared automatically when the controller is not busy. 1 Command fail. This bit is set automatically when a command written to FEECON completes unsuccessfully. This bit is cleared automatically when the FEESTA register is read by user code. 0 Command successful. This bit is set automatically by MCU when a command is completed successfully. This bit is cleared automatically when the FEESTA register is read by user code.

This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEEMOD register is set.

Rev. B | Page 18 of 92

ADuC7039

FEEMOD Register

Name: FEEMOD

Address: 0xFFFF0E04

Default Value: 0x0000

Access: Read/write

Function: This register is written by user code to configure the mode of operation of the Flash/EE memory controller.

Table 12. FEEMOD MMR Bit Designation

Bit Description

15 to 7 Not used. These bits are reserved for future functionality and should be written as 0 by user code. 6 to 5 Flash/EE security lock bits. These bits must be written as [6:5] = 1, 0 to complete the Flash/EE security protect sequence. 4 Flash/EE controller command complete interrupt enable. This bit is set by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command. This bit is cleared by user code to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command. 3 Flash/EE erase/write enable. This bit is set by user code to enable the Flash/EE erase and write access via FEECON. This bit is cleared by user code to disable the Flash/EE erase and write access via FEECON. 2 Reserved. 1

0 Reserved.

Flash/EE controller abort enable. This bit is set by user code to enable the Flash/EE controller abort functionality. This bit is cleared by user code to disable the Flash/EE controller abort functionality.

FEEADR Registers

Name: FEEADR

Address: 0xFFFF0E10

Default Value: Updated by kernel

Access: Read/write

Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEECON acts.

FEEDAT Registers

Name: FEEDAT

Address: 0xFFFF0E0C

Default Value: 0x0000

Access: Read/write

Function: This 16-bit register contains the data either read from, or to be written to, the Flash/EE memory.

Rev. B | Page 19 of 92

ADuC7039

FLASH/EE MEMORY SIGNATURE

The entire 62 kB or the part of Flash/EE memory available to the user can be signed using the FEESIG register and signature command.

This feature automatically reads the code in that section of the memory specified by the FEEADR and FEEDAT MMRS:

• FEEADR contains an address situated in the first half page

of the section to be signed.

• FEEDAT contains an address situated in the first half page

above the last page of the section to be signed. See Figure 7 in this example, Page 0 and Page 1 are signed.

0x80400

PAGE 1

0x80200

FEEDAT = 0x04XX

• If the 8 MSB of FEEADR and FEEDAT are identical, that

is, the MMRS point to the same page, nothing is signed.

• The last two 16-bit locations are not included in the

signature; they are reserved for the user-programmed signature.

• It is possible to sign half pages, by specifying a half page

address in FEEADR and FEEDAT. For example, to sign the second half of Page 0 and the first half of Page 1, FEEADR = 0x0100 and FEEDAT = 0x0300.

This feature is also used by the on-chip kernel at power-up to check the validity of Page 0 before jumping to user code. Store the signature of Page 0 at Address 0x801FC when programming the device. See the ADUC7039 Kernel section for more details.

Flash/EE Memory Signature Registers

Name: FEESIG

Address: 0xFFFF0E18

Default Value: Updated by kernel

Access: Read only

Function: This MMR contains a 24-bit signature of the

Flash/EE memory.

PAGE 0

0x80000

Figure 7. Signature Command Indexing

FEEADR = 0x00XX

08463-008

Example of User Code Signature

Int a = FEESTA; // Ensure FEESTA is cleared FEEADR = 0x0000; // Start page address FEEDAT = 0x0600; // Stop (page + 1) address FEECON = 0x0B; // Signs Page 0 to Page 2 excluding

// Address 0x805FC while (FEESTA & 0x04){} // Wait for command to finish

User code can compare the content of FEESIG with the content of Address 0x805FC.

Polynomial

A software routine is provided by Analog Devices, Inc., to calculate the unique 24-bit signature.

Rev. B | Page 20 of 92

ADuC7039

FLASH/EE MEMORY SECURITY

The 62 kB of Flash/EE memory available to the user can be read- and write-protected using the FEEHID register.

The MSB of FEEHID (Bit 31) protects the entire Flash/EE from being read through JTAG.

Bits[30:0] of FEEHID protect Page 123 to Page 0 from writing. Each bit protects four pages, that is, 2 kB. On the 30 kB version, Bits[30:15] are unused.

Flash/EE Memory Protection Registers

Name: FEEHID and FEEPRO

Address: 0xFFFF0E20 (for FEEHID) and 0xFFFF0E1C (for FEEPRO)

Default Value: 0xFFFFFFFF (for FEEHID) and 0x00000000 (for FEEPRO)

Access: Read/write

Function: These registers are written by user code to configure the protection of the Flash/EE memory.

Table 13. FEEHID and FEEPRO MMR Bit Designations

Bit Description

31 Read protection. This bit is cleared by user code to read protect the 62 kB Flash/EE block code. This bit is set by user code to allow read access to the 62 kB Flash/EE block via JTAG. 30 to 0 Write protection bits.

When set by user code, these bits unprotect Page 0 to Page 123 of the 62 kB Flash/EE code memory. Each bit write protects four pages, and each page consists of 512 bytes.

When cleared by user code, these bits write protect Page 0 to Page 123 of the 62 kB Flash/EE code memory. Each bit write protects four pages, and each page consists of 512 bytes.

The FEEPRO register mirrors the bit definitions of the FEEHID MMR. The FEEPRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. This flexibility allows the user to temporarily set and test protection settings using the FEEHID MMR and, subsequently, lock the required protection configuration (using FEEPRO) when shipping protection systems into the field.

Rev. B | Page 21 of 92

ADuC7039

In summary, there are three levels of protection as follows.

Temporary Protection

Temporary protection can be set and removed by writing directly into FEEHID MMR. This register is volatile and, therefore, protection is only in place for as long as the part remains powered on. This protection is not reloaded after a power cycle.

Keyed Permanent Protection

Keyed permanent protection can be set via FEEPRO to lock the protection configuration. The software key used at the start of the required FEEPRO write sequence is saved one time only and must be used for any subsequent access of the FEEHID or FEEPRO MMRs. A mass erase sets the software protection key back to 0xFFFF but also erases the entire user code space.

Permanent Protection

Permanent protection can be set via FEEPRO, similarly to keyed permanent protection, the only difference being that

Int a = FEESTA; // Ensure FEESTA is cleared FEEPRO = 0xFFFFFFFB; // Protect Page 8 to Page 11 FEEADR = 0x66BB; // 32-bit key value (Bits[31:16]) FEEDAT = 0xAA55; // 32-bit key value (Bits 15:0]) FEEMOD = 0x0048 // Lock security sequence FEECON = 0x0C; // Write key command while (FEESTA & 0x04){}

// Wait for command to finish

the software key used is 0xDEADDEAD. When the FEEPRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF. This also erases the entire user code space.

Sequence to Write the Software Protection Key and Set Permanent Protection

1. Write in FEEPRO corresponding to the pages to be protected.

2. Write the new (user-defined) 32-bit software protection

key in FEEADR (Bits[31:16]) and FEEDAT (Bits[15:0]).

3. Write 1, 0 in FEEMOD (Bits[6:5]) and set FEEMOD (Bit 3).

4. Run the Write Key Command 0x0C in FEECON.

To remove or modify the protection, the same sequence can be used with a modified value of FEEPRO.

The previous sequence for writing the key and setting permanent protection is illustrated in the following example, this protects writing Page 8 to Page 11 of the Flash/EE.

Rev. B | Page 22 of 92

ADuC7039

FLASH/EE MEMORY RELIABILITY

The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as

• Initial page erase sequence.

• Read/verify sequence.

• Byte program sequence.

• Second read/verify sequence.

ADuC7039 KERNEL

The ADuC7039 features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel calculates its own checksum and compares it to the checksum programmed during production test, to ensure that the kernel does not contain any error. If an error occurs, the SYSCHK register contains its default value and user mode is entered. In normal circumstances, the checksum is written to the SYSCHK MMR.

System Kernel Checksum

Name: SYSCHK

Address: 0xFFFF0244

In reliability qualification, every half-word (16-bit wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Tab l e 1, the Flash/EE memory endurance qualification of the part is carried out in accordance with the JEDEC Retention Lifetime Specification A117. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. The part is qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature (T

= 85°C) as

indicated in Table 1. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Also, note that retention lifetime, based on an activation energy of 0.6 eV, derates with T

600

450

300

RETENTIO N (Years)

150

30 40 55 70 85 100 125 135 150

Figure 8. Flash/EE Memory Data Retention

as shown in Figure 8.

JUNCTION TEM PERATURE (°C)

08463-009

Default Value: 0x00000000 (updated by kernel at power-on)

Access: Read/write

Function: At power-on, this 32-bit register holds the

kernel checksum.

The kernel then copies the factory calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are as follows:

• Precision oscillator

• Low power oscillator

• REG_AVDD/REG_DVDD

• Voltage reference

• Current ADC (offset and gain)

• Voltage/temperature ADC (offset and gain)

Processor registers and user registers that can be modified by the kernel and differ from their POR default values are as follows:

• R0 to R15

• GP0CON

• SYSCHK

• FEEADR/FEEDAT/FEECON/FEESIG

• HVDAT/HVCON

• HVCFG

• T2LD

The ADuC7039 also features an on-chip LIN downloader.

A flow chart of the execution of the kernel is shown in Figure 9. The current revision of the kernel can be derived from R5, as described in Ta ble 6 5.

After any reset, the watchdog timer is disabled once the kernel code is exited. For the duration of the kernel execution, the watchdog timer is active with a timeout period of 500 ms. This ensures that if an error occurs in the kernel, the ADuC7039 automatically resets. If LIN download mode is entered, the watchdog is periodically refreshed.

Rev. B | Page 23 of 92

ADuC7039

Normal kernel execution time, excluding LIN download, is less than 5 ms. It is only possible to enter and leave LIN download mode through a reset.

SRAM Address 0 to Address 0x2B are modified during normal kernel execution, SRAM Address 0xFF to Address 0x110 are also modified during a LIN download.

Note that even with NTRST = 0, user code is not executed unless Address 0x1FC contains either 0x16400000 or the checksum of Page 0, excluding Address 0x1FC. If Address

0x1FC does not contain this information, user code is not executed and LIN download mode is entered. During kernel execution, JTAG access is disabled.

The ADuC7039 is delivered with flash user space fully erased and if NTRST = 0 at first power-up, the LIN download mode is entered.

With NTRST = 1, user code is always executed and JTAG is enabled.

0x801FC

YES

RESET

0x801FC = 0x16400000

KERNEL

CRC

INITIALIZE WDT

INITIALIZE HV CHIP

COPY MANID TO MMRs

NTRST = 1?

YES

NTRST = 1?

YESNO

SOFTW ARE

RESET

MULTIPLE

CRC ERROR?

POWER DOW N

LIN RECEIVE D?

YES

HANDLE LIN

COMMAND

0x801FC =

PAGE0 CRC?

YES

KICK WDT

RESET

COMMAND?

YES

Figure 9. ADuC7039 Kernel Flowchart

Rev. B | Page 24 of 92

KICK WDT

TRY TO SWITCH

OFF WDT

RUN

USER CODE

USER RESET?

YES

08463-010

ADuC7039

MEMORY MAPPED REGISTERS (MMR)

The memory mapped register (MMR) space is mapped into the top 4 kB of the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the memory mapped register bank for the ADuC7039 is shown in Figure 10.

The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the ARM7 core registers (described in the ARM Registers section) reside in the MMR area.

As shown in the detailed MMR maps in the Complete MMR Listing section (Table 14 to Ta b le 2 3), the MMR data widths vary from 1 byte (8 bits) to 4 bytes (32 bits). The ARM7 core can access any of the MMRs (single byte or multiple byte width registers) with a 32-bit read or write access.

The resultant read, for example, is aligned per little endian format as previously described in this data sheet. However, errors result if the ARM7 core tries to access 4-byte (32-bit) MMRs with a 16-bit access. In the case of a (16-bit) write access to a 32-bit MMR, the (upper) 16 most significant bits are written as 0s. More obviously, in the case of a 16-bit read access to a 32-bit MMR, only 16 of the MMR bits can be read.

0xFFFFFFF

0xFFFF0E24

0xFFFF0E00

0xFFFF0D20

0xFFFF0D00

0xFFFF0A14

0xFFFF0A00

0xFFFF0810

0xFFFF0804

0xFFFF0800

0xFFFF0700

0xFFFF0560

0xFFFF0500

0xFFFF 04A4

0xFFFF0400

0xFFFF0350

0xFFFF0340

0xFFFF0334

0xFFFF0320

0xFFFF0310

0xFFFF0300

0xFFFF0248

0xFFFF0220

0xFFFF0110

0xFFFF0000

FLASH CO NTRO L

INTERFACE

GPIO

SPI

INTERFACE

LIN

HARDWARE

ADC

PLL AND

OSCILLATOR CONTROL

WATCHDOG

TIMER 2

WAKE-UP

TIMER 1

TIMER 0

REMAP AND

SYSTEM CONTROL

INTERRUPT

CONTROLL ER

Figure 10. Top Level MMR Map

08463-011

Rev. B | Page 25 of 92

ADuC7039

COMPLETE MMR LISTING

In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.

Table 14. IRQ Address Base = 0xFFFF0000

Access

Address Name Byte

0x0000 IRQSTA 4 R 0x00000000 Active IRQ source. 0x0004 IRQSIG 4 R 0x00003080 Current state of all IRQ sources (enabled and disabled). 0x0008 IRQEN 4 RW 0x00000000 Enabled IRQ sources. 0x000C IRQCLR 4 W N/A MMR to disable IRQ sources. 0x0010 SWICFG 4 W N/A Software interrupt configuration MMR. 0x0100 FIQSTA 4 R 0x00000000 Active IRQ source. 0x0104 FIQSIG 4 R 0x00003081 Current state of all IRQ sources (enabled and disabled). 0x0108 FIQEN 4 RW 0x00000000 Enabled IRQ sources. 0x010C FIQCLR 4 W N/A MMR to disable IRQ sources.

Table 15. System Control Address Base = 0xFFFF0200

Address Name Byte

0x0220 SYSMAP 1 RW N/A REMAP control register. 0x0230 RSTSTA 1 RW N/A Reset status MMR. 0x0234 RSTCLR 1 W N/A RSTSTA clear MMR. 0x0244 SYSCHK1 4 RW N/A Kernel checksum. See the System Kernel Checksum section.

Updated by kernel.

Type Default Value Description

Access Type Default Value Description

Table 16. Timer Address Base = 0xFFFF0300

Access

Address Name Byte

Typ e

Default Value Description

0x0300 T0LD 2 RW 0x0000 Timer0 load register. 0x0304 T0VAL 2 R 0x0000 Timer0 Value Register 0. 0x0308 T0CON 4 RW 0x0000 Timer0 control MMR. 0x030C T0CLRI 1 W N/A Timer0 interrupt clear register. 0x0320 T1LD 4 RW 0x00000000 Timer1 load register. 0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 value register. 0x0328 T1CON 4 RW 0x0000 Timer1 control MMR. 0x032C T1CLRI 1 W N/A Timer1 interrupt clear register. 0x0340 T2LD1 4 RW 0x0050 Timer2 load register. 0x0344 T2VAL 4 R 0x00000050 Timer2 value register. 0x0348 T2CON 2 RW 0x0000 Timer2 control MMR. 0x034C T2CLRI 1 W N/A Timer2 interrupt clear register.

Updated by kernel.

Rev. B | Page 26 of 92

ADuC7039

Table 17. PLL Base Address = 0xFFFF0400

Access

Address Name Byte

0x0400 PLLSTA 4 R N/A PLL status MMR. 0x0404 POWKEY0 4 W N/A POWCON prewrite key. 0x0408 POWCON 2 RW 0x079 Power control register. 0x040C POWKEY1 4 W N/A POWCON postwrite key. 0x0410 PLLKEY0 4 W N/A PLLCON prewrite key. 0x0414 PLLCON 1 RW 0x00 PLL clock source selection MMR. 0x0418 PLLKEY1 4 W N/A PLLCON postwrite key. 0x0440 OSCCON 1 RW 0x00 Low power oscillator calibration control MMR. 0x0444 OSCSTA 1 R 0x00 Low power oscillator calibration status MMR. 0x0448 0SCVAL0 2 R 0x0000 Low Power Oscillator Calibration Counter 0 MMR. 0x044C OSCVAL1 2 R 0x0000 Low Power Oscillator Calibration Counter 1 MMR. 0x0480 LOCCON 1 RW 0x00 LIN oscillator calibration control register. 0x0484 LOCUSR0 1 RW N/A Low power oscillator user trim register. 0x0488 LOCUSR1 2 RW N/A Precision oscillator user trim register. 0x048C LOCMAX 3 RW 0x00000 LIN oscillator calibration, maximum baud rate tolerance (LINBR + x). 0x0490 LOCMIN 3 RW 0x00000 LIN oscillator calibration, minimum baud rate tolerance (LINBR − x). 0x0494 LOCSTA 1 R 0x01 LIN oscillator calibration status register. 0x0498 LOCVAL0 1 R N/A Low power oscillator current trim value register. 0x049C LOCVAL1 2 R N/A Precision oscillator current trim value register. 0x04A0 LOCKEY 2 W N/A LIN oscillator calibration lock register.

Type Default Value Description

Table 18. ADC Address Base = 0xFFFF0500

Access

Address Name Byte

0x0500 ADCSTA 2 R 0x0000 ADC status MMR. 0x0504 ADCMSKI 1 RW 0x00 ADC interrupt source enable MMR. 0x0508 ADCMDE 1 RW 0x00 ADC mode register. 0x050C ADC0CON 2 RW 0x0002 Current ADC control MMR. 0x0510 ADC1CON 2 RW 0x0000 V/T ADC control MMR. 0x0518 ADCFLT 2 RW 0x0007 ADC filter control MMR. 0x051C ADCCFG 1 RW 0x00 ADC configuration MMR. 0x0520 ADC0DAT 2 R 0x0000 Current ADC result MMR. 0x0524 ADC1DAT 2 R 0x0000 V/T ADC result MMR. 0x0530 ADC0OF1 2 RW N/A Current ADC offset MMR. 0x0534 ADC1OF1 2 RW N/A Voltage ADC offset MMR. 0x0538 ADC2OF1 2 RW N/A Temperature ADC offset MMR. 0x053C ADC0GN1 2 RW N/A Current ADC gain MMR. 0x0540 ADC1GN1 2 RW N/A Voltage ADC gain MMR. 0x0544 ADC2GN1 2 RW N/A Temperature ADC gain MMR. 0x0548 ADC0RCL 2 RW 0x0001 Current ADC result count limit. 0x054C ADC0RCV 2 R 0x0000 Current ADC result count value. 0x0550 ADC0TH 2 RW 0x0000 Current ADC result threshold. 0x055C ADC0ACC 4 R 0x00000000 Current ADC result accumulator.

Updated by kernel.

Typ e

Default Value Description

Rev. B | Page 27 of 92

ADuC7039

Table 19. LIN Base Address = 0XFFFF0700

Access

Address Name Byte

0x0700 LINCON 2 RW 0x0000 LIN control MMR. 0x0704 LINCS 1 RW 0xFF LIN checksum MMR. 0x0708 LINBR 3 RW 0x00FA0 19-bit LIN baud rate MMR. 0x070C LINBK 3 RW 0x0157C 19-bit LIN break MMR. 0x0710 LINSTA 2 R 0x0100 LIN status MMR. 0x0714 LINDAT 1 RW 0x00 LIN data MMR. 0x0718 LINLOW 3 RW 0x00000 LIN counter to force the bus low. 0x071C LINWU 3 RW 0x00013 LIN wake-up break length.

Table 20. High Voltage Interface Base Address = 0xFFFF0804

Address Name Byte

0x0804 HVCON 1 RW N/A High voltage interface control MMR. 0x080C HVDAT 1 RW N/A High voltage interface data MMR.

Table 21. SPI Base Address = 0xFFFF0A00

Address Name Byte

0x0A00 SPISTA 2 R 0x0000 SPI status MMR. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. 0x0A08 SPITX 1 W N/A SPI transmit MMR. 0x0A0C SPIDIV 1 R/W 0x00 SPI baud rate selection MMR. 0x0A10 SPICON 2 R/W 0x0000 SPI control MMR.

Type Default Value Description

Access Type Default Value Description

Table 22. GPIO Base Address = 0xFFFF0D00

Access

Address Name Byte

Type Default Value Description

0x0D00 GPCON 4 RW 0x00000000 GPIO port control MMR. 0x0D10 GPDAT1 4 RW 0x000000FF GPIO port data control MMR. 0x0D14 GPSET 4 W N/A GPIO port data set MMR. 0x0D18 GPCLR 4 W N/A GPIO port data clear MMR.

Depends on the level on the external GPIO pins.

Table 23. Flash/EE Base Address = 0xFFFF0E00

Access

Address Name Byte

Type Default Value Description

0x0E00 FEESTA 2 R 0xXXX0 Flash/EE status MMR. 0x0E04 FEEMOD 2 RW 0x0000 Flash/EE control MMR. 0x0E08 FEECON 1 RW 0x07 Flash/EE control MMR. 0x0E0C FEEDAT 2 RW 0x0000 Flash/EE data MMR. 0x0E10 FEEADR1 2 RW 0xF009 Flash/EE address MMR. 0x0E18 FEESIG 3 R N/A Flash/EE LFSR MMR. 0x0E1C FEEPRO 4 RW 0x00000000 Flash/EE protection MMR. 0x0E20 FEEHID 4 RW 0xFFFFFFFF Flash/EE protection MMR.

Updated by kernel.

Rev. B | Page 28 of 92

+ 64 hidden pages

ANALOG DEVICES ADuC7039 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

TIMING SPECIFICATIONS

LIN Timing Specifications

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

THEORY OF OPERATION

OVERVIEW OF THE ARM7TDMI-S CORE

Thumb Mode (T)

Multiplier (M)

EmbeddedICE (I)

ARM7 Exceptions

ARM Registers

Interrupt Latency

MEMORY ORGANIZATION

SRAM

Remap

Remap Operation

Memory Format

SYSMAP Register

RSTSTA Register

RESET

RSTCLR Register

FLASH/EE MEMORY

Serial Downloading (In-Circuit Programming)

JTAG Access

FLASH/EE MMR INTERFACE

FEECON Register

Command Sequence for Executing a Mass Erase

FEESTA Register

FEEMOD Register

FEEADR Registers

FEEDAT Registers

FLASH/EE MEMORY SIGNATURE

Flash/EE Memory Signature Registers

Example of User Code Signature

Polynomial

FLASH/EE MEMORY SECURITY

Flash/EE Memory Protection Registers

Temporary Protection

Keyed Permanent Protection

Permanent Protection

Sequence to Write the Software Protection Key and Set Permanent Protection

FLASH/EE MEMORY RELIABILITY

ADuC7039 KERNEL

System Kernel Checksum

MEMORY MAPPED REGISTERS (MMR)

COMPLETE MMR LISTING