ANALOG DEVICES ADuC7034 Service Manual

Integrated Precision Battery Sensor

FEATURES

High precision ADCs Dual channel, simultaneous sampling, 16-bit Σ-Δ ADCs Programmable ADC throughput from 1 Hz to 8 kHz On-chip 5 ppm/°C voltage reference Current channel

Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: −200 mV to +300 mV Digital comparators with current accumulator feature

Voltage channel

Buffered, on-chip attenuator for 12 V battery inputs

Temperature channel

External and on-chip temperature sensor options

Microcontroller

ARM7TDMI core, 16-/32-bit RISC architecture

20.48 MHz PLL with programmable divider PLL input source

On-chip precision oscillator On-chip low power oscillator External (32.768 kHz) watch crystal

JTAG port supports code download and debug

for Automotive

ADuC7034

Memory

32 kB Flash/EE memory, 4 kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE

retention

In-circuit download via JTAG and LIN

On-chip peripherals

SAEJ2602/LIN 2.0-compatible (slave) support via UART

with hardware synchronization Flexible wake-up I/O pin, master/slave SPI serial I/O 9-pin GPIO port, 3× general-purpose timers Wake-up and watchdog timers Power supply monitor and on-chip power-on reset

Power

Operates directly from 12 V battery supply Current consumption

Normal mode 10 mA at 10 MHz

Low power monitor mode

Package and temperature range

48-lead, 7 mm × 7 mm LFCSP Fully specified for −40°C to +115°C operation

APPLICATIONS

Battery sensing/management for automotive systems

FUNCTIONAL BLOCK DIAGRAM

TDO

2.6V LDO PSM POR

ARM7TDMI

MCU

20MHz

3× TIMERS

WDT

WU TIMER

GPIO_2

GPIO_1

NTRST

GPIO_3

TMS

ADuC7034

MEMORY

32kB FLASH

4kB RAM

PRECISION

LOW POWER

ON-CHIP PLL

GPIO PORT

UART PORT

SPI PORT

GPIO_4

GPIO_5

GPIO_6

OSC

LIN

RESET

XTAL1

XTAL2

STI

LIN/BSD

GPIO_7

GPIO_8

07116-001

TDI

TCK

PRECISION ANALO G ACQUISIT ION

IIN+

IIN–

VBAT

VTEMP

VREF

BUF

RESULT

ACCUMULATOR

MUX BUF

TEMPERATURE

SENSOR

VDD

REG_AVDD

REG_DVDD

AGND

PGA

DGND

16-BIT

Σ-Δ ADC

DIGITAL

COMPARATOR

16-BIT

Σ-Δ ADC

PRECISION

REFERENCE

VSS

IO_VSS

GPIO_0

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuC7034

Features .............................................................................................. 1

ADC Comparator and Accumulator ....................................... 56

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Electrical Specifications ............................................................... 4

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 15

ESD Caution ................................................................................ 15

Pin Configuration and Function Descriptions ........................... 16

Typical Performance Characteristics ........................................... 18

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 20

Overview of the ARM7TDMI Core ......................................... 20

Memory Organization ............................................................... 22

Reset ............................................................................................. 24

Flash/EE Memory ........................................................................... 25

Programming Flash/EE Memory In-Circuit .......................... 25

Flash/EE Control Interface ........................................................ 25

Flash/EE Memory Security ....................................................... 28

Flash/EE Memory Reliability .................................................... 29

CODE Execution Time from SRAM and Flash/EE ............... 30

ADuC7034 Kernel ...................................................................... 31

Memory-Mapped Registers ........................................................... 33

Complete MMR Listing ............................................................. 34

16-Bit Sigma-Delta Analog-to-Digital Converters .................... 40

Current Channel ADC (I-ADC) .............................................. 40

Voltage/Temperature Channel ADC (V-/T-ADC) ..................... 42

ADC Ground Switch .................................................................. 43

ADC Noise Performance Tables ............................................... 43

ADC MMR Interface ................................................................. 44

ADC Power Modes of Operation ............................................. 55

Rev. B | Page 2 of 136

ADC Sinc3 Digital Filter Response .......................................... 56

ADC Calibration ........................................................................ 59

ADC Diagnostics ........................................................................ 60

Power Supply Support Circuits ..................................................... 61

ADuC7034 System Clocks ............................................................ 62

System Clock Registers .............................................................. 63

Low Power Clock Calibration ................................................... 66

Processor Reference Peripherals ................................................... 68

Interrupt System ......................................................................... 68

Timers .............................................................................................. 71

Synchronization of timers Across Asynchronous Clock

Domains ...................................................................................... 71

Programming the Timers .......................................................... 72

Timer0—Lifetime Timer ........................................................... 74

Timer1.......................................................................................... 76

Timer2—Wake-Up Timer ......................................................... 78

Timer3—Watchdog Timer ........................................................ 80

Timer4—STI Timer ................................................................... 82

General-Purpose I/O ..................................................................... 84

General-Purpose I/O Registers ................................................ 86

High Voltage Peripheral Control Interface ................................. 95

High Voltage Peripheral Control Interface Registers ............ 96

Wake-Up (WU) Pin ................................................................. 102

Handling Interrupts from the High Voltage Peripheral

Control Interface ...................................................................... 103

Low Voltage Flag (LVF) ........................................................... 103

High Voltage Diagnostics ........................................................ 103

UART Serial Interface .................................................................. 104

Baud Rate Generation .............................................................. 104

UART Register Definition ....................................................... 105

Serial Peripheral Interface ........................................................... 110

MISO Pin ................................................................................... 110



ADuC7034

MOSI Pin ................................................................................... 110

BSD Communication Hardware Interface ............................ 126

SCLK Pin ................................................................................... 110

Pin ......................................................................................... 110

SPI Register Definitions .......................................................... 110

Serial Test Interface ...................................................................... 114

Serial Test Interface Registers ................................................. 114

Serial Test Interface Output Structure ................................... 116

Using the Serial Test Interface ................................................ 116

LIN (Local Interconnect Network) Interface ........................... 117

LIN MMR Description ............................................................ 117

LIN Hardware Interface .......................................................... 121

Bit Serial Device (BSD) Interface ............................................... 126

REVISION HISTORY

5/10—Rev. A to Rev. B

Changes to Table 6 .......................................................................... 15

Changes to Timers Section ............................................................ 71

BSD Related MMRs .................................................................. 127

BSD Communication Frame ................................................... 128

BSD Data Reception ................................................................. 129

BSD Data Transmission ........................................................... 129

Wake Up from BSD Interface .................................................. 129

Part Identification ......................................................................... 130

Part Identification Registers .................................................... 130

Schematic ....................................................................................... 133

Outline Dimensions ...................................................................... 134

Ordering Guide ......................................................................... 134

8/09—Rev. 0 to Rev. A

Changes to Features Section ............................................................ 1

Changes to Table 1 ............................................................................ 4

Added Exposed Pad Notation to Figure 7 and Table 7 .............. 16

Changes to Theory of Operation .................................................. 20

Changes to Table 45 ........................................................................ 65

Changes to Figure 35 ...................................................................... 78

Changes to Table 96 ......................................................................128

Changes to Figure 57 ....................................................................131

4/08—Revision 0: Initial Version

Rev. B | Page 3 of 136

ADuC7034

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference, f precision oscillator, all specifications T

= −40°C to +115°C, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS

Conversion Rate1 Chop off, ADC normal operating mode 4 8000 Hz Chop on, ADC normal operating mode 4 2600 Hz Chop on, ADC low power mode 1 650 Hz

Current Channel

No Missing Codes1 Valid for all ADC update rates and ADC modes 16 Bits Integral Nonlinearity Offset Error Offset Error Offset Error

2, 3 , 4 , 5

1, 3, 6

1, 3

1, 2

±10 ±60 ppm of FSR

Chop off, 1 LSB = 36.6 V/gain −10 ±3 +10 LSB

Chop on −2 ±0.5 +2 V

Chop on, low power mode or low power plus

mode, MCU powered down Offset Error Offset Error Drift6

1, 3

Chop on, normal mode, CD = 1 +0.5 −1.25 −3 V

Chop off, valid for ADC gains of 4 to 64,

normal mode Offset Error Drift6

Chop off, valid for ADC gains of 128 to 512,

normal mode Offset Error Drift6 Chop on 10 nV/°C Tot al Gai n Erro r Total Gain Error Total Gain Error

1, 3, 7 , 8 , 9 , 10

1, 3, 7, 9

1, 3, 7, 9, 11

Normal mode −0.5 ±0.1 +0.5 %

Low power mode using ADCREF MMR −4 ±0.2 +4 %

Low power plus mode, using precision VREF −1 ±0.2 +1 % Gain Drift 3 ppm/°C PGA Gain Mismatch Error ±0.1 %

Output Noise

1, 12

4 Hz update rate, gain = 512, ADCFLT = 0xBF1D 60 90 nV rms

4 Hz update rate, gain = 512, ADCFLT = 0x3F1D 75 115 nV rms

10 Hz update rate, gain = 512, ADCFLT = 0x961F

10 Hz update rate, gain = 512, ADCFLT =

0x161F 1 kHz update rate, gain ≥ 64, ADCFLT = 0x8101 0.8 1.2 µV rms 1 kHz update rate, gain ≥ 64, ADCFLT = 0x0101 1 1.5 µV rms

1 kHz update rate, gain = 512, ADCFLT =

0x0007 1 kHz update rate, gain = 32, ADCFLT = 0x0007 0.8 1.2 µV rms 1 kHz update rate, gain = 8, ADCFLT = 0x8101 2.1 4.1 µV rms

1 kHz update rate, gain = 8, ADCFLT = 0x0007 1.6 2.4 µV rms

1 kHz update rate, gain = 8, ADCFLT = 0x0101 2.6 3.9 µV rms 1 kHz update rate, gain = 4, ADCFLT = 0x0007 2.0 2.8 µV rms 8 kHz update rate, gain = 32, ADCFLT = 0x0000 2.5 3.5 µV rms 8 kHz update rate, gain = 4, ADCFLT = 0x0000 14 21 µV rms ADC low power mode, f ADC low power mode, f ADC low power plus mode, f

ADC low power plus mode, f gain = 512, chop enabled

= 10.24 MHz driven from external 32.768 kHz watch crystal or on-chip

CORE

+100 −50 −300 nV

0.03 LSB/°C

30 nV/°C

100 150 nV rms

120 180 nV rms

0.6 0.9 µV rms

= 10 Hz, gain = 128 1.25 1.9 µV rms

ADC

= 1 Hz, gain = 128 0.35 0.5 µV rms

ADC

= 1 Hz, gain = 512 0.1 0.15 µV rms

ADC

= 250 Hz,

ADC

0.6 0.9 µV rms

Rev. B | Page 4 of 136

ADuC7034

Parameter Test Conditions/Comments Min Typ Max Unit

Voltage Channel13

No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error Offset Error Offset Error Drift Chop off 0.03 LSB/°C Total Gain Error Total Gain Error Gain Drift Includes resistor mismatch drift 3 ppm/°C

Output Noise 10 Hz update rate, ADCFLT = 0x961F 60 90 µV rms 1 kHz update rate, ADCFLT = 0x0007 180 270 µV rms 1 kHz update rate, ADCFLT = 0x8101 240 307 µV rms 1 kHz update rate, ADCFLT = 0x0101 270 405 µV rms 8 kHz update rate, ADCFLT = 0x0000 1600 2400 µV rms

Temperature Channel

No Missing Codes1 Valid at all ADC update rates 16 Bits

Integral Nonlinearity1 ±10 ±60 ppm of FSR

Offset Error

Offset Error Drift Chop off 0.03 LSB/°C

Tot al Gai n Erro r

Gain Drift 3 ppm/°C

Output Noise1 1 kHz update rate 7.5 11.25 µV rms ADC SPECIFICATIONS ANALOG

INPUT Current Channel

Absolute Input Voltage Range Applies to both IIN+ and IIN− −200 +300 mV

Input Voltage Range Gain = 219 ±600 mV Gain = 419 ±300 mV Gain = 8 ±150 mV Gain = 16 ±75 mV Gain = 32 ±37.5 mV Gain = 64 ±18.75 mV Gain = 128 ±9.375 mV Gain = 256 ±4.68 mV Gain = 512 ±2.3 mV

Input Leakage Current1 −3 +3 nA

Input Offset Current

Voltage Channel

Absolute Input Voltage Range 4 18 V

Input Voltage Range 0 to 28.8 V

VBAT Input Current VBAT = 18 V 3 5.5 8 µA

Temperature Channel Reference selection: REG_AVDD/2 to GND_SW/2

Absolute Input Voltage Range 100 1300 mV

Input Voltage Range 0 to VREF V

VTEMP Input Current1 2.5 160 nA

3, 5

Chop off, 1 LSB = 439.5 µV −10 ±1 +10 LSB

1, 3

Chop on 0.3 1 LSB

1, 3, 7, 10, 14

Includes resistor mismatch −0.25 ±0.06 +0.25 %

1, 3, 7, 10, 14

Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 %

1, 15

4 Hz update rate, ADCFLT = 0xBF1D 60 90 µV rms

3, 4, 5, 16

Chop off, 1 LSB = 19.84 V in unipolar mode −10 ±3 +10 LSB

1, 3

Chop on −5 +1 +5 LSB

1, 3, 14

−0.2 ±0.06 +0.2 %

Internal VREF = 1.2 V

17, 18

Gain = 1

1, 20

0.5 1.5 nA

±1.2 V

Rev. B | Page 5 of 136

ADuC7034

Parameter Test Conditions/Comments Min Typ Max Unit

VOLTAGE REFERENCE

ADC Precision Reference

Internal VREF 1.2 V Power-Up Time1 0.5 ms Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 %

Temperature Coefficient

Reference Long-Term Stability22 100 ppm/1000 hr

External Reference Input Range23 0.1 1.3 V VREF Divide-by-2 Initial Error1 0.1 0.3 % ADC Low Power Reference

Internal VREF 1.2 V Initial Accuracy Measured at TA = 25°C −5 +5 %

Initial Accuracy1 Using ADCREF, measured at TA = 25°C 0.1 %

Temperature Coefficient

ADC DIAGNOSTICS

VREF/1361 At any gain settings 8.5 9.4 mV Voltage Attenuator Current

Source

RESISTIVE ATTENUATOR

Divider Ratio 24 Resistor Mismatch Drift 3 ppm/°C

ADC GROUND SWITCH

Resistance Direct path to ground 10 Ω

20 kΩ resistor selected1 10 20 30 kΩ

Input Current

TEMPERATURE SENSOR24 After user calibration

Accuracy MCU in power-down or standby mode ±3 °C

POWER-ON RESET (POR)

POR Trip Level Refers to the voltage at the VDD pin 2.85 3.0 3.15 V POR Hysteresis 300 mV Reset Timeout from POR 20 ms

LOW VOLTAGE FLAG (LVF)

LVF Level Refers to the voltage at the VDD pin 1.9 2.1 2.3 V

POWER SUPPLY MONITOR (PSM)

PSM Trip Level Refers to the voltage at the VDD pin 6.0 V

WATCHDOG TIMER (WDT)

Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms

FLASH/EE MEMORY1

Endurance25 10,000 Cycles Data Retention

DIGITAL INPUTS All digital inputs except NTRST

Input Leakage Current Input high = REG_DVDD ±1 ±10 µA Input Pull-Up Current Input low = 0 V −80 −20 −10 µA Input Capacitance 10 pF Input Leakage Current NTRST only: input low = 0 V ±1 ±10 µA Input Pull-Down Current NTRST only: input high = REG_DVDD 30 55 100 µA

1, 21

−20 ±5 +20 ppm/°C

1, 21

−300 ±150 +300 ppm/°C

Differential voltage increase on the attenuator

3.1 3.8 V when the current source is on, over a range of T

= −40°C to +85°C

Allowed continuous current through the switch

6 mA

with direct path to ground

MCU in power-down or standby mode,

±2 °C

temperature range = −25°C to +65°C

20 Years

Rev. B | Page 6 of 136

ADuC7034

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS1 All logic inputs

Input Low Voltage (V Input High Voltage (V

CRYSTAL OSCILLATOR1

Logic Inputs, XTAL1 Only

Input Low Voltage (V

Input High Voltage (V XTAL1 Capacitance 12 pF XTAL2 Capacitance 12 pF

ON-CHIP OSCILLATORS

Low Power Oscillator 131.072 kHz

Accuracy27 Includes drift data from 1000 hour life test −3 +3 %

Precision Oscillator 131.072 kHz

Accuracy Includes drift data from 1000 hour life test −1 +1 %

MCU CLOCK RATE

MCU START-UP TIME

At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down

Oscillator Running

Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms

Crystal Powered Down

Wake Up from Interrupt 500 ms

Internal PLL Lock Time 1 ms

LIN INPUT/OUTPUT GENERAL

Baud Rate 1000 20,000 bps VDD

Input Capacitance 5.5 pF Input Leakage Current Input low = IO_VSS −800 −400 µA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 µs I

LIN_DOM_MAX

LIN_PAS_REC

LIN

LIN_PAS_DOM

LIN_NO_GND

LIN_DOM

LIN_REC

LIN_CNT

HYS

LIN_DOM_DRV_LOSUP

LIN_DOM_DRV_HISUP

LIN_RECESSIVE

Driver off, 7.0 V < V

VBAT disconnected, VDD = 0 V, 0 < V

Input leakage V

LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V

LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V

LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V

LIN receiver hysteresis voltage 0.175 VDD V

= 500 Ω 1.2 V

LOAD

= 1000 Ω 0.6 V

LOAD

= 500 Ω 2 V

LOAD

= 1000 Ω 0.8 V

LOAD

LIN recessive output voltage 0.8 VDD V VBAT Shift28 0 0.1 VDD V GND Shift28 0 0.1 VDD V

) 0.4 V

INL

) 2.0 V

INH

) 0.8 V

INL

) 1.7 V

INH

Eight programmable core clock selections

0.160 10.24 20.48 MHz within this range (binary divisions 1, 2, 4, 8, … 64, 128)

Supply voltage range at which the LIN interface

7 18 V

is functional

Current limit for driver when LIN bus is in

40 200 mA

dominant state, VBAT = VBAT (maximum)

< 18 V, VDD = V

LIN

= 0 V −1 mA

LIN

Control unit disconnected from ground, GND = VDD; 0 V < V

LIN dominant output voltage, VDD = 7 V

LIN dominant output voltage, VDD = 18 V

< 18 V; VBAT = 12 V

LIN

Rev. B | Page 7 of 136

− 0.7 V −20 +20 µA

LIN

< 18 V 10 µA

LIN

−1 +1 mA

ADuC7034

Parameter Test Conditions/Comments Min Typ Max Unit

Slave termination resistance 20 30 47 kΩ

SLAVE

SERIAL DIODE

Symmetry of Transmit

Receive Propagation Delay1 VDD (minimum) = 7 V 6 µs Symmetry of Receive Propagation

LIN VERSION1.3 SPECIFICATION

SYM

LIN VERSION 2.0 SPECIFICATION

BSD INPUT/OUTPUT29

Baud Rate 1164 1200 1236 bps Input Leakage Current Input high = VDD, or input low = IO_VSS −50 +50 µA Output Low Voltage (VOL) 1.2 V Output High Voltage (VOH) 0.8 VDD V Short-Circuit Output Current (I Input Low Voltage (V Input High Voltage (V

WAKE-UP R

VDD1

Input Leakage Current Input high = VDD 0.4 2.1 mA Input low = IO_VSS −50 +50 µA V

VIH Input high level 4.6 V VIL Input low level 1.2 V Monoflop Timeout Timeout period 0.6 1.3 2 sec Short-Circuit Output Current (I

SERIAL TEST INTERFACE R

Baud Rate 40 kbps Input Leakage Current Input high = VDD, or input low = IO_VSS −50 +70 µA VDD Supply voltage range for which STI is functional 7 18 V VOH Output high level 0.6 VDD V VOL Output low level 0.4 VDD V VIH Input high level 0.6 VDD V VIL Input low level 0.4 VDD V

PACKAGE THERMAL

SPECIFICATIONS Thermal Shutdown Thermal Impedance (θJA)32 48-lead LFCSP, stacked die 45 °C/W

Voltage drop at the internal diode 0.4 0.7 1 V

VDD (minimum) = 7 V −4 +4 µs

VDD (minimum) = 7 V −2 +2 µs

Bus load conditions (C

BUS

||R

BUS

Propagation Delay

Delay

1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω

Symmetry of rising and falling edge, VBAT = 18 V −5 +5 µs

Slew rate Dominant and recessive edges, VBAT = 18 V

Slew rate Dominant and recessive edges, VBAT = 7 V

0.5

Symmetry of rising and falling edge, VBAT = 7 V −4 +4 µs Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ,

6.8 nF||660 Ω, 10 nF||500 Ω Duty Cycle 1, TH

0.581 × VBAT, V D1 = t

BUS_REC(MIN)

Duty Cycle 2, TH

0.422 × VBAT, V D2 = t

BUS_REC(MAX)

) V

o(sc)

) 1.8 V

INL

) 0.7 VDD V

INH

= VDD = 12 V 40 80 200 mA

BSD

= 300 Ω, C

LOAD

= 0.744 × VBAT, TH

REC(MAX)

= 7.0 V … 18 V, t

SUP

/(2 × t

)

BIT

= 0.284 × VBAT, TH

REC(MIN)

= 7.0 V … 18 V; t

SUP

/(2 × t

= 91 nF, R

BUS

)

BIT

DOM(MAX)

= 50 µs,

BIT

DOM(MIN)

= 50 µs,

BIT

= 39 Ω

LIMIT

Supply voltage range at which the WU pin is

0.396

0.581

7 18 V

functional

Output high level 5 V

Output low level 2 V

) 100 140 mA

o(sc)

= 500 Ω, C

LOAD

= 2.4 nF, R

BUS

= 39 Ω

LIMIT

1, 31

140 150 160 °C

V/ µs

Rev. B | Page 8 of 136

ADuC7034

Parameter Test Conditions/Comments Min Typ Max Unit

POWER REQUIREMENTS

Power Supply Voltages

VDD (Battery Supply) 3.5 18 V REG_DVDD, REG_AVDD33 2.5 2.6 2.7 V

Power Consumption

IDD (MCU Normal Mode)34 MCU clock rate = 10.24 MHz, ADC off 10 20 mA MCU clock rate = 20.48 MHz, ADC off 20 mA IDD (MCU Powered Down)

IDD (MCU Powered Down)

IDD (Current ADC) 1.7 mA IDD (Voltage/Temperature ADC) 0.5 mA IDD (Precision Oscillator) 400 µA

These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.

Valid for a current channel ADC PGA setting of 4 to 64.

These numbers include temperature drift.

Tested at a gain range of 4; self-offset calibration removes this error.

Measured with an internal short after an initial offset calibration.

Measured with an internal short.

These numbers include internal reference temperature drift.

Factory calibrated at a gain of 1.

System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature).

Includes an initial system calibration.

Using ADC normal mode voltage reference.

Typical noise in low power modes is measured with chop enabled.

Voltage channel specifications include resistive attenuator input stage.

System calibration removes this error at the specified temperature.

RMS noise is referred to the voltage attenuator input (for example, at f

to yield these input-referred noise figures.

Valid after an initial self-calibration.

In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.

It is possible to extend the ADC input range by up to 10% by modifying the factory-set value of the gain calibration register or by using system calibration. Extending

the ADC input range can also be used to reduce the ADC input range (LSB size).

Limited by minimum/maximum absolute input voltage range.

Valid for a differential input less than 10 mV.

Measured using the box method.

The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.

References of up to REG_AVDD can be accommodated for by enabling an internal divide-by-2.

Die temperature.

Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.

Retention lifetime equivalent at a junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.

Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.

These numbers are not production tested, but are supported by LIN compliance testing.

BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and C

This specification does not apply directly to the WU pin but includes an R

In response to a thermal shutdown event, the MCU core is not shut down but is interrupted, and the high voltage I/O pins are disabled.

Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.

Internal regulated supply available at REG_DVDD (I

The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

ADC low power mode, measured over the range of T

= −10°C to +40°C, continuous ADC

conversion ADC low power mode, measured over the

range of T

= −40°C to +85°C, continuous ADC

conversion ADC low power plus mode, measured over an

ambient temperature range of TA = −10°C to +40°C, continuous ADC conversion

Average current, measured with wake-up and watchdog timer clocked from the low power oscillator, T

= −40°C to +85°C

Average current, measured with wake-up and watchdog timer clocked from low power oscillator over a range of T

= 5 mA) and REG_AVDD (I

SOURCE

= −10°C to +40°C

= 1 kHz, typical rms noise at the ADC input is 7.5 V) and scaled by the attenuator (divide-by-24)

ADC

of 39 Ω on the wake-up line.

LIMIT

SOURCE

= 1 mA).

300 400 µA

300 500 µA

520 700 µA

120 300 µA

120 175 µA

= 10 nF maximum.

Load

Rev. B | Page 9 of 136

ADuC7034

TIMING SPECIFICATIONS

SPI Timing Specifications

Table 2. SPI Master Mode Timing—Phase Mode = 1

Parameter Description Min Typ Max Unit tSL SCLK low pulse width1 (SPIDIV + 1) × t tSH SCLK high pulse width1 (SPIDIV + 1) × t t

Data output valid after SCLK edge2 (2 × t

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge2 3 × t

DHD

UCLK

tDF Data output fall time 3.5 ns tDR Data output rise time 3.5 ns tSR SCLK rise time 3.5 ns tSF SCLK fall time 3.5 ns

depends on the clock divider (CD) bits in the POWCON MMR. t

HCLK

= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.

UCLK

HCLK

= t

UCLK

/2CD.

SCLK

(POLARIT Y = 0)

SCLK

(POLARIT Y = 1)

DAV

HCLK

) + (2 × t

UCLK

) ns

HCLK

MOSI

MISO

MSB IN BITS [6:1] LSB IN

DSUtDHD

Figure 2. SPI Master Mode Timing—PHASE Mode = 1

LSBBITS [6:1]MSB

07116-002

Rev. B | Page 10 of 136

ADuC7034

Table 3. SPI Master Mode Timing—PHASE Mode = 0

Parameter Description Min Typ Max Unit tSL SCLK low pulse width1 (SPIDIV + 1) × t tSH SCLK high pulse width1 (SPIDIV + 1) × t t

Data output valid after SCLK edge2 (2 × t

DAV

Data output setup before SCLK edge ½ tSL ns

DOSU

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge2 3 × t

DHD

UCLK

tDF Data output fall time 3.5 ns tDR Data output rise time 3.5 ns tSR SCLK rise time 3.5 ns tSF SCLK fall time 3.5 ns

depends on the clock divider (CD) bits in the POWCON MMR. t

HCLK

= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.

UCLK

HCLK

= t

UCLK

/2CD.

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

DOSU

DAV

HCLK

) + (2 × t

UCLK

) ns

HCLK

MOSI

MISO

MSB IN BITS [6:1] LSB IN

DSUtDHD

Figure 3. SPI Master Mode Timing—PHASE Mode = 0

LSBBITS [6:1]MSB

7116-003

Rev. B | Page 11 of 136

ADuC7034

Table 4. SPI Slave Mode Timing—PHASE Mode = 1

Parameter Description Min Typ Max Unit

tSS

to SCLK edge

tSL SCLK low pulse width1 (SPIDIV + 1) × t tSH SCLK high pulse width1 (SPIDIV + 1) × t t

Data output valid after SCLK edge2 (3 × t

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge2 4 × t

DHD

tDF Data output fall time 3.5 ns tDR Data output rise time 3.5 ns tSR SCLK rise time 3.5 ns tSF SCLK fall time 3.5 ns t

SFS

depends on the clock divider (CD) bits in the POWCON MMR. t

HCLK

= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.

UCLK

high after SCLK edge

½ t

UCLK

½ t

= t

/2CD.

HCLK

UCLK

HCLK

) + (2 × t

UCLK

) ns

HCLK

SCLK

(POLARIT Y = 0)

SCLK

(POLARIT Y = 1)

MISO

MOSI

DAV

DSUtDHD

MSB IN BITS [6:1] LSB IN

SFS

LSBBITS [6:1]MSB

07116-004

Figure 4. SPI Slave Mode Timing—PHASE Mode = 1

Rev. B | Page 12 of 136

ADuC7034

Table 5. SPI Slave Mode Timing—PHASE Mode = 0

Parameter Description Min Typ Max Unit

tSS

to SCLK edge

tSL SCLK low pulse width1 (SPIDIV + 1) × t tSH SCLK high pulse width1 (SPIDIV + 1) × t t

Data output valid after SCLK edge2 (3 × t

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge2 4 × t

DHD

tDF Data output fall time 3.5 ns tDR Data output rise time 3.5 ns tSR SCLK rise time 3.5 ns tSF SCLK fall time 3.5 ns t

DOCS

SFS

depends on the clock divider (CD) bits in the POWCON MMR. t

HCLK

= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.

UCLK

Data output valid after SS

high after SCLK edge

edge2

DOCS

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

½ t

UCLK

(3 × t ½ t

= t

DAV

/2CD.

UCLK

HCLK

) + (2 × t

UCLK

) + (2 × t

UCLK

SFS

) ns

HCLK

) ns

HCLK

MISO

MOSI

MSB IN BITS [6:1] LSB IN

DSUtDHD

Figure 5. SPI Slave Mode Timing—PHASE Mode = 0

Rev. B | Page 13 of 136

LSBBITS [6:1]MSB

07116-005

ADuC7034

LIN Timing Specifications

TRANSMIT

INPUT TO

TRANSMITTING

NODE

(TRANSCEIVER SUPPLY

OF TRANSMIT TING NODE)

SUP

RxD

(OUTP UT OF RECEIVI NG NODE 1)

RECESSIVE

DOMINANT

REC (MAX)

DOM (MAX)

REC (MIN)

DOM (MI N)

BIT

LIN_DOM (M AX)

LIN_DO M (MI N)

RX_PDF

BIT

LIN_REC ( MIN)

LIN_REC ( MAX)

RX_PDR

BIT

THRESHOLDS OF RECEIVING NO DE 1

THRESHOLDS OF RECEIVING NO DE 2

LIN

BUS

(OUTPUT O F RECEIVING NODE 2)

RxD

Figure 6. LIN 2.0 Timing Specification

RX_PDR

RX_PDF

07116-006

Rev. B | Page 14 of 136

ADuC7034

ABSOLUTE MAXIMUM RATINGS

= −40°C to +115°C, unless otherwise noted.

Table 6.

Parameter Rating

AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V VBAT to AGND −22 V to +40 V VDD to VSS −0.3 V to +33 V VDD to VSS for 1 sec −0.3 V to +40 V LIN to IO_VSS −16 V to +40 V STI and WU to IO_VSS −3 V to +33 V Wake-Up Continuous Current 50 mA Short-Circuit Current of High

Voltage I/O Pins Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V VREF to AGND −0.3 V to REG_AVDD + 0.3 V ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V ESD Human Body Model (HBM) Rating

HBM-ADI0082 (Based on ANSI/ESD STM5.1-2007) All Pins except LIN and VBAT

LIN and VBAT ±6KV

IEC 61000-4-2 for LIN and VBAT ±7 kV Storage Temperature 125°C Junction Temperature

Transient 150°C

Continuous 130°C Lead Temperature

Soldering Reflow (15 sec) 260°C

100 mA

1 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 15 of 136

ADuC7034

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IO_VSS

STINCVSSNCVDDWUNCNCNC

LIN/BS

4847464544434241403938

XTAL2

RESET

TCK

TDI

DGND

TDO

NTRST

TMS

1 2

4 5 6

9 10 11

GPIO_5/IRQ1/RxD

GPIO_6/ TxD

GPIO_7/IRQ4 GPIO_8/IRQ5

NOTES

1. NC = NO CONNECT.

2. THE EXPO SED PAD SHOULD BE CONNECTED TO DGND.

PIN 1 INDICATOR

ADuC7034

TOP VIEW

(Not to Scale)

13141516171819

VBAT

VREF

VTEMP

GND_SW

2021222324

IIN–

IIN+

AGND

35 34 33

31 30

28 27 26 25

AGND

REG_AVDD

Figure 7. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

RESET

I Reset Input. Active low. This pin has an internal weak pull-up resistor to REG_DVDD and should

be left unconnected when not in use. For added security and robustness, it is recommended that this pin be strapped via a resistor to REG_DVDD.

2 GPIO_5/IRQ1/RxD I/O

General-Purpose Digital IO 5/External Interrupt Request 1 (Active High)/Receive Data for UART Serial Port. By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

3 GPIO_6/TxD I/O

General-Purpose Digital IO 6/Transmit Data for UART Serial Port. By default and after a poweron reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

4 GPIO_7/IRQ4 I/O

General-Purpose Digital IO 7/External Interrupt Request 4 (Active High). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

5 GPIO_8/IRQ5 I/O

General-Purpose Digital IO 8/External Interrupt Request 5 (Active High). By default and after power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

6 TCK I

JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part. TCK is an input pin only and has an internal weak pull-up resistor. This pin should be left unconnected when not in use.

7 TDI I

JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the part. TDI is an input pin only and has an internal weak pull-up resistor. This pin should be left

unconnected when not in use. 8, 34, 35 DGND S Ground Reference for On-Chip Digital Circuits. 9, 16, 23,

32, 38 to

No Connect. Not internally connected and are reserved for possible future use. Therefore, do

not externally connect these pins. These pins can be grounded, if required. 40, 43, 45

17, 25, 26 NC

No Connect. Internally connected and are reserved for possible future use. Therefore, do not

externally connect these pins. These pins can be grounded, if required. 10 TDO O

JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on

the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an

internal weak pull-up resistor. This pin should be left unconnected when not in use.

XTAL136

DGND DGND REG_DVDD

GPIO_4/ECLK GPIO_3/MOSI

GPIO_2/MISO

GPIO_1/SCLK GPIO_0/IRQ0/SS NC NC

07116-007

Rev. B | Page 16 of 136

ADuC7034

Pin No. Mnemonic Type1 Description

11 NTRST I

12 TMS I

13 VBAT I Battery Voltage Input to Resistor Divider. 14 VREF I

15 GND_SW I

18 VTEMP I External Pin for NTC/PTC Temperature Measurement. 19 IIN+ I Positive Differential Input for Current Channel. 20 IIN− I Negative Differential Input for Current Channel. 21, 22 AGND S Ground Reference for On-Chip Precision Analog Circuits. 24 REG_AVDD S Nominal 2.6 V Output from On-Chip Regulator. 27

GPIO_0/IRQ0/SS

I/O

28 GPIO_1/SCLK I/O

29 GPIO_2/MISO I/O

30 GPIO_3/MOSI I/O

31 GPIO_4/ECLK I/O

33 REG_DVDD S Nominal 2.6 V Output from the On-Chip Regulator. 36 XTAL1 O Crystal Oscillator Output. If an external crystal is not used, this pin should be left unconnected. 37 XTAL2 I

41 WU I/O

42 VDD S Battery Power Supply to On-Chip Regulator. 44 VSS S Ground Reference. This is the ground reference for the internal voltage regulators. 46 STI I/O

47 IO_VSS S Ground Reference for High Voltage I/O Pins. 48 LIN/BSD I/O Local Interconnect Network IO/Bit Serial Device IO. This is a high voltage pin. EPAD Exposed Pad The exposed pad should be connected to digital ground.

I = input, O = output, S = supply.

JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part. NTRST is an input pin only and has an internal weak pull-down resistor. This pin should be left unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode.

JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports on the part. TMS is an input pin only and has an internal weak pull-up resistor. This pin should be left unconnected when not in use.

External Reference Input Terminal. When this input is not used, connect it directly to the AGND system ground. This pin should be left unconnected when not in use.

Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature channel and the external reference. When this input is not used, connect it directly to the AGND system ground.

General-Purpose Digital IO 0/External Interrupt Request 0 (Active High)/Slave Select Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

General-Purpose Digital IO 1/Serial Clock Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

General-Purpose Digital IO 2/Master Input, Slave Output (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

General-Purpose Digital IO 3/Master Output, Slave Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

General-Purpose Digital IO 4/2.56 MHz Clock Output. By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use.

Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system ground.

High Voltage Wake-Up. This high voltage I/O pin has an internal 10 kΩ pull-down resistor and a high-side driver to VDD. If this pin is not being used, it should not be connected externally.

High Voltage Serial Test Interface Output. If this pin is not used, externally connect it to the IO_VSS ground reference.

Rev. B | Page 17 of 136

ADuC7034

TYPICAL PERFORMANCE CHARACTERISTICS

–0.2

VDD = 4V

–0.4

–0.6

OFFSET (µV)

–0.8

–1.0

VDD = 18V

CORE OFF

–0.5

–1.0

–1.5

OFFSET (µV)

–2.0

CD = 1

CD = 0

–1.2

–40 –10 20 50 80 115 140

TEMPERATURE ( °C)

Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU

–0.5

–1.0

–1.5

OFFSET (µV)

–2.0

–2.5

4 6 8 1012141618

–40°C

+25°C

+115°C

VDD (V)

Figure 9. ADC Current Channel Offset vs. VDD (10 MHz, MCU)

–2.5

4 6 8 101214161820

07116-056

VDD (V)

07116-058

Figure 10. ADC Current Channel Offset vs. Supply @ 25°C

07116-057

Rev. B | Page 18 of 136

ADuC7034

TERMINOLOGY

Conversion Rate

The conversion rate specifies the rate at which an output result is available from the ADC after the ADC has settled.

The Σ- conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, providing a valid 16-bit data conversion result for output rates from 1 Hz to 8 kHz.

Note that when software switches from one input to another on the same ADC, the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this may require multiple conversion cycles.

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition (111 ... 110 to 111 ... 111). The error is expressed as a percentage of full scale.

No Missing Codes

No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits (as 2

bits, where N is no missing codes) and specifies the number of codes (ADC results) that are guaranteed to occur through the full ADC input range.

Offset Error

Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition.

Offset Error Drift

Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per degrees Celsius.

Gain Error

Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function.

Output Noise

The output noise is specified as the standard deviation (that is, 1 × Σ) of the distribution of ADC output codes that are collected when the ADC input voltage is at a dc voltage. It is expressed as µV rms. The output, or rms noise, can be used to calculate the effective resolution of the ADC as defined by the following equation:

Effective Resolution = log

(Full-Scale Range/RMS Noise)

where Effective Resolution is expressed in bits.

The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes that are collected when the ADC input voltage is at dc. The peak-topeak noise is therefore calculated as 6.6 times the rms noise.

The peak-to-peak noise can be used to calculate the ADC (noise-free code) resolution for which there is no code flicker within a 6.6 × Σ limit as defined by the following equation:

Noise-Free Code Resolution = log

(Full-Scale Range/Peak-

to-Peak Noise)

where Noise-Free Code Resolution is expressed in bits.

Rev. B | Page 19 of 136

ADuC7034

THEORY OF OPERATION

The ADuC7034 is a complete system solution for battery monitoring in 12 V automotive applications. This device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, including battery current, voltage, and temperature, over a wide range of operating conditions.

Minimizing external system components, the device is powered directly from the 12 V battery. An on-chip low dropout regulator generates the supply voltage for two integrated 16-bit Σ- ADCs. The ADCs precisely measure battery current, voltage, and temperature to characterize the state of health and state of charge of the car battery.

A Flash/EE memory-based ARM7™ microcontroller (MCU) is also integrated on chip. It is used both to preprocess the acquired battery variables and to manage communication from the ADuC7034 to the main electronic control unit (ECU) via a local interconnect network (LIN) interface that is integrated on chip.

Both the MCU and the ADC subsystem can be individually configured to operate in normal or flexible power-saving modes of operation.

In its normal operating mode, the MCU is clocked indirectly from an on-chip oscillator via the phase-locked loop (PLL) at a maximum clock rate of 20.48 MHz. In its power-saving operating modes, the MCU can be totally powered down, waking up only in response to an ADC conversion result being ready, a digital comparator event, a wake-up timer event, a power-on rest (POR) event, or an external serial communication event.

The ADC can be configured to operate in a normal (full power) mode of operation, interrupting the MCU after various sample conversion events. The current channel features two low power modes—low power mode and low power plus mode—that generate conversion results to a lower performance specification.

On-chip factory firmware supports in-circuit Flash/EE reprogramming via the LIN or JTAG serial interface ports, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting the ADuC7034.

The ADuC7034 operates directly from the 12 V battery supply and is fully specified over a temperature range of −40°C to +115°C. The ADuC7034 is functional but has degraded performance at temperatures from 115°C to 125°C.

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit reduced instruction set computer (RISC) developed by ARM Ltd. The ARM7TDMI is a von Neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16, or 32 bits, and the length of the instruction word can

be either 16 bits or 32 bits, depending on the mode in which the core is operating.

The ARM7TDMI is an ARM7 core with four additional features, as listed in Tabl e 8.

Table 8. ARM7TDMI

Feature Description

T Support for the Thumb® (16-bit) instruction set D Support for debug M Enhanced multiplier I

Includes the EmbeddedICE™ module to support embedded system debugging

Thumb Mode (T)

An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set, called the Thumb instruction set, which is compressed into 16 bits. Faster code execution from 16-bit memory and greater code density can be achieved by using the Thumb instruction set; therefore, the ARM7TDMI core is particularly suited for embedded applications.

However, the Thumb mode has three limitations:

• Relative to ARM, the Thumb code usually requires more

instructions to perform a task. Therefore, ARM code is best for maximizing the performance of time-critical code in most applications.

• The Thumb instruction set does not include some instruct-

tions that are needed for exception handling; therefore, ARM code may be required for exception handling.

• When an interrupt occurs, the core vectors to the interrupt

location in memory and executes the code present at that address. The first command is required to be in ARM code.

Multiplier (M)

The ARM7TDMI instruction set includes an enhanced multiplier with four extra instructions to perform 32-bit × 32-bit multiplication with a 64-bit result, or 32-bit × 32-bit multiplication-accumulation (MAC) with a 64-bit result.

EmbeddedICE (I)

The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. When in the debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memorymapped registers.

Rev. B | Page 20 of 136

ADuC7034

ARM7 Exceptions

The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows:

• Normal interrupt (IRQ). This is provided to service

general-purpose interrupt handling of internal and external events.

• Fast interrupt (FIQ). This is provided to service a data

transfer or a communication channel with low latency. FIQ has priority over IRQ.

• Memory abort (prefetch and data).

• Attempted execution of an undefined instruction.

• Software interrupt (SWI) instruction. This can be used to

make a call to an operating system.

Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type.

The priority of these exceptions and vector address are listed in Tabl e 9.

Table 9. Exception Priorities and Vector Addresses

Priority Exception Address

1 Hardware reset 0x00 2 Memory abort (data) 0x10 3 FIQ 0x1C 4 IRQ 0x18 5 Memory abort (prefetch) 0x0C 6 Software interrupt1 0x08 6 Undefined instruction1 0x04

A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive.

The vectors for the exception modes listed in Tabl e 9 are located at Address 0x00 to Address 0x1C, with a reserved register at Address 0x14. Location 0x14 must be written as either 0x27011970 or the checksum of Page 0 (excluding Location 0x14); otherwise, user code does not execute and LIN download mode is entered.

ARM Registers

The ARM7TDMI has 16 standard registers. R0 to R12 are used for data manipulation, R13 is the stack pointer, R14 is the link register, and R15 is the program counter that indicates the instruction currently being executed. The link register contains the address from which the user has branched (if the branch and link command was used) or the command during which an exception occurred.

The stack pointer contains the current location of the stack. As a general rule, on an ARM7TDMI the stack starts at the top of the available RAM area and descends, using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. On the ADuC7034, the stack begins at 0x00040FFC and then descends. When programming using highlevel languages, such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used.

When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 11. The FIQ mode has additional registers (R8 to R12) that support faster interrupt processing. With the increased number of noncritical registers, the interrupt can be processed without the need to save or restore these registers, thereby reducing the response time of the interrupt handling process.

More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the ARM7TDMI technical manual and the ARM architecture manual, available directly from ARM Ltd.

USABLE IN USER MO DE

SYSTEM MODES ONLY

R13_ABT

R14_ABT

ABORT

MODE

R13_IRQ

R14_IRQ

SPSR_IRQ

IRQ

MODE

R13_UND

R14_UND

SPSR_UND

UNDEFINED

MODE

R10

R11

R12

R13

R14

R15 (PC)

CPSR

USER MODE

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

SPSR_FIQ

Figure 11. Register Organization

FIQ

MODE

R13_SVC

R14_SVC

SPSR_SVC

SVC

MODE

SPSR_ABT

Interrupt Latency

The worst-case latency for an FIQ consists of the longest possible time for the request to pass through the synchronizer, for the longest instruction to complete (the longest instruction is an LDM) and load all the registers including the PC, and for the data abort entry and the FIQ entry to complete. At the end of this time, the ARM7TDMI executes the instruction at Address 0x1C (the FIQ interrupt vector address). Therefore, the maximum FIQ latency is 50 processor cycles, or just over 2.44 s in a system using a continuous 20.48 MHz processor clock.

07116-008

Rev. B | Page 21 of 136

ADuC7034

The maximum IRQ latency can be similarly calculated, but must allow for the fact that FIQ has higher priority and may delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode, which reduces the time to 22 cycles.

The minimum latency for a FIQ or IRQ is five cycles. This consists of the shortest time for the request to pass through the synchronizer plus the time to enter the exception mode.

Note that the ARM7TDMI initially (first instruction) runs in ARM (32-bit) mode when an exception occurs. The user can immediately switch from ARM mode to Thumb mode if required, for example, when executing interrupt service routines.

MEMORY ORGANIZATION

The ARM7 MCU core, which has a von Neumann-based architecture, sees memory as a linear array of 2 As shown in Figure 13, the ADuC7034 maps this into four distinct user areas, namely, a memory area that can be remapped, an SRAM area, a Flash/EE area, and a memory-mapped register (MMR) area.

byte locations.

0xFFFF 0000

0xFFFF0FFF

0x00087FFF

0x00080000

0x00040FFF

0x00040000

0x00007FFF

0x00000000

Figure 13. ADuC7034 Memory Map

SRAM

The ADuC7034 features 4 kB of SRAM, organized as 1024 × 32 bits, that is, 1024 words located at 0x00040000.

The RAM space can be used as data memory and also as a volatile program space.

RESERVED

MMRs

RESERVED

FLASH/EE

RESERVED

SRAM

RESERVED

REMAPPABLE MEMO RY SPACE (FLASH/EE OR SRAM)

07116-010

• For the ADuC7034, the first 30 kB of this memory space is

used as an area into which the on-chip Flash/EE or SRAM can be remapped.

• The ADuC7034 features a second 4 kB area at the top of

the memory map used to locate the MMRs, through which all on-chip peripherals are configured and monitored.

• The ADuC7034 features an SRAM size of 4 kB.

• The ADuC7034 features 32 kB of on-chip Flash/EE

memory, 30 kB of which are available to the user and 2 kB of which are reserved for the on-chip kernel.

Any access, either a read or a write, to an area not defined in the memory map results in a data abort exception.

Memory Format

The ADuC7034 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address; the most significant byte, in the highest byte address.

BIT 31

BYTE 2

BYTE 3

. . .

32 BITS

BYTE 1

Figure 12. Little Endian Format

. . .

BYTE 0

. . .

BIT 0

0xFFFFFFFF

0x00000004

0x00000000

07116-009

ARM code can run directly from SRAM at full clock speed because the SRAM array is configured as a 32-bit-wide memory array. SRAM is readable/writeable in 8-/16-/32-bit segments.

Remap

The ARM exception vectors are situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020.

By default, after a reset, the Flash/EE memory is mapped to Address 0x00000000.

It is possible to remap the SRAM to Address 0x00000000. This is accomplished by setting Bit 0 of the SYSMAP0 MMR. To revert Flash/EE to Address 0x00000000, Bit 0 of SYSMAP0 is cleared.

It is sometimes desirable to remap RAM to Address 0x00000000 to optimize the interrupt latency of the ADuC7034 because code can run in full 32-bit ARM mode and at maximum core speed. It should be noted that when an exception occurs, the core defaults to ARM mode.

Rev. B | Page 22 of 136

ADuC7034

Remap Operation

When a reset occurs on the ADuC7034, execution starts automatically in the factory-programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7034 is in normal mode, it executes the power-on configuration routine of the kernel and then jumps to the reset vector, Address 0x00000000, to execute the user’s reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE.

The remap command must be executed from the absolute Flash/EE address, not from the mirrored, remapped segment of memory, which may be replaced by SRAM. If a remap operation is executed while operating code from the mirrored location, prefetch/data aborts may occur or the user may observe abnormal program operation.

Any kind of reset remaps the Flash/EE memory to the bottom of the memory array.

SYSMAP0 Register

Name: SYSMAP0

Address: 0xFFFF0220

Default Value: Updated by the kernel

Access: Read/write access

Function: This 8-bit register allows user code to remap

either RAM or Flash/EE space into the bottom of the ARM memory space, starting at Address 0x00000000.

Table 10. SYSMAP0 MMR Bit Designations

Bit Description

7 to 1

0 Remap bit.

Reserved. These bits are reserved and should be written as 0 by user code.

Set by the user to remap the SRAM to Address 0x00000000.

Cleared automatically after a reset to remap the Flash/EE memory to Address 0x00000000.

Rev. B | Page 23 of 136

ADuC7034

RESET

There are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written to by user code to initiate a software reset event. The bits in this register can be cleared to 0 by writing to the RSTCLR MMR. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset events are tabulated in Ta ble 1 2.

RSTSTA Register

Name: RSTSTA

Address: 0xFFFF0230

Default Value: Depends on type of reset

Access: Read/write access

Function: This 8-bit register indicates the source of the

last reset event and can be written to by user code to initiate a software reset.

RSTCLR Register

Name: RSTCLR

Address: 0xFFFF0234

Access: Write only

Function: This 8-bit write only register clears the

corresponding bit in RSTSTA.

Table 11. RSTSTA/RSTCLR MMR Bit Designations

Bit Description

7 to 4

Not used. These bits are not used and always

read as 0. 3 External reset. Set automatically to 1 when an external reset occurs. Cleared by setting the corresponding bit in RSTCLR. 2 Software reset. Set to 1 by user code to generate a software reset. Cleared by setting the corresponding bit in RSTCLR.1 1 Watchdog timeout.

Set automatically to 1 when a watchdog timeout

occurs. Cleared by setting the corresponding bit in RSTCLR. 0 Power-on reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.

If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset.

Table 12. Device Reset Implications

Impact

Reset

Reset External Pins to Default State

Execute Kernel

Reset All External MMRs (Excluding RSTSTA)

Reset All HV Indirect Registers

Reset Peripherals

Reset Watc hdog Timer

Valid RAM1

RSTSTA Status (After a Reset Event)

POR Ye s Ye s Yes Yes Ye s Yes Yes/No2 RSTSTA[0] = 1 Watchdog Yes Yes Yes Yes Yes No Yes RSTSTA[1] = 1 Software Yes Yes Yes Yes Yes No Yes RSTSTA[2] = 1 External Pin Yes Yes Yes Yes Yes No Yes RSTSTA[3] = 1

RAM is not valid in the case of a reset following a LIN download.

The impact on RAM is dependent on the HVMON[3] contents if LVF is enabled. When LVF is enabled using HVCFG0[2], RAM has not been corrupted by the POR reset

mechanism if the LVF status bit, HVMON[3], is 1. See the Low Voltage Flag (LVF) section for more information.

Rev. B | Page 24 of 136

ADuC7034

FLASH/EE MEMORY

The ADuC7034 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space.

Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, with the erasure being performed in page blocks. Therefore, Flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated within the ADuC7034, Flash/EE memory technology allows the user to update program code space in-circuit without the need to replace one-time programmable (OTP) devices at remote operating nodes.

The Flash/EE memory is physically located at Address 0x80000. Upon a hard reset, the Flash/EE memory maps to Address 0x00000000. The factory-set default contents of all Flash/EE memory locations is 0xFF. Flash/EE can be read in 8-/16-/32-bit segments and written in segments of 16 bits. The Flash/EE is rated for 10,000 endurance cycles. This rating is based on the number of times that each byte is cycled, that is, erased and programmed. Implementing a redundancy scheme in the software ensures greater than 10,000 endurance cycles.

The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data.

PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT

The Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port.

Serial Downloading (In-Circuit Programming)

The ADuC7034 facilitates code download via the LIN pin.

JTAG Access

The ADuC7034 features an on-chip JTAG debug port to facilitate code downloading and debugging.

ADuC7034 Flash/EE Memory

The total 32 kB of Flash/EE is organized as 15,000 × 16 bits. Of this total, 30 kB are user space and 2 kB are reserved for boot loader/kernel space.

FLASH/EE CONTROL INTERFACE

Access to and control of the Flash/EE memory on the ADuC7034 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as a single block of 32 kB.

It should be noted that the MCU core is halted until the command completes. User software must ensure that the Flash/EE controller completes any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle is completed, the Flash/EE page may become corrupt. User code, LIN, and JTAG programming use the Flash/EE control interface, consisting of the following MMRs:

The entire Flash/EE is available to the user as code and nonvolatile data memory. There is no distinction between data space and program space during ARM code processing. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. When operating at speeds of less than 20.48 MHz, the Flash/EE memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit ARM operation code) within a single core clock period. Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is recommended to use ARM mode. For 20.48 MHz operation (that is, CD = 0), it is recommended to operate in Thumb mode.

The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to erase a page, regardless of CD. Writing a 16-bit word at CD = 0, 1, 2, or 3 requires 50 s; at CD = 4 or 57, 0 s; at CD = 6, 80 s; and at CD = 7, 105 s.

It is possible to write to a single 16-bit location only twice between erasures; that is, it is possible to walk bytes, not bits. If a location is written to more than twice, the contents of the Flash/EE page may become corrupt.

Rev. B | Page 25 of 136

• FEE0STA: read only register. Reflects the status of the

Flash/EE control interface.

• FEE0MOD: sets the operating mode of the Flash/EE

control interface.

• FEE0CON: 8-bit command register. The commands are

interpreted as described in Ta ble 1 3.

• FEE0DAT: 16-bit data register.

• FEE0ADR: 16-bit address register.

• FEE0SIG: holds the 24-bit code signature as a result of the

signature command being initiated.

• FEE0HID: protection MMR. Controls read and write

protection of the Flash/EE memory code space. If previously configured via the FEE0PRO register, FEE0HID may require a software key to enable access.

• FEE0PRO: a buffer of the FEE0HID register. Stores the

FEE0HID value and therefore automatically downloads to the FEE0HID registers on subsequent reset and power-on events.

The FEE0CON Register to FEE0DAT Register sections provide detailed descriptions of the bit designations for each of the Flash/EE control MMRs.

ADuC7034

FEE0CON Register

Name: FEE0CON

Address: 0xFFFF0E08

Default Value: 0x07

Access: Read/write access

Function: This 8-bit register is written by user code to control the operating modes of the Flash/EE memory controller.

Table 13. Command Codes in FEE0CON

Code Command Description

0x001 Reserved Reserved. This command should not be written by user code. 0x011 Single read Load FEE0DAT with the 16-bit data indexed by FEE0ADR. 0x021 Single write Write FEE0DAT at the address pointed by FEE0ADR. This operation takes 50 s. 0x031 Erase write

0x041 Single verify

0x051 Single erase Erase the page indexed by FEE0ADR. 0x061 Mass erase

0x07 Idle Default command. 0x08 Reserved Reserved. This command should not be written by user code. 0x09 Reserved Reserved. This command should not be written by user code. 0x0A Reserved Reserved. This command should not be written by user code. 0x0B Signature This command results in a 24-bit, LFSR-based signature being generated and loaded into FEE0SIG.

0x0C Protect

0x0D Reserved Reserved. This command should not be written by user code. 0x0E Reserved Reserved. This command should not be written by user code. 0x0F Ping No operation, interrupt generated.

The FEE0CON register reads 0x07 immediately after the execution of this command.

Erase the page indexed by FEE0ADR and write FEE0DAT at the location pointed by FEE0ADR. This operation takes 20 ms.

Compare the contents of the location pointed by FEE0ADR to the data in FEE0DAT. The result of the comparison is returned in FEE0STA Bit 1.

Erase 30 kB of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To prevent accidental execution, a command sequence is required to execute this instruction; this is described in the Command Sequence for Executing a Mass Erase section.

If FEE0ADR is less than 0x87800, this command results in a 24-bit, LFSR-based signature of the user code space from the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.

If FEE0ADR is greater than 0x87800, the kernel and manufacturing data is signed. This operation takes 120 s.

This command can be run one time only. The value of FEE0PRO is saved and can be removed only with a mass erase (0x06) or with the software protection key.

Rev. B | Page 26 of 136

ADuC7034

Command Sequence for Executing a Mass Erase

Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation:

1. Set Bit 3 in FEE0MOD.

2. Write 0xFFC3 in FEE0ADR.

3. Write 0x3CFF in FEE0DAT.

4. Run the mass erase command (Code 0x06) in FEE0CON.

This sequence is illustrated in the following example:

FEE0MOD = 0x08; FEE0ADR = 0xFFC3; FEE0DAT = 0x3CFF; FEE0CON = 0x06; //Mass erase command while (FEE0STA & 0x04){} //Wait for command to finish

FEE0STA Register

Name: FEE0STA

Address: 0xFFFF0E00

Default Value: 0x20

Access: Read only

Function: This 8-bit, read only register can be read by

user code and reflects the current status of the Flash/EE memory controller.

Table 14. FEE0STA MMR Bit Designation

Bit Description

7 to 4 Not used. These bits are not used and always read as 0. 3 Flash/EE interrupt status bit.

2 Flash/EE controller busy. Set automatically when the Flash/EE controller is busy. Cleared automatically when the controller is not busy. 1 Command fail.

0 Command successful.

Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEE0MOD register is set.

Cleared automatically when the FEE0STA register is read by user code.

Set automatically when a command written to FEE0CON fails.

Cleared automatically when the FEE0STA register is read by user code.

Set automatically by MCU when a command is completed successfully.

Cleared automatically when the FEE0STA register is read by user code.

FEE0MOD Register

Name: FEE0MOD

Address: 0xFFFF0E04

Default Value: 0x00

Access: Read/write access

Function: This register is written by user code to

configure the mode of operation of the Flash/EE memory controller.

Table 15. FEE0MOD MMR Bit Designation

Bit Description

6 to 5

4 Flash/EE controller command complete interrupt enable.

3 Flash/EE erase/write enable.

2 Reserved. 1 Flash/EE controller abort enable.

0 Reserved.

Not used. These bits are reserved for future functionality and should be written as 0 by user code.

Flash/EE security lock bits. These bits must be written as [6:5] = 10 to complete the Flash/EE security protect sequence.

Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.

Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.

Set by user code to enable the Flash/EE erase and write access via FEE0CON.

Cleared by user code to disable the Flash/EE erase and write access via FEE0CON.

Set to 1 by user code to enable the Flash/EE controller abort functionality.

Cleared by user code to disable the Flash/EE controller abort functionality.

FEE0ADR Registers

Name: FEE0ADR

Address: 0xFFFF0E10

Default Value:

Nonzero, see the

System Identification Register section

Access: Read/write access

Function: This 16-bit register dictates the address acted

upon when a Flash/EE command is executed via FEE0CON.

Rev. B | Page 27 of 136

ADuC7034

FEE0DAT Register

Name: FEE0DAT

Address: 0xFFFF0E0C

Default Value: 0x0000

that the protection configuration is automatically loaded upon subsequent power-on or reset events. This flexibility allows the user to temporarily set and test protection settings using the FEE0HID MMR and then lock the required protection configuration (using FEE0PRO) when shipping protection systems into the field.

Access: Read/write access

Function: This 16-bit register contains the data either

read from or to be written to the Flash/EE memory.

FLASH/EE MEMORY SECURITY

There are three levels of protection: temporary protection, keyed permanent protection, and permanent protection.

Flash/EE Memory Protection Registers

Name: FEE0HID and FEE0PRO

Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C

The 30 kB of Flash/EE memory available to the user can be read and write protected using the FFE0HID register.

Default Value: 0xFFFFFFFF (for FEE0HID) and 0x00000000

The FEE0HID MMR protects the 30 kB of Flash/EE memory. Bits[0:28] of this register write protect Page 0 to Page 57. Each bit protects two pages, that is, 1 kB. Bit 29 to Bit 30 protect Page 58 and Page 59, respectively; that is, each bit write protects a single page of 512 bytes. The MSB of this register (Bit 31) protects the

Access: Read/write access

Function: These registers are written by user code to

entire Flash/EE from being read through JTAG.

The FEE0PRO register mirrors the bit definitions of the FEE0HID MMR. The FEE0PRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so

Table 16. FEE0HID MMR and FEE0PRO MMR Bit Designations

Bit Description

31 Read protection bit. Set by user code to allow read access to the 32 kB Flash/EE block via JTAG. Cleared by user code to read protect the 32 kB Flash/EE block code. 30 Write protection bit. Set by user code to allow writes to Page 59. Cleared by user code to write protect Page 59. 29 Write protection bit. Set by user code to allow writes to Page 58. Cleared by user code to write protect Page 58. 28 to 0 Write protection bits.

Set by user code to allow writes to Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages and each page consists of 512 bytes.

Cleared by user code to write protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two pages and each page consists of 512 bytes.

(for FEE0PRO)

configure the protection of the Flash/EE memory.

Rev. B | Page 28 of 136

ADuC7034

Temporary Protection

Temporary protection can be set and removed by writing directly into the FEE0HID MMR. This register is volatile and, therefore, protection is only in place for as long as the part remains powered on. The protection setting is not reloaded after a power cycle.

Keyed Permanent Protection

Keyed permanent protection can be set via FEE0PRO to lock the protection configuration. The software key used at the start of the required FEE0PRO write sequence is saved one time only and must be used for any subsequent access of the FEE0HID or FEE0PRO MMRs. A mass erase sets the software protection key back to 0xFFFF but also erases the entire user code space.

Permanent Protection

Permanent protection can be set via FEE0PRO, similar to how keyed permanent protection is set, with the only difference being that the software key used is 0xDEADDEAD. When the FEE0PRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF. This also erases the entire user code space.

Sequence to Write the Software Protection Key and Set Permanent Protection

1. Write in FEE0PRO corresponding to the pages to be

protected.

2. Write the new (user-defined) 32-bit software protection

key in FEE0ADR (Bits[31:16]) and FEE0DAT (Bits[15:0]).

3. Write 10 in FEE0MOD (Bits[6:5]) and set FEE0MOD (Bit 3).

4. Run the protect command (Code 0x0C) in FEE0CON.

To remove or modify the protection, the same sequence can be used with a modified value of FEE0PRO.

The previous sequence for writing the key and setting permanent protection is illustrated in the following example, this protects writing Page 4 and Page 5 of the Flash/EE:

Int a = FEE0STA; // Ensure FEE0STA is cleared FEE0PRO = 0xFFFFFFFB; // Protect Page 4 and Page 5 FEE0ADR = 0x66BB; // 32-bit key value (Bits[31:16]) FEE0DAT = 0xAA55; // 32-bit key value (Bits[15:0]) FEE0MOD = 0x0048 // Lock security sequence FEE0CON = 0x0C; // Write key command while (FEE0STA & 0x04){} // Wait for command to finish

FLASH/EE MEMORY RELIABILITY

The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as

• Initial page erase sequence

• Read/verify sequence

• Byte program sequence

• Second read/verify sequence

In reliability qualification, every halfword (16 bits wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Tabl e 1, the Flash/EE memory endurance qualification of the part is carried out in accordance with JEDEC Retention Lifetime Specification A117. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the part is qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature (T

= 85°C). As part of this qualification procedure, the

Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for the fully specified retention lifetime every time the Flash/EE memory is reprogrammed. In addition, note that the retention lifetime, based on an activation energy of 0.6 eV, derates with T

as shown in Figure 14.

600

450

300

RETENTIO N (Years)

150

25 40 55 70 85 100 115 130 145

Figure 14. Flash/EE Memory Data Retention

JUNCTION TEMPERATURE (°C)

07116-012

Rev. B | Page 29 of 136

ADuC7034

CODE EXECUTION TIME FROM SRAM AND FLASH/EE

This section describes SRAM and Flash/EE access times during execution for applications where execution time is critical.

Execution from SRAM

Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns, and a clock cycle is 49 ns minimum. However, when the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM. If the data is in Flash/EE, two cycles must be added: one cycle to execute the instruction and two cycles to retrieve the 32-bit data from Flash/EE. A control flow instruction, such as a branch instruction, takes one cycle to fetch and two cycles to fill the pipeline with the new instructions.

Execution from Flash/EE

In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction.

In ARM mode with CD = 0, two cycles are needed to fetch the 32-bit instructions. With CD > 0, no extra cycles are required for the fetch because the Flash/EE memory continues to be clocked at full speed. In addition, some dead time is needed before accessing data for any value of CD bits.

Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline if CD = 0.

A data processing instruction involving only the core register does not require any extra clock cycles. Data transfer instructions are more complex and are summarized in Ta b le 1 7.

Table 17. Typical Execution Cycles in ARM/Thumb Mode

Fetch

Instructions

LD 2/1 1 2 LDH 2/1 1 1 LDM/PUSH 2/1 N 2 × N STR 2/1 1 2 × 50 µs STRH 2/1 1 50 s STRM/POP 2/1 N 2 × N × 50 µs

With 1 < N ≤ 16, N is the number of data to load or store in the multiple load/store instruction.

By default, Flash/EE code execution is suspended during any Flash/EE erase or write cycle. A page (512 bytes) erase cycle takes 20 ms and a write (16 bits) word command takes 50 s. However, the Flash/EE controller allows erase/write cycles to be aborted if the ARM core receives an enabled interrupt during the current Flash/EE erase/write cycle. The ARM7 can, therefore, immediately service the interrupt and then return to repeat the Flash/EE command. The abort operation typically requires 10 clock cycles. If the abort operation is not feasible, the user can run Flash/EE programming code and the relevant interrupt routines from SRAM to allow the core to immediately service the interrupt.

Cycles

Dead Time Data Access

Rev. B | Page 30 of 136

+ 106 hidden pages

ANALOG DEVICES ADuC7034 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

TIMING SPECIFICATIONS

SPI Timing Specifications

LIN Timing Specifications

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

OVERVIEW OF THE ARM7TDMI CORE

Thumb Mode (T)

Multiplier (M)

EmbeddedICE (I)

ARM7 Exceptions

ARM Registers

Interrupt Latency

MEMORY ORGANIZATION

SRAM

Memory Format

Remap

Remap Operation

SYSMAP0 Register

RESET

RSTSTA Register

RSTCLR Register

FLASH/EE MEMORY

PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT

Serial Downloading (In-Circuit Programming)

JTAG Access

ADuC7034 Flash/EE Memory

FLASH/EE CONTROL INTERFACE

FEE0CON Register

Command Sequence for Executing a Mass Erase

FEE0STA Register

FEE0MOD Register

FEE0ADR Registers

Nonzero, see the

FEE0DAT Register

FLASH/EE MEMORY SECURITY

Flash/EE Memory Protection Registers

Temporary Protection

Keyed Permanent Protection

Permanent Protection

Sequence to Write the Software Protection Key and Set Permanent Protection

FLASH/EE MEMORY RELIABILITY

CODE EXECUTION TIME FROM SRAM AND FLASH/EE

Execution from SRAM

Execution from Flash/EE