ANALOG DEVICES ADuC7033 Service Manual
Integrated Precision Battery Sensor for
Silicon Anomaly
This anomaly list describes the known bugs, anomalies, and workarounds for the ADuC7033 integrated precision battery sensor. The
anomalies listed apply to all ADuC7033 packaged material branded as follows:
First Line ADuC7033
Second Line BSTZ-88
Analog Devices, Inc. is committed, through future silicon revisions, to continuously improving silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
Automotive System
ADuC7033
ADuC7033 FUNCTIONALITY ISSUES
Silicon
Revision
Identifier
8L/88 A60
Kernel
Revision
Identifier
Chip Marking
ADuC7033
BSTZ-88
Silicon
Status
Release Rev. B 4
Anomaly Sheet No. of Reported Anomalies
ADuC7033 PERFORMANCE ISSUES
Silicon
Revision
Identifier
8L/88 A60
Kernel
Revision
Identifier
Chip Marking
ADuC7033
BSTZ-88
Silicon
Status
Release Rev. B 2
Anomaly Sheet No. of Reported Anomalies
Rev. B
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ADuC7033 Silicon Anomaly
ANOMALIES
ADuC7033 Functionality Issues
1. LIN Communication with VDD > 31 V [er001]:
Background:
Issue:
Workaround:
Related Issues:
2. LIN Short-Circuit Recognition [er002]:
Background:
Issue:
Workaround:
Related Issues:
3. Power-On Reset [er003]:
Background:
Issue:
Workaround:
The ADuC7033 is specified for operation up to 40 V.
If the LIN communication occurs with VDD > 31 V, the ADuC7033 resets.
Pending.
None.
The ADuC7033 features LIN short-circuit protection. In the event of a short circuit on the LIN bus, an interrupt is
generated. HVCFG1[2] allows users to enable/disable this interrupt. It is enabled by default.
If the LIN is shorted to VDD with a resistance lower than 120 Ω, LIN can oscillate over temperature and supply and a
short may not be detected.
Pending.
None.
The ADuC7033 integrates a power-on reset (POR) circuit holding the ASIC in reset for 20 ms typically after VDD reaches
3 V typically.
Under particular conditions, the POR does not release the reset signal, that is, the ASIC remains in reset until a power
cycle occurs. This POR issue only occurs under three specific and coincident power-on conditions:
• Fast ramp on VDD, nominally faster than 100 s from V
• Initial value of VDD (V
) ~1.2 V
init
to 12 V
init
• Voltage on REG_DVDD at time the VDD ramp is reapplied ~175 mV
A fast VDD ramp (that is, ramping from ~1.2 V to 12 V in <100 µs) is required as one of the conditions to initiate the
reported POR issue. Analog Devices recommends careful selection of external power supply decoupling components
to ensure that the VDD supply ramp rate can always be guaranteed to be >100 µs under all VBAT power-on conditions.
Specifically, in modules that already incorporate a series resistor and decoupling capacitor to ground on the VDD line
between the reverse protection diode and the VDD pin (see Figure 1), choose the series resistor/decoupling capacitor
combination to give an RC time constant of at least 100 µs, such as 10 Ω and 10 µF.
10Ω
VDD
10µF
ADuC7033
REG_DVDD
2.2µF
Related Issues:
07069-002
Figure 1.
Alternatively, in the specific case of customer modules where the VDD decoupling capacitor cannot be increased
beyond 4.7 µF, then increasing the series resistor to 20 Ω and increasing the REG_DVDD decoupling capacitor from
2.2 µF to 10 µF also slews the VDD supply power-on ramp to ~200 µs. This is also an appropriate and recommended
containment measure.
None.
Rev. B | Page 2 of 4
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