ANALOG DEVICES ADuC7032-8L Service Manual
K
Integrated Precision Battery Sensor
FEATURES
High precision analog-to-digital converters (ADCs)
Dual channel, simultaneous sampling, 16-bit Σ-Δ ADCs
Third independent ADC for temperature sensing
Programmable ADC throughput from 1 Hz to 8 kHz
On-chip 5 ppm/°C voltage reference
Current channel
Fully differential, buffered input
Programmable gain: 1 to 512
ADC input range: −200 mV to +300 mV
Digital comparators, with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery inputs
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
20.48 MHz PLL with programmable divider
PLL input source
On-chip precision oscillator
On-chip low power oscillator
External (32.768 kHz) watch crystal
JTAG port supports code download and debug
for Automotive System
ADuC7032-8L
Memory
96 kB Flash/EE memory, 6 kB SRAM
10k-cycle Flash/EE endurance, 20-year Flash/EE retention
In-circuit download via JTAG and LIN
64 × 16-bit result FIFO for current and voltage ADC
On-chip peripherals
LIN 1.3- and 2.0-compatible (slave) support via UART with
hardware synchronization
Flexible wake-up I/O pin, master/slave SPI serial I/O
9-pin GPIO port, 2× general-purpose timers
Wake-up and watchdog timers
Power supply monitor, on-chip power-on reset
Power
Operates directly from 12 V battery supply
Current consumption
Normal mode: 10 mA at 10 MHz
Low power monitor mode: 175 μA
Package and temperature range
48-lead, 7 mm × 7 mm LQFP
Fully specified for −40°C to +105°C operation
APPLICATIONS
Battery sensing/management for automotive systems
FUNCTIONAL BLOCK DIAGRAM
IIN+
IIN–
VBAT
VTEMP
GND_SW
VREF
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
PRECISION ANALOG ACQUI S ITION
PGA
RESULT
ACCUMULATOR
MUX
TEMPERATURE
SENSOR
VDD
REG_AVDD
BUF
BUF
REG_DVDD
16-BIT
Σ-∆ ADC
DIGITAL
COMPARATOR
16-BIT
Σ-∆ ADC
16-BIT
Σ-∆ ADC
PRECISION
REFERENCE
VSS
AGND
DGND
IO_VSS
Figure 1.
TDI TDO NTRST TMS
TC
ADuC7032-8L
2.6V LDO
PSM
POR
ARM7TDMI
MCU
20MHz
2× TIMERS
WDT
W/U TIMER
GPIO_0
GPIO_1
GPIO_2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
128B ADC FIFO
®
LOW POWER
ON-CHIP PLL
GPIO_3
GPIO_4
MEMORY
96kB FLASH
6kB SRAM
PRECISION
OSC (1%)
OSC
GPIO PORT
UART PORT
SPI PORT
LIN
GPIO_5
GPIO_6
RESET
XTAL1
XTAL2
WU
LIN
GPIO_7
GPIO_8
05986-001
ADuC7032-8L
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Specifications............................................................... 4
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 20
Overview of the ARM7TDMI® Core ....................................... 20
Memory Organization ............................................................... 22
Reset .............................................................................................24
Flash/EE Memory and the ADuC7032-8L ............................. 25
Flash/EE Control Interface........................................................ 25
Flash/EE Memory Security ....................................................... 28
Flash/EE Memory Reliability.................................................... 31
Code Execution Time from SRAM and Flash/EE .....................31
ADuC7032-8L Kernel................................................................ 32
Memory Mapped Registers....................................................... 34
Complete MMR Listing............................................................. 35
16-Bit, Sigma-Delta Analog-to-Digital Converters ................... 39
Current Channel ADC (I-ADC) .............................................. 39
Voltage Channel ADC (V-ADC).............................................. 40
Temperature Channel ADC (T-ADC)..................................... 40
ADC Ground Switch.................................................................. 41
ADC Noise Performance Tables............................................... 42
ADC MMR Interface .................................................................43
ADC Power Modes of Operation............................................. 54
ADC Diagnostics........................................................................ 59
Power Supply Support Circuits..................................................... 60
ADuC7032-8L System Clocks ...................................................... 61
ADuC7032-8L Low Power Clock Calibration........................ 65
Processor Reference Peripherals................................................... 67
Interrupt System......................................................................... 67
Timers .............................................................................................. 69
Synchronization of Timers Across Asynchronous Clock
Domains ...................................................................................... 70
Programming the Timers.......................................................... 71
Timer0—Lifetime Timer........................................................... 71
Timer1.......................................................................................... 73
Timer2—Wake-Up Timer......................................................... 75
Timer3—Watchdog Timer........................................................ 77
General-Purpose I/O ..................................................................... 79
High Voltage Peripheral Control Interface................................. 89
WU (Wake-Up) Pin ................................................................... 95
Handling Interrupts from the High Voltage Peripheral
Control Interface ........................................................................ 96
Low Voltage Flag (LVF)............................................................. 96
High Voltage Diagnostics .......................................................... 96
UART Serial Interface.................................................................... 97
Baud Rate Generation................................................................ 97
UART Register Definitions....................................................... 97
Serial Peripheral Interface........................................................... 101
MISO (Master In, Slave Out Data I/O Pin) ..........................101
MOSI (Master Out, Slave In Pin)........................................... 101
SCLK (Serial Clock I/O Pin)................................................... 101
Chip Select (SS) Input Pin....................................................... 101
SPI Registers Definitions......................................................... 101
LIN (Local Interconnect Network) Interface............................ 104
LIN MMR Description............................................................ 104
LIN Hardware Interface .......................................................... 108
ADuC7032-8L On-Chip Diagnostics........................................ 112
ADC Diagnostics...................................................................... 112
High Voltage I/O Diagnostics................................................. 112
Part Identification......................................................................... 113
ADuC7032-8L Example Schematic ........................................... 116
Outline Dimensions..................................................................... 117
Ordering Guide ........................................................................ 117
Rev. A | Page 2 of 120
ADuC7032-8L
REVISION HISTORY
11/10—Rev. 0 to Rev. A
Changed ±4.68 mV to ±9.375 mV, Table 32................................42
Changes to Timers Section ............................................................69
Added Synchronization of Timers Across Asynchronous Clock
Domains Section .............................................................................70
Added Figure 32 and Figure 33; Renumbered Sequentially......70
Added Programming the Timers Section, Halting Timer2
Section, Starting Timer2 Section, and
Example Code Section....................................................................71
Updated Outline Dimensions......................................................117
Changes to Ordering Guide.........................................................117
8/07—Revision 0: Initial Version
Rev. A | Page 3 of 120
ADuC7032-8L
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference; f
precision oscillator. All specifications T
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPECIFICATIONS
Conversion Rate1
Chop off, ADC normal operating mode 4 8000 Hz
Chop on, ADC normal operating mode 4 2600 Hz
Chop on, ADC low power mode 1 650 Hz
Current Channel
No Missing Codes1 Valid for all ADC update rates and ADC modes 16 Bits
Integral Nonlinearity
Offset Error
Offset Error
Offset Error
Offset Error
Offset Error
1, 2 , 3, 4, 5
2, 3, 4, 6
1, 3, 6
1, 3
1, 3
Offset Error Drift6 Chop off, valid for ADC gains of 4 to 64, normal mode 0.03 LSB/°C
Offset Error Drift6 Chop off, valid for ADC gains of 128 to 512, normal mode 30 nV/°C
Offset Error Drift6 Chop on 10 nV/°C
Total Gain Error
Total Gain Error
Total Gain Error
Gain Drift 3 ppm/°C
PGA Gain Mismatch Error ±0.1 %
Output Noise
10 Hz update rate, gain = 512, chop enabled 100 150 nV rms
1 kHz update rate, gain = 512 0.6 0.9 μV rms
1 kHz update rate, gain = 32 0.8 1.2 μV rms
1 kHz update rate, gain = 4 2.0 2.8 μV rms
8 kHz update rate, gain = 32 2.5 3.5 μV rms
8 kHz update rate, gain = 4 14 21 μV rms
ADC low power mode, f
ADC low power mode, f
ADC low power plus mode, f
Voltage Channel12
No Missing Codes1 Valid at all ADC update rates 16 Bits
Integral Nonlinearity
Offset Error
Offset Error
1, 3, 5
1, 3
Offset Error Drift Chop off 0.03 LSB/°C
Total Gain Error
Total Gain Error
Gain Drift
Output Noise
10 Hz update rate 60 90 μV rms
1 kHz update rate 180 270 μV rms
8 kHz update rate 1600 2400 μV rms
1, 2
±10 ±60 ppm of FSR
Chop off, 1 LSB = (36.6/gain) μV, after initial offset calibration −10 ±3 +10 LSB
Chop off, 1 LSB = (36.6/gain) μV −15 +35 LSB
Chop on −2 ±0.5 +2 μV
Chop on, low power mode or low power plus mode, MCU powered
Chop on, normal mode, CD = 1 0 −1.5 −5 μV
1, 3, 7 , 8, 9
Normal mode −0.5 ±0.1 +0.5 %
1, 3, 7, 9, 10
1, 3, 7, 9
Low power plus mode, using precision VREF −1 ±0.2 +1 %
1, 11
4 Hz update rate, gain = 512, chop enabled 60 90 nV rms
1
Chop off, 1 LSB = 439.5 μV −10 ±1 +10 LSB
Chop on 0.3 1 LSB
1, 3, 7, 13, 14
1, 3, 7, 13, 14
1, 15
4 Hz update rate 60 90 μV rms
= 10.24 MHz, driven from external 32.768 kHz watch crystal or on-chip
CORE
= −40°C to +105°C, unless otherwise noted.
A
down 0 −200 −650 nV
Low power mode −4 ±0.2 +4 %
= 10 Hz, gain = 128 1.25 1.9 μV rms
ADC
= 1 Hz, gain = 128 0.35 0.5 μV rms
ADC
= 1 Hz, gain = 512 0.1 0.15 μV rms
ADC
±10 ±60 ppm of FSR
Includes resistor mismatch −0.25 ±0.06 +0.25 %
Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 %
Includes resistor mismatch drift 3 ppm/°C
Rev. A | Page 4 of 120
ADuC7032-8L
Parameter Test Conditions/Comments Min Typ Max Unit
Temperature Channel
No Missing Codes1 Valid at all ADC update rates 16 Bits
Integral Nonlinearity
Offset Error
Offset Error
1, 3, 5, 16, 17, 18
1, 3
Offset Error Drift
Total Gain Error
Gain Drift
Output Noise
ADC SPECIFICATIONS,
ANALOG INPUT
Current Channel
Absolute Input Voltage
Range
Input Voltage Range
Gain = 221 ±600 mV
Gain = 421 ±300 mV
Gain = 8 ±150 mV
Gain = 16 ±75 mV
Gain = 32 ±37.5 mV
Gain = 64 ±18.75 mV
Gain = 128 ±9.375 mV
Gain = 256 ±4.68 mV
Gain = 512 ±2.3 mV
Input Leakage Current
Input Offset Current
Voltage Channel
Absolute Input Voltage
Range
Input Voltage Range 0 to 28.8 V
VBAT Input Current VBAT = 18 V 3 5.5 8 μA
Temperature Channel
Absolute Input Voltage
Range
Input Voltage Range 0 to VREF V
VTEMP Input Current1 2.5 100 nA
VOLTAGE REFERENCE
ADC Precision Reference
Internal VREF 1.2 V
Power-Up Time1 0.5 ms
Initial Accuracy1 Measured at TA = 35°C −0.15 +0.15 %
Internal VREF Temperature
Coefficient
Long-Term Stability24 100 ppm/
External Reference Input
Range
25
VREF Divide-by-2 Initial Error1 0.1 0.3 %
ADC Low Power Reference
Internal VREF
Initial Accuracy
Initial Accuracy10 Using ADCREF, measured at TA = 35°C 0.1 %
Temperature Coefficient
RESISTIVE ATTENUATOR
Divider Ratio 24
Resistor Mismatch Drift 3 ppm/°C
ADC GROUND SWITCH
Resistance Direct path to ground 10 Ω
20 kΩ resistor selected 10 20 30 kΩ
Input Current 6 mA
1
±10 ±60 ppm of FSR
Chop off, 1 LSB = 19.84 μV −10 ±3 +10 LSB
Chop on −5 1 +5 LSB
1, 3, 14, 17, 18
0.03 LSB/°C
−0.25 ±0.06 +0.25 %
3 ppm/°C
1
1 kHz update rate 7.5 11.25 μV rms
Internal VREF = 1.2 V
Applies to both IIN+ and IIN− −200 +300 mV
19, 20
1, 22
Gain = 121 ±1.2 V
1
−3 +3 nA
0.5 1.5 nA
4 18 V
100 1300 mV
1, 23
−20 ±5 +20 ppm/°C
1000 hr
0.1 1.3 V
1.2 V
Measured at TA = 35°C −5 +5 %
1, 23
−300 +300 ppm/°C
Rev. A | Page 5 of 120
ADuC7032-8L
Parameter Test Conditions/Comments Min Typ Max Unit
TEMPERATURE SENSOR
Accuracy MCU in power-down or standby mode;
POWER-ON RESET (POR)
POR Trip Level Refers to voltage at VDD pin 2.85 3.0 3.15 V
POR Hysteresis 300 mV
Reset Timeout from POR 20 ms
LOW VOLTAGE FLAG (LVF)
LVF Level Refers to voltage at VDD pin 1.9 2.1 2.3 V
POWER SUPPLY MONITOR (PSM)
PSM Trip Level Refers to voltage at VDD pin 6.0 V
WATCHDOG TIMER (WDT)
Timeout Period
Timeout Step Size 7.8 ms
FLASH/EE MEMORY
Endurance27 10,000 Cycles
Data Retention28 20 Years
DIGITAL INPUTS All digital inputs except NTRST
Input Leakage Current Input (high) = REG_DVDD −10 ±1 +10 μA
Input Pull-Up Current
Input Capacitance
Input Leakage Current NTRST only: input (low) = 0 V −10 ±1 +10 μA
Input Pull-Down Current NTRST only: input (high) = REG_DVDD 30 55 100 μA
LOGIC INPUTS
1
Input Low Voltage (VINL) 0.4 V
Input High Voltage (VINH) 2.0 V
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
Input Low Voltage (VINL) 0.8 V
Input High Voltage (VINH) 1.7 V
XTAL1 Capacitance 12 pF
XTAL2 Capacitance 12 pF
ON-CHIP OSCILLATORS
Low Power Oscillator 131.072 kHz
Accuracy29 Includes drift data from 1000 hr life test −3 +3 %
Precision Oscillator 131.072 kHz
Accuracy Includes drift data from 1000 hr life test −1 +1 %
MCU CLOCK RATE Eight programmable core clock selections within this range (binary
MCU START-UP TIME
At Power-On Includes kernel power-on execution time 25 ms
After Reset Event Includes kernel power-on execution time 5 ms
From MCU Power-Down
Oscillator Running
Wake-Up from Interrupt 2 ms
Wake-Up from LIN 2 ms
Crystal Powered Down
Wake-Up from Interrupt 500 ms
Internal PLL Lock Time 1 ms
1, 26
−4 +4 °C
temperature range = −40°C to −30°C
MCU in power-down or standby mode;
−3 +3 °C
temperature range = −30°C to −16°C
MCU in power-down or standby mode;
−2 +2 °C
temperature range = −16°C to +40°C
MCU in power-down or standby mode;
−4 +4 °C
temperature range = +40°C to +70°C
MCU in power-down or standby mode;
−8 +8 °C
temperature range = +70°C to +85°C
MCU in power-down or standby mode;
−12 +12 °C
temperature range = +85°C to +105°C
1
1
32.768 kHz clock, 256 prescale 0.008 512 sec
Input (low) = 0 V −80 −20 −10 μA
10 pF
All logic inputs
1
0.160 10.24 20.48 MHz
divisions 1, 2, 4, 8. . .64, 128)
Rev. A | Page 6 of 120
ADuC7032-8L
Parameter Test Conditions/Comments Min Typ Max Unit
LIN I/O GENERAL
Baud Rate 1000 20,000 Bits/sec
VDD Supply voltage range at which the LIN interface is functional 7 18 V
Input Capacitance 5.5 pF
LIN Comparator Response
1
Time
I
LIN DOM MAX
I
LIN_PAS_REC
I
LIN_PAS_DOM1
I
LIN_NO_GND
V
V
V
V
V
Driver off; 7.0 V < V
30
LIN_DOM1
LIN_REC1
1
LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V
LIN_CNT
1
LIN receiver hysteresis voltage 0.175 VDD V
HYS
LIN_DOM_DRV_LOSUP1
RL 500 Ω 1.2 V
RL 1000 Ω 0.6 V
V
LIN_DOM_DRV_HISUP
1
LIN dominant output voltage; VDD = 18 V
RL 500 Ω 2 V
RL 1000 Ω 0.8 V
V
LIN_RECESSIVE
LIN recessive output voltage 0.8 VDD V
VBAT Shift30 0 0.1 VDD V
GND Shift
R
V
30
Slave termination resistance 20 29 47 kΩ
SLAVE
30
SERIAL DIODE
Voltage drop at the serial diode, D
Transmit Propagation Delay1 V
Symmetry of Transmit
Propagation Delay1 V
Receive Propagation Delay1
Symmetry of Receive
Propagation Delay1 V
LIN v.1.3 SPECIFICATION
1
dV
dt
1
dV
dt
t
SYM1
Symmetry of rising and falling edge, VBAT = 7 V −4 +4 μs
LIN 2.0 SPECIFICATION
D1 Duty Cycle 1 0.396
TH
TH
V
D1 = t
D2 Duty Cycle 2
TH
TH
V
D2 = t
Using 22 Ω resistor 38 90 μs
Current limit for driver when LIN bus is in dominant state;
40 200 mA
VBAT = VBAT(MAX)
< 18 V; VDD = V
BUS
Input leakage V
= 0 V −1 mA
LIN
Control unit disconnected from ground,
GND = VDD; 0 V < V
< 18 V; VBAT = 12 V
LIN
− 0.7 V −20 +20 μA
LIN
−1 +1 mA
LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V
LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V
LIN dominant output voltage; VDD = 7.0 V
0 0.1 VDD V
Ser_Int
= 7 V 4 μs
DDMIN
Bus load conditions (C
BUS
||R
BUS
):
0.4 0.7 1 V
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
= 7 V −2 +2 μs
DDMIN
V
= 7 V
DDMIN
= 7 V −2 +2 μs
DDMIN
||R
Bus load conditions (C
BUS
BUS
):
6 μs
1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Dominant and recessive edges, VBAT = 18 V 1 2 3 V/μs
Slew rate
Dominant and recessive edges, VBAT = 7 V 0.5 3 V/μs
Symmetry of rising and falling edge, VBAT = 18 V −5 +5 μs
||R
Bus load conditions ( C
BUS
BUS
):
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
= 0.744 × VBAT,
REC(MAX)
= 0.581 × VBAT,
DOM(MAX)
= 7.0 V…18 V; t
SUP
BUS_REC(MIN)
REC(MIN)
DOM(MIN)
= 7.0 V…18 V; t
SUP
BUS_REC(MAX)
/(2 × t
= 0.284 × VBAT,
= 0.422 × VBAT,
/(2 × t
= 50 μs,
BIT
)
BIT
= 50 μs,
BIT
) 0.581
BIT
Rev. A | Page 7 of 120
ADuC7032-8L
Parameter Test Conditions/Comments Min Typ Max Unit
PACKAGE THERMAL
SPECIFICATIONS
Thermal Shutdown31 140 150 160 °C
Thermal Impedance (θJA)32
Top die 50 °C/W
POWER REQUIREMENTS
Power Supply Voltages
VDD (Battery Supply) 3.5 18 V
REG_DVDD, REG_AVDD33 2.5 2.6 2.7 V
Power Consumption
IDD (MCU Normal Mode)34 MCU clock rate = 10.24 MHz, ADC off 10 20 mA
MCU clock rate = 20.48 MHz, ADC off 20 30 mA
IDD (MCU Powered Down)1 ADC low power mode, measured over an ambient temperature range
ADC low power mode, measured over an ambient temperature range
Average current, measured with wake-up and watchdog timer
Average current, measured with wake-up and watchdog timer clocked
IDD (Current ADC) 1.7 mA
IDD (Voltage/Temperature
ADC)
IDD (Precision Oscillator) 400 μA
1
Not guaranteed by production test, but by design and/or characterization data at production release.
2
Valid for current ADC gain setting of PGA = 4 to 64.
3
These numbers include temperature drift.
4
Tested at gain range = 4; self-offset calibration removes this error.
5
Measured with an internal short after an initial offset calibration.
6
Measured with an internal short.
7
Includes internal reference temperature drift.
8
Factory calibrated at gain = 1.
9
System calibration at specific gain range removes the error at this gain range at that temperature.
10
Valid when used in conjunction with the ADCREF (the low power mode reference error) MMR.
11
Typical noise in low power modes is measured with chop enabled.
12
Voltage channel specifications include resistive attenuator input stage.
13
Includes an initial system calibration.
14
System calibration removes this error at that temperature.
15
RMS noise is referred to voltage attenuator input. For example, at f
yields these input referred noise figures.
16
ADC self-offset calibration removes this error.
17
Valid after an initial self-calibration.
18
Factory calibrated for the internal temperature sensor during final production test.
19
In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
20
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
21
Limited by minimum/maximum absolute input voltage range.
22
Valid for a differential input less than 10 mV.
23
Measured using box method.
24
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
25
References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2.
26
Die temperature.
27
Endurance is qualified to 10,000 cycles, as per JEDEC Std. 22 Method A117, and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
28
Retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
29
Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
30
These numbers are not production tested but are supported by LIN compliance testing.
31
The MCU core is not shut down, but an interrupt is generated, if enabled.
32
Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
33
Internal regulated supply available at REG_DVDD (I
34
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
48-lead LQFP, stacked die
Bottom die 25 °C/W
300 400 μA
of −10°C to +40°C (continuous ADC c onversion)
300 500 μA
of −40°C to +85°C (continuous ADC c onversion)
ADC low power plus mode, measured over an ambient temperature
520 700 μA
range of −10°C to +40°C (continuous ADC conversion)
120 300 μA
clocked from low power oscillator (−40°C to +85°C)
120 175 μA
from low power oscillator over an ambient temperature range of −10°C
to +40°C
Per ADC 0.5 mA
= 1 kHz, typical rms noise at the ADC input is 7.5 μV, which, when scaled by the attenuator (24),
ADC
= 5 mA) and REG_AVDD (I
SOURCE
SOURCE
= 1 mA).
Rev. A | Page 8 of 120
ADuC7032-8L
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing (PHASE Mode = 1)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLK edge2 (2 × t
DAV
t
Data input setup time before SCLK edge 0 ns
DSU
t
Data input hold time after SCLK edge2 3 × t
DHD
ns
UCLK
tDF Data output fall time 3.5 ns
tDR Data output rise time 3.5 ns
tSR SCLK rise time 3.5 ns
tSF SCLK fall time 3.5 ns
1
t
depends on the clock divider or CD bits in PLLCON MMR. t
HCLK
2
t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
UCLK
HCLK
= t
UCLK
/2CD.
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
DAV
t
SL
t
DF
t
DR
t
SR
ns
HCLK
ns
HCLK
) + (2 × t
UCLK
t
SF
) ns
HCLK
MOSI
MISO
MSB IN BITS[6:1] LSB IN
t
DSUtDHD
Figure 2. SPI Master Mode Timing (PHASE Mode = 1)
LSBBITS[6:1]MSB
05986-002
Rev. A | Page 9 of 120
ADuC7032-8L
Table 3. SPI Master Mode Timing (PHASE Mode = 0)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLK edge2 (2 × t
DAV
t
Data output setup time before SCLK edge ½ tSL ns
DOSU
t
Data input setup time before SCLK edge 0 ns
DSU
t
Data input hold time after SCLK edge2 3 × t
DHD
ns
UCLK
tDF Data output fall time 3.5 ns
tDR Data output rise time 3.5 ns
tSR SCLK rise time 3.5 ns
tSF SCLK fall time 3.5 ns
1
t
depends on the clock divider or CD bits in PLLCON MMR. t
HCLK
2
t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
UCLK
HCLK
= t
UCLK
/2CD.
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
DOSU
t
SH
t
t
SL
t
DAV
DF
t
DR
t
SR
ns
HCLK
ns
HCLK
) + (2 × t
UCLK
t
SF
) ns
HCLK
MOSI
MISO
MSB IN BITS[6:1] LSB IN
t
DSUtDHD
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
LSBBITS[6:1]MSB
5986-003
Rev. A | Page 10 of 120
ADuC7032-8L
Table 4. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter Description Min Typ Max Unit
tSS
to SCLK edge
SS
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLK edge2 (3 × t
DAV
t
Data input setup time before SCLK edge 0 ns
DSU
t
Data input hold time after SCLK edge2 4 × t
DHD
tDF Data output fall time 3.5 ns
tDR Data output rise time 3.5 ns
tSR SCLK rise time 3.5 ns
tSF SCLK fall time 3.5 ns
t
SFS
1
t
depends on the clock divider or CD bits in PLLCON MMR. t
HCLK
2
t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
UCLK
high after SCLK edge
SS
HCLK
= t
UCLK
SS
½ t
½ t
/2CD.
ns
SL
ns
HCLK
ns
HCLK
) + (2 × t
UCLK
ns
UCLK
ns
SL
) ns
HCLK
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MISO
MOSI
t
CS
t
SH
t
DAV
t
DSUtDHD
t
SL
t
DF
MSB IN BITS[6:1] LSB IN
t
DR
t
SR
t
SFS
t
SF
LSBBITS[6:1]MSB
05986-004
Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. A | Page 11 of 120
ADuC7032-8L
Table 5. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter Description Min Typ Max Unit
tSS
to SCLK edge
SS
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLK edge2 (3 × t
DAV
t
Data input setup time before SCLK edge 0 ns
DSU
t
Data input hold time after SCLK edge2 4 × t
DHD
tDF Data output fall time 3.5 ns
tDR Data output rise time 3.5 ns
tSR SCLK rise time 3.5 ns
tSF SCLK fall time 3.5 ns
t
DOCS
t
SFS
1
t
depends on the clock divider or CD bits in PLLCON MMR. t
HCLK
2
t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
UCLK
Data output valid after SS
high after SCLK edge
SS
edge2
HCLK
= t
UCLK
SS
t
t
DOCS
SS
t
SH
t
DAV
t
DF
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
½ t
ns
UCLK
ns
SL
(3 × t
t
/2CD.
SL
t
DR
½ t
ns
SL
t
SR
ns
HCLK
ns
HCLK
) + (2 × t
UCLK
) + (2 × t
UCLK
t
SFS
t
SF
) ns
HCLK
) ns
HCLK
MISO
MOSI
MSB IN BITS[6:1] LSB IN
t
DSUtDHD
Figure 5. SPI Slave Mode Timing (PHASE Mode = 0)
LSBBITS[6:1]MSB
05986-005
Rev. A | Page 12 of 120
ADuC7032-8L
LIN Timing Specifications
TxD (INPUT TO TRANSCEIVE R FRO M CO NT RO L L ER)
RECEIVING
THRESHOLD
t
TRANS_PDF
BUS SIGNAL
t
RxD (OUTPUT OF TRANSCEI VE R TO CONTROLLER)
V
SUP
V
BUSREC
60%
40%
V
BUSDOM
GND
(MEASURED FROM POINT WHEN THE
REC_PDF
SWITCHING THRESHOLD IS SURPASSED)
t
FALL_60%
t
SLOPE_FALL
t
FALL_40%
Figure 6. LIN v.1.3 Timing Specifications
V
SWING
t
RISE_40%
t
t
SLOPE_RISE
t
RISE_60%
TRANS_PDR
t
REC_PDR
TIME
05986-006
Rev. A | Page 13 of 120
ADuC7032-8L
TRANSMIT
INPUT TO
TRANSMITTING
NODE
V
(TRANSCEIVER SUP PL Y
OF T R AN SMITTING NODE)
SUP
RxD
(OUTPUT OF RECEIV ING NODE 1)
RECESSIVE
DOMINANT
TH
REC (MAX)
TH
DOM (MAX)
TH
REC (MIN)
TH
DOM (MIN)
t
BIT
t
LIN_DO M (MAX)
t
LIN_DO M (MIN)
t
RX_PDF
t
BIT
t
LIN_REC ( MIN)
t
LIN_REC (MAX)
t
RX_PDR
t
BIT
THRESHOLDS OF
RECEIVING NODE 1
THRESHOLDS OF
RECEIVING NODE 2
LIN
BUS
(OUTPUT OF RECEIV ING NODE 2)
RxD
t
RX_PDR
Figure 7. LIN 2.0 Timing Specifications
t
RX_PDF
05986-007
Rev. A | Page 14 of 120
ADuC7032-8L
ABSOLUTE MAXIMUM RATINGS
= −40°C to +105°C, unless otherwise noted.
T
A
Table 6.
Parameter Rating
AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V
VBAT to AGND −22 V to +40 V
VDD to VSS −0.3 V to +33 V
VDD to VSS for 1 sec −0.3 V to +40 V
LIN to IO_VSS −16 V to +40 V
WU to IO_VSS −3 V to +33 V
WU Continuous Current 50 mA
High Voltage I/O Pins Short-Circuit
Current
Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V
VREF to AGND −0.3 V to REG_AVDD + 0.3 V
ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V
Storage Temperature 130°C
Junction Temperature (Transient) 150°C
Junction Temperature (Continuous) 130°C
Lead Temperature
Soldering Reflow (15 sec) 260°C
100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 15 of 120
ADuC7032-8L
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LIN
IO_VSS
RESERVEDNCVSSNCVDDWUNCNCNC
4847464544434241403938
XTAL2
37
RESET
GPIO_5/IRQ1/RxD
GPIO_6/TxD
GPIO_7/IRQ4
GPIO_8/IRQ5
TCK
TDI
DGND
NC
TDO
NTRST
TMS
1
2
3
4
5
6
7
8
9
10
11
12
NC = NO CONNECT
PIN 1
IDENTIFIER
1314151617181920212223
VREF
VBAT
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1
RESET
I
Reset Input Pin, Active Low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When
not in use, this pin remains unconnected. For added security and robustness, it is recommended
that this pin be strapped, via a resistor, to REG_DVDD.
2 GPIO_5/IRQ1/RxD I/O
General-Purpose Digital Input/Output 5, External Interrupt Request 1, or Receive Data. By default
and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up
resistor and, when not in use, it can be left unconnected. This multifunction pin can be configured
in one of three states, namely
General-Purpose Digital I/O 5.
External Interrupt Request 1, active high.
Receive data for UART serial port.
This pin can also be used as a clock input to Timer1.
3 GPIO_6/TxD I/O
General-Purpose Digital Input/Output 6 or Transmit Data. By default and after power-on reset, this
pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use,
it can be left unconnected. This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 6.
Transmit data for UART serial port.
4 GPIO_7/IRQ4 I/O
General-Purpose Digital Input/Output 7 or External Interrupt Request 4. By default and after
power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and,
when not in use, it can be left unconnected. This multifunction pin can be configured in one of
two states, namely
General-Purpose Digital I/O 7.
External Interrupt Request 4, active high.
5 GPIO_8/IRQ5 I/O
General-Purpose Digital Input/Output 8 or External Interrupt Request 5. By default and after
power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor
and, when not in use, it can be left unconnected. This multifunction pin can be configured in
one of two states, namely
General-Purpose Digital I/O 8.
External Interrupt Request 5, active high.
This pin can also be used as a clock input to Timer1.
ADuC7032-8L
TOP VIEW
(Not to S cale)
NC
NC
GND_SW
IIN–
IIN+
VTEMP
AGND
Figure 8. Pin Configuration
AGND
NC
24
REG_AVDD
36
XTAL1
35
DGND
34
DGND
33
REG_DVDD
32
NC
31
GPIO_4/ECLK
30
GPIO_3/MOSI
29
GPIO_2/MISO
28
GPIO_1/SCLK
27
GPIO_0/IRQ0/SS
26
NC
25
NC
05986-008
Rev. A | Page 16 of 120
ADuC7032-8L
Pin No. Mnemonic Type1 Description
6 TCK I
7 TDI I
8, 34, 35 DGND S Ground Reference for On-Chip Digital Circuits.
9, 16, 17,
23, 25, 26,
32, 38, 39,
40, 43, 45
10 TDO O
11 NTRST I
12 TMS I
13 VBAT I Battery Voltage Input to Resistor Divider.
14 VREF I
15 GND_SW S
18 VTEMP I External Pin for NTC/PTC Temperature Measurement.
19 IIN+ I Positive Differential Input for Current Channel.
20 IIN− I Negative Differential Input for Current Channel.
21, 22 AGND S Ground Reference for On-Chip Precision Analog Circuits.
24 REG_AVDD S Nominal 2.6 V Output from On-Chip Regulator.
27
28 GPIO_1/SCLK I/O
29 GPIO_2/MIS0 I/O
30 GPIO_3/MOSI I/O
31 GPIO_4/ECLK I/O
33 REG_DVDD S Nominal 2.6 V Output from the On-Chip Regulator.
NC
I/O
GPIO_0/IRQ0/SS
JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part.
It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin
remains unconnected.
JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the
part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin
remains unconnected.
No Connect. This pin is not connected internally but is reserved for possible future use. Therefore,
this pin should not be connected externally. NC pins can be grounded, if required.
JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on
the part. It is an output pin only. At power-on, this output is disabled and pulled high via an
internal, weak, pull-up resistor. When not in use, this pin remains unconnected.
JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part.
It is an input pin only, and it has an internal, weak, pull-down resistor. When not in use, this pin
remains unconnected. It is also monitored by the on-chip kernel to enable LIN boot load mode.
JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports
on the part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use,
this pin remains unconnected.
External Reference Input Terminal. If this input is not used, connect it directly to the AGND
system ground.
Switch to Internal Analog Ground Reference. Negative input for external temperature channel
and external reference. If this input is not used, connect it directly to the AGND system ground.
General-Purpose Digital I/O 0, External Interrupt Request 0, or SPI Interface. By default and after
power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor
and, when not in use, it remains unconnected. This multifunction pin can be configured in one
of three states, namely
General-Purpose Digital I/O 0.
External Interrupt Request 0, active high.
SPI interface, slave select input.
General-Purpose Digital I/O 1 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 1.
SPI interface, serial clock input.
General-Purpose Digital I/O 2 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected.This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 2.
SPI interface, master input/slave output pin.
General-Purpose Digital I/O 3 or SPI Interface. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 3.
SPI interface, master output/slave input pin.
General-Purpose Digital I/O 4 or Clock Output. By default and after power-on reset, this pin is
configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it
remains unconnected. This programmable digital I/O pin can also be configured to output
a 2.56 MHz clock.
Rev. A | Page 17 of 120
ADuC7032-8L
Pin No. Mnemonic Type1 Description
36 XTAL1 O Crystal Oscillator Output. If an external crystal is not in use, this pin remains unconnected.
37 XTAL2 I
41 WU O High Voltage Wake-Up Transmit Pin. When not in use, this pin remains unconnected.
42 VDD S Battery Power Supply to On-Chip Regulator.
44 VSS S Ground Reference for the Internal Voltage Regulators.
46 RESERVED
47 IO_VSS S Ground Reference for High Voltage Input/Output Pins.
48 LIN I/O LIN Serial Interface Input/Output Pin.
1
I = input, O = output, S = supply.
Crystal Oscillator Input. If an external crystal is not in use, connect this pin to the DGND system
ground.
Reserved for High Voltage Output Only Functionality. This pin should be connected externally to
the IO_VSS ground reference.
Rev. A | Page 18 of 120
ADuC7032-8L
TERMINOLOGY
Conversion Rate
The conversion rate specifies the rate at which an output result
is available from the ADC, once the ADC has settled.
The Σ-Δ conversion techniques used on this part mean that
while the ADC front-end signal is oversampled at a relatively high
sample rate, a subsequent digital filter is employed to decimate
the output to give a valid 16-bit data conversion result at output
rates from 1 Hz to 8 kHz.
Note that when software switches from one input to another
(on the same ADC), the digital filter must first be cleared and
then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this can take multiple
conversion cycles.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation of any code from a
straight line passing through the endpoints of the transfer function.
The endpoints of the transfer function are zero scale, a point
0.5 LSB below the first code transition; and full scale, a point
0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.
No Missing Codes
No missing codes is a measure of the differential nonlinearity
of the ADC. The error is expressed in bits and specifies the
number of codes (ADC results) as 2
N
bits, where N = no missing
codes, guaranteed to occur through the full ADC input range.
Offset Error
Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.
Offset Error Drift
Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSBs per °C.
Gain Error
Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured span and the
ideal span between any two points in the transfer function.
Output Noise
Output noise is the standard deviation (or 1 × Σ) of ADC output
codes distribution collected when the ADC input voltage is
at a dc voltage. It is expressed as micro root mean square (μ rms).
The output or rms noise can be used to calculate the effective
resolution of the ADC, as defined by the following equation:
Effective Resolution = log
(Full-Scale Range/rms Noise) bits
2
The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Σ of the distribution of ADC output codes
collected when the ADC input voltage is at dc. The peak-topeak noise is, therefore, calculated as 6.6 × the rms noise.
The peak-to-peak noise can be used to calculate the ADC
(noise free, code) resolution for which there is no code flicker
within a 6.6 sigma limit, as defined by the following equation:
Noise Free Code Resolution = log
(Full-Scale Range/
2
Peak-to-Peak Noise) bits
Tabl e 8. Dat a S h ee t Acr o nyms
Acronym Definition
ADC analog-to-digital converter
ARM advanced RISC machine
ECU electronic control unit
JTAG joint test action group
LDO low dropout
LIN local interconnect network
LSB least significant byte/bit
LVF low voltage flag
MAC multiplication accumulation
MCU microcontroller
MMR memory mapped register
MSB most significant byte/bit
PID protected identifier
PLL phase-locked loop
POR power-on reset
PSM power supply monitor
rms root mean square
Rev. A | Page 19 of 120
ADuC7032-8L
THEORY OF OPERATION
The ADuC7032-8L is a complete system solution for battery
monitoring in 12 V automotive applications. The device integrates
all of the required features to precisely and intelligently monitor,
process, and diagnose 12 V battery parameters, including
battery current, voltage, and temperature, over a wide range of
operating conditions.
Minimizing external system components, the device is powered
directly from the 12 V battery. An on-chip, low dropout (LDO)
regulator generates the supply voltage for the three integrated
16-bit ADCs. The ADCs precisely measure battery current,
voltage, and temperature, which can be used to characterize the
state of health and charge of a car battery.
A Flash/EE memory-based ARM7™ microcontroller (MCU) is
also integrated on-chip and is used both to preprocess the
acquired battery variables and to manage communications from
the ADuC7032-8L to the main electronic control unit (ECU)
via a local interconnect network (LIN) interface, which is
integrated on-chip.
Both the MCU and the ADC subsystem can be individually
configured to operate in normal or flexible power saving modes
of operation.
In its normal operating mode, the MCU is clocked indirectly
from an on-chip oscillator via the phase-locked loop (PLL) at
a maximum clock rate of 20.48 MHz. In its power-saving operating
modes, the MCU can be totally powered down, waking up only
in response to an ADC conversion result ready, digital comparators,
the wake-up timer, a power-on reset (POR), or an external serial
communication event.
The ADC can be configured to operate in a normal (full-power)
mode of operation, interrupting the MCU after various sample
conversion events. The current channel features two low power
modes: low power and low power plus, generating conversion
results to a lower performance specification.
On-chip factory firmware supports in-circuit Flash/EE memory
reprogramming via the LIN or JTAG serial interface ports, and
nonintrusive emulation is supported via the JTAG interface. These
features are incorporated into a low cost QuickStart™ Plus
development system supporting the ADuC7032-8L.
The ADuC7032-8L operates directly from the 12 V battery
supply and is fully specified over a temperature range of −40°C
to +105°C. The ADuC7032-8L is functional, with degraded
performance, at temperatures from 105°C to 125°C.
OVERVIEW OF THE ARM7TDMI® CORE
The ARM7 core is a 32-bit reduced instruction set computer
(RISC), developed by ARM Ltd. The ARM7TDMI is
a von Neumann-based architecture, which means that it uses
a single 32-bit bus for instruction and data. The length of the
data can be 8, 16, or 32 bits; and the length of the instruction word
is either 16 bits or 32 bits, depending on the mode in which the
core is operating.
The ARM7TDMI is an ARM7 core with four additional features,
as listed in Tabl e 9 .
Table 9. ARM7TDMI Features
Feature Description
T Support for the Thumb® (16-bit) instruction set
D Support for debug
M Enhanced multiplier
I
Thumb Mode (T)
An ARM® instruction is 32 bits long. The ARM7TDMI processor
supports the Thumb instruction set, which has been compressed
into 16 bits. Faster code execution from 16-bit memory and
greater code density can be achieved by using the Thumb
instruction set, which makes the ARM7TDMI core particularly
suited for embedded applications.
However, Thumb mode has three limitations.
• Relative to ARM, Thumb code usually requires more
instructions to perform that same task. Therefore, in most
applications ARM code is best used for maximizing the
performance of time-critical code.
• The Thumb instruction set does not include some
instructions that are needed for exception handling.
Therefore, ARM code may be required for exception
handling.
• When an interrupt occurs, the core vectors to the
interrupt location in memory and executes the code
present at this address. It is required that the first
command be in ARM code.
Multiplier (M)
The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions that perform 32-bit ×
32-bit multiplication with a 64-bit result and 32-bit × 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
Includes the EmbeddedICE™ module to support
embedded system debugging
Rev. A | Page 20 of 120
ADuC7032-8L
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module contains
the breakpoint and watchpoint registers, which allow nonintrusive
user code debugging. These registers are controlled through the
JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the processor
registers may be interrogated, as well as the Flash/EE, the SRAM,
and the memory mapped registers.
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions follow:
• Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events.
• Fast interrupt or FIQ. It is provided to service data transfer or
a communication channel with low latency. FIQ has priority
over IRQ.
• Memory abort (prefetch and data).
• Attempted execution of an undefined instruction.
• Software interrupt (SWI) instruction. It can be used to
make a call to an operating system.
Typically, the programmer defines interrupts as IRQ; but for
higher priority interrupts, the programmer can define interrupts
as being of the FIQ type.
The priority of the above exceptions and vector addresses are
shown in Tab l e 1 0 .
Table 10. Exception Priority
Priority Exception Vector Address
1 Hardware reset 0x00
2 Memory abort (data) 0x10
3 FIQ 0x1C
4 IRQ 0x18
5 Memory abort (prefetch) 0x0C
6 Software interrupt1 0x04
6 Undefined instruction1 0x04
1
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
The exceptions in Tab le 1 0 are located from Address 0x00 to
Address 0x1C, with a reserved location at 0x14. This location is
required to be written with either 0x27011970 or the checksum
of Page 0, excluding Location 0x14. If this is not done, user code
is not executed, and LIN download mode is entered.
ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are used
for data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched, if the branch and
link command was used, or the command during which an
exception occurred.
The stack pointer (R13) contains the current location of the stack.
Typically, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends, using the area as required.
A separate stack is defined for each exception. The size of each
stack is user configurable and is dependent on the target
application. On the ADuC7032-8L, the stack begins at
0x000417FC and descends.
When programming using a high level language such as C, it is
necessary to ensure that the stack does not overflow. This is
dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14), as represented
in Figure 9. The FIQ mode has more registers (R8 to R12),
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, reducing the
response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
USABLE IN USER MODE
SYSTEM MODES ONLY
R13_ABT
R14_ABT
ABORT
MODE
R13_IRQ
R14_IRQ
SPSR_IRQ
IRQ
MODE
R13_UND
R14_UND
SPSR_UND
UNDEFINED
MODE
R15 (PC)
CPSR
USER MODE
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
SPSR_FIQ
FIQ
MODE
R13_SVC
R14_SVC
SPSR_SVC
SVC
MODE
SPSR_ABT
Figure 9. Register Organization
05986-009
Rev. A | Page 21 of 120
ADuC7032-8L
Interrupt Latency
• The worst-case latency for an FIQ consists of the following:
• The longest time the request can take to pass through
the synchronizer
• Plus the time for the longest instruction to complete
(the longest instruction is an LDM that loads all the registers,
including the PC)
• Plus the time for the data abort entry
• Plus the time for FIQ entry
At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, or just over 2.44 μs in a system
using a continuous 20.48 MHz processor clock. The maximum
IRQ latency calculation is similar, but it must allow for the fact
that FIQ has higher priority and could delay entry into the IRQ
handling routine for an arbitrary length of time. This time can
be reduced to 42 cycles if the LDM command is not used; some
compilers have an option to compile without using this command.
Another option is to run the part in Thumb mode, where the time
is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
It consists of the shortest time the request can take through the
synchronizer, plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode, if required
(for example, when executing interrupt service routines).
MEMORY ORGANIZATION
The ARM7 (a von Neumann architecture) MCU core sees memory
as a linear array of 2
ADuC7032-8L maps this memory into four distinct user areas,
namely
• A remappable memory area
• An SRAM area
• A Flash/EE area
• A memory mapped register (MMR) area
The first 96 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. A second
4 kB area at the top of the memory map is used to locate the
memory mapped registers (MMR), through which all on-chip
peripherals are configured and monitored. The remaining two
areas of memory are constituted as 6 kB of SRAM and 96 kB of
on-chip Flash/EE memory. There are 94 kB of on-chip Flash/EE
memory available to the user, and the remaining 2 kB are reserved
for the on-chip kernel. These areas are described in more detail
in the sections that follow.
Any access, either read or write, to an area not defined in the
memory map results in a data abort exception.
32
byte locations. As shown in Figure 10, the
0xFFFF0000
0x00080000
0x00040000
0x00000000
0xFFFF0FFF
0x00097FFF
0x00417FF
0x0017FFF
Figure 10. ADuC7032-8L Memory Map
Memory Format
The ADuC7032-8L memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address, and the most significant byte is located in the
highest byte address.
BIT 31
BYTE 2
BYTE 3
.
.
.
B
7
3
Figure 11. Little Endian Format
SRAM
The ADuC7032-8L features 6 kB of SRAM available to the user,
organized as 1536 bits × 32 bits, that is, 1536 words, that are
located at 0x00040000. RAM space can be used as data memory
and as a volatile program space.
ARM code can run directly from SRAM at full clock speed,
given that the SRAM array is configured as a 32-bit wide
memory array.
SRAM is read/write in 8-, 16-, and 32-bit segments.
RESERVED
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
BYTE 1
.
.
.
A
6
2
32 BITS
BYTE 0
.
.
.
9
8
5
4
1
0
5986-011
BIT 0
.
0xFFFFFFFF
.
.
0x00000004
0x00000000
5986-010
Rev. A | Page 22 of 120
ADuC7032-8L
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically mapped
to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000
by setting Bit 0 of the SYSMAP0 MMR, which is located at
0xFFFF0220. To revert Flash/EE to Address 0x00000000, Bit 0 of
SYSMAP0 is cleared.
It may be desirable to remap RAM to Address 0x00000000 to
optimize the interrupt latency of the ADuC7032-8L, as code
can be run in full 32-bit ARM mode and at the maximum core
speed. It should be noted that when an exception occurs, the
core defaults to ARM mode.
Remap Operation
When a reset occurs on the ADuC7032-8L, execution starts
automatically in the factory-programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed
by user code.
If the ADuC7032-8L is in normal mode, it executes the poweron configuration routine of the kernel and then jumps to the
reset vector, Address 0x00000000, to execute the user reset
exception routine.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset routine must always be written in Flash/EE.
Precautions must be taken to execute the remap command from
the absolute Flash/EE address, and not from the mirrored,
remapped segment of memory, because this segment may be
replaced by the SRAM. If a remap operation is executed while
operating code from the mirrored location, prefetch/data aborts
may occur; or the user may observe abnormal program operation.
This operation is reversible. The Flash/EE can be remapped to
Address 0x00000000 by clearing Bit 0 of the SYSMAP0 MMR.
Precautions must again be taken to execute the remap function
from outside the mirrored area.
Any kind of reset logically remaps the Flash/EE memory to the
bottom of the memory array.
SYSMAP0 Register
Name: SYSMAP0
Address: 0xFFFF0220
Default Value: Updated by the kernel
Access: Read/write
Function: This 8-bit register allows user code to remap either RAM or Flash/EE space into the bottom of the ARM memory space,
starting at Address 0x00000000.
Table 11. SYSMAP0 MMR Bit Designations
Bit Description
7 to 1 Reserved. These bits are reserved and should be written as 0 by user code.
0
Remap Bit.
Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE memory to 0x00000000.
Rev. A | Page 23 of 120
ADuC7032-8L
RESET
There are four kinds of reset: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register indicates
the source of the last reset and can be written by user code to
initiate a software reset event. The bits in this register can be
cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234.
Table 12. Device Reset Implications
Reset All
Impact/Reset
POR1 Yes Yes Yes Yes Yes Yes/No
Watchdog Reset Yes Yes Yes Yes Yes Yes RSTSTA[1] = 1
Software Reset Yes Yes Yes Yes Yes Yes RSTSTA[2] = 1
External Reset Pin Yes Yes Yes Yes Yes Yes RSTSTA[3] = 1
1
RAM is valid except in the case of a reset following a LIN download.
2
The impact of RAM is dependent on the contents of HVSTA[6] if LVF is enabled. When LVF is enabled using (HVCFG0[2]), RAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[6] = 1. See the Low Voltage Flag (LVF) section for more information.
Reset External Pins
to Default State
Kernel
Executed
External MMRs
(Excluding RSTSTA)
RSTCLR Register
Name: RSTCLR
Address: 0xFFFF0234
Default Value: 0x00
Access: Write on ly
Function: This 8-bit write-only register clears the corresponding bit in RSTSTA.
RSTSTA Register
Name: RSTSTA
Address: 0xFFFF0230
Default Value: 0x01
Access: Read/write
Function: This 8-bit register indicates the source of the last reset event and can be written by user code to initiate
a software reset.
The bit designations in RSTCLR mirror those of RSTSTA.
These registers can be used during a reset exception service
routine to identify the source of the reset. The implications of
all four kinds of reset event are listed in Table 1 2.
Reset All
High Voltage
Indirect
Registers
Peripherals
Reset
RAM
Valid
1
2
RSTSTA
(Status After
Reset Event)
RSTSTA[0] = 1
Table 13. RSTCLR/RSTSTA MMR Bit Designations
Bit Description
7 to 4 Not Used. These bits are not used and always read as 0.
3
External Reset.
Set to 1 automatically when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
2
Software Reset.
1
Set to 1 by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR.
1
Watchdog Timeout.
Set to 1 automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-On Reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset.
Rev. A | Page 24 of 120
ADuC7032-8L
FLASH/EE MEMORY AND THE ADUC7032-8L
The ADuC7032-8L incorporates Flash/EE memory technology
on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space.
Like EEPROM, Flash memory can be programmed in-system
at the byte level, although it must first be erased, the erase being
performed in page blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the
ADuC7032-8L, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
Flash/EE Memory
The total 96 kB of Flash/EE memory is organized as 48 kB × 16
bits. Of the 96 kB, 94 kB is user space, and 2 kB is reserved for
boot loader/kernel space. The page size of this Flash/EE memory
is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to
erase a page, and 50 μs to write a 16-bit word. These Flash/EE
timings are independent of the MCU core clock.
There is 94 kB of Flash/EE memory available to the user as code
and nonvolatile data memory. There is no distinction between
data and program, because ARM code shares the same space.
The real width of the Flash/EE memory is 16 bits, which means
that in ARM mode (32-bit instruction), two accesses to the
Flash/EE are necessary for each instruction fetch. When operating
at speeds less than 20.48 MHz, the Flash/EE memory controller
can transparently fetch the second 16-bit halfword (part of the
32-bit ARM operation code) within a single core clock period.
Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is
recommended that ARM mode be used. For 20.48 MHz
operation (that is, CD = 0), it is recommended that Thumb
mode be used.
The Flash/EE memory is physically located at Address 0x80000.
Upon a hard reset, it is logically mapped to 0x00000000. The
factory default contents of all Flash/EE memory locations is
0xFF. Flash/EE can be read in 8-, 16-, and 32-bit segments and
written in segments of 16 bits. The Flash/EE is rated for 10,000
endurance cycles. This rating is based on the number of times
that each individual halfword (16-bit location) is cycled, that is,
erased and programmed. A redundancy scheme can be implemented in software to ensure greater than 10,000 cycles of
endurance.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
It is possible to write to a single 16-bit location only twice between
erases; that is, it is possible to walk bytes, not bits. If a location
is written to more than twice, the contents of the Flash/EE page
may be corrupted.
The 94 kB of Flash/EE memory can be programmed in-circuit,
using a serial download mode via the LIN interface or the
integrated JTAG port.
Serial Downloading (In-Circuit Programming)
The ADuC7032-8L facilitates code download via the LIN pin.
JTAG Access
The ADuC7032-8L features an on-chip JTAG debug port to
facilitate code download and debug.
FLASH/EE CONTROL INTERFACE
The access to and control of the Flash/EE memory on the
ADuC7032-8L is managed by an on-chip memory controller.
The controller manages the Flash/EE memory as two separate
blocks (Block 0 and Block 1).
Block 0 consists of the 32 kB Flash/EE memory mapped from
0x00090000 to 0x00097FFF (including the 2 kB kernel space
that is reserved at the top of this block).
Block 1 consists of the 6 kB Flash/EE memory mapped from
0x00080000 to 0x0008FFFF.
Note that the MCU core can continue to execute code from one
memory block while an active erase or program cycle is being
carried out on the other block. If a command operates on the
same block as the code currently executing, the core is halted
until the command is completed. This also applies to code
execution.
User code, LIN, and JTAG programming use the Flash/EE
control interface, which consists of the following MMRs:
• FEExSTA (x = 0 or 1): read-only register that reflects the
status of the Flash/EE memory control interface
• FEExMOD (x = 0 or 1): sets the operating mode of the
Flash/EE memory control interface
• FEExCON (x = 0 or 1): 8-bit command register;
the commands are interpreted as described in
• FEExDAT (x = 0 or 1): 16-bit data register
• FEExADR (x = 0 or 1): 16-bit address register
• FEExSIG (x = 0 or 1): holds the 24-bit code signature
as a result of the signature command being initiated
Tabl e 14 .
Rev. A | Page 25 of 120
ADuC7032-8L
• FEExHID (x = 0 or 1) is a protection MMR that controls
read- and write-protection of the Flash/EE memory code
space. If previously configured via the FEExPRO register,
FEExHID may require a software key to enable access.
• FEExPRO (x = 0 or 1) is a buffer of the FEExHID register,
which is used to store the FEExHID value so it is automatically downloaded to the FEExHID registers on subsequent
reset and power-on events.
FEE0CON and FEE1CON Registers
Name: FEE0CON and FEE1CON
Address: 0xFFFF0E08 and 0xFFFF0E88
Default Value (Both Registers): 0x07
Access: Read/write
Function: These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0
(32 kB) and Block 1 (64 kB).
Table 14. Command Codes in FEE0CON and FEE1CON
Code Command Description1
0x002 Reserved Reserved. This command should not be written by user code.
0x012 Single read Load FEExDAT with the 16-bit data indexed by FEExADR.
0x022 Single write Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
0x032 Erase-write
0x042 Single verify
0x052 Single erase Erase the page indexed by FEExADR.
0x062 Mass erase
0x07 Default command.
0x08 Reserved Reserved. This command should not be written by user code.
0x09 Reserved Reserved. This command should not be written by user code.
0x0A Reserved Reserved. This command should not be written by user code.
0x0B Signature
0x0C Protect
0x0D Reserved Reserved. This command should not be written by user code.
0x0E Reserved Reserved. This command should not be written by user code.
0x0F Ping No operation, interrupt generated.
1
x in the register names designates 0 or 1 for Flash/EE Block 0 or Flash/EE Block 1.
2
The FEExCON always reads 0x07 immediately after execution of any of these commands.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation
takes 20 ms.
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison
is returned in FEExSTA Bit 1.
Erase Block 0 (30 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec.
To prevent accidental execution, a command sequence is required to execute this instruction. This sequence is
described in the Command Sequence for Executing a Mass Erase section.
FEE0CON. This command results in a 24-bit LFSR-based signature being generated and loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space
from the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed.
FEE1CON. This command results in a 24-bit LFSR-based signature being generated, beginning at FEE1ADR and
ending at the end of the 64 kB block, and loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the software protection key.
Note that user software must ensure that the Flash/EE controller
has completed any erase or write cycle before the PLL is powered
down. If the PLL is powered down before an erase or write cycle
has completed, the Flash/EE page or byte may be corrupted.
The following sections describe in detail the bit designations of
each of the Flash/EE control MMRs.
Rev. A | Page 26 of 120
ADuC7032-8L
Command Sequence for Executing a Mass Erase
Because of the significance of the mass erase command,
a specific code sequence must be executed to initiate this
operation.
1. Set Bit 3 in FEExMOD.
2. Write 0xFFC3 in FEExADR.
3. Write 0x3CFF in FEExDAT.
4. Run the mass erase command 0x06 in FEExCON.
Command Sequence Example
The command sequence for executing a mass erase is illustrated in the following example:
Int a = FEExSTA; // Ensure FEExSTA is cleared
FEExMOD = 0x08;
FEExADR = 0xFFC3;
FEExDAT = 0x3CFF;
FEExCON = 0x06; // Mass-Erase command
while (FEExSTA & 0x04){} // Wait for command to finish
FEE0STA and FEE1STA Registers
Name: FEE0STA and FEE1STA
Address: 0xFFFF0E00 and 0xFFFF0E80
Default Value (Both Registers): 0x20
Access: Read only
Function: These 8-bit read-only registers can be read by user code and reflect the current status of the Flash/EE memory controllers.
To run the mass-erase command via FEE0CON, write protection
on the lower 64 kB must be disabled; that is, FEE1HID and
FEE1PRO are set to 0xFFFFFFFF. This is accomplished by first
removing the protection or by erasing the lower 64 kB first.
Table 15. FEE0STA and FEE1STA MMR Bit Designations
Bit Description1
15 to 4 Not Used. These bits are not used and are always read as 0.
3
2
Flash Interrupt Status Bit.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set.
Cleared automatically when the FEExSTA register is read by user code.
Flash/EE Controller Busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
1
Command Fail.
Set automatically when a command written to FEExCON completes unsuccessfully.
Cleared automatically when the FEExSTA register is read by user code.
0
Command Successful.
Set automatically by MCU when a command is completed successfully.
Cleared automatically when the FEExSTA register is read by user code.
1
x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1.
FEE0ADR and FEE1ADR Registers
Name: FEE0ADR and FEE1ADR
Address: 0xFFFF0E10 and 0xFFFF0E90
Default Value: Nonzero (FEE0ADR), 0x0000 (FEE1ADR)
Access: Read/write
Function: This 16-bit register dictates the address acted upon by any Flash/EE command executed via FEExCON.
FEE0DAT and FEE1DAT Registers
Name: FEE0DAT and FEE1DAT
Address: 0xFFFF0E0C and 0xFFFF0E8C
Default Value (Both Registers): 0x0000
Access: Read/write
Function: This 16-bit register contains the data either read from or to be written to the Flash/EE memory controllers.
Rev. A | Page 27 of 120
ADuC7032-8L
FEE0MOD and FEE1MOD Registers
Name: FEE0MOD and FEE1MOD
Address: 0xFFFF0E04 and 0xFFFF0E84
Default Value (Both Registers): 0x00
Access: Read/write
Function: These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers.
Table 16. FEE0MOD and FEE1MOD MMR Bit Designations
Bit Description1
15 to 7 Not Used. These bits are reserved for future functionality and should be written as 0 by user code.
6 to 5 Flash/EE Security Lock Bits. These bits must be written as [6:5] = 10 to complete the Flash security protect sequence.
4
3
2 Reserved. Should be written as 0.
1
0 Reserved. Should be written as 0.
1
x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1.
FLASH/EE MEMORY SECURITY
The 94 kB of Flash/EE memory available to the user can be
read-protected and write-protected using the FFE0HID and
FEE1HID registers.
In Block 0, the FEE0HID MMR protects the 30 kB of Flash/EE
memory. Bit 0 to Bit 28 of this register protect Page 0 to Page 57
from writing. Each bit protects two pages, that is, 1 kB. Bit 29 to
Bit 30 protect Page 58 and Page 59, respectively; that is, each bit
write-protects a single page of 512 bytes. The MSB of this register
(Bit 31) protects Block 0 from being read through JTAG.
The FEE0PRO register mirrors the bit definitions of the FEE0HID
MMR. The FEE0PRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so that
the protection configuration is automatically loaded on
subsequent power-on or reset events.
Flash/EE Controller Command Complete Interrupt Enable.
Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.
Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
Flash/EE Erase/Write Enable.
Set by user code to enable the Flash/EE erase and write access via FEExCON.
Cleared by user code to disable the Flash/EE erase and write access via FEExCON.
Flash/EE Controller Abort Enable.
Set to 1 by user code to enable the Flash/EE controller abort functionality.
This flexibility allows the user to set and test protection settings
temporarily using the FEE0HID MMR and subsequently lock
the required protection configuration (using FEE0PRO) when
shipping protection systems into the field.
In Block 1 (64 kB), the FEE1HID MMR protects the 64 kB of
Flash/EE memory. Bit 0 to Bit 29 of this register protect Page 0
to Page 119 from writing. Each bit protects four pages, that is, 2 kB.
Bit 30 protects Page 120 to Page 127; that is, Bit 30 write-protects
eight pages of 512 bytes. The MSB of this register (Bit 31) protects
Flash/EE Block 1 from being read through JTAG.
As with Block 0, the FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR allows user
code to lock the protection or security configuration of the
Flash/EE memory so that the protection configuration is
automatically loaded on subsequent power-on or reset events.
Rev. A | Page 28 of 120
ADuC7032-8L
Block 0, Flash/EE Memory Protection Registers
Name: FEE0HID and FEE0PRO
Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO)
Default Value (Both Registers): 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO)
Access: Read/write
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Table 17. FEE0HID and FEE0PRO MMR Bit Designations
Bit Description
31
30
29
28 to 0
Block 1, Flash/EE Memory Protection Registers
Name: FEE1HID and FEE1PRO
Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO)
Default Value (Both Registers): 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO)
Access: Read/write
Function: These registers are written by user code to configure the protection of the Flash/EE memory.
Read Protection Bit.
Cleared by the user to protect the 32 kB Flash/EE block code via JTAG read access.
Set by the user to allow reading of the 32 kB Flash/EE block code via JTAG read access.
Write-Protection Bit.
Set by user code to unprotect Page 59.
Cleared by user code to write-protect Page 59.
Write-Protection Bit.
Set by user code to unprotect Page 58.
Cleared by user code to write-protect Page 58.
Write-Protection Bits.
When set by user code, these bits unprotect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write-protects
two pages, and each page consists of 512 bytes.
When cleared by user code, these bits write-protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit writeprotects two pages, and each page consists of 512 bytes.
Table 18. FEE1HID and FEE1PRO MMR Bit Designations
Bit Description
31
30
29 to 0
Read-Protection Bit.
Cleared by the user to protect the 64 kB Flash/EE block code via JTAG read access.
Set by the user to allow reading of the 64 kB Flash/EE block code via JTAG read access.
Write-Protection Bit.
When set by user code, this bit protects Page 120 to Page 127 of the 64 kB Flash/EE code memory. This bit write-protects eight
pages, and each page consists of 512 bytes.
When cleared by user code, this bit write-protects Page 120 to Page 127 of the 64 kB Flash/EE code memory. This bit writeprotects eight pages, and each page consists of 512 bytes.
Write-Protection Bits.
When set by user code, these bits unprotect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write-protects
four pages, and each page consists of 512 bytes.
When cleared by user code, these bits write-protect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit writeprotects two pages, and each page consists of 512 bytes.
Rev. A | Page 29 of 120
ADuC7032-8L
In summary, there are three levels of memory protection:
• Temporary protection can be set and removed by writing
directly into the FEExHID MMR. This register is volatile;
therefore, protection is in place only while the part remains
powered on. Protection is not reloaded after a power cycle.
• Keyed permanent protection can be set via FEExPRO,
which is used to lock the protection configuration. The
software key used at the start of the required FEExPRO
write sequence is saved once and must subsequently be
used for any subsequent access to the FEExHID or
FEExPRO MMRs. A mass erase sets the key back to
0xFFFF but also erases the entire user code space.
• Permanent protection can be set via FEExPRO, similarly to
keyed permanent protection. The only difference is that
the software key used is 0xDEADDEAD. Once the
FEExPRO write sequence is saved, only a mass erase sets
the key back to 0xFFFFFFFF. This mass erase also erases
the entire user code space.
Sequence Example
The sequence to write the key and set permanent protection is illustrated in the following example, which protects writing Page 4 and Page 5
of the Flash/EE:
FEExPRO = 0xFFFFFFFB; // Protect Page 4 and Page 5
FEExADR = 0x66BB; // 32-bit key value Bits[31:16]
FEExDAT = 0xAA55; // 32-bit key value Bits[15:0]
FEExMOD = 0x0048; // Lock security sequence
FEExCON = 0x0C; // Write key command
while (FEExSTA & 0x04){} // Wait for command to finish
Sequence to Write the Key and Set Permanent Protection
1. Write in FEExPRO corresponding to the pages to be
protected.
2. Write the new (user-defined) 32-bit key in FEExADR
Bits[31:16] and FEExDAT Bits[15:0].
3. Write 1,0 in FEExMOD Bits[6:5] and set FEExMOD Bit 3.
4. Run the write key command 0x0C in FEExCON.
Rev. A | Page 30 of 120
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