ANALOG DEVICES ADuC7032 Service Manual

MicroConverter

® Integrated,

Preliminary Technical Data

FEATURES

High Precision ADCs

Dual Channel, Simultaneous Sampling, 16-Bit Σ−∆ ADCs
Third Independent ADC for Temperature Sensing
Programmable ADC throughput from 1Hz to 8KHz
On-Chip 5ppm/°C Voltage Reference
Current Channel
Fully differential, Buffered Input
Programmable Gain 1 to 512
ADC Input Range -200mV to +300mV
Digital Comparators, with Current Accumulator Feature
Voltage Channel
Buffered, On-Chip attenuator for 12V battery Inputs
Temperature Channel
External and On-Chip Temperature Sensor Options

Microcontroller

ARM7TDMI Core, 16/32-bit RISC architecture

20.48MHz PLL with Programmable Divider
PLL Input Source: On-Chip Precision Oscillator

On-Chip Low-Power Oscillator

External (32.768KHz) Watch Crystal

JTAG Port supports code download and debug

FUNCTIONAL BLOCK DIAGRAM

Precision Battery Sensor

ADuC7032

Memory

96k Bytes Flash/EE Memory, 6k Bytes SRAM
10KCycles Flash Endurance, 20 Years Flash Retention
In-Circuit Download via JTAG and LIN
64 x 16bit Result FIFO for Current and Voltage ADC

On-Chip Peripherals

LIN 1.2, 1.3 and 2.0 (Slave) Compatible Support via UART

with Hardware Synchronization

Flexible Wake-up I/O Pin, Master/Slave SPI Serial I/O
9-Pin GPIO Port, 2 X General Purpose Timers
Wake-up and Watchdog Timers

Power Supply Monitor, On-Chip Power-On-Reset
Power
Operates directly from 12V Battery Supply
Current Consumption
Normal Mode 10mA at 10MHz
Low Power Monitor Mode
Package and Temperature Range

48 Pin LQFP 7X7 mm body package

Fully specified for –40°C to 105°C operation

APPLICATIONS
Battery Sensing/Management for Automotive Systems

T
S

S

R

O

I

K

T

M

D

D

C

N

T

T

T

T

PRECISION ANALOG ACQUISITION

IIN+

IIN-

VBAT

VTEMP

GND_SW

VREF

BUF

PGA

RESULT

ACCUMULATOR

BUF

BUF

MUX

TEMP

SENSOR

D

D
D
V

D

D

N

D

D

V

V

G

A

D

A

_

_

G

G

E

E

R

R

Σ−∆

DIGITAL

COMPARATOR

Σ−∆

Σ−∆

PRECISION

REFERENCE

S

D

S

S

S

N

V

V

G

_

D

O

I

16-BIT

16-BIT

16-BIT

Figure 1: ADuC7032 Functional Block Diagram

D

Rev. Pr

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Preliminary Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or p atent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective
companies.

ADC

ADC

ADC

2.5V LDO
PSM
POR

ARM7 TDMI

MCU

20MHz

2xTIMERS

WDT

W/U TIMER

1

0

_

_
O

IO

I

P

P

G

G

2
_

IO
P
G

96KB FLASH

128B ADC FIFO

LOW POWER

ON-CHIP PLL

4

3

_

_
O

IO

I

P

P

G

G

MEMORY

6KB RAM

PRECISION

OSC

OSC

GPIO PORT
UART PORT

SPI PORT

LIN

6

5

7

_

_

_

O

O

I

IO

I

P

P

P

G

G

G

RESET

XTAL1

XTAL2

WU

LIN

8
_

O

I
P
G

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

www.analog.com

Preliminary Technical Data ADuC7032

TABLE OF CONTENTS

TABLE OF CONTENTS................................................... 2

ADUC7032 DATASHEET TABLES.................................5

ADUC7032 DATASHEET FIGURES ..............................7

ADUC7032SPECIFICATIONS ........................................8

ELECTRICAL SPECIFICATIONS............................................ 8

TIMING SPECIFICATIONS ................................................. 15

SPI Timing Specifications...........................................15

LIN Timing Specifications.......................................... 19

SPECIFICATION TERMINOLOGY............................. 21

ABSOLUTE MAXIMUM RATINGS ............................22

ORDERING GUIDE ........................................................... 22

ESD Caution...............................................................22

PIN FUNCTION DESCRIPTIONS ...............................23

ADUC7032 GENERAL DESCRIPTION.......................26

OVERVIEW OF THE ARM7TDMI CORE ........................... 26

ARM7 Exceptions.......................................................27

ARM Registers............................................................ 27

Interrupt latency.........................................................28

MEMORY ORGANISATION ................................................28

Memory Format..........................................................28

SRAM..........................................................................28

Remap.........................................................................29

Remap operation........................................................ 29

SYSMAP0 Register :................................................... 29

ADUC7032 RESET .......................................................... 30

RSTCLR Register :..................................................... 30

RSTSTA Register :...................................................... 30

FLASH/EE MEMORY AND THE ADUC7032......................31

FLASH/EE MEMORY CONTROL INTERFACE...................... 31

FEE0CON and FEE1CON Registers : ....................... 32

FEE0ST A and FEE1STA Registers :...........................33

FEE0ADR and FEE1ADR Registers:.........................33

FEE0DAT and FEE1DAT Registers:..........................33

FEE0MOD and FEE1MOD Registers :.....................34

FLASH/EE MEMORY SECURITY ........................................34

Block0, Flash/EE Memory Protection Registers :......35

Block1, Flash/EE Memory Protection Registers :......35

FLASH/EE MEMORY RELIABILITY .................................. 36

CODE EXECUTION TIME FROM SRAM AND FLASH/EE 37

Execution from SRAM................................................ 37

Execution from Flash/EE ...........................................37

ADUC7032 KERNEL ....................................................... 38

MEMORY MAPPED REGISTERS ........................................ 40

16-BIT Σ−∆ ANALOG TO DIGITAL CONVERTERS.45

CURRENT CHANNEL ADC (I-ADC) ................................45

VOLTAGE CHANNEL ADC (V-ADC)................................46

TEMPERATURE CHANNEL ADC (T-ADC) ........................46

ADC GROUND SWITCH ...................................................47

ADC NOISE PERFORMANCE TABLES ...............................48

ADC MMR INTERFACE...................................................49

ADC Status Register :.................................................49

ADC Interrupt Mask Register :...................................50

ADC Mode Register : .................................................51

Current Channel ADC Control Register :...................52

Voltage Channel ADC Control Register :...................53

Temperature Channel ADC Control Register :...........54

ADC Filter Register : .................................................55

ADC Configuration Register :....................................57

Current Channel ADC Data Register :.......................58

Voltage Channel Data Register:.................................58

Temperature Channel ADC Data Register :...............58

ADC FIFO Register : .................................................58

Current Channel ADC Offset Calibration Register :..58

Voltage Channel Offset Calibration Register :...........58

Temperature Channel Offset Calibration Register:....58

Current Channel ADC Gain Calibration Register :...59

Voltage Channel Gain Calibration Register :.............59

Temperature Channel Gain Calibration Register :.....59

Current Channel ADC Result Counter Limit Register:

....................................................................................59

Current Channel ADC Result Count Register:...........59

Current Channel ADC Threshold Register:................59

Current Channel ADC Threshold Count Limit Register:

....................................................................................59

Current Channel ADC Threshold Count Register:.....60

Current Channel ADC Accumulator Register:...........60

Current Channel ADC Accumulator Threshold

Register: .....................................................................60

Low Power Voltage Reference Scaling Factor............60

ADC POWER MODES OF OPERATION...............................60

ADC Startup Procedure..............................................60

ADC Normal Power Mode..........................................61

ADC Low Power Mode...............................................61

ADC Low Power-Plus Mode.......................................61

ADC Sinc3 Digital Filter Response............................61

ADC Calibration.........................................................64

Using the Offset and Gain Calibration Registers.......64

Understanding the Offset and Gain Calibration

Registers.....................................................................65

ADC DIAGNOSTICS.........................................................65

Current ADC Diagnostics...........................................65

Temperature ADC Diagnostics...................................66

POWER SUPPLY SUPPORT CIRCUITS.....................67

ADUC7032 SYSTEM CLOCKS.....................................68

PLLSTA Register : ......................................................69

PLLCON Pre-write Key PLLKEY0:...........................70

Rev. PrD | Page 2 of 128

Preliminary Technical Data ADuC7032

PLLCON Pre-write Key PLLKEY1:........................... 70

PLLCON Register :.................................................... 70

POWCON Pre-write Key POWKEY0:....................... 70

POWCON Pre-write Key POWKEY1:....................... 70

POWCON Register :..................................................71

ADUC7032 LOW POWER CLOCK CALIBRATION ............. 72

OSC0TRM Register :..................................................73

OSC0CON Register : .................................................73

OSC0STA Register :................................................... 74

OSC0VAL0 Register :................................................. 74

OSC0VAL1 Register :................................................. 74

PROCESSOR REFERENCE PERIPHERALS............75

INTERRUPT SYSTEM........................................................ 75

TIMERS ........................................................................... 77

TIMER0 – LIFE-TIME TIMER ............................................ 78

Timer0 Value Register :.............................................. 78

Timer0 Capture Register :.......................................... 78

Timer0 Control Register :...........................................79

Timer0 Load Registers:.............................................. 79

Timer0 Clear Register :.............................................. 79

TIMER1 ........................................................................... 80

Timer1 Load Registers:.............................................. 80

Timer1 Clear Register :.............................................. 80

Timer1 Value Register :.............................................. 80

Timer1 Capture Register :.......................................... 81

Timer1 Control Register :...........................................81

TIMER2 - WAKE-UP TIMER ............................................. 82

Timer2 Load Registers:.............................................. 82

Timer2 Clear Register :.............................................. 82

Timer2 Value Register :.............................................. 82

Timer2 Control Register :...........................................83

TIMER3 - WATCHDOG TIMER........................................... 84

Timer3 Load Register :............................................... 84

Timer3 Value Register :.............................................. 84

Timer3 Clear Register :.............................................. 85

Timer3 Control Register :...........................................85

GENERAL P URPOSE I/O ............................................. 86

GPIO Port0 Control Register : ..................................88

GPIO Port1 Control Register : ..................................89

GPIO Port2 Control Register : ..................................89

GPIO Port0 Data Register :.......................................90

GPIO Port1 Data Register :.......................................91

GPIO Port2 Data Register :.......................................92

GPIO Port0 Set Register :.......................................... 93

GPIO Port1 Set Register :.......................................... 94

GPIO Port2 Set Register :.......................................... 94

GPIO Port0 Clear Register : .....................................95

GPIO Port1 Clear Register : .....................................95

GPIO Port2 Clear Register : .....................................96

HIGH VOLTAGE PERIPHERAL CONTROL

INTERFACE....................................................................97

High Voltage Interface Control Register :.................. 98

High Voltage Data Register:......................................99

High Voltage Configuration0 Register :...................100

High Voltage Configuration1 Register :...................101

High Voltage Interrupt Status Register :...................102

High Voltage Monitor Register :...............................103

WAKE-UP(WU).............................................................104

Wake-Up(WU) Pin Circuit Description....................104

HANDLING INTERRUPTS FROM THE HIGH VO LTAG E

PERIPHERAL CONTROL INTERFACE................................ 105

LOW VOLTAGE FLAG ( LV F )......................................... 105

HIGH VOLTAGE DIAGNOSTICS....................................... 105

UART SERIAL INTERFACE.......................................106

BAUD RATE GENERATION ..............................................106

Normal 450 UART baud rate generation. ................106

ADuC7032 Fractional divider: ................................106

UART REGISTER DEFINITION ........................................ 107

UART TX Register:..................................................107

UART RX Register:..................................................107

UART Divisor Latch Register 0:...............................107

UART Divisor Latch Register 1:...............................107

UART Control Register 0: .......................................108

UART Control Register 1: .......................................109

UART Status Register 0:..........................................109

UART Interrupt Enable Register 0:.......................... 110

UART Interrupt Identification Register 0:................ 110

UART Fractional Divider Register:..........................111

SERIAL PERIPHERAL INTERFACE........................ 112

SPI Control Register :.............................................. 113

SPI Status Register :................................................. 114

SPI Receive Register :.............................................. 114

SPI Transmit Register :.............................................114

SPI Divider Register : .............................................. 114

LIN (LOCAL INTERCONNECT NETWORK )

INTERFACE ..................................................................115

LIN MMR DESCRIPTION .............................................. 115

LIN Hardware Synchronization Status Register :.....116

LIN Hardware Synchronization Control Register 0: 117
LIN Hardware Synchronization Control Register 1: 118
LIN Hardware Synchroniz at i o n Timer0 Register : ... 118

LIN Hardware Break Timer1 Register :....................119

LIN HARDWARE INTERFACE .........................................119

LIN Frame Protocol................................................. 119

LIN Frame Break Symbol.........................................120

LIN Frame Synchronization Byte.............................120

LIN Frame Protected Identifier................................120

LIN Frame Data Byte...............................................121

LIN Frame Data Tr ansmission and Reception .........121

Example LIN Hardware Synchronization Routine....122

LIN Diagnostics........................................................123

ADUC7032 ON-CHIP DIAGNOSTICS.......................124

ADC Diagnostics......................................................124

High Voltage I/O Diagnostics...................................124

PART IDENTIFICATION ............................................125

Rev. PrD | Page 3 of 128

Preliminary Technical Data ADuC7032

System Serial ID Register 0: ....................................125

System Serial ID Register 1: ....................................126

System Kernel Checksum:........................................126

System Identification FEE0ADR:.............................127

OUTLINE DIMENSIONS.............................................128

Rev. PrD | Page 4 of 128

Preliminary Technical Data ADuC7032

ADUC7032 DATASHEET TABLES

Table 1 : ADUC7032—SPECIFICATIONS 8

Table 2 : SPI Master Mode Timing (PHASE Mode = 1) 15

Table 3 : SPI Master Mode Timing (PHASE Mode = 0) 16

Table 4 : SPI Slave Mode Timing (PHASE Mode = 1) 17

Table 5 : SPI Slave Mode Timing (PHASE Mode = 0) 18

Table 6. Absolu t e Maxim u m R atings (TA = -40°C to 105°C

unless otherwise noted) 22

Table 7: Pin Function Descriptions 23

Table 8: SYSMAP0 MMR Bit Designations 29

Table 9 : Device RESET Implications 30

Table 10: RSTSTA/RSTCLR MMR Bit Designations 30

Table 11: Command Codes in FEE0CON and FEE1CON 32

Table 12: FEE0STA and FEE1STA MMR bit designations 33

Table 13: FEE0MOD and FEE1MOD MMR bit designations 34

Table 14: FEE0HID and FEE0PRO MMR bit designations 35

Table 15: FEE1HID and FEE1PRO MMR bit designations 35

Table 16: Typical execution cycles in ARM/Thumb mode 37

Table 17 : Complete MMR List 41

Table 18 : GND_SW Configuration 47

Table 19 : Current Channel ADC, Normal Power Mode, Typical

Output RMS Noise (µV) 48

Table 20 : Voltage Channel ADC, Typical Output RMS Noise

(referred to ADC Voltage attenuator Input)(µV) 48

Table 21 : Temperat ure Chan nel ADC, Typical Out put RMS

Noise (µV) 48

Table 29 : Allowable Combinations of SF and AF 56

Table 30: ADCCFG MMR Bit Designations 57

Table 31 : Allowable Combinations of SF and AF 61

Table 32 : Common ADCFLT Configurations 63

Table 33: Current ADC Diagnostics 66

Table 34: Temperature ADC Diagnostics 66

Table 35 : PLLSTA MMR Bit Description 69

Table 36: PLLCON MMR Bit description 70

Table 37 : POWCON MMR bit designations 71

Table 38 : OSC0TRM MMR Bit Definition 73

Table 39: OSC0CON MMR Bit Definition 73

Table 40 : OSC0STA MMR Bit Definition 74

Table 41 : IRQ/FIQ MMRs bit description 75

Table 42 : SWICFG MMR Bit Descriptions 76

Table 43 : Timer Event Capture 77

Table 44 : T0CON MMR Bit Descriptions 79

Table 45 : T1CON MMR Bit Descriptions 81

Table 46 : T2CON MMR Bit Descriptions 83

Table 47 : T3CON MMR Bit Definition 85

Table 48 : External GPIO Pin to Internal Port Signal

Assignments 87

Table 49 : GP0CON MMR Bit Designations 88

Table 50 : GP1CON MMR Bit Designations 89

Table 51 : GP2CON MMR Bit Designations 89

Table 22 : ADCSTA MMR Bit Designations 49

Table 23 : ADCMDE MMR Bit Designations 51

Table 24 : ADC0CON MMR Bit Designations 52

Table 25 : ADC1CON MMR Bit Designations 53

Table 26 : ADC2CON MMR Bit Designations 54

Table 27 : ADCFLT MMR Bit Designations 55

Table 28 : ADC Conversion Rates and Settling Times 56

Rev. PrD | Page 5 of 128

Table 52 : GP0DAT MMR Bit Descriptions 90

Table 53 : GP1DAT MMR Bit Descriptions 91

Table 54 :GP2DAT MMR Bit Descriptions 92

Table 55 : GP0SET MMR Bit Descriptions 93

Table 56 : GP1SET MMR Bit Descriptions 94

Table 57 : GP2SET MMR Bit Descriptions 94

Table 58 : GP0CLR MMR Bit Descriptions 95

Preliminary Technical Data ADuC7032

Table 59 : GP1CLR MMR Bit Descriptions 95

Table 74 : COMIEN0 MMR Bit Descriptions 110

Table 60 : GP2CLR MMR Bit Descriptions 96

Table 61: HVCON MMR Write Bit Designations 98

Table 62: HVCON MMR Read Bit Designations 98

Table 63: HVDAT MMR Bit Designations 99

Table 64: HVCFG0 Bit Designations 100

Table 65: HVCFG1 Bit Designations 101

Table 66: HVSTA Bit Designations 102

Table 67: HVMON Bit Designations 103

Table 68: High Voltage Diagnostics 105

Table 69 : Baud rate using the standard Baud rate generator 106

Table 70: Baud rate using the Fractional Baud rate generator 106

Table 71 : COMCON0 MMR Bit Descriptions 108

Table 72 : COMCON1 MMR Bit Descriptions 109

Table 73: COMSTA0 MMR Bit Descriptions 109

Table 75 : COMIID0 MMR Bit Descriptions 110

Table 76 : COMDIV2 MMR Bit Descriptions 111

Table 77 : SPI Output Pins 112

Table 78: SPI speed vs. clock divider bits in master mode 112

Table 79 : SPICON MMR Bit Descriptions 113

Table 80 : SPISTA MMR Bit Descriptions 114

Table 81 : LHSSTA MMR Bit Descriptions 116

Table 82 : LHSCON0 MMR Bit Descriptions 117

Table 83 : LHSCON1 MMR Bit Descriptions 118

Table 84 : SYSSER0 MMR Bit Descriptions 125

Table 85: SYSSER1 MMR Bit Descriptions 126

Table 86: FEE0ADR System Identification MMR Bit

Descriptions 127

Rev. PrD | Page 6 of 128

Preliminary Technical Data ADuC7032

ADUC7032 DATASHEET FIGURES

Figure 1: ADuC7032 Functional Block Diagram..........................1

Figure 2. SPI Master Mode Timing (PHASE Mode = 1)............15

Figure 3. SPI Master Mode Timing (PHASE Mode = 0)............16

Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)...............17

Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)..............18

Figure 6 : LIN V1.3 Timing Specification....................................19

Figure 7 : LIN V2.0 Timing Specification....................................20

Figure 8 : Package Pin Configuration...........................................22

Figure 9: ADuC7032 Register Organization................................27

Figure 10: Little Endian Format ....................................................28

Figure 11: ADuC7032 Memory Map...........................................28

Figure 12. Flash/EE Memory Data Retention .............................36

Figure 13: ADuC7032 Kernel Flowchart......................................39

Figure 14: Top Level MMR Map ...................................................40

Figure 15: Current ADC, Top Level Overview............................45

Figure 16 : Voltage/ Temperature ADC, Top Level Overview...46

Figure 17 : Example External Temperature Sensor Circuits......47

Figure 18: Internal Ground Switch Configuration .....................47

Figure 19 : Typical Digital Filter Response at FADC=1.0kHz

(ADCFLT = 0x0007)..............................................................62

Figure 20 : ModifiedSinc3 Digital Filter Response at

FADC=1.0kHz (ADCFLT = 0x0087)...................................62

Figure 24 : Typical Digital Filter Response at FADC=4Hz,

(ADCFLT = 0xBF1D)............................................................63

Figure 25 : Typical Digital Filter Response at FADC=1Hz,

(ADCFLT = 0xBD1F..............................................................63

Figure 26: Typical Power-On Cycle ..............................................67

Figure 27: ADuC7032 System Clock Generation .......................68

Figure 28 : Example OSC0TRM Calibration Routine................72

Figure 29: Interrupt Structure .......................................................76

Figure 30 : Timer 0 block diagram................................................78

Figure 31 : Timer 1 Block Diagram ..............................................80

Figure 32 : Timer 2 block diagram................................................82

Figure 33 : Timer3 Block Diagram ..............................................84

Figure 34 : ADuC7032 GPIO.........................................................86

Figure 35 : High Voltage Interface, Top Level Block Diagram..97

Figure 36 : WU Circuit, Block Diagram ....................................104

Figure 37 : Fractional Divider Baud Rate generation...............106

Figure 38 : LIN I/O, Block Diagram...........................................115

Figure 39 : LIN Interface Timing ...............................................119

Figure 40 : LIN Break Field..........................................................120

Figure 41 : LIN Synch byte Field .................................................120

Figure 42 : LIN Identifier Byte Field...........................................120

Figure 43 : LIN Data Byte Field...................................................121

Figure 21 : Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x0000)..............................................................62

Figure 22 : Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x4000)..............................................................62

Figure 23 Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x961F)..............................................................63

Figure 44 : Example LIN Configuration ....................................123

Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48),

Rev. PrD | Page 7 of 128

Dimensions shown in millimeters.....................................128

Preliminary Technical Data

ADUC7032SPECIFICATIONS

ADuC7032

ELECTRICAL SPECIFICATIONS

(VDD =3.5V to18V, V

= 1.2 V Internal Reference, f

REF

Table 1 : ADUC7032—SPECIFICATIONS

= 10.24MHz driven from external 32.768kHz watch crystal or on-chip

CORE

precision oscillator, All specifications TA = -40°C to 105C, unless otherwise noted.)

Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPECIFICATIONS

1

Conversion Rate

Chop Off, ADC Normal Operating Mode
Chop On, ADC Normal Operating Mode
Chop On, ADC Low Power Mode

4 8000
4 2600
1 650

Hz
Hz
Hz

Current Channel

No Missing Codes 1
Integral Nonlinearity
Offset Error

Offset Error

2, 3, 4, 5

1, 3, 6

Chop On -2 ±0.5 +2

1, 2

Valid for all ADC Update Rates and ADC Modes

Chop Off, 1LSB = (36.6/Gain)µV

Offset Error Drift6 Chop off, Valid for ADC Gains of 4 – 64,

Normal Mode

Offset Error Drift6

Chop off. Valid for ADC Gains of 128 – 512,
Normal Mode

16
±10 ±60

Bits
PPM of FSR

-10 ±3 +10 LSB

µV

0.03 LSB/°C

30 nV/°C
Offset Error Drift6 Chop On 10 nV/°C
Total Gain Error
Total Gain Error
Total Gain Error

1, 3, 7, 8, 9

1, 3, 7, 9, 10

1, 3, 7, 9, 11

Normal Mode
Low Power Mode
Low Power-Plus Mode, using Precision Vref

-0.5 ±0.1 +0.5

-2 ±0.2 +2

-1 ±0.2 +1

%
%

%
Gain Drift 3 ppm/°C
PGA Gain Mismatch Error ±0.1 %
Output Noise

1, 12

4Hz Update Rate, Gain = 512, Chop Enabled 60 90 nV rms

10Hz Update Rate, Gain = 512, Chop Enabled 100 150 nV rms
1KHz Update Rate, Gain = 512 0.6 0.9 µV rms
1KHz Update Rate, Gain = 32 0.8 1.2 µV rms
1KHz Update Rate, Gain = 4 2.0 2.8 µV rms
8KHz Update Rate, Gain = 32 2.5 3.5 µV rms
8KHz Update Rate, Gain = 4 14 21 µV rms
ADC Low Power Mode, F
ADC Low Power Mode, F
ADC Low Power-Plus Mode,F

= 10Hz, Gain=128 1.25 1.9 µV rms

ADC

= 1Hz, Gain=128 0.35 0.5 µV rms

ADC

=1Hz,Gain=512 0.1 0.15 µV rms

ADC

Voltage Channel 13

No Missing Codes 1 Valid at all ADC Update Rates 16 Bits
Integral Nonlinearity
Offset Error
Offset Error

3, 5

1, 3

1

±10 ±60 ppm of FSR

Chop Off , 1 LSB16=439.5uV -10 ±1 +10 LSB

Chop On 0.3 1 LSB
Offset Error Drift Chop Off 0.03 LSB/°C
Total Gain Error
Total Gain Error
Gain Drift
Output Noise

1,3, 7, 14

Includes Resistor Mismatch -0.25 ±0.06 +0.25 %

1,3, 7, 14

Temperature Range = -25°C to 65°C -0.15 ±0.03 +0.15 %

Includes Resistor Mismatch Drift 3 ppm/°C

1, 15

4Hz Update Rate 60 90 µV rms
10Hz Update Rate 60 90 µV rms
1KHz Update Rate 180 270 µV rms
8KHz Update Rate 1600 2400 µV rms

Rev. PrD | Page 8 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

Temperature Channel

No Missing Codes 1 Valid at all ADC Update Rates 16 Bits
Integral Nonlinearity
Offset Error
Offset Error

3, 5,16, 17

1, 3

Offset Error Drift
Total Gain Error
Gain Drift
Output Noise

ADC SPECIFICATIONS

ANALOG INPUT

Current Channel

Absolute Input Voltage Range Applies to both IIN+ and IIN-

Input Voltage Range
Gain =222 ±600 mV
Gain =422 ±300 mV
Gain =8 ±150 mV
Gain = 16 ±75 mV
Gain = 32 ±37.5 mV
Gain = 64 ±18.75 mV
Gain = 128 ±9.375 mV
Gain = 256 ±4.68 mV
Gain = 512 ±2.3 mV

Input Leakage Current

Input Offset Current

Voltage Channel

Absolute Input Voltage Range 4 18 V

Input Voltage Range 0 to 28.8 V

VBAT Input Current VBAT = 18V 4 5.5 7 µA

Temperature Channel

Absolute Input Voltage Range 100 1300 mV

Input Voltage Range 0 to VREF V

VTEMP Input Current1 2.5 100 nA

VOLTAGE REFERENCE

ADC Precision Reference

Internal V

Power Up Time1 0.5 Ms
Initial Accuracy1 Measured at TA = 35°C -0.15 0.15 %
Internal V

Coefficient

Long term stability25 100 ppm/1000h
External Reference Input

Range

V

26

Divide by 2 Initial Error

REF

ADC Low Power Reference

Internal V
Initial Accuracy
Initial Accuracy10 Using ADCREF, measured at TA = 35°C 0.1 %
Temperature Coefficient

1

±10 ±60 ppm of FSR

Chop Off , 1 LSB16=19.84uV -10 ±3 +10 LSB

Chop On -5 1 5 LSB

1,3, 18, 19, 17

-0.2 ±0.06 +0.2 %

0.03 LSB/°C

3 ppm/°C

1

20,21

1

1, 23

0.5 1.5 nA

1KHz Update Rate 7.5 11.25 µV rms

Internal V

REF

=1.2V

Gain =122 ±1.2

-200 +300

mV

-3 3 nA

REF

Temperature

REF

1, 24

REF

1.2 V

-20 ±5 +20

0.1 1.3

1

0.1 0.3 %

ppm/°C

V

1.2 V
Measured at TA = 35°C -5 5 %

1, 24

-300 ±150 +300 ppm/°C

Rev. PrD | Page 9 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit
RESISTIVE ATTENUATOR

Divider Ratio 24
Resistor Mismatch Drift

ADC Ground Switch

Resistance Direct path to ground 10

Input Current

TEMPERATURE SENSOR27

Accuracy MCU in power down or standby mode ±3 °C

POWER-ON RESET (POR)

POR Trip Level Refers to Voltage at VDD pin 2.85 3.0 3.15 V
POR Hysteresis 300 mV

RESET Time-Out from POR

LOW VOLTAGE FLAG (LVF)

LVF Level

POWER SUPPLY MONITOR (PSM)

PSM Trip Level

WATCHDOG TIMER (WDT)

Timeout Period

1

Timeout Step Size

FLASH/EE MEMORY

1

Endurance28 32.768Khz Clock, 256 pre-scale 10,000 Cycles

Data Retention29 TJ = 85°C 20 Years

DIGITAL INPUTS

Input Leakage Current Input (High) = REG_DVDD ±1 ±10 µA
Input Pull-up Current
Input Capacitance

Input Leakage Current NTRST Only :Input (Low) = 0V ±1 ±10 µA
Input Pull-down Current

3 ppm/°C

Ω

20kΩ Resistor selected

10 20 30

kΩ

6 mA

MCU in power down or standby mode
Temperature Range = -25°C to 65°C

±2 °C

20 msec

Refers to Voltage at VDD pin 1.9 2.1 2.3 V

Refers to Voltage at VDD pin 6.0 V

32.768Khz Clock, 256 pre-scale 0.008 512 sec

7.8 msec

All digital inputs except NTRST

Input (Low) = 0V 10 20 80 µA
10 pF

NTRST Only : Input (High) = REG_DVDD 30 55 100 µA

Rev. PrD | Page 10 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS

VINL, Input Low Voltage 0.4 V
VINH, Input High Voltage

CRYSTAL OSCILLATOR

Logic Inputs, XTAL1 Only

VINL, Input Low Voltage 0.8 V
VINH, Input High Voltage 1.7 V
XTAL1 Capacitance 12 pF
XTAL2 Capacitance

ON-CHIP OSCILLATORS

Low Power Oscillator 131.072 kHz
Accuracy30 Includes drift data from 1000hr life-test -6 3

Precision Oscillator 131.072 kHz

Accuracy Includes drift data from 1000hr life-test -1.2 1.2 %

1

All Logic inputs

2.0 V

1

12 pF

%

MCU CLOCK RATE

8 programmable core clock selections within

0.160 10.24 20.48

MHz

this range (binary divisions 1,2,4,8…..64, 128)

MCU START-UP TIME

at Power-On Includes kernel power-on execution time 25

after Reset Event Includes kernel power-on execution time 5

From MCU Power-Down

Oscillator Running

Wakeup from Interrupt

Wakeup from LIN

Crystal Powered Down

Wakeup from Interrupt

2

2

500

msec

msec

msec

msec

msec

Internal PLL Lock Time 1 msec

LIN I/O General

Baud Rate 1000 20000 Bits/sec

VDD Supply Voltage Range for which the LIN

interface is functional

7 18

V

Input capacitance 5.5 pF

LIN comparator response

Error! Bookmark not defined.

time

I

LIN DOM MAX

I

LIN_PAS_REC

I

LIN_PAS_DOM1

Current Limit for driver when LIN Bus is in

Driver Off ; 7.0V < V

Using 22Ohm resistor 38 90 µs

dominant state. V

Input Leakage V

= V

BAT

< 18V ; VDD = V

BUS

= 0V -1 mA

LIN

BAT (MAX)

-0.7V 20 µA

LIN

40 200

mA

Rev. PrD | Page 11 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

I

LIN_NO_GND

V

V

V

V

V

V

V

V

VLIN_RECESSIVE

V

GND-Shift

R

V

LIN I/O General Contd.

Transmit Propagation Delay 1

31

Control Unit disconnected from ground

GND = V

LIN_DOM1

LIN_REC1

1

LIN Receiver Centre Voltage, VDD > 7.0V 0.475VDD 0.5 V

LIN_CNT

1

LIN Receiver Hysteresis Voltage 0.175VDD V

HYS

LIN_DOM_DRV_LOSUP1

LIN_DOM_DRV_HISUP

LIN_DOM_DRV_LOSUP1

LIN_DOM_DRV_HISUP

1

-Shift31 0 0.1V

BAT

31

LIN Receiver Dominant State, VDD > 7.0V 0.4VDD V

LIN Receiver Recessive State, VDD > 7.0V 0.6VDD V

LIN Dominant Output Voltage. VDD 7V, RL 500Ω

LIN Dominant Output Voltage. V

LIN Dominant Output Voltage. VDD 7V, RL 1000Ω

LIN Dominant Output Voltage. V

LIN Recessive Output Voltage 0.8 VDD V

DD

; 0V V

<18V ; V

LIN

= 12V

BAT

18V,RL 500Ω

DD

18V,RL 1000Ω

DD

-1 1

DD

0.525VDD V

1.2 V

2 V

0.6 V

0.8 V

DD

0 0.1VDD V

Slave Termination Resistance 20 30 47

slave

31

Serial Diode

Voltage Drop at the serial diode D

Ser_Int

0.4 0.7 1 V

VDD

= 7V

MIN

Bus Load Conditions ( C

BUS

|| R

BUS

):

4

mA

V

KΩ

µs

Symmetry of Transmit

1

Propagation Delay

Receive Propagation Delay

Symmetry of Receive

Propagation Delay

1

LIN V1.3 Specification

dV

1

dt

dV

1

dt

t

SYM

t

SYM1

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

VDD

= 7V

MIN

1

VDD

MIN

= 7V

VDD

= 7V

MIN

Bus Load Conditions ( C

BUS

|| R

BUS

) :

-2 2

6

-2 2

µs

µs

µs

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

Slew Rate
Dominant and recessive Edges V

BAT

= 18V

Slew Rate
Dominant and recessive Edges V

BAT

= 7V

Symmetry of rising and falling edge V
Symmetry of rising and falling edge V

BAT

BAT

= 18V
= 7V

1 2 3

0.5 3 V/µs

-5 5

-4 4

V/µs

µs
µs

Rev. PrD | Page 12 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

LIN V2.0 Specification

|| R

Bus Load Conditions ( C

BUS

BUS

) :

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

D1 Duty Cycle 1

TH

REC(MAX)

TH

DOM(MAX)

V

= 7.0V…18V; t

SUP

D2

D1 = t
Duty Cycle 2
TH
TH

D2 = t

BUS_REC(MIN)

REC(MIN)

DOM(MIN)

V

= 7.0V…18V; t

SUP

BUS_REC(MAX)

= 0.744 * V

= 0.581 * V

/ (2 * t

= 0..284 * V

= 0.422 * V

/ (2 * t

BAT

BAT

= 50µs

BIT

BIT

BAT

BAT

= 50µs

BIT

BIT

)

0.396

)

0.581

Wake

R

= 1kOhm, C

L

= 91nF, R

BUS

= 39Ohms

LIMIT

VDD1

32

V

OH

32

V

OL

Supply Voltage Range for which the Wake Pin is
functional

Output High Level 5 V

Output Low Level 2 V

7 18

V

VIH Input High Level 4.6 V

VIL

Monoflop Timeout

Package Thermal Specifications

Input Low Level 1.2 V
Timeout Period

1.3 sec

Thermal Shutdown

Thermal Impedance (θja)34

33

140 150 160 °C

48 LQFP, Stacked Die

Top Die 50 °C/W

Bottom Die 25

°C/W

POWER REQUIREMENTS

Power Supply Voltages

VDD (Battery Supply) 3.5 18 V

REG_DV

REG_AV

DD,

35

DD

2.5 2.6 2.7 V

Power Consumption

IDD – MCU Normal Mode36 MCU Clock Rate = 10.24MHz, ADC Off 10 20 mA

IDD – MCU Normal Mode36 MCU Clock Rate = 20.48MHz, ADC Off 20 mA

IDD – MCU Powered Down1

IDD–MCU Powered Down1

ADC Low Power Mode, measured over an
ambient temperature range of -10°C to +40°C

(Continuous ADC Conversion )

ADC Low Power Mode, measured over an
ambient temperature range of -40°C to +85°C

(Continuous ADC Conversion )

300 400

300 500

µA

µA

Rev. PrD | Page 13 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

IDD – MCU Powered Down

IDD – MCU Powered Down

IDD – MCU Powered Down1

IDD – Current ADC
I

– Voltage/Temperature ADC

DD

I

– Precision Oscillator

DD

1

These numbers are not production tested but are guaranteed by design and/or characterization data at production release

2

Valid for Current ADC Gain setting of PGA=4 to 64

3

These numbers include temperature drift

4

Tested at Gain Range=4, Self-Offset Calibration will remove this error.

5

Measured with an internal short after an initial offset calibration.

6

Measured with an internal short

7

These numbers include internal reference temperature drift.

8

Factory Calibrated at Gain = 1.

9

System calibration at specific gain range will remove the error at this gain range

10

When used in conjunction with ADCREF, the Low Power Mode Reference error MMR.

11

Using ADC Normal Mode Voltage Reference

12

Typical Noise in Low Power modes is measured with Chop enabled.

13

Voltage Channel Specifications include resistive attenuator input stage

14

System Calibration will remove this error

15

rms noise is referred to Voltage attenuator input, for example at F
input referred noise figures

16

ADC Self Offset calibration will remove this error.

17

Valid after an initial Self Calibration

18

Factory calibrated for the internal temperature sensor during final production test.

19

System Calibration will remove this error

20

In ADC Low Power Mode the input range is fixed at ±9.375mV. In ADC Low Power Plus Mode the input range is fixed at ±2.34375mV.

21

It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the Gain Calibration register or using system calibration. This approach
can also be used to reduce the ADC Input Range (LSB Size).

22

Limited by minimum absolute input voltage range.

23

Valid for a differential input less than 10mV

24

Measured using Box Method

25

The long-term stability specification is non cumulative. The drift in subsequent 1,000 hour periods is significantly lower than in the first 1,000 hour period.

26

References of up to REG_AVDD can be accommodated by enabling an internal Divide-by-2

27

Die Temperature.

28

Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +125°C. Typical endurance at 25°C is 170,000 cycles.

29

Retention lifetime equivalent at junction temperature (Tj) = 85°C as per JEDEC Std. 22 method A117. Retention lifetime will de-rate with junction temperature.

30

Low Power oscillator can be calibrated against either the precision oscillator or the external 32.768kHz crystal in user code

31

These numbers are not production tested, but are supported by LIN Compliance testing.

32

Specified after Rlimit of 39Ohms

33

The MCU core is not shutdown but an interrupt is generated, if enabled.

34

Thermal Impedance can be used to calculate the thermal gradient from ambient to die temperature.

35

Internal Regulated Supply available at REG_DVDD (I

36

Typical, additional supply current consumed during Flash memory program and erase cycles is 7mA and 5mA respectively.

1

ADC Low Power-Plus Mode, measured over an
ambient temperature range of -10°C to +40°C

(Continuous ADC Conversion )

Average Current, Measured with Wake and
Watchdog Timer clocked from Low Power
Oscillator

Average Current, Measured with Wake and
Watchdog Timer clocked from Low Power
Oscillator over an ambient temperature range of

-10°C to +40°C

Per ADC

520 700

120 300

120 175

1.7

0.5
400

µA

µA

µA

mA
mA
µA

=1KHz, typical rms noise at the ADC input is 7.5uV, scaled by the attenuator (24) yields these

ADC

=5mA), and REG_AVDD (I

SOURCE

SOURCE

=1mA)

Rev. PrD | Page 14 of 128

Preliminary Technical Data ADuC7032

TIMING SPECIFICATIONS

SPI Timing Specifications

Table 2 : SPI Master Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit
tSL SCLOCK low pulsewidth (SPIDIV + 1) × t
tSH SCLOCK high pulsewidth (SPIDIV + 1) × t
t

Data output valid after SCLOCK edge ns

DAV

t

Data input setup time before SCLOCK edge ns

DSU

t

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns
tDR Data output rise time ns
tSR SCLOCK rise time ns
tSF SCLOCK fall time ns

ns

HCLK

ns

HCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MOSI

MISO

t

DAV

t

SH

t

DSUtDHD

t

SL

t

DF

MSB IN BITS 6 – 1 L SB IN

t

DR

Figure 2. SPI Master Mode Timing (PHASE Mode = 1)

t

SR

t

SF

LSBBITS 6 – 1MSB

05994-002

Rev. PrD | Page 15 of 128

Preliminary Technical Data ADuC7032

Table 3 : SPI Master Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit
tSL SCLOCK low pulsewidth (SPIDIV + 1) × t
tSH SCLOCK high pulsewidth (SPIDIV + 1) × t
t

Data output valid after SCLOCK edge ns

DAV

t

Data output setup before SCLOCK edge ns

DOSU

t

Data input setup time before SCLOCK edge ns

DSU

t

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns
tDR Data output rise time ns
tSR SCLOCK rise time ns
tSF SCLOCK fall time ns

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

t

DOSU

t

SH

t

t

SL

t

DAV

DF

t

DR

t

SR

t

SF

ns

HCLK

ns

HCLK

MOSI

MISO

MSB IN BITS 6 – 1 LSB IN

t

DSUtDHD

Figure 3. SPI Master Mode Timing (PHASE Mode = 0)

LSBBITS 6 – 1MSB

5994-003

Rev. PrD | Page 16 of 128

Preliminary Technical Data ADuC7032

Table 4 : SPI Slave Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit
tCS CS to SCLOCK edge ns
tSL SCLOCK low pulsewidth (SPIDIV + 1) × t
tSH SCLOCK high pulsewidth (SPIDIV + 1) × t
t

Data output valid after SCLOCK edge ns

DAV

t

Data input setup time before SCLOCK edge ns

DSU

t

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns
tDR Data output rise time ns
tSR SCLOCK rise time ns
tSF SCLOCK fall time ns
t

CS high after SCLOCK edge ns

SFS

CS

ns

HCLK

ns

HCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MISO

MOSI

t

CS

t

SH

t

DAV

t

DSUtDHD

t

SL

t

DF

MSB IN BITS 6 – 1 LSB IN

t

DR

t

SR

t

SFS

t

SF

LSBBIT S 6 – 1MSB

05994-004

Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)

Rev. PrD | Page 17 of 128

Preliminary Technical Data ADuC7032

Table 5 : SPI Slave Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit

tCS CS to SCLOCK edge ns
tSL SCLOCK low pulsewidth (SPIDIV + 1) × t
tSH SCLOCK high pulsewidth (SPIDIV + 1) × t
t

Data output valid after SCLOCK edge ns

DAV

t

Data input setup time before SCLOCK edge ns

DSU

t

Data input hold time after SCLOCK edge ns

DHD

ns

HCLK

ns

HCLK

tDF Data output fall time ns
tDR Data output rise time ns
tSR SCLOCK rise time ns
tSF SCLOCK fall time ns
t

Data output valid after CS edge ns

DOCS

t

CS high after SCLOCK edge ns

SFS

CS

t

SFS

t

SF

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

t

DOCS

t

CS

t

SH

t

DF

t

DAV

t

SL

t

DR

t

SR

MISO

MOSI

MSB IN BITS 6 – 1 LSB IN

t

DSUtDHD

Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)

LSBBITS 6 – 1MSB

05994-005

Rev. PrD | Page 18 of 128

Preliminary Technical Data ADuC7032

LIN Timing Specifications

Figure 6 : LIN V1.3 Timing Specification

Rev. PrD | Page 19 of 128

Preliminary Technical Data ADuC7032

TRANSMIT

INPUT TO

TRANSMITTING

NODE

RECESSIVE

DOMINANT

t

BIT

t

BIT

t

BIT

V

(TRANSCEIVER SUPPLY

OF TRANSMITTING NODE)

SUP

RxD

(OUTPUT O F RECEIVING NO DE 1)

RxD

(OUTPUT O F RECEIVING NO DE 2)

TH

REC (MAX)

TH

DOM (MAX)

TH

REC (MIN)

TH

DOM (MI N)

t

LIN_DOM (M AX)

t

LIN_DO M (MIN)

t

RX_PDF

t

LIN_REC ( MIN)

t

LIN_REC ( MAX)

t

RX_PDR

Figure 7 : LIN V2.0 Timing Specification

t

RX_PDR

t

RX_PDF

THRESHOLDS OF
RECEIVING NO DE 1

THRESHOLDS OF
RECEIVING NO DE 2

LIN

BUS

05994-005

Rev. PrD | Page 20 of 128

Preliminary Technical Data ADuC7032

SPECIFICATION TERMINOLOGY

CONVERSION RATE:

The conversion rate specifies the rate at which an output result
is available from the ADC, once the ADC has settled.

The sigma-delta conversion techniques used on this part mean
that while the ADC front-end signal is over-sampled at a
relatively high sample rate, a subsequent digital filter is
employed to decimate the output to give a valid 16-Bit data
conversion result at output rates from 1Hz to 8 KHz.

It should also be noted that when software switches from one
input to another (on the same ADC), the digital filter must first
be cleared and then allowed to average a new result. Depending
on the configuration of the ADC and the type of filter this can
take multiple conversion cycles.

INTEGRAL NON_LINEARITY (INL):

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition and full scale, a point 0.5
LSB above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.

NO MISSING CODES:

This is a measure of the Differential Non-Linearity of the ADC.
The error is expressed in bits and specifies the number of codes
(ADC results) as 2^N Bits, where is N = No Missing Codes,
guaranteed to occur through the full ADC input range.

Acronyms used in this Datasheet:

ADC Analog to Digital Converter
ARM Advanced RISC Machine
JTAG Joint Test Action Group
LIN Local Interconnect Network
LSB Least Significant Byte/Bit
LVF Low Voltage Flag
MCU MicroController
MMR Memory Mapped Register
MSB Most Significant Byte/Bit
PID Protected Identifier
POR Power On Reset
PSM Power Supply Monitor
RMS Root Mean Square

OFFSET ERROR:

This is the deviation of the first code transition ADC input
voltage from the ideal first code transition.

OFFSET ERROR DRIFT:

Offset Error Drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSBs per °C.

GAIN ERROR

This is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span
between any two points in the transfer function.

OUTPUT NOISE:

The output noise is specified as the standard deviation (or 1 X
Sigma) of ADC output codes distribution collected when the
ADC input voltage is at a dc voltage. It is expressed as µ rms.
The output or RMS noise can be used to calculate the Effective
Resolution of the ADC as defined by the following equation

Effective Resolution= Log 2 (Full-Scale Range / RMS Noise) Bits

The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 X Sigma of the distribution of ADC output codes
collected when the ADC input voltage is at dc. The peak-to­peak noise is therefore calculated as 6.6 times the RMS noise.

The peak-to-peak noise can be used to calculate the ADC
(Noise Free, Code) Resolution for which there will be no code
flicker within a 6.6-Sigma limit as defined by the following
equation

Noise Free Code Resolution = Log
Peak Noise) Bits

(Full-Scale Range / Peak to

2

Rev. PrD | Page 21 of 128

Preliminary Technical Data ADuC7032

ABSOLUTE MAXIMUM RATINGS

Table 6. Absolute Maximum Ratings (TA = -40°C to 105°C unless otherwise noted)

Parameter Rating

AGND to DGND to VSS to IO_VSS -0.3V to +0.3V
VBAT to AGND -22V to 40V
VDD to VSS

to VSS for 1 second

V

DD

-0.3V to 33V

-0.3V to 40V
LIN to IO_VSS -16V to 40V
WU to IO_VSS
Wake Continuous Current
HV IO Pins Short Circuit Current

-3V to 33V

50mA

100mA
Digital I/O Voltage to DGND -0.3V to REG_DVDD +0.3
VREF to AGND -0.3V to REG_AV

DD

+ 0.3
ADC Inputs to AGND -0.3V to REG_AVDD +0.3
ESD (HBM) Rating
LIN, WU and VBAT

± 4KV
All other pins ± 2KV
Storage Temperature Range 125°C
Junction Temperature (transient) 150°C
Junction Temperature (continuous) 130°C
Lead Temperature, Soldering

Reflow (15 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

Figure 8 : Package Pin Configuration

3740 39 384142434445464748

36

35

34

33

32

31

30

29

28

27

26

25

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ESD Caution

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrD | Page 22 of 128

Preliminary Technical Data ADuC7032

PIN FUNCTION DESCRIPTIONS

Table 7: Pin Function Descriptions

Pin# Mnemonic Type* Function

Reset Input Pin, Active Low. This pin has an internal, weak pull-up resistor to

RESET

1

2 GPIO_5/IRQ1/RxD I/O

3 GPIO_6/TxD I/O

4 GPIO_7/IRQ4 I/O

5 GPIO_8/ IRQ5 I/O

6 TCK I

7 TDI I

8 DGND S Ground Reference for On-Chip Digital Circuits

9 NC

10 TDO O

11 NTRST I

12 TMS I

REG_DVDD. If this pin is not being used it can be left not connected. For

I

added security and robustness, it is recommended that this pin be strapped
via a resistor to REG_DVDD.

General Purpose Digital I/O 5 is a Multi-Function Pin. By default and after
Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 3 states, namely:

General Purpose Digital I/O 5
External Interrupt Request 1, Active High
Receive Data for UART Serial Port
This Pin may also be used as a clock input to Timer1.
General Purpose Digital I/O 6 is a Multi-Function Pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 6
Transmit Data for UART Serial Port
General Purpose Digital I/O 7 is a multi-function pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 7
External Interrupt Request 4, Active High
General Purpose Digital I/O 8 is a multi-function pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 8
External Interrupt Request 5, Active High
This Pin may also be used as a clock input to Timer1.
JTAG Test Clock. This clock input pin is one of the standard 5 pin JTAG debug

port on the part. TCK is an input pin only and has an internal weak pull-up
resistor. If not being used this pin can be left unconnected

JTAG Test Data Input. This data input pin is one of the standard 5 pin JTAG
debug port on the part. TDI is an input pin only and has an internal weak pull­up resistor. If not being used this pin can be left unconnected

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

JTAG Test Data Output. This data output pin is one of the standard 5 pin JTAG
debug port on the part. TDO is an output pin only. On power-on this output is
disabled and pulled high via an internal weak pull-up resistor. If not being
used this pin can be left unconnected

JTAG Test Reset. This Reset input pin is one of the standard 5 pin JTAG debug
port on the part. NTRST is an input pin only and has an internal weak pull­down resistor. If not being used this pin can be left unconnected. NTRST is
also monitored by the on-chip kernel to enable LIN boot-load mode.

JTAG Test Mode Select. This Mode Select input pin is one of the standard 5
pin JTAG debug port on the part. TMS is an input pin only and has an internal
weak pull-up resistor. If not being used this pin can be left unconnected

Rev. PrD | Page 23 of 128

Preliminary Technical Data ADuC7032

Pin# Mnemonic Type* Function

13 VBAT I Battery Voltage Input to resistor divider

14 VREF I

15 GND_SW S

16 NC

17 NC

18 VTEMP
19 IIN+ I Positive Differential Input for Current Channel
20 IIN- I Negative Differential Input for Current Channel
21 AGND S Ground Reference for On-Chip Precision Analog Circuits
22 AGND S Ground Reference for On-Chip Precision Analog Circuits

23 NC

24 REG_AVDD S Nominal 2.6V output from on chip regulator

25 NC

26 NC

27

28 GPIO_1/SCLK I/O

29 GPIO_2/MIS0 I/O

30 GPIO_3/MOSI I/O

31 GPIO_4/ECLK I/O

32 NC

GPIO_0/IRQ0/SS

External Reference Input Terminal. If this input is not being used it should be
connected directly to the AGND system ground

Switch to internal analog ground reference.
Negative input for external temperature channel and external reference
If this input is not being used it should be connected directly to the AGND

system ground.
No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally
No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally

I External Pin for NTC/PTC temperature measurement

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

General Purpose Digital I/O 0 is a Multi-Function Pin. By default and after
Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 3 states, namely:

I/O

General Purpose Digital I/O 0
External Interrupt Request 0, Active High
SPI Interface, Slave Select Input
General Purpose Digital I/O 1 is a Multi-Function Pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 1
SPI Interface, Serial Clock Input
General Purpose Digital I/O 2 is a Multi-Function Pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 2
SPI Interface, Master Input/Slave Output Pin
General Purpose Digital I/O 3 is a Multi-Function Pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal
weak pull-up resistor and if not being used it can be left unconnected. This
multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 3
SPI Interface, Master Output/Slave Input Pin
General Purpose Digital I/O 4 is a programmable digital I/O pin. By default and

after Power-On-Reset, this pin is configured as an input. The pin has an
internal weak pull-up resistor and if not being used this pin can be left
unconnected.

GPIO4 is can also be configured to output a 2.56MHz clock
No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally

Rev. PrD | Page 24 of 128

Preliminary Technical Data ADuC7032

Pin# Mnemonic Type* Function

33 REG_DVDD S Nominal 2.6V output from the on-chip regulator
34 DGND S Ground Reference for On-Chip Digital Circuits
35 DGND S Ground Reference for On-Chip Digital Circuits

36 XTAL1 O

37 XTAL2 I

38 NC

39 NC

40 NC

41 WU O

42 VDD S Battery Power Supply to on-chip regulator

43 NC

44 VSS S Ground Reference for the internal Voltage Regulators

45 NC

46 Reserved

47 IO_VSS S Ground Reference for High Voltage I/O Pins
48 LIN I/O LIN Serial Interface Input/Output Pin

*

I = Input, O = Output, S = Supply

No Connect ( NC ) pins may be grounded if required.

Crystal Oscillator Output. If an external Crystal is not being used, this pin can
be left unconnected.

Crystal Oscillator Input. If an external Crystal is not being used, this pin should
be connected to the DGND system ground.

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

High Voltage Wake-Up Transmit pin. If this pin is not being used, it should not
be connected externally.

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

No Connect, this pin is not connected internally but is reserved for possible
future use, this pin should therefore not be connected externally

This pin is reserved for HV-IO Output only functionality. This pin should
connected externally to the IO_VSS ground reference

Rev. PrD | Page 25 of 128

Preliminary Technical Data ADuC7032

ADUC7032 GENERAL DESCRIPTION

The ADuC7032 is a complete, system solution for battery
monitoring in 12V automotive applications. The device
integrates all of the required features to precisely and
intelligently monitor, process and diagnose 12V battery
parameters including battery current, voltage and temperature
over a wide range of operating conditions.

Minimizing external system components, the device is powered
directly from the 12V battery. An on-chip LDO, Low Drop­Out, regulator generates the supply voltage for the three
integrated 16-Bit Σ−∆ ADCs. The ADCs precisely measure
battery current, voltage and temperature, which may be used to
characterize the car battery’s state of health and charge.

A Flash/EE memory based ARM7 microcontroller (MCU) is
also integrated on-chip and is used both to pre-process the
acquired battery variables, and to manage communications
from the ADuC7032 to the main Electronic Control Unit
(ECU) via a Local Interconnect Network (LIN) interface, which
is integrated on-chip.

Both the MCU and the ADC sub-system can be individually
configured to operate in normal or flexible power-saving
modes of operation.

In its normal operating mode the MCU is clocked indirectly
from an on-chip oscillator via the Phase Locked Loop (PLL) at
a maximum clock rate of 20.48MHz.
In its power-saving operating modes, the MCU can be totally
powered down, waking up only in response to an ADC
conversion result ready, digital comparators, the wake-up
timer, a POR or an external serial communication event.

The ADC can be configured to operate in a normal (full power)
mode of operation, interrupting the MCU after various sample
conversion events. The Current Channel features two low
power modes, Low Power and Low Power-Plus, generating
conversion results to a lower performance specification.

On-chip factory firmware supports in-circuit Flash/EE
reprogramming via the LIN or JTAG serial interface ports while
non-intrusive emulation is also supported via the JTAG
interface. These features are incorporated into a low-cost
QuickStart Development System supporting the ADuC7032.

The ADuC7032 operates directly from the 12V battery supply
and is fully specified over a temperature range of -40°C to
105°C. The ADuC7032 is functional, with degraded
performance, at temperatures from 105°C to 125°C.

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC), developed by ARM Ltd. The ARM7TDMI is a Von
Neumann based architecture, which means that it uses a single
32-bit bus for instruction and data. The length of the data can
be 8, 16 or 32 bits and the length of the instruction word is
either 16 bits or 32 bits, depending on which mode the core is
operating in.

The ARM7TDMI is an ARM7 core with 4 additional features:

- T support for the Thumb (16 bit) instruction set.

- D support for debug

- M enhanced multiplier

- I includes the EmbeddedICE module to support

embedded system debugging.

Thumb mode (T)

An ARM instruction is 32-bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16-bits, the Thumb instruction set. Faster code
execution from 16-bit memory and greater code density can be
achieved by using the Thumb instruction set, which makes the
ARM7TDMI core particularly suited for embedded
applications.

However the Thumb mode has three limitations:

- Relative to ARM, Thumb code usually requires more
instructions to perform that same task. Therefore, ARM code
is best for maximizing the performance of time-critical code.
In most applications.

- The Thumb instruction set does not include some
instructions which are needed for exception handling, so
ARM code may be required for exception handling.

- When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at this
address. The first command is required to be in ARM code.

Multiplier (M)

The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions which perform 32-bit by
32-bit multiplication with 64-bit result and 32-bit by 32-bit
multiplication-accumulation (MAC) with 64-bit result.

Rev. PrD | Page 26 of 128

Preliminary Technical Data ADuC7032

EmbeddedICE (I)

ARM Registers

The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers which allow
non intrusive user code debugging. These registers are
controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be interrogated, as well as the Flash/EE,
the SRAM and the Memory Mapped Registers.

ARM7 Exceptions

The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are:

- Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events

- Fast interrupt or FIQ. It is provided to service data transfer or
communication channel with low latency. FIQ has priority
over IRQ

- Memory abort (Prefetch and Data)

- Attempted execution of an undefined instruction

- Software interrupt (SWI) instruction which can be used to

make a call to an operating system.

Typically the programmer will define interrupts as IRQ but for
higher priority interrupts, the programmer can define
interrupts as of type FIQ.

The priority of the above exceptions and vector address are as
follows:

1. Hardware Reset 0x00

2. Memory Abort ( Data ) 0x10

3. FIQ 0x1C

4. IRQ 0x18

5. Memory Abort ( Prefetch ) 0x0C

6. Software Interrupt and 0x08
Undefined Instruction 0x04

A Software interrupt and an Undefined Instruction

Note:

exception have the same priority and are mutually exclusive.

NOTE:

The above list are located from 0x00 -0x1C, with a
reserved location at 0x14. This location is required to be written
with either 0x27011970 or the checksum of Page Zero,
excluding location 0x14. If this is not done, user code will not
be executed and LIN download mode will be entered. For more
information please refer to the ADuC7032 LIN download
Te ch n o te .

The ARM7TDMI has 16 standard registers. R0-R12 are used for
data manipulation, R13 is the stack pointer, R14 is the link
register and R15 is the program counter which indicates the
instruction currently being executed. The link register contains
the address from which the user has branched, if the branch and
link command was used, or the command during which an
exception occurred.

The stack pointer contains the current location of the stack. As
a general rule of thumb on an ARM7TDMI, the stack starts at
the top of the available RAM area, and descends, using the area
as required. A separate stack is defined for each of the
exceptions. The size of each stack is user configurable and is
dependent on the target application. On the ADuC7032 the
stack begins at 0x000417FC and descends.

Whilst programming using high level languages, such as C, it
may be possible to ensure that the stack does not overflow. This
is dependent on the compiler used.

When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented in
Figure 9. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of non-critical registers, the interrupt may be
processed without the need to save or restore these registers,
which reduces the response time of the interrupt handling
process.

More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents available from ARM Ltd.:

- DDI0029G, ARM7TDMI Technical Reference Manual.

- DDI0100E, ARM Architecture Reference Manual..

USABLE IN USE R MODE

SYSTEM MODES ONLY

R13_ABT

R14_ABT

ABORT

MODE

R13_IRQ

R14_IRQ

SPSR_IRQ

IRQ

MODE

R13_UND

R14_UND

SPSR_UND

UNDEFINED

MODE

05994-008

R15 (PC)

CPSR

USER MODE

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

SPSR_FIQ

Figure 9: ADuC7032 Register Organization

FIQ

MODE

R13_SVC

R14_SVC

SPSR_SVC

SVC

MODE

SPSR_ABT

Rev. PrD | Page 27 of 128

Preliminary Technical Data ADuC7032

Interrupt latency

The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 50 processor cycles, which
is just over 2.44µS in a system using a continuous 20.48MHz
processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time may be reduced to 42 cycles
if the LDM command is not used, some compilers have an
option to compile without using this command. Another option
is to run the part in THUMB mode where this is reduced to 22
cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.

st

Note that the ARM7TDMI will initially (1

instruction) run in
ARM (32-bit) mode when an exception occurs. The user may
immediately switch from ARM mode to Thumb mode if
required, e.g. when executing interrupt service routines.

MEMORY ORGANISATION

The ARM7, a Von Neumann architecture, MCU core sees

memory as a linear array of 232 byte locations. As shown in
Figure 11, the ADuC7032 maps this into 4 distinct user areas
namely, a re-mappable memory area, an SRAM area, a Flash/EE
area and a Memory Mapped Register (MMR) area.

The first 96kBytes of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. A
second 4kByte area at the top of the memory map is used to
locate the Memory Mapped Registers (MMR), through which
all on-chip peripherals are configured and monitored. The
remaining 2 areas of memory are constituted as 6kByte of
SRAM and 96kByte of On-Chip Flash/EE memory. 94kByte of
On-Chip Flash/EE memory are available to the user, and the
remaining 2kBytes are reserved for the on-chip Kernel. These
areas are described in more detail below.

Memory Format

The ADuC7032 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.

BIT 31

BYTE 3

.
.
.

B

7

3

BYTE 2

BYTE 1

.

.

.

.

.

.

A

9

6

5

2

1

32 BITS

Figure 10: Little Endian Format

BYTE 0

.
.
.

8

4

0

BIT 0

0xFFFFFFFFh

0x00000004h

0x00000000h

5994-009

RESERVED

FFFF 0000h

FFFF0FFFh

00097FFFh

00080000h

00417FFh

00040000h

0017FFFh

00000000h

Figure 11: ADuC7032 Memory Map

MMRs

RESERVED

FLASH/EE

RESERVED

SRAM

RESERVED

RE-MAPP ABLE MEMORY SPACE
(FLASH/EE OR SRAM)

5994-011

SRAM

6kBytes of SRAM are available to the user, organized as 1536 X
32 bits, i.e. 1536Words, which is located at 0x40000. The RAM
space can be used as data memory and also as a volatile
program space.

ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array.

SRAM is read/writeable in 8/16/32 bit segments.

Any access, either reading or writing, to an area not defined in
the memory map will result in a Data Abort exception.

Rev. PrD | Page 28 of 128

Preliminary Technical Data ADuC7032

code. This so called kernel is hidden and cannot be accessed by

Remap

The ARM exception vectors are all situated at the bottom of the
memory array, from address 0x00000000 to address
0x00000020.

By default, after a reset, the Flash/EE memory is logically
mapped to address 0x00000000.

It is possible to logically REMAP the SRAM to address
0x00000000. This is done by a setting bit zero of the SYSMAP0
MMR, which is located at 0xFFFF0220. To revert Flash/EE to
0x00000000, bit zero of SYSMAP0 is cleared.

It may be desirable to remap RAM to 0x00000000 to optimize
the interrupt latency of the ADuC7032, as code may be run in
full 32bit ARM mode and at the maximum core speed. It should
be noted that when an exception occurs, the core will default to
ARM mode.

Remap operation

When a reset occurs on the ADuC7032, execution starts
automatically in the factory programmed internal configuration

user code. If the ADuC7032 is in normal mode, it will execute
the power-on configuration routine of the kernel and then jump
to the reset vector address, 0x00000000, to execute the users
reset exception routine.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset routine must always be written in
Flash/EE.

Precaution must be taken to execute the REMAP command
from the absolute Flash/EE address, and not from the mirrored,
remapped segment of memory, as this will be replaced by the
SRAM. If a remap operation is executed whilst operating code
from the mirrored location, Prefetch/Data aborts may occur or
the user may observe abnormal program operation.

This operation is reversible: the Flash/EE memory may be
remapped at address 0x00000000 by clearing bit zero of the
SYSMAP0 MMR. Precaution must again be taken to execute the
remap function from outside the mirrored area.

Any kind of reset will logically remap the Flash/EE memory to
the bottom of the memory array.

SYSMAP0 Register :

Name : SYSMAP0
Address : 0xFFFF0220
Default Value : 0x00
Access : Read/Write Access

Function : This 8-bit register allows user code to remap either RAM or Flash/EE memory space into the bottom of the ARM

memory space starting at location 0x00000000.

Table 8: SYSMAP0 MMR Bit Designations

Bit Description

7-1 Reserved

These bits are reserved and should be written as 0 by user code

0

Remap Bit.

Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE memory to 0x00000000.

Rev. PrD | Page 29 of 128

Preliminary Technical Data ADuC7032

ADUC7032 RESET

There are four kinds of reset: external reset, Power-on-reset,
watchdog reset and software reset. The RSTSTA register
indicates the source of the last reset and can also be written by
user code to initiate a software reset event. The bits in this
register can be cleared to ‘0’ by writing to the RSTCLR MMR at

Table 9 : Device RESET Implications

0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The
implications of all four kinds of reset event are tabulated in
Table 9 b e low.

IMPACT

RESET

POR

Watchdog
Reset

Software Reset

External Reset
Pin

Note1: If LVF is enabled(HVCFG0[2]), RAM has not been corrupt by the POR reset mechanism if LVF Status bit HVSTA[6] is ‘1’.

Reset
External
Pins to
Default
State

    

     

     

     

Kernel
Executed

Reset All
External MMRs

(excluding
RSTSTA)

RSTCLR Register :

Name : RSTCLR
Address : 0xFFFF0234
Default Value : 0x00
Access : Write Only

Function : This 8-bit write only register clears the

corresponding bit in RSTSTA.

Reset All
HV
Indirect
Registers

Peripherals
Reset

RAM
Valid

Note 1 RSTSTA[0] =1

RSTSTA

(Status after
Reset Event)

RSTSTA[1] =1

RSTSTA[2] =1

RSTSTA[3] =1

RSTSTA Register :

Name : RSTSTA
Address : 0xFFFF0230
Default Value : 0x01
Access : Read/Write Access

Function : This 8-bit register indicates the source of

the last reset event and can also be written
by user code to initiate a software reset.

Table 10: RSTSTA/RSTCLR MMR Bit Designations

Bit Description

7-4 Not Used

These bits are not used and will always read as ‘0’

3

External Reset

Set to 1 automatically when an external reset occurs
Cleared by setting the corresponding bit in RSTCLR

2

Software Reset

Set to ‘1’ by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR

1

Watchdog timeout

Set to 1 automatically when a watchdog timeout occurs
Cleared by setting the corresponding bit in RSTCLR

0

Power-on-reset

Set automatically when a power-on-reset occurs
Cleared by setting the corresponding bit in RSTCLR

Rev. PrD | Page 30 of 128