Datasheet ADuC7032 Datasheet (ANALOG DEVICES)

MicroConverter

® Integrated,

Preliminary Technical Data

FEATURES

High Precision ADCs

Dual Channel, Simultaneous Sampling, 16-Bit Σ−∆ ADCs Third Independent ADC for Temperature Sensing Programmable ADC throughput from 1Hz to 8KHz On-Chip 5ppm/°C Voltage Reference Current Channel Fully differential, Buffered Input Programmable Gain 1 to 512 ADC Input Range -200mV to +300mV Digital Comparators, with Current Accumulator Feature Voltage Channel Buffered, On-Chip attenuator for 12V battery Inputs Temperature Channel External and On-Chip Temperature Sensor Options

Microcontroller

ARM7TDMI Core, 16/32-bit RISC architecture

20.48MHz PLL with Programmable Divider PLL Input Source: On-Chip Precision Oscillator

On-Chip Low-Power Oscillator

External (32.768KHz) Watch Crystal

JTAG Port supports code download and debug

FUNCTIONAL BLOCK DIAGRAM

Precision Battery Sensor

ADuC7032

Memory

96k Bytes Flash/EE Memory, 6k Bytes SRAM 10KCycles Flash Endurance, 20 Years Flash Retention In-Circuit Download via JTAG and LIN 64 x 16bit Result FIFO for Current and Voltage ADC

On-Chip Peripherals

LIN 1.2, 1.3 and 2.0 (Slave) Compatible Support via UART

with Hardware Synchronization

Flexible Wake-up I/O Pin, Master/Slave SPI Serial I/O 9-Pin GPIO Port, 2 X General Purpose Timers Wake-up and Watchdog Timers

Power Supply Monitor, On-Chip Power-On-Reset Power Operates directly from 12V Battery Supply Current Consumption Normal Mode 10mA at 10MHz Low Power Monitor Mode Package and Temperature Range

48 Pin LQFP 7X7 mm body package

Fully specified for –40°C to 105°C operation

APPLICATIONS Battery Sensing/Management for Automotive Systems

T S

PRECISION ANALOG ACQUISITION

IIN+

IIN-

VBAT

VTEMP

GND_SW

VREF

BUF

PGA

RESULT

ACCUMULATOR

BUF

MUX

TEMP

SENSOR

D D V

Σ−∆

DIGITAL

COMPARATOR

Σ−∆

PRECISION

REFERENCE

16-BIT

Figure 1: ADuC7032 Functional Block Diagram

Rev. Pr

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Preliminary Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

ADC

2.5V LDO PSM POR

ARM7 TDMI

MCU

20MHz

2xTIMERS

WDT

W/U TIMER

_ O

2 _

IO P G

96KB FLASH

128B ADC FIFO

LOW POWER

ON-CHIP PLL

_ O

MEMORY

6KB RAM

PRECISION

OSC

GPIO PORT UART PORT

SPI PORT

LIN

RESET

XTAL1

XTAL2

LIN

8 _

I P G

www.analog.com

Preliminary Technical Data ADuC7032

TABLE OF CONTENTS

TABLE OF CONTENTS................................................... 2

ADUC7032 DATASHEET TABLES.................................5

ADUC7032 DATASHEET FIGURES ..............................7

ADUC7032SPECIFICATIONS ........................................8

ELECTRICAL SPECIFICATIONS............................................ 8

TIMING SPECIFICATIONS ................................................. 15

SPI Timing Specifications...........................................15

LIN Timing Specifications.......................................... 19

SPECIFICATION TERMINOLOGY............................. 21

ABSOLUTE MAXIMUM RATINGS ............................22

ORDERING GUIDE ........................................................... 22

ESD Caution...............................................................22

PIN FUNCTION DESCRIPTIONS ...............................23

ADUC7032 GENERAL DESCRIPTION.......................26

OVERVIEW OF THE ARM7TDMI CORE ........................... 26

ARM7 Exceptions.......................................................27

ARM Registers............................................................ 27

Interrupt latency.........................................................28

MEMORY ORGANISATION ................................................28

Memory Format..........................................................28

SRAM..........................................................................28

Remap.........................................................................29

Remap operation........................................................ 29

SYSMAP0 Register :................................................... 29

ADUC7032 RESET .......................................................... 30

RSTCLR Register :..................................................... 30

RSTSTA Register :...................................................... 30

FLASH/EE MEMORY AND THE ADUC7032......................31

FLASH/EE MEMORY CONTROL INTERFACE...................... 31

FEE0CON and FEE1CON Registers : ....................... 32

FEE0ST A and FEE1STA Registers :...........................33

FEE0ADR and FEE1ADR Registers:.........................33

FEE0DAT and FEE1DAT Registers:..........................33

FEE0MOD and FEE1MOD Registers :.....................34

FLASH/EE MEMORY SECURITY ........................................34

Block0, Flash/EE Memory Protection Registers :......35

Block1, Flash/EE Memory Protection Registers :......35

FLASH/EE MEMORY RELIABILITY .................................. 36

CODE EXECUTION TIME FROM SRAM AND FLASH/EE 37

Execution from SRAM................................................ 37

Execution from Flash/EE ...........................................37

ADUC7032 KERNEL ....................................................... 38

MEMORY MAPPED REGISTERS ........................................ 40

16-BIT Σ−∆ ANALOG TO DIGITAL CONVERTERS.45

CURRENT CHANNEL ADC (I-ADC) ................................45

VOLTAGE CHANNEL ADC (V-ADC)................................46

TEMPERATURE CHANNEL ADC (T-ADC) ........................46

ADC GROUND SWITCH ...................................................47

ADC NOISE PERFORMANCE TABLES ...............................48

ADC MMR INTERFACE...................................................49

ADC Status Register :.................................................49

ADC Interrupt Mask Register :...................................50

ADC Mode Register : .................................................51

Current Channel ADC Control Register :...................52

Voltage Channel ADC Control Register :...................53

Temperature Channel ADC Control Register :...........54

ADC Filter Register : .................................................55

ADC Configuration Register :....................................57

Current Channel ADC Data Register :.......................58

Voltage Channel Data Register:.................................58

Temperature Channel ADC Data Register :...............58

ADC FIFO Register : .................................................58

Current Channel ADC Offset Calibration Register :..58

Voltage Channel Offset Calibration Register :...........58

Temperature Channel Offset Calibration Register:....58

Current Channel ADC Gain Calibration Register :...59

Voltage Channel Gain Calibration Register :.............59

Temperature Channel Gain Calibration Register :.....59

Current Channel ADC Result Counter Limit Register:

....................................................................................59

Current Channel ADC Result Count Register:...........59

Current Channel ADC Threshold Register:................59

Current Channel ADC Threshold Count Limit Register:

....................................................................................59

Current Channel ADC Threshold Count Register:.....60

Current Channel ADC Accumulator Register:...........60

Current Channel ADC Accumulator Threshold

Low Power Voltage Reference Scaling Factor............60

ADC POWER MODES OF OPERATION...............................60

ADC Startup Procedure..............................................60

ADC Normal Power Mode..........................................61

ADC Low Power Mode...............................................61

ADC Low Power-Plus Mode.......................................61

ADC Sinc3 Digital Filter Response............................61

ADC Calibration.........................................................64

Using the Offset and Gain Calibration Registers.......64

Understanding the Offset and Gain Calibration

Registers.....................................................................65

ADC DIAGNOSTICS.........................................................65

Current ADC Diagnostics...........................................65

Temperature ADC Diagnostics...................................66

POWER SUPPLY SUPPORT CIRCUITS.....................67

ADUC7032 SYSTEM CLOCKS.....................................68

PLLSTA Register : ......................................................69

PLLCON Pre-write Key PLLKEY0:...........................70

Rev. PrD | Page 2 of 128

Preliminary Technical Data ADuC7032

PLLCON Pre-write Key PLLKEY1:........................... 70

PLLCON Register :.................................................... 70

POWCON Pre-write Key POWKEY0:....................... 70

POWCON Pre-write Key POWKEY1:....................... 70

POWCON Register :..................................................71

ADUC7032 LOW POWER CLOCK CALIBRATION ............. 72

OSC0TRM Register :..................................................73

OSC0CON Register : .................................................73

OSC0STA Register :................................................... 74

OSC0VAL0 Register :................................................. 74

OSC0VAL1 Register :................................................. 74

PROCESSOR REFERENCE PERIPHERALS............75

INTERRUPT SYSTEM........................................................ 75

TIMERS ........................................................................... 77

TIMER0 – LIFE-TIME TIMER ............................................ 78

Timer0 Value Register :.............................................. 78

Timer0 Capture Register :.......................................... 78

Timer0 Control Register :...........................................79

Timer0 Load Registers:.............................................. 79

Timer0 Clear Register :.............................................. 79

TIMER1 ........................................................................... 80

Timer1 Load Registers:.............................................. 80

Timer1 Clear Register :.............................................. 80

Timer1 Value Register :.............................................. 80

Timer1 Capture Register :.......................................... 81

Timer1 Control Register :...........................................81

TIMER2 - WAKE-UP TIMER ............................................. 82

Timer2 Load Registers:.............................................. 82

Timer2 Clear Register :.............................................. 82

Timer2 Value Register :.............................................. 82

Timer2 Control Register :...........................................83

TIMER3 - WATCHDOG TIMER........................................... 84

Timer3 Load Register :............................................... 84

Timer3 Value Register :.............................................. 84

Timer3 Clear Register :.............................................. 85

Timer3 Control Register :...........................................85

GENERAL P URPOSE I/O ............................................. 86

GPIO Port0 Control Register : ..................................88

GPIO Port1 Control Register : ..................................89

GPIO Port2 Control Register : ..................................89

GPIO Port0 Data Register :.......................................90

GPIO Port1 Data Register :.......................................91

GPIO Port2 Data Register :.......................................92

GPIO Port0 Set Register :.......................................... 93

GPIO Port1 Set Register :.......................................... 94

GPIO Port2 Set Register :.......................................... 94

GPIO Port0 Clear Register : .....................................95

GPIO Port1 Clear Register : .....................................95

GPIO Port2 Clear Register : .....................................96

HIGH VOLTAGE PERIPHERAL CONTROL

INTERFACE....................................................................97

High Voltage Interface Control Register :.................. 98

High Voltage Data Register:......................................99

High Voltage Configuration0 Register :...................100

High Voltage Configuration1 Register :...................101

High Voltage Interrupt Status Register :...................102

High Voltage Monitor Register :...............................103

WAKE-UP(WU).............................................................104

Wake-Up(WU) Pin Circuit Description....................104

HANDLING INTERRUPTS FROM THE HIGH VO LTAG E

PERIPHERAL CONTROL INTERFACE................................ 105

LOW VOLTAGE FLAG ( LV F )......................................... 105

HIGH VOLTAGE DIAGNOSTICS....................................... 105

UART SERIAL INTERFACE.......................................106

BAUD RATE GENERATION ..............................................106

Normal 450 UART baud rate generation. ................106

ADuC7032 Fractional divider: ................................106

UART REGISTER DEFINITION ........................................ 107

UART TX Register:..................................................107

UART RX Register:..................................................107

UART Divisor Latch Register 0:...............................107

UART Divisor Latch Register 1:...............................107

UART Control Register 0: .......................................108

UART Control Register 1: .......................................109

UART Status Register 0:..........................................109

UART Interrupt Enable Register 0:.......................... 110

UART Interrupt Identification Register 0:................ 110

UART Fractional Divider Register:..........................111

SERIAL PERIPHERAL INTERFACE........................ 112

SPI Control Register :.............................................. 113

SPI Status Register :................................................. 114

SPI Receive Register :.............................................. 114

SPI Transmit Register :.............................................114

SPI Divider Register : .............................................. 114

LIN (LOCAL INTERCONNECT NETWORK )

INTERFACE ..................................................................115

LIN MMR DESCRIPTION .............................................. 115

LIN Hardware Synchronization Status Register :.....116

LIN Hardware Synchronization Control Register 0: 117 LIN Hardware Synchronization Control Register 1: 118 LIN Hardware Synchroniz at i o n Timer0 Register : ... 118

LIN Hardware Break Timer1 Register :....................119

LIN HARDWARE INTERFACE .........................................119

LIN Frame Protocol................................................. 119

LIN Frame Break Symbol.........................................120

LIN Frame Synchronization Byte.............................120

LIN Frame Protected Identifier................................120

LIN Frame Data Byte...............................................121

LIN Frame Data Tr ansmission and Reception .........121

Example LIN Hardware Synchronization Routine....122

LIN Diagnostics........................................................123

ADUC7032 ON-CHIP DIAGNOSTICS.......................124

ADC Diagnostics......................................................124

High Voltage I/O Diagnostics...................................124

PART IDENTIFICATION ............................................125

Rev. PrD | Page 3 of 128

Preliminary Technical Data ADuC7032

System Serial ID Register 0: ....................................125

System Serial ID Register 1: ....................................126

System Kernel Checksum:........................................126

System Identification FEE0ADR:.............................127

OUTLINE DIMENSIONS.............................................128

Rev. PrD | Page 4 of 128

Preliminary Technical Data ADuC7032

ADUC7032 DATASHEET TABLES

Table 1 : ADUC7032—SPECIFICATIONS 8

Table 2 : SPI Master Mode Timing (PHASE Mode = 1) 15

Table 3 : SPI Master Mode Timing (PHASE Mode = 0) 16

Table 4 : SPI Slave Mode Timing (PHASE Mode = 1) 17

Table 5 : SPI Slave Mode Timing (PHASE Mode = 0) 18

Table 6. Absolu t e Maxim u m R atings (TA = -40°C to 105°C

unless otherwise noted) 22

Table 7: Pin Function Descriptions 23

Table 8: SYSMAP0 MMR Bit Designations 29

Table 9 : Device RESET Implications 30

Table 10: RSTSTA/RSTCLR MMR Bit Designations 30

Table 11: Command Codes in FEE0CON and FEE1CON 32

Table 12: FEE0STA and FEE1STA MMR bit designations 33

Table 13: FEE0MOD and FEE1MOD MMR bit designations 34

Table 14: FEE0HID and FEE0PRO MMR bit designations 35

Table 15: FEE1HID and FEE1PRO MMR bit designations 35

Table 16: Typical execution cycles in ARM/Thumb mode 37

Table 17 : Complete MMR List 41

Table 18 : GND_SW Configuration 47

Table 19 : Current Channel ADC, Normal Power Mode, Typical

Output RMS Noise (µV) 48

Table 20 : Voltage Channel ADC, Typical Output RMS Noise

(referred to ADC Voltage attenuator Input)(µV) 48

Table 21 : Temperat ure Chan nel ADC, Typical Out put RMS

Noise (µV) 48

Table 29 : Allowable Combinations of SF and AF 56

Table 30: ADCCFG MMR Bit Designations 57

Table 31 : Allowable Combinations of SF and AF 61

Table 32 : Common ADCFLT Configurations 63

Table 33: Current ADC Diagnostics 66

Table 34: Temperature ADC Diagnostics 66

Table 35 : PLLSTA MMR Bit Description 69

Table 36: PLLCON MMR Bit description 70

Table 37 : POWCON MMR bit designations 71

Table 38 : OSC0TRM MMR Bit Definition 73

Table 39: OSC0CON MMR Bit Definition 73

Table 40 : OSC0STA MMR Bit Definition 74

Table 41 : IRQ/FIQ MMRs bit description 75

Table 42 : SWICFG MMR Bit Descriptions 76

Table 43 : Timer Event Capture 77

Table 44 : T0CON MMR Bit Descriptions 79

Table 45 : T1CON MMR Bit Descriptions 81

Table 46 : T2CON MMR Bit Descriptions 83

Table 47 : T3CON MMR Bit Definition 85

Table 48 : External GPIO Pin to Internal Port Signal

Assignments 87

Table 49 : GP0CON MMR Bit Designations 88

Table 50 : GP1CON MMR Bit Designations 89

Table 51 : GP2CON MMR Bit Designations 89

Table 22 : ADCSTA MMR Bit Designations 49

Table 23 : ADCMDE MMR Bit Designations 51

Table 24 : ADC0CON MMR Bit Designations 52

Table 25 : ADC1CON MMR Bit Designations 53

Table 26 : ADC2CON MMR Bit Designations 54

Table 27 : ADCFLT MMR Bit Designations 55

Table 28 : ADC Conversion Rates and Settling Times 56

Rev. PrD | Page 5 of 128

Table 52 : GP0DAT MMR Bit Descriptions 90

Table 53 : GP1DAT MMR Bit Descriptions 91

Table 54 :GP2DAT MMR Bit Descriptions 92

Table 55 : GP0SET MMR Bit Descriptions 93

Table 56 : GP1SET MMR Bit Descriptions 94

Table 57 : GP2SET MMR Bit Descriptions 94

Table 58 : GP0CLR MMR Bit Descriptions 95

Preliminary Technical Data ADuC7032

Table 59 : GP1CLR MMR Bit Descriptions 95

Table 74 : COMIEN0 MMR Bit Descriptions 110

Table 60 : GP2CLR MMR Bit Descriptions 96

Table 61: HVCON MMR Write Bit Designations 98

Table 62: HVCON MMR Read Bit Designations 98

Table 63: HVDAT MMR Bit Designations 99

Table 64: HVCFG0 Bit Designations 100

Table 65: HVCFG1 Bit Designations 101

Table 66: HVSTA Bit Designations 102

Table 67: HVMON Bit Designations 103

Table 68: High Voltage Diagnostics 105

Table 69 : Baud rate using the standard Baud rate generator 106

Table 70: Baud rate using the Fractional Baud rate generator 106

Table 71 : COMCON0 MMR Bit Descriptions 108

Table 72 : COMCON1 MMR Bit Descriptions 109

Table 73: COMSTA0 MMR Bit Descriptions 109

Table 75 : COMIID0 MMR Bit Descriptions 110

Table 76 : COMDIV2 MMR Bit Descriptions 111

Table 77 : SPI Output Pins 112

Table 78: SPI speed vs. clock divider bits in master mode 112

Table 79 : SPICON MMR Bit Descriptions 113

Table 80 : SPISTA MMR Bit Descriptions 114

Table 81 : LHSSTA MMR Bit Descriptions 116

Table 82 : LHSCON0 MMR Bit Descriptions 117

Table 83 : LHSCON1 MMR Bit Descriptions 118

Table 84 : SYSSER0 MMR Bit Descriptions 125

Table 85: SYSSER1 MMR Bit Descriptions 126

Table 86: FEE0ADR System Identification MMR Bit

Descriptions 127

Rev. PrD | Page 6 of 128

Preliminary Technical Data ADuC7032

ADUC7032 DATASHEET FIGURES

Figure 1: ADuC7032 Functional Block Diagram..........................1

Figure 2. SPI Master Mode Timing (PHASE Mode = 1)............15

Figure 3. SPI Master Mode Timing (PHASE Mode = 0)............16

Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)...............17

Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)..............18

Figure 6 : LIN V1.3 Timing Specification....................................19

Figure 7 : LIN V2.0 Timing Specification....................................20

Figure 8 : Package Pin Configuration...........................................22

Figure 9: ADuC7032 Register Organization................................27

Figure 10: Little Endian Format ....................................................28

Figure 11: ADuC7032 Memory Map...........................................28

Figure 12. Flash/EE Memory Data Retention .............................36

Figure 13: ADuC7032 Kernel Flowchart......................................39

Figure 14: Top Level MMR Map ...................................................40

Figure 15: Current ADC, Top Level Overview............................45

Figure 16 : Voltage/ Temperature ADC, Top Level Overview...46

Figure 17 : Example External Temperature Sensor Circuits......47

Figure 18: Internal Ground Switch Configuration .....................47

Figure 19 : Typical Digital Filter Response at FADC=1.0kHz

(ADCFLT = 0x0007)..............................................................62

Figure 20 : ModifiedSinc3 Digital Filter Response at

FADC=1.0kHz (ADCFLT = 0x0087)...................................62

Figure 24 : Typical Digital Filter Response at FADC=4Hz,

(ADCFLT = 0xBF1D)............................................................63

Figure 25 : Typical Digital Filter Response at FADC=1Hz,

(ADCFLT = 0xBD1F..............................................................63

Figure 26: Typical Power-On Cycle ..............................................67

Figure 27: ADuC7032 System Clock Generation .......................68

Figure 28 : Example OSC0TRM Calibration Routine................72

Figure 29: Interrupt Structure .......................................................76

Figure 30 : Timer 0 block diagram................................................78

Figure 31 : Timer 1 Block Diagram ..............................................80

Figure 32 : Timer 2 block diagram................................................82

Figure 33 : Timer3 Block Diagram ..............................................84

Figure 34 : ADuC7032 GPIO.........................................................86

Figure 35 : High Voltage Interface, Top Level Block Diagram..97

Figure 36 : WU Circuit, Block Diagram ....................................104

Figure 37 : Fractional Divider Baud Rate generation...............106

Figure 38 : LIN I/O, Block Diagram...........................................115

Figure 39 : LIN Interface Timing ...............................................119

Figure 40 : LIN Break Field..........................................................120

Figure 41 : LIN Synch byte Field .................................................120

Figure 42 : LIN Identifier Byte Field...........................................120

Figure 43 : LIN Data Byte Field...................................................121

Figure 21 : Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x0000)..............................................................62

Figure 22 : Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x4000)..............................................................62

Figure 23 Typical Digital Filter Response at FADC=8KHz,

(ADCFLT = 0x961F)..............................................................63

Figure 44 : Example LIN Configuration ....................................123

Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48),

Rev. PrD | Page 7 of 128

Dimensions shown in millimeters.....................................128

Preliminary Technical Data

ADUC7032SPECIFICATIONS

ADuC7032

ELECTRICAL SPECIFICATIONS

(VDD =3.5V to18V, V

= 1.2 V Internal Reference, f

REF

Table 1 : ADUC7032—SPECIFICATIONS

= 10.24MHz driven from external 32.768kHz watch crystal or on-chip

CORE

precision oscillator, All specifications TA = -40°C to 105C, unless otherwise noted.)

Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS

Conversion Rate

Chop Off, ADC Normal Operating Mode Chop On, ADC Normal Operating Mode Chop On, ADC Low Power Mode

4 8000 4 2600 1 650

Hz Hz Hz

Current Channel

No Missing Codes 1 Integral Nonlinearity Offset Error

Offset Error

2, 3, 4, 5

1, 3, 6

Chop On -2 ±0.5 +2

1, 2

Valid for all ADC Update Rates and ADC Modes

Chop Off, 1LSB = (36.6/Gain)µV

Offset Error Drift6 Chop off, Valid for ADC Gains of 4 – 64,

Normal Mode

Offset Error Drift6

Chop off. Valid for ADC Gains of 128 – 512, Normal Mode

16 ±10 ±60

Bits PPM of FSR

-10 ±3 +10 LSB

µV

0.03 LSB/°C

30 nV/°C Offset Error Drift6 Chop On 10 nV/°C Total Gain Error Total Gain Error Total Gain Error

1, 3, 7, 8, 9

1, 3, 7, 9, 10

1, 3, 7, 9, 11

Normal Mode Low Power Mode Low Power-Plus Mode, using Precision Vref

-0.5 ±0.1 +0.5

-2 ±0.2 +2

-1 ±0.2 +1

% %

% Gain Drift 3 ppm/°C PGA Gain Mismatch Error ±0.1 % Output Noise

1, 12

4Hz Update Rate, Gain = 512, Chop Enabled 60 90 nV rms

10Hz Update Rate, Gain = 512, Chop Enabled 100 150 nV rms 1KHz Update Rate, Gain = 512 0.6 0.9 µV rms 1KHz Update Rate, Gain = 32 0.8 1.2 µV rms 1KHz Update Rate, Gain = 4 2.0 2.8 µV rms 8KHz Update Rate, Gain = 32 2.5 3.5 µV rms 8KHz Update Rate, Gain = 4 14 21 µV rms ADC Low Power Mode, F ADC Low Power Mode, F ADC Low Power-Plus Mode,F

= 10Hz, Gain=128 1.25 1.9 µV rms

ADC

= 1Hz, Gain=128 0.35 0.5 µV rms

ADC

=1Hz,Gain=512 0.1 0.15 µV rms

ADC

Voltage Channel 13

No Missing Codes 1 Valid at all ADC Update Rates 16 Bits Integral Nonlinearity Offset Error Offset Error

3, 5

1, 3

±10 ±60 ppm of FSR

Chop Off , 1 LSB16=439.5uV -10 ±1 +10 LSB

Chop On 0.3 1 LSB Offset Error Drift Chop Off 0.03 LSB/°C Total Gain Error Total Gain Error Gain Drift Output Noise

1,3, 7, 14

Includes Resistor Mismatch -0.25 ±0.06 +0.25 %

1,3, 7, 14

Temperature Range = -25°C to 65°C -0.15 ±0.03 +0.15 %

Includes Resistor Mismatch Drift 3 ppm/°C

1, 15

4Hz Update Rate 60 90 µV rms 10Hz Update Rate 60 90 µV rms 1KHz Update Rate 180 270 µV rms 8KHz Update Rate 1600 2400 µV rms

Rev. PrD | Page 8 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

Temperature Channel

No Missing Codes 1 Valid at all ADC Update Rates 16 Bits Integral Nonlinearity Offset Error Offset Error

3, 5,16, 17

1, 3

Offset Error Drift Total Gain Error Gain Drift Output Noise

ADC SPECIFICATIONS

ANALOG INPUT

Current Channel

Absolute Input Voltage Range Applies to both IIN+ and IIN-

Input Voltage Range Gain =222 ±600 mV Gain =422 ±300 mV Gain =8 ±150 mV Gain = 16 ±75 mV Gain = 32 ±37.5 mV Gain = 64 ±18.75 mV Gain = 128 ±9.375 mV Gain = 256 ±4.68 mV Gain = 512 ±2.3 mV

Input Leakage Current

Input Offset Current

Voltage Channel

Absolute Input Voltage Range 4 18 V

Input Voltage Range 0 to 28.8 V

VBAT Input Current VBAT = 18V 4 5.5 7 µA

Temperature Channel

Absolute Input Voltage Range 100 1300 mV

Input Voltage Range 0 to VREF V

VTEMP Input Current1 2.5 100 nA

VOLTAGE REFERENCE

ADC Precision Reference

Internal V

Power Up Time1 0.5 Ms Initial Accuracy1 Measured at TA = 35°C -0.15 0.15 % Internal V

Coefficient

Long term stability25 100 ppm/1000h External Reference Input

Range

Divide by 2 Initial Error

REF

ADC Low Power Reference

Internal V Initial Accuracy Initial Accuracy10 Using ADCREF, measured at TA = 35°C 0.1 % Temperature Coefficient

±10 ±60 ppm of FSR

Chop Off , 1 LSB16=19.84uV -10 ±3 +10 LSB

Chop On -5 1 5 LSB

1,3, 18, 19, 17

-0.2 ±0.06 +0.2 %

0.03 LSB/°C

3 ppm/°C

20,21

1, 23

0.5 1.5 nA

1KHz Update Rate 7.5 11.25 µV rms

Internal V

REF

=1.2V

Gain =122 ±1.2

-200 +300

-3 3 nA

REF

Temperature

REF

1, 24

REF

1.2 V

-20 ±5 +20

0.1 1.3

0.1 0.3 %

ppm/°C

1.2 V Measured at TA = 35°C -5 5 %

1, 24

-300 ±150 +300 ppm/°C

Rev. PrD | Page 9 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit RESISTIVE ATTENUATOR

Divider Ratio 24 Resistor Mismatch Drift

ADC Ground Switch

Resistance Direct path to ground 10

Input Current

TEMPERATURE SENSOR27

Accuracy MCU in power down or standby mode ±3 °C

POWER-ON RESET (POR)

POR Trip Level Refers to Voltage at VDD pin 2.85 3.0 3.15 V POR Hysteresis 300 mV

RESET Time-Out from POR

LOW VOLTAGE FLAG (LVF)

LVF Level

POWER SUPPLY MONITOR (PSM)

PSM Trip Level

WATCHDOG TIMER (WDT)

Timeout Period

Timeout Step Size

FLASH/EE MEMORY

Endurance28 32.768Khz Clock, 256 pre-scale 10,000 Cycles

Data Retention29 TJ = 85°C 20 Years

DIGITAL INPUTS

Input Leakage Current Input (High) = REG_DVDD ±1 ±10 µA Input Pull-up Current Input Capacitance

Input Leakage Current NTRST Only :Input (Low) = 0V ±1 ±10 µA Input Pull-down Current

3 ppm/°C

Ω

20kΩ Resistor selected

10 20 30

kΩ

6 mA

MCU in power down or standby mode Temperature Range = -25°C to 65°C

±2 °C

20 msec

Refers to Voltage at VDD pin 1.9 2.1 2.3 V

Refers to Voltage at VDD pin 6.0 V

32.768Khz Clock, 256 pre-scale 0.008 512 sec

7.8 msec

All digital inputs except NTRST

Input (Low) = 0V 10 20 80 µA 10 pF

NTRST Only : Input (High) = REG_DVDD 30 55 100 µA

Rev. PrD | Page 10 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS

VINL, Input Low Voltage 0.4 V VINH, Input High Voltage

CRYSTAL OSCILLATOR

Logic Inputs, XTAL1 Only

VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 1.7 V XTAL1 Capacitance 12 pF XTAL2 Capacitance

ON-CHIP OSCILLATORS

Low Power Oscillator 131.072 kHz Accuracy30 Includes drift data from 1000hr life-test -6 3

Precision Oscillator 131.072 kHz

Accuracy Includes drift data from 1000hr life-test -1.2 1.2 %

All Logic inputs

2.0 V

12 pF

MCU CLOCK RATE

8 programmable core clock selections within

0.160 10.24 20.48

MHz

this range (binary divisions 1,2,4,8…..64, 128)

MCU START-UP TIME

at Power-On Includes kernel power-on execution time 25

after Reset Event Includes kernel power-on execution time 5

From MCU Power-Down

Oscillator Running

Wakeup from Interrupt

Wakeup from LIN

Crystal Powered Down

Wakeup from Interrupt

500

msec

Internal PLL Lock Time 1 msec

LIN I/O General

Baud Rate 1000 20000 Bits/sec

VDD Supply Voltage Range for which the LIN

interface is functional

7 18

Input capacitance 5.5 pF

LIN comparator response

Error! Bookmark not defined.

time

LIN DOM MAX

LIN_PAS_REC

LIN_PAS_DOM1

Current Limit for driver when LIN Bus is in

Driver Off ; 7.0V < V

Using 22Ohm resistor 38 90 µs

dominant state. V

Input Leakage V

= V

BAT

< 18V ; VDD = V

BUS

= 0V -1 mA

LIN

BAT (MAX)

-0.7V 20 µA

LIN

40 200

Rev. PrD | Page 11 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

LIN_NO_GND

VLIN_RECESSIVE

GND-Shift

LIN I/O General Contd.

Transmit Propagation Delay 1

Control Unit disconnected from ground

GND = V

LIN_DOM1

LIN_REC1

LIN Receiver Centre Voltage, VDD > 7.0V 0.475VDD 0.5 V

LIN_CNT

LIN Receiver Hysteresis Voltage 0.175VDD V

HYS

LIN_DOM_DRV_LOSUP1

LIN_DOM_DRV_HISUP

LIN_DOM_DRV_LOSUP1

LIN_DOM_DRV_HISUP

-Shift31 0 0.1V

BAT

LIN Receiver Dominant State, VDD > 7.0V 0.4VDD V

LIN Receiver Recessive State, VDD > 7.0V 0.6VDD V

LIN Dominant Output Voltage. VDD 7V, RL 500Ω

LIN Dominant Output Voltage. V

LIN Dominant Output Voltage. VDD 7V, RL 1000Ω

LIN Dominant Output Voltage. V

LIN Recessive Output Voltage 0.8 VDD V

; 0V V

<18V ; V

LIN

= 12V

BAT

18V,RL 500Ω

18V,RL 1000Ω

-1 1

0.525VDD V

1.2 V

2 V

0.6 V

0.8 V

0 0.1VDD V

Slave Termination Resistance 20 30 47

slave

Serial Diode

Voltage Drop at the serial diode D

Ser_Int

0.4 0.7 1 V

VDD

= 7V

MIN

Bus Load Conditions ( C

BUS

|| R

BUS

KΩ

µs

Symmetry of Transmit

Propagation Delay

Receive Propagation Delay

Symmetry of Receive

Propagation Delay

LIN V1.3 Specification

SYM

SYM1

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

VDD

= 7V

MIN

VDD

MIN

= 7V

VDD

= 7V

MIN

Bus Load Conditions ( C

BUS

|| R

BUS

) :

-2 2

µs

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

Slew Rate Dominant and recessive Edges V

BAT

= 18V

Slew Rate Dominant and recessive Edges V

BAT

= 7V

Symmetry of rising and falling edge V Symmetry of rising and falling edge V

BAT

= 18V = 7V

1 2 3

0.5 3 V/µs

-5 5

-4 4

V/µs

µs µs

Rev. PrD | Page 12 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

LIN V2.0 Specification

|| R

Bus Load Conditions ( C

BUS

) :

1nF||1kΩ ; 6.8nF|| 660 Ω ; 10nF || 500Ω

D1 Duty Cycle 1

REC(MAX)

DOM(MAX)

= 7.0V…18V; t

SUP

D1 = t Duty Cycle 2 TH TH

D2 = t

BUS_REC(MIN)

REC(MIN)

DOM(MIN)

= 7.0V…18V; t

SUP

BUS_REC(MAX)

= 0.744 * V

= 0.581 * V

/ (2 * t

= 0..284 * V

= 0.422 * V

/ (2 * t

BAT

= 50µs

BIT

BAT

= 50µs

BIT

)

0.396

)

0.581

Wake

= 1kOhm, C

= 91nF, R

BUS

= 39Ohms

LIMIT

VDD1

Supply Voltage Range for which the Wake Pin is functional

Output High Level 5 V

Output Low Level 2 V

7 18

VIH Input High Level 4.6 V

VIL

Monoflop Timeout

Package Thermal Specifications

Input Low Level 1.2 V Timeout Period

1.3 sec

Thermal Shutdown

Thermal Impedance (θja)34

140 150 160 °C

48 LQFP, Stacked Die

Top Die 50 °C/W

Bottom Die 25

°C/W

POWER REQUIREMENTS

Power Supply Voltages

VDD (Battery Supply) 3.5 18 V

REG_DV

REG_AV

DD,

2.5 2.6 2.7 V

Power Consumption

IDD – MCU Normal Mode36 MCU Clock Rate = 10.24MHz, ADC Off 10 20 mA

IDD – MCU Normal Mode36 MCU Clock Rate = 20.48MHz, ADC Off 20 mA

IDD – MCU Powered Down1

IDD–MCU Powered Down1

ADC Low Power Mode, measured over an ambient temperature range of -10°C to +40°C

(Continuous ADC Conversion )

ADC Low Power Mode, measured over an ambient temperature range of -40°C to +85°C

(Continuous ADC Conversion )

300 400

300 500

µA

Rev. PrD | Page 13 of 128

Preliminary Technical Data ADuC7032

Parameter Test Conditions/Comments Min Typ Max Unit

IDD – MCU Powered Down

IDD – MCU Powered Down1

IDD – Current ADC I

– Voltage/Temperature ADC

– Precision Oscillator

These numbers are not production tested but are guaranteed by design and/or characterization data at production release

Valid for Current ADC Gain setting of PGA=4 to 64

These numbers include temperature drift

Tested at Gain Range=4, Self-Offset Calibration will remove this error.

Measured with an internal short after an initial offset calibration.

Measured with an internal short

These numbers include internal reference temperature drift.

Factory Calibrated at Gain = 1.

System calibration at specific gain range will remove the error at this gain range

When used in conjunction with ADCREF, the Low Power Mode Reference error MMR.

Using ADC Normal Mode Voltage Reference

Typical Noise in Low Power modes is measured with Chop enabled.

Voltage Channel Specifications include resistive attenuator input stage

System Calibration will remove this error

rms noise is referred to Voltage attenuator input, for example at F input referred noise figures

ADC Self Offset calibration will remove this error.

Valid after an initial Self Calibration

Factory calibrated for the internal temperature sensor during final production test.

System Calibration will remove this error

In ADC Low Power Mode the input range is fixed at ±9.375mV. In ADC Low Power Plus Mode the input range is fixed at ±2.34375mV.

It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the Gain Calibration register or using system calibration. This approach can also be used to reduce the ADC Input Range (LSB Size).

Limited by minimum absolute input voltage range.

Valid for a differential input less than 10mV

Measured using Box Method

The long-term stability specification is non cumulative. The drift in subsequent 1,000 hour periods is significantly lower than in the first 1,000 hour period.

References of up to REG_AVDD can be accommodated by enabling an internal Divide-by-2

Die Temperature.

Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +125°C. Typical endurance at 25°C is 170,000 cycles.

Retention lifetime equivalent at junction temperature (Tj) = 85°C as per JEDEC Std. 22 method A117. Retention lifetime will de-rate with junction temperature.

Low Power oscillator can be calibrated against either the precision oscillator or the external 32.768kHz crystal in user code

These numbers are not production tested, but are supported by LIN Compliance testing.

Specified after Rlimit of 39Ohms

The MCU core is not shutdown but an interrupt is generated, if enabled.

Thermal Impedance can be used to calculate the thermal gradient from ambient to die temperature.

Internal Regulated Supply available at REG_DVDD (I

Typical, additional supply current consumed during Flash memory program and erase cycles is 7mA and 5mA respectively.

ADC Low Power-Plus Mode, measured over an ambient temperature range of -10°C to +40°C

(Continuous ADC Conversion )

Average Current, Measured with Wake and Watchdog Timer clocked from Low Power Oscillator

Average Current, Measured with Wake and Watchdog Timer clocked from Low Power Oscillator over an ambient temperature range of

-10°C to +40°C

Per ADC

520 700

120 300

120 175

1.7

0.5 400

µA

mA mA µA

=1KHz, typical rms noise at the ADC input is 7.5uV, scaled by the attenuator (24) yields these

ADC

=5mA), and REG_AVDD (I

SOURCE

=1mA)

Rev. PrD | Page 14 of 128

Preliminary Technical Data ADuC7032

TIMING SPECIFICATIONS

SPI Timing Specifications

Table 2 : SPI Master Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit tSL SCLOCK low pulsewidth (SPIDIV + 1) × t tSH SCLOCK high pulsewidth (SPIDIV + 1) × t t

Data output valid after SCLOCK edge ns

DAV

Data input setup time before SCLOCK edge ns

DSU

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns tDR Data output rise time ns tSR SCLOCK rise time ns tSF SCLOCK fall time ns

HCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MOSI

MISO

DAV

DSUtDHD

MSB IN BITS 6 – 1 L SB IN

Figure 2. SPI Master Mode Timing (PHASE Mode = 1)

LSBBITS 6 – 1MSB

05994-002

Rev. PrD | Page 15 of 128

Preliminary Technical Data ADuC7032

Table 3 : SPI Master Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit tSL SCLOCK low pulsewidth (SPIDIV + 1) × t tSH SCLOCK high pulsewidth (SPIDIV + 1) × t t

Data output valid after SCLOCK edge ns

DAV

Data output setup before SCLOCK edge ns

DOSU

Data input setup time before SCLOCK edge ns

DSU

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns tDR Data output rise time ns tSR SCLOCK rise time ns tSF SCLOCK fall time ns

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

DOSU

DAV

HCLK

MOSI

MISO

MSB IN BITS 6 – 1 LSB IN

DSUtDHD

Figure 3. SPI Master Mode Timing (PHASE Mode = 0)

LSBBITS 6 – 1MSB

5994-003

Rev. PrD | Page 16 of 128

Preliminary Technical Data ADuC7032

Table 4 : SPI Slave Mode Timing (PHASE Mode = 1)

Parameter Description Min Typ Max Unit tCS CS to SCLOCK edge ns tSL SCLOCK low pulsewidth (SPIDIV + 1) × t tSH SCLOCK high pulsewidth (SPIDIV + 1) × t t

Data output valid after SCLOCK edge ns

DAV

Data input setup time before SCLOCK edge ns

DSU

Data input hold time after SCLOCK edge ns

DHD

tDF Data output fall time ns tDR Data output rise time ns tSR SCLOCK rise time ns tSF SCLOCK fall time ns t

CS high after SCLOCK edge ns

SFS

HCLK

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

MISO

MOSI

DAV

DSUtDHD

MSB IN BITS 6 – 1 LSB IN

SFS

LSBBIT S 6 – 1MSB

05994-004

Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)

Rev. PrD | Page 17 of 128

Preliminary Technical Data ADuC7032

Table 5 : SPI Slave Mode Timing (PHASE Mode = 0)

Parameter Description Min Typ Max Unit

tCS CS to SCLOCK edge ns tSL SCLOCK low pulsewidth (SPIDIV + 1) × t tSH SCLOCK high pulsewidth (SPIDIV + 1) × t t

Data output valid after SCLOCK edge ns

DAV

Data input setup time before SCLOCK edge ns

DSU

Data input hold time after SCLOCK edge ns

DHD

HCLK

tDF Data output fall time ns tDR Data output rise time ns tSR SCLOCK rise time ns tSF SCLOCK fall time ns t

Data output valid after CS edge ns

DOCS

CS high after SCLOCK edge ns

SFS

SCLOCK

(POLARITY = 0)

SCLOCK

(POLARITY = 1)

DOCS

DAV

MISO

MOSI

MSB IN BITS 6 – 1 LSB IN

DSUtDHD

Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)

LSBBITS 6 – 1MSB

05994-005

Rev. PrD | Page 18 of 128

Preliminary Technical Data ADuC7032

LIN Timing Specifications

Figure 6 : LIN V1.3 Timing Specification

Rev. PrD | Page 19 of 128

Preliminary Technical Data ADuC7032

TRANSMIT

INPUT TO

TRANSMITTING

NODE

RECESSIVE

DOMINANT

BIT

(TRANSCEIVER SUPPLY

OF TRANSMITTING NODE)

SUP

RxD

(OUTPUT O F RECEIVING NO DE 1)

RxD

(OUTPUT O F RECEIVING NO DE 2)

REC (MAX)

DOM (MAX)

REC (MIN)

DOM (MI N)

LIN_DOM (M AX)

LIN_DO M (MIN)

RX_PDF

LIN_REC ( MIN)

LIN_REC ( MAX)

RX_PDR

Figure 7 : LIN V2.0 Timing Specification

RX_PDR

RX_PDF

THRESHOLDS OF RECEIVING NO DE 1

THRESHOLDS OF RECEIVING NO DE 2

LIN

BUS

05994-005

Rev. PrD | Page 20 of 128

Preliminary Technical Data ADuC7032

SPECIFICATION TERMINOLOGY

CONVERSION RATE:

The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled.

The sigma-delta conversion techniques used on this part mean that while the ADC front-end signal is over-sampled at a relatively high sample rate, a subsequent digital filter is employed to decimate the output to give a valid 16-Bit data conversion result at output rates from 1Hz to 8 KHz.

It should also be noted that when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter this can take multiple conversion cycles.

INTEGRAL NON_LINEARITY (INL):

This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition and full scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale.

NO MISSING CODES:

This is a measure of the Differential Non-Linearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2^N Bits, where is N = No Missing Codes, guaranteed to occur through the full ADC input range.

Acronyms used in this Datasheet:

ADC Analog to Digital Converter ARM Advanced RISC Machine JTAG Joint Test Action Group LIN Local Interconnect Network LSB Least Significant Byte/Bit LVF Low Voltage Flag MCU MicroController MMR Memory Mapped Register MSB Most Significant Byte/Bit PID Protected Identifier POR Power On Reset PSM Power Supply Monitor RMS Root Mean Square

OFFSET ERROR:

This is the deviation of the first code transition ADC input voltage from the ideal first code transition.

OFFSET ERROR DRIFT:

Offset Error Drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per °C.

GAIN ERROR

This is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function.

OUTPUT NOISE:

The output noise is specified as the standard deviation (or 1 X Sigma) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as µ rms. The output or RMS noise can be used to calculate the Effective Resolution of the ADC as defined by the following equation

Effective Resolution= Log 2 (Full-Scale Range / RMS Noise) Bits

The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 X Sigma of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-topeak noise is therefore calculated as 6.6 times the RMS noise.

The peak-to-peak noise can be used to calculate the ADC (Noise Free, Code) Resolution for which there will be no code flicker within a 6.6-Sigma limit as defined by the following equation

Noise Free Code Resolution = Log Peak Noise) Bits

(Full-Scale Range / Peak to

Rev. PrD | Page 21 of 128

Preliminary Technical Data ADuC7032

ABSOLUTE MAXIMUM RATINGS

Table 6. Absolute Maximum Ratings (TA = -40°C to 105°C unless otherwise noted)

Parameter Rating

AGND to DGND to VSS to IO_VSS -0.3V to +0.3V VBAT to AGND -22V to 40V VDD to VSS

to VSS for 1 second

-0.3V to 33V

-0.3V to 40V LIN to IO_VSS -16V to 40V WU to IO_VSS Wake Continuous Current HV IO Pins Short Circuit Current

-3V to 33V

50mA

100mA Digital I/O Voltage to DGND -0.3V to REG_DVDD +0.3 VREF to AGND -0.3V to REG_AV

+ 0.3 ADC Inputs to AGND -0.3V to REG_AVDD +0.3 ESD (HBM) Rating LIN, WU and VBAT

± 4KV All other pins ± 2KV Storage Temperature Range 125°C Junction Temperature (transient) 150°C Junction Temperature (continuous) 130°C Lead Temperature, Soldering

Reflow (15 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

13 14 15 16 17 18 19 20 21 22 23 24

Figure 8 : Package Pin Configuration

3740 39 384142434445464748

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ESD Caution

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrD | Page 22 of 128

Preliminary Technical Data ADuC7032

PIN FUNCTION DESCRIPTIONS

Table 7: Pin Function Descriptions

Pin# Mnemonic Type* Function

Reset Input Pin, Active Low. This pin has an internal, weak pull-up resistor to

RESET

2 GPIO_5/IRQ1/RxD I/O

3 GPIO_6/TxD I/O

4 GPIO_7/IRQ4 I/O

5 GPIO_8/ IRQ5 I/O

6 TCK I

7 TDI I

8 DGND S Ground Reference for On-Chip Digital Circuits

9 NC

10 TDO O

11 NTRST I

12 TMS I

REG_DVDD. If this pin is not being used it can be left not connected. For

added security and robustness, it is recommended that this pin be strapped via a resistor to REG_DVDD.

General Purpose Digital I/O 5 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 3 states, namely:

General Purpose Digital I/O 5 External Interrupt Request 1, Active High Receive Data for UART Serial Port This Pin may also be used as a clock input to Timer1. General Purpose Digital I/O 6 is a Multi-Function Pin. By default and after

Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely:

General Purpose Digital I/O 6 Transmit Data for UART Serial Port General Purpose Digital I/O 7 is a multi-function pin. By default and after

General Purpose Digital I/O 7 External Interrupt Request 4, Active High General Purpose Digital I/O 8 is a multi-function pin. By default and after

General Purpose Digital I/O 8 External Interrupt Request 5, Active High This Pin may also be used as a clock input to Timer1. JTAG Test Clock. This clock input pin is one of the standard 5 pin JTAG debug

port on the part. TCK is an input pin only and has an internal weak pull-up resistor. If not being used this pin can be left unconnected

JTAG Test Data Input. This data input pin is one of the standard 5 pin JTAG debug port on the part. TDI is an input pin only and has an internal weak pullup resistor. If not being used this pin can be left unconnected

No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally

JTAG Test Data Output. This data output pin is one of the standard 5 pin JTAG debug port on the part. TDO is an output pin only. On power-on this output is disabled and pulled high via an internal weak pull-up resistor. If not being used this pin can be left unconnected

JTAG Test Reset. This Reset input pin is one of the standard 5 pin JTAG debug port on the part. NTRST is an input pin only and has an internal weak pulldown resistor. If not being used this pin can be left unconnected. NTRST is also monitored by the on-chip kernel to enable LIN boot-load mode.

JTAG Test Mode Select. This Mode Select input pin is one of the standard 5 pin JTAG debug port on the part. TMS is an input pin only and has an internal weak pull-up resistor. If not being used this pin can be left unconnected

Rev. PrD | Page 23 of 128

Preliminary Technical Data ADuC7032

Pin# Mnemonic Type* Function

13 VBAT I Battery Voltage Input to resistor divider

14 VREF I

15 GND_SW S

16 NC

17 NC

18 VTEMP 19 IIN+ I Positive Differential Input for Current Channel 20 IIN- I Negative Differential Input for Current Channel 21 AGND S Ground Reference for On-Chip Precision Analog Circuits 22 AGND S Ground Reference for On-Chip Precision Analog Circuits

23 NC

24 REG_AVDD S Nominal 2.6V output from on chip regulator

25 NC

26 NC

28 GPIO_1/SCLK I/O

29 GPIO_2/MIS0 I/O

30 GPIO_3/MOSI I/O

31 GPIO_4/ECLK I/O

32 NC

GPIO_0/IRQ0/SS

External Reference Input Terminal. If this input is not being used it should be connected directly to the AGND system ground

Switch to internal analog ground reference. Negative input for external temperature channel and external reference If this input is not being used it should be connected directly to the AGND

system ground. No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally

I External Pin for NTC/PTC temperature measurement

No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally

General Purpose Digital I/O 0 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 3 states, namely:

I/O

General Purpose Digital I/O 0 External Interrupt Request 0, Active High SPI Interface, Slave Select Input General Purpose Digital I/O 1 is a Multi-Function Pin. By default and after

General Purpose Digital I/O 1 SPI Interface, Serial Clock Input General Purpose Digital I/O 2 is a Multi-Function Pin. By default and after

General Purpose Digital I/O 2 SPI Interface, Master Input/Slave Output Pin General Purpose Digital I/O 3 is a Multi-Function Pin. By default and after

General Purpose Digital I/O 3 SPI Interface, Master Output/Slave Input Pin General Purpose Digital I/O 4 is a programmable digital I/O pin. By default and

after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used this pin can be left unconnected.

GPIO4 is can also be configured to output a 2.56MHz clock No Connect, this pin is not connected internally but is reserved for possible

future use, this pin should therefore not be connected externally

Rev. PrD | Page 24 of 128

Preliminary Technical Data ADuC7032

Pin# Mnemonic Type* Function

33 REG_DVDD S Nominal 2.6V output from the on-chip regulator 34 DGND S Ground Reference for On-Chip Digital Circuits 35 DGND S Ground Reference for On-Chip Digital Circuits

36 XTAL1 O

37 XTAL2 I

38 NC

39 NC

40 NC

41 WU O

42 VDD S Battery Power Supply to on-chip regulator

43 NC

44 VSS S Ground Reference for the internal Voltage Regulators

45 NC

46 Reserved

47 IO_VSS S Ground Reference for High Voltage I/O Pins 48 LIN I/O LIN Serial Interface Input/Output Pin

I = Input, O = Output, S = Supply

No Connect ( NC ) pins may be grounded if required.

Crystal Oscillator Output. If an external Crystal is not being used, this pin can be left unconnected.

Crystal Oscillator Input. If an external Crystal is not being used, this pin should be connected to the DGND system ground.

No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally

High Voltage Wake-Up Transmit pin. If this pin is not being used, it should not be connected externally.

No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally

This pin is reserved for HV-IO Output only functionality. This pin should connected externally to the IO_VSS ground reference

Rev. PrD | Page 25 of 128

Preliminary Technical Data ADuC7032

ADUC7032 GENERAL DESCRIPTION

The ADuC7032 is a complete, system solution for battery monitoring in 12V automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process and diagnose 12V battery parameters including battery current, voltage and temperature over a wide range of operating conditions.

Minimizing external system components, the device is powered directly from the 12V battery. An on-chip LDO, Low DropOut, regulator generates the supply voltage for the three integrated 16-Bit Σ−∆ ADCs. The ADCs precisely measure battery current, voltage and temperature, which may be used to characterize the car battery’s state of health and charge.

A Flash/EE memory based ARM7 microcontroller (MCU) is also integrated on-chip and is used both to pre-process the acquired battery variables, and to manage communications from the ADuC7032 to the main Electronic Control Unit (ECU) via a Local Interconnect Network (LIN) interface, which is integrated on-chip.

Both the MCU and the ADC sub-system can be individually configured to operate in normal or flexible power-saving modes of operation.

In its normal operating mode the MCU is clocked indirectly from an on-chip oscillator via the Phase Locked Loop (PLL) at a maximum clock rate of 20.48MHz. In its power-saving operating modes, the MCU can be totally powered down, waking up only in response to an ADC conversion result ready, digital comparators, the wake-up timer, a POR or an external serial communication event.

The ADC can be configured to operate in a normal (full power) mode of operation, interrupting the MCU after various sample conversion events. The Current Channel features two low power modes, Low Power and Low Power-Plus, generating conversion results to a lower performance specification.

On-chip factory firmware supports in-circuit Flash/EE reprogramming via the LIN or JTAG serial interface ports while non-intrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting the ADuC7032.

The ADuC7032 operates directly from the 12V battery supply and is fully specified over a temperature range of -40°C to 105°C. The ADuC7032 is functional, with degraded performance, at temperatures from 105°C to 125°C.

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC), developed by ARM Ltd. The ARM7TDMI is a Von Neumann based architecture, which means that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits and the length of the instruction word is either 16 bits or 32 bits, depending on which mode the core is operating in.

The ARM7TDMI is an ARM7 core with 4 additional features:

- T support for the Thumb (16 bit) instruction set.

- D support for debug

- M enhanced multiplier

- I includes the EmbeddedICE module to support

embedded system debugging.

Thumb mode (T)

An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, the Thumb instruction set. Faster code execution from 16-bit memory and greater code density can be achieved by using the Thumb instruction set, which makes the ARM7TDMI core particularly suited for embedded applications.

However the Thumb mode has three limitations:

- Relative to ARM, Thumb code usually requires more instructions to perform that same task. Therefore, ARM code is best for maximizing the performance of time-critical code. In most applications.

- The Thumb instruction set does not include some instructions which are needed for exception handling, so ARM code may be required for exception handling.

- When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at this address. The first command is required to be in ARM code.

Multiplier (M)

The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions which perform 32-bit by 32-bit multiplication with 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result.

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Preliminary Technical Data ADuC7032

EmbeddedICE (I)

ARM Registers

The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow non intrusive user code debugging. These registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers may be interrogated, as well as the Flash/EE, the SRAM and the Memory Mapped Registers.

ARM7 Exceptions

The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are:

- Normal interrupt or IRQ. It is provided to service general- purpose interrupt handling of internal and external events

- Fast interrupt or FIQ. It is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ

- Memory abort (Prefetch and Data)

- Attempted execution of an undefined instruction

- Software interrupt (SWI) instruction which can be used to

make a call to an operating system.

Typically the programmer will define interrupts as IRQ but for higher priority interrupts, the programmer can define interrupts as of type FIQ.

The priority of the above exceptions and vector address are as follows:

1. Hardware Reset 0x00

2. Memory Abort ( Data ) 0x10

3. FIQ 0x1C

4. IRQ 0x18

5. Memory Abort ( Prefetch ) 0x0C

6. Software Interrupt and 0x08 Undefined Instruction 0x04

A Software interrupt and an Undefined Instruction

Note:

exception have the same priority and are mutually exclusive.

NOTE:

The above list are located from 0x00 -0x1C, with a reserved location at 0x14. This location is required to be written with either 0x27011970 or the checksum of Page Zero, excluding location 0x14. If this is not done, user code will not be executed and LIN download mode will be entered. For more information please refer to the ADuC7032 LIN download Te ch n o te .

The ARM7TDMI has 16 standard registers. R0-R12 are used for data manipulation, R13 is the stack pointer, R14 is the link register and R15 is the program counter which indicates the instruction currently being executed. The link register contains the address from which the user has branched, if the branch and link command was used, or the command during which an exception occurred.

The stack pointer contains the current location of the stack. As a general rule of thumb on an ARM7TDMI, the stack starts at the top of the available RAM area, and descends, using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. On the ADuC7032 the stack begins at 0x000417FC and descends.

Whilst programming using high level languages, such as C, it may be possible to ensure that the stack does not overflow. This is dependent on the compiler used.

When an exception occurs, some of the standard register are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 9. The FIQ mode has more registers (R8 to R12) supporting faster interrupt processing. With the increased number of non-critical registers, the interrupt may be processed without the need to save or restore these registers, which reduces the response time of the interrupt handling process.

More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following documents available from ARM Ltd.:

- DDI0029G, ARM7TDMI Technical Reference Manual.

- DDI0100E, ARM Architecture Reference Manual..

USABLE IN USE R MODE

SYSTEM MODES ONLY

R13_ABT

R14_ABT

ABORT

MODE

R13_IRQ

R14_IRQ

SPSR_IRQ

IRQ

MODE

R13_UND

R14_UND

SPSR_UND

UNDEFINED

MODE

05994-008

R15 (PC)

CPSR

USER MODE

R10

R11

R12

R13

R14

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

SPSR_FIQ

Figure 9: ADuC7032 Register Organization

FIQ

MODE

R13_SVC

R14_SVC

SPSR_SVC

SVC

MODE

SPSR_ABT

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Preliminary Technical Data ADuC7032

Interrupt latency

The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 2.44µS in a system using a continuous 20.48MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time may be reduced to 42 cycles if the LDM command is not used, some compilers have an option to compile without using this command. Another option is to run the part in THUMB mode where this is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode.

Note that the ARM7TDMI will initially (1

instruction) run in ARM (32-bit) mode when an exception occurs. The user may immediately switch from ARM mode to Thumb mode if required, e.g. when executing interrupt service routines.

MEMORY ORGANISATION

The ARM7, a Von Neumann architecture, MCU core sees

memory as a linear array of 232 byte locations. As shown in Figure 11, the ADuC7032 maps this into 4 distinct user areas namely, a re-mappable memory area, an SRAM area, a Flash/EE area and a Memory Mapped Register (MMR) area.

The first 96kBytes of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped. A second 4kByte area at the top of the memory map is used to locate the Memory Mapped Registers (MMR), through which all on-chip peripherals are configured and monitored. The remaining 2 areas of memory are constituted as 6kByte of SRAM and 96kByte of On-Chip Flash/EE memory. 94kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the on-chip Kernel. These areas are described in more detail below.

Memory Format

The ADuC7032 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.

BIT 31

BYTE 3

. . .

BYTE 2

BYTE 1

32 BITS

Figure 10: Little Endian Format

BYTE 0

. . .

BIT 0

0xFFFFFFFFh

0x00000004h

0x00000000h

5994-009

RESERVED

FFFF 0000h

FFFF0FFFh

00097FFFh

00080000h

00417FFh

00040000h

0017FFFh

00000000h

Figure 11: ADuC7032 Memory Map

MMRs

RESERVED

FLASH/EE

RESERVED

SRAM

RESERVED

RE-MAPP ABLE MEMORY SPACE (FLASH/EE OR SRAM)

5994-011

SRAM

6kBytes of SRAM are available to the user, organized as 1536 X 32 bits, i.e. 1536Words, which is located at 0x40000. The RAM space can be used as data memory and also as a volatile program space.

ARM code can run directly from SRAM at full clock speed given that the SRAM array is configured as a 32-bit wide memory array.

SRAM is read/writeable in 8/16/32 bit segments.

Any access, either reading or writing, to an area not defined in the memory map will result in a Data Abort exception.

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Preliminary Technical Data ADuC7032

code. This so called kernel is hidden and cannot be accessed by

Remap

The ARM exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020.

By default, after a reset, the Flash/EE memory is logically mapped to address 0x00000000.

It is possible to logically REMAP the SRAM to address 0x00000000. This is done by a setting bit zero of the SYSMAP0 MMR, which is located at 0xFFFF0220. To revert Flash/EE to 0x00000000, bit zero of SYSMAP0 is cleared.

It may be desirable to remap RAM to 0x00000000 to optimize the interrupt latency of the ADuC7032, as code may be run in full 32bit ARM mode and at the maximum core speed. It should be noted that when an exception occurs, the core will default to ARM mode.

Remap operation

When a reset occurs on the ADuC7032, execution starts automatically in the factory programmed internal configuration

user code. If the ADuC7032 is in normal mode, it will execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE.

Precaution must be taken to execute the REMAP command from the absolute Flash/EE address, and not from the mirrored, remapped segment of memory, as this will be replaced by the SRAM. If a remap operation is executed whilst operating code from the mirrored location, Prefetch/Data aborts may occur or the user may observe abnormal program operation.

This operation is reversible: the Flash/EE memory may be remapped at address 0x00000000 by clearing bit zero of the SYSMAP0 MMR. Precaution must again be taken to execute the remap function from outside the mirrored area.

Any kind of reset will logically remap the Flash/EE memory to the bottom of the memory array.

SYSMAP0 Register :

Name : SYSMAP0 Address : 0xFFFF0220 Default Value : 0x00 Access : Read/Write Access

Function : This 8-bit register allows user code to remap either RAM or Flash/EE memory space into the bottom of the ARM

memory space starting at location 0x00000000.

Table 8: SYSMAP0 MMR Bit Designations

Bit Description

7-1 Reserved

These bits are reserved and should be written as 0 by user code

Remap Bit.

Set by the user to remap the SRAM to 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to 0x00000000.

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Preliminary Technical Data ADuC7032

ADUC7032 RESET

There are four kinds of reset: external reset, Power-on-reset, watchdog reset and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to ‘0’ by writing to the RSTCLR MMR at

Table 9 : Device RESET Implications

0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset event are tabulated in Table 9 b e low.

IMPACT

RESET

POR

Watchdog Reset

Software Reset

External Reset Pin

Note1: If LVF is enabled(HVCFG0[2]), RAM has not been corrupt by the POR reset mechanism if LVF Status bit HVSTA[6] is ‘1’.

Reset External Pins to Default State

    

     

Kernel Executed

Reset All External MMRs

(excluding RSTSTA)

RSTCLR Register :

Name : RSTCLR Address : 0xFFFF0234 Default Value : 0x00 Access : Write Only

Function : This 8-bit write only register clears the

corresponding bit in RSTSTA.

Reset All HV Indirect Registers

Peripherals Reset

RAM Valid

Note 1 RSTSTA[0] =1

RSTSTA

(Status after Reset Event)

RSTSTA[1] =1

RSTSTA[2] =1

RSTSTA[3] =1

RSTSTA Register :

Name : RSTSTA Address : 0xFFFF0230 Default Value : 0x01 Access : Read/Write Access

Function : This 8-bit register indicates the source of

the last reset event and can also be written by user code to initiate a software reset.

Table 10: RSTSTA/RSTCLR MMR Bit Designations

Bit Description

7-4 Not Used

These bits are not used and will always read as ‘0’

External Reset

Set to 1 automatically when an external reset occurs Cleared by setting the corresponding bit in RSTCLR

Software Reset

Set to ‘1’ by user code to generate a software reset. Cleared by setting the corresponding bit in RSTCLR

Watchdog timeout

Set to 1 automatically when a watchdog timeout occurs Cleared by setting the corresponding bit in RSTCLR

Power-on-reset

Set automatically when a power-on-reset occurs Cleared by setting the corresponding bit in RSTCLR

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Preliminary Technical Data ADuC7032

FLASH/EE MEMORY AND THE ADUC7032

The ADuC7032 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space.

Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer to the ideal memory device that includes non-volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7032 Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes.

Flash/EE Memory

The total 96kBytes of Flash/EE memory are organized as 48k X 16 bits. 94kBytes are user space and 2kBytes are reserved for boot loader/kernel space. The page size of this Flash/EE memory is 512Bytes. Typically, it takes the Flash/EE memory controller 20msec to erase a page, and 50µsec to write a 16-Bit word. These Flash/EE memory timings are independent of MCU core clock.

battery parameter data.

It is possible to write to a single 16 bit location only twice between erases, i.e. It is possible to walk bytes, not bits. If a location is written to more than twice, then it is possible that the contents of the Flash/EE page may be corrupted.

The 94kBytes of Flash/EE memory can be programmed incircuit, using a serial download mode via the LIN interface or the integrated JTAG port.

(1) Serial Downloading (In-Circuit Programming)

The ADuC7032 facilitates code download via the LIN pin.

(2) JTAG access

The ADuC7032 features an on-chip JTAG Debug Port to facilitate code download and debug.

FLASH/EE MEMORY CONTROL INTERFACE

The access to and control of the Flash/EE memory on the ADuC7032 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (0 and 1).

Block 0 consists of the 32KB Flash/EE memory mapped from 0x0009 0000 to 0x0009 7FFF (including the 2KB kernel space which is reserved at the top of this block).

94kBytes of Flash/EE memory are available to the user as code and non-volatile data memory. There is no distinction between data and program, as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE memory are necessary for each instruction fetch. When operating at speeds less than 20.48MHz the Flash/EE memory controller can transparently fetch the second 16-bit half word (part of the 32-bit ARM op-code) within a single core clock period. It is therefore recommend that for speeds less than

20.48MHz, i.e. CD > 0, that ARM mode is used. For 20.48MHz operation, i.e. CD = 0 , it is recommended to operate in THUMB mode.

The Flash/EE memory is physically located at 0x80000. Upon a hard reset it is logically mapped to 0x00000000. The factory default contents of all Flash/EE memory locations is 0xFF. Flash/EE memory may be read in 8/16/32 bit segments, and written in segments of 16 bits. The Flash/EE memory is rated for 10K endurance cycles. This rating is based on the number of times that each individual half word ( 16 bit location ) is cycled i.e. erased and programmed. A redundancy scheme may be implemented in software to ensure greater than 10K cycles endurance.

The user may also write data variables to the Flash/EE memory during run-time code execution, e.g. for storing diagnostic

Block 1 consists of the 64KB Flash/EE memory mapped from from 0x0008 0000 to 0x0008 FFFF.

It should be noted that MCU core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. If a command operates on the same block as the code currently executing, the core is halted until the command is completed, this also applies to code execution.

User Code, LIN and JTAG programming use the Flash/EE memory Control Interface, which consists of the following MMRs :

- FEExSTA (x= 0 or 1): read only register, reflects the status of the Flash Control Interface

- FEExMOD (x= 0 or 1): sets the operating mode of the Flash Control Interface

- FEExCON (x= 0 or 1): 8-bit command register. The commands are interpreted as described in Table 11.

- FEExDAT (x= 0 or 1): 16-bit data register.

- FEExADR (x= 0 or 1): 16-bit address register.

- FEExSIGN (x= 0 or 1): Holds the 24-bit code signature as a

result of the signature command being initiated.

- FEExHIDE (x= 0 or 1): Protection MMR. Controls read and write protection of the Flash memory code space. If previously configured via the FEEPRO register, FEEHIDE may require a software key to enable access.

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Preliminary Technical Data ADuC7032

- FEExPRO (x= 0 or 1): A buffer of the FEEHIDE register, which is used to store the FEEHIDE value, so it is automatically downloaded to the FEEHIDE registers on subsequent reset and power-on events.

NOTE: User Software must ensure that the Flash/EE memory

The following sections describe in detail the bit designations of each of Flash/EE control MMRs

controller has completed any Erase or Write cycle before the PLL is powered down. If the PLL is powered down before an Erase or Write cycle is

FEE0CON and FEE1CON Registers :

Name : FEE0CON and FEE1CON Address : 0xFFFF0E08 and 0xFFFF0E88 Default Value (both registers) : 0x07 Access : Read/Write Access

Function : These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for

Block0 (32KB) and Block1 (64KB).

Table 11: Command Codes in FEE0CON and FEE1CON

Code Command Description (note x is 0 or 1 to designate Flash/EE Block 0 or 1)

0x00* Reserved 0x01* 0x02* 0x03*

0x04*

0x05* 0x06*

Single Read Load FEExDAT with the 16-bit data indexed by FEExADR Single Write Erase-Write Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This

Single Verify Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the

Single Erase Erase the page indexed by FEExADR Mass erase

0x07 Default command. 0x08 0x09

Reserved

Reserved 0x0A Reserved 0x0B Signature FEE0CON:

0x0C Protect This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass

0x0D 0x0E

Reserved Reserved, this command should not be written by user code

0x0F Ping No operation, interrupt generated

The FEExCON will always read 0x07 immediately after execution of any of these commands.

Reserved, this command should not be written by user code

Write FEExDAT at the address pointed by FEExADR. This operation takes 50µs.

operation takes 20ms

comparison is returned in FEExSTA bit 1

Erase Block0(30kByte) or Block1(64kByte) of user space. The 2kByte Kernel is protected. This operation takes 1.2s To prevent accidental execution, a command sequence is required to execute this instruction, this is described below.

Reserved, this command should not be written by user code Reserved, this command should not be written by user code Reserved, this command should not be written by user code

This command will result in a 24-bit LFSR based signature been generated and loaded into FEE0SIG. If FEE0ADR is less than 0x97800, this command will result in a 24 bit LFSR based signature of the user code space from the page specified in FEE0ADR upwards, including the Kernel, security bits and Flash/EE key. If FEE0ADR is greater than 0x97800, the Kernel and manufacturing data is signed

FEE1CON: This command will result in a 24-bit LFSR based signature been generated, beginning at FEE1ADR and ending at the end of the 63.5k Block, and loaded into FEE1SIG. The last page of this block is not included in the Sign generation.

erase (0x06) or with the key

completed, the Flash/EE page or byte may be corrupted.

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Preliminary Technical Data ADuC7032

Command Sequence for executing a Mass Erase

Giving the significance of the ‘Mass Erase’ command, a specific code sequence must be executed to initiate this operation.

1. Set bit 3 in FEExMOD.

2. Write 0xFFC3 in FEExADR

3. Write 0x3CFF in FEExDAT

4. Run the Mass Erase command 0x06 in FEExCON

FEE0STA and FEE1STA Registers :

Name : FEE0STA and FEE1STA Address : 0xFFFF0E00 and 0xFFFF0E80 Default Value (both registers) : 0x00 Access : ReadOnly

This sequence is illustrated in the following example,:

FEExMOD= 0x08 FEExADR= 0xFFC3 FEExDAT= 0x3CFF FEExCON= 0x06; // Mass-Erase command while (FEExSTA & 0x04){} //Wait for command to finish

Note: To run the mass erase command via FEE0CON, Write protection on the lower 64kbytes must be disabled, i.e. FEE1HIDE/FEE1PRO are set to 0xFFFFFFFF.. This may be done be first removing the protection or erasing the lower 64kbytes first.

Function : These 8-bit read only registers can be read by user code and reflect the current status of the Flash/EE memory controllers.

Table 12: FEE0STA and FEE1STA MMR bit designations

Bit Description (note x is 0 or 1 to designate Flash/EE Block 0 or 1)

15-4 Not Used

These bits are not used and will always read as 0.

FEE0ADR and FEE1ADR Registers:

Name : FEE0ADR and FEE1ADR Address : 0xFFFF0E10 and 0xFFFF0E90 Default Value : Non Zero Access : Read/Write Access

Flash Interrupt Status Bit Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set Cleared automatically when the FEExSTA register is read by user code Flash/EE controller busy

Set automatically when the Flash/EE controller is busy Cleared automatically when the controller is not busy

Command fail

Set automatically when a command written to FEExCON completes unsuccessfully Cleared automatically when the FEExSTA register is read by user code

Command Successful

Set automatically by MCU when a command is completed successfully. Cleared automatically when the FEExSTA register is read by user code

FEE0DAT and FEE1DAT Registers:

Name : FEE0DAT and FEE1DAT Address : 0xFFFF0E0C and 0xFFFF0E8C Default Value : Non Zero Access : Read/Write Access

Function : This 16-bit register dictates the address

upon which any Flash/EE command executed via FEExCON will act upon.

Rev. PrD | Page 33 of 128

Function : This 16-bit register contains the data either

read from or to be written to the Flash/EE memory.

Preliminary Technical Data ADuC7032

FEE0MOD and FEE1MOD Registers :

Name : FEE0MOD and FEE1MOD Address : 0xFFFF0E04 and 0xFFFF0E84 Default Value (both registers) : 0x00 Access : Read/Write

Function : These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers.

Table 13: FEE0MOD and FEE1MOD MMR bit designations

Bit Description (note: x is 0 or 1 to designate Flash/EE Block 0 or 1)

15-7 Not Used

These bits are reserved for future functionality and should be written as 0 by user code 6, 5

Flash/EE Security Lock Bits

These bits must be written as [6,5] = 1,0 to complete the Flash security protect sequence

Flash/EE Controller Command Complete Interrupt Enable

This bit is set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE

command.

This bit is cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.

Flash/EE Erase/Write Enable

Set by user code to enable the Flash/EE erase and write access via FEExCON

Cleared by user code to disable the Flash/EE erase and write access via FEExCON

Reserved and should be written as zero

Flash/EE Controller Abort Enable

This bit is set to 1 by user code to enable the Flash/EE controller abort functionality.

Reserved and should be written as zero

FLASH/EE MEMORY SECURITY

The 94kByte of Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers.

In Block0, the FEE0HID MMR protects the 30kBytes. Bits 0-28 of this register protect pages 0-57 from writing. Each bit protects 2 pages, i.e. 1kBytes. Bits 29-30 protect pages 58 and 59 respectively, i.e. each bit write protects a single page of 512 bytes. The MSB of this register (Bit31) protects Block0 from been read via JTAG.

The FEE0PRO register mirrors the bit definitions of the FEE0HID MMR. The FEE0PRO MMR allows user code to lock the protection or security configuration of the Flash memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. This flexibility allows the user to set and test protection settings temporarily using the

FEE0HID MMR and subsequently lock the required protection configuration (using FEE0PRO) when shipping protection systems into the field.

In Block1 (64K), the FEE1HID MMR protects the 64kBytes. Bits 0-29 of this register protect pages 0-119 from writing. Each bit protects 4 pages, i.e. 2kBytes. Bit30 protect pages 120-127, i.e. bit 30 write protects eight pages of 512 bytes. The MSB of this register (Bit31) protects Flash/EE Block1, from been read via JTAG.

As with Block0, FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR is allows user code to lock the protection or security configuration of the Flash memory so that the protection configuration is automatically loaded on subsequent power-on or reset events.

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Preliminary Technical Data ADuC7032

Block0, Flash/EE Memory Protection Registers :

Name : FEE0HID and FEE0PRO Address : 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) Default Value (both registers) : 0xFFFFFFFF Access : Read/Write Access

Function : These registers are written by user code to configure the protection of the Flash/EE memory.

Table 14: FEE0HID and FEE0PRO MMR bit designations

Bit Description (note: x is 0 or 1 to designate Flash/EE Block 0 or 1)

28-0

Read protection

Cleared by user to protect the 32kbyte Flash/EE Block code via JTAG read access Set by user to allow reading the 32kbyte Flash/EE Block code via JTAG read access

Write Protection Bit This bit is set by user code to unprotect protect page 59 This bit is cleared by user code write protect page 59

Write Protection Bit This bit is set by user code to unprotect page 58 This bit is cleared by user code write protect page 58

Write Protection Bits When set by user code these bits will unprotect pages 0-57 of the 30KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes. When cleared by user code these bits will write protect pages 0-57 of the 30KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes.

Block1, Flash/EE Memory Protection Registers :

Name : FEE1HID and FEE1PRO Address : 0xFFFF0EA0 (for FEE0HID) and 0xFFFF0E9C (for FEE0PRO) Default Value (both registers) : 0xFFFFFFFF Access : Read/Write Access

Function : These registers are written by user code to configure the protection of the Flash/EE memory.

Table 15: FEE1HID and FEE1PRO MMR bit designations

Bit Description

29-0 Write Protection Bits

Read protection

Cleared by user to protect the 64kbyte Flash/EE Block code via JTAG read access Set by user to allow reading the 64kbyte Flash/EE Block code via JTAG read access

Read protection When set by user code these bits will protect pages 120-127 of the 64KB Flash/EE code memory. This bit write protects 8 pages and each page consists of 512 bytes. When cleared by user code these bits will write protect pages 120-127 of the 64KB Flash/EE code memory.This bit write protects 8 pages and each page consists of 512 bytes.

When set by user code these bits will unprotect pages 0-119 of the 64KB Flash/EE code memory. Each bit write protects 4 pages and each pages consists of 512 bytes. When cleared by user code these bits will write protect pages 0-119 of the 64KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes.

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Preliminary Technical Data ADuC7032

In Summary, there are three levels of protection:

- Temporary Protection can be set and removed by writing directly into FEExHID MMR. This register is volatile and therefore protection will only be in place while the part remains powered on. This protection is not reloaded after a power cycle.

- Keyed Permanent Protection can be set via FEExPRO which is used to lock the protection configuration. The software key used at the start of the required FEExPRO write sequence is saved once and MUST subsequently be used for any subsequent access of the FEExHID or FEExPRO MMRs. A mass erase will set the key back to 0xFFFF but will also erase the entire user code space.

- Permanent Protection can be set via FEExPRO, similarily to Keyed Permanent Protection, the only difference been that the software key used is 0xDEADDEAD. Once the FEExPRO write sequence is saved, only a mass erase will set the key back to 0xFFFFFFFF. This will also erase the entire user code space.

Sequence to write the key and set permanent protection:

1. Write in FEExPRO corresponding to the pages to be protected.

2. Write the new (user defined) 32 bit key in FEExADR [ Bits 31-16 ] and FEExDAT [ Bits 15-0 ].

3. Write 1,0 in FEExMOD[6:5] and set FEExMOD[3].

4. Run the write key command 0x0C in FEExCON.

To remove or modify the protection the same sequence can be used with a modified value of FEExPRO.

The sequence above is illustrated in the following example, this protects writing pages 4 and 5of the FLASH:

FLASH/EE MEMORY RELIABILITY

The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as:

1. Initial page erase sequence.

2. Read/verify sequence a single Flash/EE.

3. Byte program sequence memory.

4. Second read/verify sequence endurance cycle.

In reliability qualification, every half word (16-bit wide) location of the three pages(top, middle and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Table 1, the parts’ Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 . the results allow the specification of a minimum endurance figure over supply, temperature of 10,000 cycles.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts is qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature

J = 85°C). As part of this qualification procedure, the

(T Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Also note that retention lifetime, based on an activation energy of 0.6 eV, derates with T as shown in Figure 12.

600

FEExPRO =0xFFFFFFFB; //Protect pages 4 and 5 FEExADR =0x66BB; //32 bit key value [Bits 31-16] FEExDAT =0xAA55; //32 bit key value [Bits 15-0] FEExMOD = 0x0048 // Lock Security Sequence FEExCON = 0x0C; // Write key command while (FEExSTA & 0x04){} //Wait for command to finish

Rev. PrD | Page 36 of 128

450

300

RETENTIO N (Years)

150

30 40 55 70 85 100 125 135 150

JUNCTION TEM PERATURE (°C)

Figure 12. Flash/EE Memory Data Retention

04955-085

Preliminary Technical Data ADuC7032

CODE EXECUTION TIME FROM SRAM AND FLASH/EE

This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical.

Execution from SRAM

Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2ns and a clock cycle is 49ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM, or three cycle if the data is in Flash/EE, one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycle to fill the pipeline with the new instructions.

Execution from Flash/EE

Because the Flash/EE width is 16-bit, execution from Flash/EE cannot be done in one cycle, as from SRAM, when CD bit =0. Also some dead time is needed before accessing data for any value of CD bits.

In ARM mode, where instructions are 32 bits, two extra cycles are needed to fetch any instruction when CD = 0 and in Thumb mode, where instructions are 16 bits, one extra cycle is needed to fetch any instruction.

Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipe-line. A data processing instruction involving only core register doesn’t require any extra clock cycle but if it involves data in Flash/EE,

an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarized Table 16.

Table 16: Typical execution cycles in ARM/Thumb mode

Instructions

LD 2/1

LDH 2/1

LDM/POP 2/1

STR 2/1

STRH 2/1

STM/PUSH 2/1

With 1<N≤16, N number of data to load or store in the multiple load/store instruction.

By default, Flash/EE code execution will be suspended during any Flash/EE erase or write cycle. A page (512 Bytes) erase cycle will take 20 ms and a write (16 bits) word command will take 50us. However, the FLASH/EE controller allows Erase/Write cycles to be aborted, if the ARM core receives an enabled interrupt during the current FLASH/EE Erase/Write cycle. The ARM7 can therefore immediately service the interrupt and then return to repeat the FLASH/EE command. The Abort operation will typically take 10 clock cycles. If the abort operation is not feasible, it is possible to run FLASH/EE programming code and the relevant interrupt routines from SRAM, allowing the core to service the Interrupt immediately.

Fetch cycles

Dead time

1 2

1 1

N 2 x N

Data access

2 x 50µs 50µs 2 x N x 50µs

Rev. PrD | Page 37 of 128

Preliminary Technical Data ADuC7032

ADUC7032 KERNEL

The ADuC7032 features an on-chip Kernel resident in the top 2k of the Flash/EE Code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space, into the various on-chip peripherals. The peripherals calibrated by the Kernel are:

- PSM Power Supply Monitor

- Precision, Oscillator

- Low Power, Oscillator

- REG_AVDD/ REG_DVDD

- Low Power Voltage Reference

- Normal Mode Voltage Reference

- Current ADC ( Offset and Gain )

- Voltage ADC ( Offset and Gain )

- Temperature ADC ( Offset and Gain )

User MMRs which may be modified by the kernel and differ from their POR default values are as follows:

- R0-R15

- GP0CON/GP2CON

- SYSCHK

- ADCMDE/ADC0CON

- FEE0ADR/FEE0CON/FEESIG

- HVDAT/HVCON

- HVCFG0/1

- T3LD

The ADuC7032 also features an On-Chip LIN downloader. The operation of this download is detailed in “ADuC7032Series Flash/EE Programming via LIN” Technote.

A flow chart showing the execution of the kernel is shown in Figure 13.

The current revision of the Kernel may be derived from SYSSER1, as described in Table 85.

For the duration of Kernel execution, the Watchdog Timer is active with a timeout period of 30ms. This ensures that if an error occurs in the Kernel, the ADuC7032 will be reset. After any reset, the Watchdog timer is disabled once the Kernel code is exited.

Normal Kernel execution time, excluding LIN Download, is approximately 5ms.

It is only possible to leave LIN download mode via a Reset.

SRAM is not corrupted during normal Kernel execution. SRAM is corrupted during LIN download Kernel execution.

User code will not be executed unless location 0x14

NOTE:

contains either 0x27011970 or the checksum of Page Zero, excluding location 0x14. If location 0x14 does not contain this information user code will not be executed and LIN download mode will be entered. For more information please refer to the relevant LIN download Technote.

Rev. PrD | Page 38 of 128

Preliminary Technical Data ADuC7032

INITIALIZE ON-CHIP

PERIPHERALS T O FACTORY

CALIBRATED STAT E

PAGE ERASED?

0x14 = 0xfffffff f

YES

LIN COMMAND

NO YES

YES

JTAG MODE?

NTRST = 1

KEY PRESENT?

0x14 = 0x27011970

CHECKSUM PRESENT?

0x14 = CHECKSUM

FLAG PAGE 0 ERROR

RESET

COMMAND

YES

EXECUTE

USER CODE

Figure 13: ADuC7032 Kernel Flowchart

05994-013

Rev. PrD | Page 39 of 128

Preliminary Technical Data ADuC7032

MEMORY MAPPED REGISTERS

The Memory Mapped Register (MMR) space is mapped into the top 4kBytes of the MCU memory space and accessed by indirect addressing, load and store commands, through the ARM7 banked registers. An outline of the ADuC7032s Memory Mapped Register Bank is shown in Figure 14.

The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the ARM7 core registers (described in ARM Registers) reside in the MMR area.

As can be seen from the detailed MMR map in Table 17, the MMR data widths vary from 1 Byte (8 bits) to 4 Bytes (32 bits). The ARM7 core can access any of the MMRs (single byte or multiple byte width registers) with a 32 bit read or write access. The resultant read for example, aligned per ‘little endian’ format described earlier. However, errors will result if the ARM7 core tries to access 4 Byte (32 bit) MMRs with a 16-bit access. In the case of a (16-bit) write access to a 32-bit MMR, the (upper) 16 most significant bits will be written as 0’s. More obviously, in the case of a 16-bit read access to a 32-bit MMR, only 16 of the MMR bits can be read.

0xFFFFFFFF

0xFFFF 1000

0xFFFF0E00

0xFFFF0D50

0xFFFF0D00

0xFFFF0A14

0xFFFF0A00

0xFFFF 0894

0xFFFF 0880

0xFFFF 0810

0xFFFF 0800

0xFFFF079C

0xFFFF 0780

0xFFFF 0730

0xFFFF 0700

0xFFFF 0568

0xFFFF 0500

0xFFFF044C

0xFFFF 0400

0xFFFF 0394

0xFFFF 0380

0xFFFF 0370

0xFFFF 0360

0xFFFF 0350

0xFFFF 0340

0xFFFF 0334

0xFFFF 0320

0xFFFF 0318

0xFFFF 0300

0xFFFF 0244

0xFFFF 0220

0xFFFF 0110

0xFFFF 0000

FLASH CONTRO L

INTERFACE

GPIO

SPI

SERIAL TEST

INTERFACE

HV INTERFACE

LIN/BSD

HARDWARE

UART

ADC

PLL AND

OSCILLATOR CONTROL

GENERAL PURPO SE

TIMER 4

WATCHDOG

TIMER 3

WAKE UP

TIMER 2

GENERAL PURPO SE

TIMER 1

TIMER 0

REMAP AND

SYSTEM CONT ROL

INTERRUPT

CONTROLL ER

Figure 14: Top Level MMR Map

05994-014

Rev. PrD | Page 40 of 128

Preliminary Technical Data ADuC7032

Table 17 : Complete MMR List

Address Name Byte

Access

Typ e

IRQ address base = 0xFFFF0000

0x0000 IRQSTA 4 R

0x0004 IRQSIG1 4 R

0x0008 IRQEN 4 RW

0x000C IRQCLR 4 W

0x0010 SWICFG 4 W

0x0100 FIQSTA 4 R

0x0104 FIQSIG1 4 R

0x0108 FIQEN 4 RW

0x010C FIQCLR 4 W

System Control address base = 0xFFFF0200 0x0220 SYSMAP0 1 RW

0x0230

0x0234

0x0238

0x023C

0x0240

RSTSTA 1 RW

RSTCLR 1 W

SYSSER0

SYSSER1

SYSCHK

4 RW

Timer address base = 0xFFFF0300 0x0300 T0LD 4 RW

0x0304 T0VAL0 2 R

0x0308 T0VAL1 4 R

0x030C T0CON 2 RW

0x0310 T0CLRI 1 W

0x0314 T0CAP 2 RW

0x0320 T1LD 4 RW

0x0324 T1VAL 4 R

0x0328 T1CON 2 RW

0x032C T1CLRI 1 W

0x0330 T1CAP 4 RW

0x0340 T2LD 4 RW

0x0344 T2VAL 4 R

0x0348 T2CON 2 RW

0x034C T2CLRI 1 W

0x0360 T3LD2 2 RW

0x0364 T3VAL2 2 R

Default

Value

0x00000000

Page

Description

Active IRQ Source

Current State of all IRQ sources ( Enabled and Disabled )

Enabled IRQ sources

MMR used to disabled IRQ Sources

76 Software Interrupt Configuration MMR

0x00000000

Active IRQ Source

Current State of all IRQ sources ( Enabled and Disabled )

Enabled IRQ sources

MMR used to disabled IRQ Sources

29 REMAP control Register

0x01 30 Reset Status MMR

0x00 30 RSTSTA clear MMR

125 SYSTEM Serial Number 0

126 SYSTEM Serial Number 1

126 Kernel Checksum

0x00000000 79 Timer 0 Load Register

0x0000 78 Timer 0 Value Register 0

0x00000000 78 Timer 0 Value Register 1

0x0000 79 Timer 0 Control MMR

0xFF 79 Timer 0 Interrupt Clear Register

0x0000 78 Timer 0 Capture Register

0x00000000 80 Timer 1 Load Register

0xFFFFFFFF 80 Timer 1 Value Register

0x0000 81 Timer 1 Control MMR

0xFF 80 Timer 1 Interrupt Clear Register

0x00000000 81 Timer 1 Capture Register

0x00000000 82 Timer 2 Load Register

0xFFFFFFFF 82 Timer 2 Value Register

0x00 83 Timer 2 Control MMR

0xFF 82 Timer 2 Interrupt Clear Register

84 Timer 3 Load Register

84 Timer 3 Value Register

Rev. PrD | Page 41 of 128

Preliminary Technical Data ADuC7032

0x0368 T3CON2 2 RW

0x036C T3CLRI2 1 W

PLL base address = 0xFFFF0400 0X0400 PLLSTA 4 RW

0x0404 POWKEY0 4 W

0x0408 POWCON 1 RW

0x040C POWKEY1 4 W

0x0410 PLLKEY0 4 W

0x0414 PLLCON 1 RW

0x0418 PLLKEY1 4 W

0x042C OSC0TRM 1 RW

0x0440 OSC0CON 1 RW

0x0444 OSC0STA 1 R

0x0448 0SC0VAL0 2 R

0x044C OSC0VAL1 2 R

ADC address base = 0xFFFF0500 0x0500 ADCSTA 2 R

0x0504 ADCMSKI 1 RW

0x0508 ADCMDE 1 RW

85 Timer 3 Control MMR

85 Timer 3 Interrupt Clear Register

0x02 69 PLL Status MMR

70 POWCON Pre Write Key

0x79 71 Power Control and Core speed Control Register

70 POWCON Post Write Key

70 PLLCON Pre Write Key

0x00 70 PLL clock source selection MMR

70 PLLCON Post Write Key

0x08 73 Low Power Oscillator trim bits MMR.

0x00 73 Low Power Oscillator Calibration Control MMR

0x00 74 Low Power Oscillator Calibration Status MMR

0x00 74 Low Power Oscillator Calibration Counter 0 MMR

0x00 74 Low Power Oscillator Calibration Counter 1 MMR

0x0000 49 ADC Status MMR

0x00 50 ADC Interrupt Source Enable MMR

0x00 51 ADC Mode Register

0x050C ADC0CON 2 RW

0x0510 ADC1CON 2 RW

0x0514 ADC2CON 2 RW

0x0518 ADCFLT 2 RW

0x051C ADCCFG 1 RW

0x0520 ADC0DAT 2 R

0x0524 ADC1DAT 2 R

0x0528 ADC2DAT 2 R

0x052C ADCFIFO 4 R

0x0530 ADC0OF2 2 RW

0x0534 ADC1OF2 2 RW

0x0538 ADC2OF2 2 RW

0x053C ADC0GN2 2 RW

0x0540 ADC1GN2 2 RW

0x0544 ADC2GN2 2 RW

0x0548 ADC0RCL 2 RW

0x0000 52 Current ADC Control MMR

0x0000 53 Voltage ADC Control MMR

0x0000 54 Temperature ADC Control MMR

0x0007 55 ADC Filter Control MMR

0x00 57 ADC Configuration MMR

0x0000 58 Current ADC Result MMR

0x0000 58 V ADC Result MMR

58 Current/Voltage Result FIFO

58 Current ADC Offset MMR

58 Voltage ADC Offset MMR

58 Temperature ADC Offset MMR

59 Current ADC Gain MMR

59 Voltage ADC Gain MMR

59 Temperature ADC Gain MMR

0x0001 59 Current ADC Result Count Limit

0x054C ADC0RCV 2 R

0x0550 ADC0TH 2 RW

0x0000 59 Current ADC Result Count Value

0x0000 59 Current ADC Result Threshold

Rev. PrD | Page 42 of 128

Preliminary Technical Data ADuC7032

0x0554 ADC0TCL 1 RW

0x01 59 Current ADC Result Threshold Count Limit

0x0558 ADC0THV 1 R

0x055C ADC0ACC 4 R

0x0560 ADC0ATH 4 RW

0x057C ADCREF2 4 R

UART BASE ADDRESS = 0XFFFF0700 0x0700 COMTX 1 W

COMRX 1 R

COMDIV0 1 RW

0x0704 COMIEN0 1 RW

COMDIV1 1 R/W

0x0708 COMIID0 1 R

0x070C COMCON0 1 RW

0x0710 COMCON1 1 RW

0x0714 COMSTA0 1 R

0X072C COMDIV2 2 RW

LIN Hardware Sync base address = 0XFFFF0780 0x0780 LHSSTA 1

0x0784 LHSCON0 2

0x0788 LHSVAL0 2

0x078C LHSCON1 1

0x0790 LHSVAL1 1.5

High Voltage Interface base address = 0xFFFF0800 0x0804 HVCON 1 RW

0x080C HVDAT 1.5 RW

SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 R

0x0A04 SPIRX 1 R

0x0A08 SPITX 1 W

0x0A0C SPIDIV 1 RW

0x0A10 SPICON 2 RW

GPIO base address = 0xFFFF0D00 0x0D 00 GP0CON 4 RW

0x0D 04 GP1CON 4 RW

0x0D 08 GP2CON 4 RW

0x0D 20 GP0DAT3 4 RW

0x0D 24 GP0SET3 4 W

0x0D 28 GP0CLR3 4 W

0x0D 30 GP1DAT3 4 RW

0x0D 34 GP1SET3 4 W

R 0x00 116 LHS Status MMR

R/W 0x0000 117 LHS Control MMR 0

R/W 0x0000 118 LHS Timer 0 MMR

R/W 0x32 118 LHS Control MMR 1

R/W 0x0000 119 LHS Timer 1 MMR

0x00 60 Current ADC Result Threshold Count Limit Value

0x00000000 60 Current ADC Result Accumulator

0x00000000 60 Current ADC Result Accumulator Threshold

60 Low Power Mode Voltage Reference Scaling Factor

0x00 107 UART Transmit Register

107 UART Receive Register

107 UART Standard Baud Rate Generator Divisor Value 0

0x00 110 UART Interrupt Enable MMR 0

107 UART Standard Baud Rate Generator Divisor Value 1

0x01 110 UART Interrupt Identification 0

0x00 108 UART Control Register 0

0x00 109 UART Control Register 1

0x60 109 UART Status Register 0

0x0000 111 UART Fractional Divider MMR

99 High Voltage Interface Control MMR

99 High Voltage Interface Data MMR

0x00 114 SPI Status MMR

0x00 114 SPI Receive MMR

0x00 114 SPI Transmit MMR

0x1B 114 SPI Baud Rate Select MMR

0x00 113 SPI Control MMR

0x00000000 88 GPIO Port 0 Control MMR

0x00000000 89 GPIO Port 1 Control MMR

0x00000000 89 GPIO Port 2 Control MMR

0x000000XX 90 GPIO Port 0 Data Control MMR

0x000000XX 93 GPIO Port 0 Data Set MMR

0x000000XX 95 GPIO Port 0 Data Clear MMR

0x000000XX 91 GPIO Port 1 Data Control MMR

0x000000XX 94 GPIO Port 1 Data Set MMR

Rev. PrD | Page 43 of 128

Preliminary Technical Data ADuC7032

0x0D 38 GP1CLR3 4 W

0x0D 40 GP2DAT3 4 W

0x0D 44 GP2SET3 4 W

0x0D 48 GP2CLR3 4 W

Flash/EE base address = 0xFFFF0E00 0x0E00 FEE0STA 1 R

0x0E04 FEE0MOD 2 RW

0x0E08 FEE0CON 1 RW

0x0E0C FEE0DAT 2 RW

0x0E10 FEE0ADR 2 RW

0x0E18 FEE0SIG 3 R

0x0E1C FEE0PRO 4 RW

0x0E20 FEE0HID 4 RW

0x0E80 FEE1STA 1 R

0x0E84 FEE1MOD 2 RW

0x0E88 FEE1CON 1 RW

0x0E8C FEE1DAT 2 RW

0x0E90 FEE1ADR 2 RW

0x0E98 FEE1SIG 3 R

0x0E9C FEE1PRO 4 RW

0x0EA0 FEE1HID 4 RW

Depends on the level on the external interrupt pins GP0, GP5, GP7 and GP8

Updated by Kernel

Depends on the level on the external GPIO pins

0x000000XX 95 GPIO Port 1 Data Clear MMR

0x000000XX 92 GPIO Port 2 Data Control MMR

0x000000XX 94 GPIO Port 2 Data Set MMR

0x000000XX 96 GPIO Port 2 Data Clear MMR

0x00 33 Flash/EE Status MMR

0x00 34 Flash/EE Control MMR

0x07 32 Flash/EE Control MMR

33 Flash/EE Data MMR

33 Flash/EE Address MMR

0xFFFFFF Flash/EE LFSR MMR

0x00000000 35 Flash/EE Protection MMR

0xFFFFFFFF 35 Flash/EE Protection MMR

0x00 33 Flash/EE Status MMR

0x00 34 Flash/EE Control MMR

0x07 32 Flash/EE Control MMR

33 Flash/EE Data MMR

33 Flash/EE Address MMR

0x0000 Flash/EE LFSR MMR

0x00000000 35 Flash/EE Protection MMR

0xFFFFFFFF 35 Flash/EE Protection MMR

Rev. PrD | Page 44 of 128

Preliminary Technical Data ADuC7032

16-BIT Σ−∆ ANALOG TO DIGITAL CONVERTERS

The ADuC7032 incorporates three independent sigma-delta ADCs namely, the Current Channel ADC (I-ADC), the Voltage Channel ADC (V-ADC) and the Temperature Channel ADC (T-ADC). These precision measurement channels integrate onchip buffering, programmable gain amplifier, 16-bit sigmadelta modulators and digital filtering and are intended for the precision measurement of current, voltage and temperature variables in 12V automotive battery systems.

CURRENT CHANNEL ADC (I-ADC)

This ADC is intended to convert battery current sensed through an external 100μΩ shunt resistor. On-Chip programmable gain mean the I-ADC can be configured to accommodate battery current levels from ±1A to ±1500A

As shown in Figure 15 below, the I-ADC employs a sigma-delta conversion technique to realize 16 bits of no missing codes performance. The sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains

the digital information. A modified Sinc3 programmable lowpass filter is then employed to decimate the modulator output data stream to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz in Normal mode and 1Hz to 2kHz in Low Power Mode.

The I-ADC also incorporates counter, comparator and accumulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions have elapsed or if the I-ADC result exceeds a programmable threshold value. A fast ADC-Over-Range feature is also supported. Once enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results.

The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on.

Diagnosti c Current So urces

Two 50uA IIN+ and IIN-

IN+

IN-

VREF/ 136

GND

ANALOG INPUT

Current Sour ces

REG_AVDDREG_AVDD

ANALOGINPUT

Diagnostic Voltage Source

VREF/136 Voltage Input

ANALOG INPUT

PROGRAMM ABLE

CHOPPING

THE INPUTSARE

ALTERNATELY REVERSED

THROUGH THE

CONVERSION CYCLE.

BUFFER AMPLIFIER

THE BUFFER AMPLIFIER

PRESENTS A HIGH

IMPEDANCE INPUT STAGE FOR THEPGA DRIVING THE SIGMA_DELTA MODULATOR.

PROGRAMMABLE GA IN

AMPLIFIER

THE PROGRAMMAB LE

GAIN AMPLIFIER ALLOWS

EIGHT BIPOLAR INPUT

RANGES FROM ±2.3mV TO

±1.2V (INT V

REF

PGA

BUF

CHOP

PRECISION

REFERENCE

THE INTERNAL 5PPM/C

REFERNCE IS ROUTEDTO THE ADC BY DEFAULT. AN EXTERNAL REFRENCEON THE VREF PIN CAN

ALSO BE SELECTED

THE SINC3FILTER REMOVES

QUANTIZATIONNOISE INTRODUCED

BY THE MODULATOR. THE UPDATE

RATE AND BANDWIDTH OF THIS

FILTERARE PROGRAMMABLE

Figure 15: Current ADC, Top Level Overview

THE MODULATOR PROVIDES

DATA STREAM (THE OUTPUT

OF WHICH IS ALSO CHOPPED)

THE DUTY CYCLEOF WHICH

REPRESENTS THESAMPLED

=1.2V).

SIGMADELTA

MODULATOR

INTERNAL

REFERNCE

VREF

PROGRAMMABLE

DIGITAL FIL TER

VIA THE ADCFLT MMR

SIGMA-DELTA

MODULATOR

AHIGHFREQUENCY1-BIT

TO THE DIGITAL FILTER,

ANALOG INPUT VOLTAGE.

SIGMA-DELTA A/D CONVERTER

PROGRAMMABLE

DIGITAL

FILTER

OUTPUT SC ALING

THE OUPUT WORD FROM THE

DIGITAL FILTER IS SCALED

BY THE CALIBRATION

COEFFICIENTS BEFORE

BEING PROVIDED AS

THE CONVERSION RESULT.

DIGITAL COMPARATOR

THE ADC RESULT IS

COMPARED TO A PRESET

SIGMA-DELTA ADC

THE SIGMA-DELTA

ARCHITECTURE ENSURES

16 BITS NO MISSING

CODES.

CHOP

OFFSET

COEFFICIENT

GAIN

COEFFICIENT

THRESHOLD

OUTPUT AV ERAGE

AS PART OFTHE CHOPPING

IMPLEMENTATION, EACH

DATA-WORD OUTPUT

FROM T HE FIL TER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR

OUTPUT

AVERAGE

OUTPUT FORMAT

ADC

RESULT

ADC

THRESHOLD

THRESHOLD COUNTER

COUNTS UP IFADC

RESULT>THRESHOLD

COUNTS DOWN/RESET IF ADC

RESULT<THRESHOL. GENER-

ATES AN INTERRUPT ON

COUNTER OVERFLOW

ADC ACCUMUL ATOR

ACCUMULATES THE ADC

RESULT

ADC RESULT

ACCUMULATOR

RESULT

ADC RESULT

COUNTER

THRESHOLD

COUNTER

ADC

ADC FAST OVER-RANGE

GENERATES AN ADC

INTERRUPT IF THE CURRENT

INPUT IS GROSSLY

OVER-RANGED

ADC INTERRUPT GENERATOR

GENERATES AN ADC RESULT

FROM ANY ONE OF FOUR

SOURCES

ADC RESULT COUN TER

COUNTS ADC RESULTS,

GENERATES AN INTERRUPT

ON COUNTERO VERFLOW

ADC

INTERRUPT

Rev. PrD | Page 45 of 128

Preliminary Technical Data ADuC7032

VOLTAGE CHANNEL ADC (V-ADC)

This ADC is intended to convert battery voltage As with the Current Channel ADC described previously, this ADC employs an identical sigma-delta conversion technique, including a modified Sinc3 low-pass filter to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz. An external RC filter network is not required as this is implemented internally in the voltage channel.

The external battery voltage (VBAT) is routed to the ADC input via an on-chip high voltage, resistive attenuator This must be enabled/disabled via HVCFG1[7].

The time to a first valid (fully settled) result on the voltage channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on.

This ADC is again buffered but unlike the current channel has a fixed VBAT input range of 0 V to 28.8V (assuming an internal 1.2V reference). A top level overview of this ADC signal chain is shown in Figure 16 below.

TEMPERATURE CHANNEL ADC (T-ADC)

This ADC is intended to convert battery temperature. The battery temperature can be derived via the on-chip temperature sensor or an external temperature sensor input.

The time to a first valid (fully settled) result after an input channel switch on the temperature channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on.

As with the Current and Voltage Channel ADCs, this ADC employs an identical sigma-delta conversion technique, including a modified Sinc3 low-pass filter to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz

VBAT

DIFFERENT IAL

ATTENUATOR

DIVIDE BY 24,INPUT

ATTENUATOR

45R

BUF

ALTERNATELY REVERSED

CONVERSION CYCLE.

CHOP

BUFFER AMPLIFIER

THE BU FFER AMP LIFIER

PRESENTS A HIGH

IMPEDANCE INPUT STAGE

FOR THE ANALOG INPUT.

THE INTERNAL 5PPM/C

REFERNCE IS ROUTED TO THE ADC BY DEFAULT.AN EXTERNAL REFRENCEON THE VREF PINCAN

ALSO BE SELECTED

Figure 16 : Voltage/ Temperature ADC, Top Level Overview

ANALOG INPUT

PROGRAMM ABLE

CHOPPING

THE INPUTS ARE

THROUGH THE

PRECISION

REFERENCE

PROGRAMMABLE

DIGITAL FILTER

THE SINC3FILTER REMOVES QUANTIZATION NOISEINTRODUCED BY THE MODULATOR. THE UPDATE

RATE AND BANDWIDTH OF THIS

FILTER ARE PROGRAMMABLE

VIA THE ADCFLT MMR

SIGMA-DELTA

MODULATOR

THE MODULATOR PROVIDES

AHIGHFREQUENCY1-BIT

DATA STREAM (THE OUTPUT

OF WHICH IS ALSOCHOPPED)

TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED

ANALOG INPUT VOLTAGE.

SIGMA-DELTA A/D CONVERTER

SIGMADELTA

MODULATOR

INTERNAL

REFERNCE

VREF

PROGRAMMABLE

SIGMA-DELTA ADC

THE SIGMA-DELTA

ARCHITECTURE ENSURES

16 BIT S NO MIS SING

DIGITAL

FILTER

OFFSET

COEFFICIENT

GAIN

COEFFICIENT

OUTPUT SCALING

THE OUPUT WORDFROM THE

DIGITAL FILTER ISSCALED

BY THE CALIBRATION

COEFFICIENTS BEFORE

BEING PROVIDED AS

THE CONVERSION RESULT.

ADC RESULT

FINAL (16-BIT) ADC RESULT

CODES.

CHOP

AS PART OF THE CHOPPING

IMPLEMENTATION, EACH

SUMMED AND AVERAGED WITH ITS PRE DECESSOR

OUTPUT

AVERAGE

OUTPUT FORMAT

ADC

RESULT

OUTPUT AVE RAGE

DATA-WORD OUTPUT

FROM T HE FILTER IS

Rev. PrD | Page 46 of 128

Preliminary Technical Data ADuC7032

ADC GROUND SWITCH

The ADuC7032 features an integrated ground switch pin, GND_SW located on Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground, or a connection to ground via a 20kΩ, this additional resistor may be used to reduce the number of external components required for an NTC circuit.

The ground switch feature may be used for reducing power consumption on application specific boards..

An example application is shown in Figure 17. This diagram shows an external NTC used in two modes, one using the internal 20kΩ resistor, and the second showing a direct connection to ground, via the GND_SW. ADCCFG[7] controls the connection of the ground switch to ground and ADCMDE[6] controls the GND_SW resistance.

REG_AVDD

REF

VTEMP

NTC

20kΩ

Figure 17 : Example External Temperature Sensor Circuits

NTC

REG_AVDD

VTEMP

05994-017

The possible combinations are shown in Table 18.

Table 18 : GND_SW Configuration

ADCCFG[7] ADCMDE[6] GND_SW

0 0 Floating

0 1 Floating

1 0 Direct connection to Ground

1 1

GND_SW

Figure 18: Internal Ground Switch Configuration

Connected to ground via 20kΩ

resistor

ADCCFG[7]

20kΩ

ADCMDE[6]

05994-018

Rev. PrD | Page 47 of 128

Preliminary Technical Data ADuC7032

ADC NOISE PERFORMANCE TABLES

Table 19, Table 20 and Table 21 below show the output RMS noise in μV for some typical output update rates on the I and V/T ADCs. The numbers are typical and are generated at a differential input voltage of 0 V The output RMS noise is specified as the standard deviation (or 1 X Sigma) of the distribution of ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as µV RMS.

Table 19 : Current Channel ADC, Normal Power Mode, Typical Output RMS Noise (µV)

Data

ADCFLT

0xBF1D 4Hz 0.040 0.040 0.043 0.087 0.087 0.175 0.35 0.7 2.8 2.8

0x961F 10Hz 0.060 0.060 0.060 0.087 0.087 0.175 0.35 0.7 2.8 2.8

0x007F 50Hz 0.142 0.142 0.144 0.145 0.170 0.305 0.380 0.7 2.8 2.8

0x0007 1KHz 0.620 0.620 0.625 0.625 0.770 1.310 1.650 2.520 7.600 7.600

Update

Rate

±2.3mV

(512)

±4.6mV

(256)

±4.68mV

(128)

±18.75mV

(64)

ADC Input Range

±37.5mV

(32)

±75mV

(16)

±150mV

(8)

±300mV

(4*)

±600mV

(2*)

±1.2V

(1*)

0x0000 8KHz 2.000 2.000 2.000 2.000 2.650 4.960 8.020 15.0 55.0 55.0

*Please note that the maximum absolute input voltage allowed is -200mV to 300mV relative to ground

Table 20 : Voltage Channel ADC, Typical Output RMS Noise (referred to ADC Voltage attenuator Input)(µV)

Data

ADCFLT

Update

Rate

0xBF1D 4Hz 65

0x961F 10Hz

0x0007 1KHz

0x0000 8KHz

Table 21 : Temperature Channel ADC, Typical Output RMS Noise (µV)

Data

ADCFLT

Update

Rate

0xBF1D 4Hz

28.8V ADC

Input

Range

180

1600

0-1.2V

ADC

Input

Range

2.8

0x961F 10Hz

0x0007 1KHz

0x0000 8KHz

Rev. PrD | Page 48 of 128

2.8

7.5

Preliminary Technical Data ADuC7032

ADC MMR INTERFACE

The ADC is controlled and configured via a number of MMRs that are described in detail in the following pages:

ADC Status Register :

Name : ADCSTA Address : 0xFFFF0500 Default Value : 0x0000 Access : Read Only Function : This read only register holds general status information related to the mode of operation or current status of the

ADuC7032ADCs.

Table 22 : ADCSTA MMR Bit Designations

Bit Description

15 ADC Calibration Status

This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to.

14 ADC Temperature Conversion Error

This bit is set automatically in hardware to indicate that a temperature conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.

13 ADC Voltage Conversion Error

This bit is set automatically in hardware to indicate that a voltage conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.

12 ADC Current Conversion Error

This bit is set automatically in hardware to indicate that an a current conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.

Not Used This bit is reserved for future functionality and should not be monitored by user code

9 ADCFIFO Error Flag

This bit is set to 1 automatically to indicate that the FIFO has overflowed. This bit does not cause an interrupt but is latched high and can only be cleared by disabling the FIFO or reconfiguring the ADC.

This bit will read 0 is the FIFO is disabled or if the FIFO has not overflowed.

8 ADC FIFO Empty Flag

This bit is set to 1 automatically to indicate the ADC FIFO is empty. It is a flag bit only and cannot generate an interrupt. This bit reads 0 if the ADC FIFO is disabled.

7 ADC FIFO Full Flag

This bit is set to 1 automatically to indicate the ADC FIFO is full and any subsequent I and V ADC conversion results will overflow and corrupt the ADC FIFO. This bit is cleared by disabling the FIFO or reconfiguring the ADC.

6 Accumulator Comparator Threshold Exceeded

This bit indicates that the absolute value of the Current Channel Accumulator has exceeded the programmed threshold.

This bit is cleared by disabling the Accumulator Comparator function in ADCCFG[6,5] or by reconfiguring the ADC.

Not Used This bit is reserved for future functionality and should not be monitored by user code

Rev. PrD | Page 49 of 128

Preliminary Technical Data ADuC7032

4 Current Channel ADC Comparator Threshold

This bit is only valid if the Current Channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is used (ADC0TCL), this bit is only set once the specified number of I-ADC conversions equals the value in the ADC0THV MMR.

3 Current Channel ADC Over-Range Bit

If the Over-Range Detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the I-ADC input is grossly (>30% approx.) over-ranged. This bit is updated every 125usecs. Once set, t

ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR.

2 Temperature Conversion Result Ready Bit

If the Temperature Channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in the temperature data register (ADC2DAT MMR) This bit is cleared by reading either ADC2DAT or ADC0DAT.

1 Voltage Conversion Result Ready Bit

If the Voltage Channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the voltage data register (ADC1DAT MMR) This bit is cleared by reading either ADC1DAT or ADC0DAT.

0 Current Conversion Result Ready Bit

If the Current Channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the current data register (ADC0DAT MMR) This bit is cleared by reading ADC0DAT.

his bit can only be cleared by software when

NOTES

1. All bits defined in the top 8 MSBs (bits 8–15) of the MMR are used as flags only and will not generate interrupts

2. All bits defined in the lower 8 LSBs (bits 0-7) of this MMR are logic OR’ed to produce a single ADC interrupt to the MCU core.

3. In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt.

4. Each ADC interrupt source can be individually masked via the ADCMSKI MMR described below

5. All ADC Result Ready bits are cleared by a read of the ADC0DAT MMR. If the Current Channel ADC is not enabled, all ADC

Result Ready bits are cleared by a read of the ADC1DAT or ADC2DAT MMRs.

6. To ensure that I-ADC, V-ADC and T-ADC conversion data are synchronous, user code should first read the ADC2DAT/ADC1DAT MMRs and then ADC0DAT MMR.

7. New ADC conversion results will not be written to the ADCxDAT MMRs unless the respective ADC Result Ready bits are first cleared. The only exception to this rule is data conversion result updates when the ARM core is powered down. In this modes ADCxDAT registers will always contain the most recent ADC conversion result even though the Ready bits have not been cleared.

ADC Interrupt Mask Register :

Name : ADCMSKI Address : 0xFFFF0504 Default Value : 0x00 Access : Read/Write

Function : This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the

same as the lower 8-bits in the ADCSTA MMR. If a bit is set by user code to a ‘1’, the respective interrupt is enabled. By default all bits are ‘0’ meaning all ADC interrupt sources are disabled.

Rev. PrD | Page 50 of 128

Preliminary Technical Data ADuC7032

ADC Mode Register :

Name : ADCMDE Address : 0xFFFF0508 Default Value : 0x00 Access : Read/Write

Function : The ADC Mode MMR is an 8-bit register that configures the mode .of operation of the ADC sub-system

Table 23 : ADCMDE MMR Bit Designations

Bit Description

7 Not Used

This bit is reserved for future functionality and be written as 0 by user code

20KΩ resistor select:

This bit is set to 1 to select the 20 KΩ resistor as shown in Figure 18 This bit is set to 0 to select the direct path to ground as shown in Figure 18 ( Default ).

5 Low Power Mode Reference Select:

This bit is set to 1 to enable the Precision Voltage Reference in ADC Low Power Mode. This will increase current consumption. This bit is set to 0 to enable the Low Power Voltage Reference in ADC Low Power Mode ( Default ).

4-3 ADC Power Mode Configuration

0, 0 ADC Normal Mode If enabled, the ADC will operate with normal current consumption yielding optimum electrical performance 0, 1 ADC Low Power Mode If enabled, the I-ADC will operate with reduced current consumption. This limitation is current consumption is achieved, (at the expense of ADC noise performance) by fixing the gain to 128 and using the on-chip low power (131kHz) oscillator to drive the ADC circuits directly. 1, 0 ADC Low Power-Plus Mode If enabled, the ADC will again operate with reduced current consumption. In this mode the gain is fixed to 512 and the current consumed is 200uA (approx.) more than ADC low Power Mode above. The additional current consumed also ensures ADC noise performance is better than that achieved in ADC Low Power Mode. 1, 1 Not Defined

2-0 ADC Operation Mode Configuration

0, 0, 0 ADC Power-Down Mode All ADC circuits (including internal reference) are powered-down 0, 0, 1 ADC Continuous Conversion Mode In this mode, any enabled ADC will continuously convert. 0, 1, 0 ADC Single Conversion Mode In this mode, any enabled ADC will perform a single conversion. The ADC will enter Idle Mode once the single shot conversion is complete. A single conversion will take 2/3 ADC clock cycles depending on the CHOP mode.

0, 1, 1 ADC IDLE Mode In this Mode, the ADC is fully powered on but is held in RESET 1, 0, 0 ADC Self-Offset Calibration In this mode, an offset calibration is performed on any enabled ADC using an internally generated 0V. The calibration is carried out at the user programmed ADC settings, therefore, as with a normal single ADC conversion, it will take 2/3 ADC conversion cycles before a fully settled calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to IDLE Mode and the Calibration and Conversion Ready status bits are set at the end of an offset calibration cycle. 1, 0, 1 ADC Self Gain Calibration In this mode, a gain calibration against an internal reference voltage is performed on all enabled ADCs. A gain calibration is a 2 stage process and takes twice the time of an offset calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to IDLE Mode and the calibration and Conversion Ready status bits are set at the end of an gain calibration cycle. An ADC self gain calibration should only be carried out on the Current Channel ADC while pre-programmed, factory calibration coefficients (downloaded automatically from internal Flash) should be used for voltage temperature measurements. If an external NTC is used, an ADC Self Calibration should be done on the temperature channel.

Rev. PrD | Page 51 of 128

Preliminary Technical Data ADuC7032

1, 1, 0 ADC System Zero-Scale Calibration In this mode, an zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the user programmed ADC settings, therefore, as with a normal single ADC conversion, it will take 3 ADC conversion cycles before a fully settled calibration result is ready. 1, 1, 1 ADC System Full-Scale Calibration In this mode, an full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins.

Current Channel ADC Control Register :

Name : ADC0CON Address : 0xFFFF050C Default Value : 0x0002 Access : Read/Write

Function : The Current Channel ADC Control MMR is an 16-bit register that is used to configure the I-ADC. Note: If the Current ADC is reconfigured via ADC0CON, the Voltage and Temperature ADCs are also reset.

Table 24 : ADC0CON MMR Bit Designations

Bit Description

15 Current Channel ADC Enable

This bit is set to 1 by user code to enable the I-ADC

Clearing this bit to 0, powers down the I-ADC and resets the respective ADC READY bit in the ADCSTA MMR to 0

14, 13 IIN Current Source Enable

0, 0 Current Sources Off 0, 1 Enable 50uA current source on IIN+ 1, 0 Enable 50uA current source on IIN1, 1 Enable 50uA current source on both IIN- and IIN+

NOTE: These current sources have a tolerance of +-30%. A PGA gain equal to or greater than 2 ( ADC0CON [3-0 ] != 0000 ) must be used when current sources are enabled.

12– 10

9 Current Channel ADC Output Coding

7, 6 Current Channel ADC Input Select

5, 4 Current Channel ADC Reference Select

Not Used These bits are reserved for future functionality and should be written as zero

This bit is set to 1 by user code to configure I-ADC output coding as unipolar

This bit is cleared to 0 by user code to configure I-ADC output coding as 2’s complement

Not Used This bit is reserved for future functionality and should be written as zero

0, 0 IIN+, IIN0, 1 IIN-, IIN- Diagnostic, internal short configuration 1, 0 ADC Reference/136, 0V Diagnostic, test voltage for gain settings <= 128 ADC Reference/(1.0625XGain), 0V Diagnostic, test voltage for gain settings > 128 Note: If (REG_AVDD, AGND) divided by 2 Reference is selected, REG_AVDD is used for Vref in this mode. This will lead to ADC0DAT scaled by two 1, 1 Not Defined

0, 0 Internal, 1.2V precision reference selected. In ADC Low Power Mode, the Voltage Reference selection is controlled by ADCMDE[5] 0, 1 External reference inputs (VREF, GND_SW) selected 1, 0 External reference inputs divided by 2 (VREF, GND_SW)/2 selected, this allows an external reference up to REG_AVDD 1, 1 (REG_AVDD, AGND) divided by 2 selected

Rev. PrD | Page 52 of 128

Preliminary Technical Data ADuC7032

3 - 0 Current Channel ADC Gain Select (note, nominal I-ADC Full-scale Input Voltage = (Vref/GAIN)

0, 0, 0, 0 I-ADC Gain =1 0, 0, 0, 1 I-ADC Gain =2 0, 0, 1, 0 I-ADC Gain =4 0, 0, 1, 1 I-ADC Gain =8 0, 1, 0, 0 I-ADC Gain =16 0, 1, 0, 1 I-ADC Gain =32 0, 1, 1, 0 I-ADC Gain =64 0, 1, 1, 1 I-ADC Gain =128 1, 0, 0, 0 I-ADC Gain =256 1, 0, 0, 1 I-ADC Gain =512 1, x, x, x I-ADC Gain is undefined

Voltage Channel ADC Control Register :

Name : ADC1CON Address : 0xFFFF0510 Default Value : 0x0000 Access : Read/Write

Function : The Voltage Channel ADC Control MMR is an 16-bit register that is used to configure the V-ADC.

Note: When enabling/disabling the Voltage ADC, the Voltage Attenuator must also be enabled/disabled via HVCFG1[7].

Bit Description

15 Voltage Channel ADC Enable

This bit is set to 1 by user code to enable the V-ADC. When enabling/disabling the Voltage ADC, the Voltage Attenuator

must also be enabled/disabled via HVCFG1[7].

Clearing this bit to 0, powers down the V-ADC.

14– 10 Not Used

These bits are reserved for future functionality and should not be modified by user code

9 Voltage Channel ADC Output Coding

This bit is set to 1 by user code to configure V-ADC output coding as unipolar

This bit is cleared to 0 by user code to configure V-ADC output coding as 2’s compliment

8 Not Used

This bit is reserved for future functionality and should be written as 0 by user code

7, 6 Voltage Channel ADC Input Select

0, 0 VBAT/24, AGND VBAT attenuator selected 0, 1 Not Defined 1, 0 Not Defined 1, 1 Internal Short Shorted Input

5, 4 Voltage Channel ADC Reference Select

0, 0 Internal, 1.2V precision reference selected. 0, 1 External reference inputs (VREF, GND_SW) selected. 1, 0 External reference inputs divided by 2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD 1, 1 (REG_AVDD, AGND) divided by 2 selected.

3 – 0 Not Used

These bits are reserved for future functionality and should be written as 0 by user code

Table 25 : ADC1CON MMR Bit Designations

Rev. PrD | Page 53 of 128

Preliminary Technical Data ADuC7032

Temperature Channel ADC Control Register :

Name : ADC2CON Address : 0xFFFF0514 Default Value : 0x0000 Access : Read/Write

Function : The Temperature Channel ADC Control MMR is an 16-bit register that is used to configure the T-ADC.

Note: The Temperature channel is calibrated to read 0x0000 at 0°K.

The temperature gradient is then 16 codes per degree Celsius

Table 26 : ADC2CON MMR Bit Designations

Bit Description

15 Temperature Channel ADC Enable

This bit is set to 1 by user code to enable the T-ADC

Clearing this bit to 0, powers down the T-ADC

14, 13 VTEMP Current Source Enable

0, 0 Current Sources Off 0, 1 Enable 50uA current source on VTEMP+ 1, 0 Enable 50uA current source on GND_SW 1, 1 Enable 50uA current source on both VTEMP+ and GND_SW NOTE: These current sources have a tolerance of +-30%.

12– 10 Not Used

These bits are reserved for future functionality and should not be modified by user code

9 Temperature Channel ADC Output Coding

This bit is set to 1 by user code to configure T-ADC output coding as unipolar

This bit is cleared to 0 by user code to configure T-ADC output coding as 2’s compliment

8 Not Used

This bit is reserved for future functionality and should be written 0 by user code

7, 6 Temperature Channel ADC Input Select

0, 0 Internal Temperature Sensor The Temperature gradient is 0.5mV/°C. This is only applicable to the Internal Temperature Sensor 0, 1 External ( VTEMP, GND_SW)

1, 0 Shorted Input ( GND_SW, GND_SW) 1, 1 ADC Reference/136

5, 4 Temperature Channel ADC Reference Select

3 – 0 Not Used

This bit is reserved for future functionality and should be written 0 by user code

Rev. PrD | Page 54 of 128

Preliminary Technical Data ADuC7032

ADC Filter Register :

Name : ADCFLT Address : 0xFFFF0518 Default Value : 0x0007 Access : Read/Write

Function : The ADC Filter MMR is an 16-bit register that controls the speed and resolution of the on-chip ADCs.

Note: If ADCFLT is modified, the Current, Voltage and Temperature ADCs are reset. An additional time of 60us per

enabled ADC is required before the first ADC result is available.

Table 27 : ADCFLT MMR Bit Designations

Bit Description

13 - 8

6 – 0

Chop enable Set by user to enable system chopping of all active ADCs. When this bit is set the ADC will have very low offset errors and

drift but the ADC output rate will be reduced by a factor of 3 if AF=0 (see Sinc3 Decimation Factor bits below). If AF ≠ 0, then ADC output update rate will be the same with chop on or off. When chop is enabled, the settling time is 2 output periods.

Note: Should only be used with SF > 1

Running Average Set by user to enable a running average by 2 function reducing ADC noise. This function is automatically enabled when chopping is active. It is an optional feature when chopping is inactive and if enabled (when chopping is inactive) does not reduce ADC output rate but will increase the settling time by 1 conversion period. Cleared by user to disable the running average function.

Averaging Factor ( AF ) The value written to these bits is use to implement a programmable 1

order Sinc post filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Sinc Decimation Factor bits below. Sinc3 Modify Set by user to modify the standard Sinc3 frequency response to increase the filter stopband rejection by 5dBs approx. This is achieved by inserting a second notch (NOTCH2) at F

NOTCH2

= 1.333 * F

NOTCH

where F

is the location of the 1st

NOTCH

notch in the response. Sinc3 Decimation Factor (SF) The value (SF) written in these bits controls the over sampling (decimation factor) of the Sinc3 filter. The output rate from the Sinc3 filter is given by F

= ( 512,000 / ( [SF+1] X 64 )) Hz when the CHOP bit (bit#15 above) = 0 and AF=0 (note AF = Averaging Factor)

ADC

Note : this is valid for all SF values <= 125 For SF= 126, F For SF= 127, F

For information on calculating the F

is forced to 60Hz

ADC

is forced to 50Hz

ADC

for SF ( other than 126 and 127 ) and AF values please refer to Table 2 8.

ADC

Note:

- Due to limitations on the digital filter internal data-path, there are some limitations on the combinations of SF(Sinc3 Decimation Factor) and AF(Averaging Factor) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode. If all three ADCs are enabled, then the minimum value of SF written by user code must be 1

- In low power mode and low power-plus mode, the ADC is driven directly by the low power oscillator (131KHz) and not 512KHz. All F

calculations should be divided by 4 (approx).

ADC

- For optimal ADC performance, SF should be increased before AF is used.

Rev. PrD | Page 55 of 128

Preliminary Technical Data ADuC7032

Table 28 : ADC Conversion Rates and Settling Times

Chop

Enabled

No No No

No No Yes

No Yes No

No Yes Yes

Yes N/A N/A

*An additional time of 60us per enabled ADC is required before the first ADC result is available.

Running

Average

Table 29 : Allowable Combinations of SF and AF

AF Range

Averaging Factor F

512000

+SF

512000

(SF+1) x 64 x (AF+3) +

0 1 to 7 8 to63

ADC

64*]1[

+SF

]3[*64*]1[

AFSF ++

64*]1[

]3[*64*]1[

AFSF ++

Settling

ADC

0-31

32-63

64-127

        

Rev. PrD | Page 56 of 128

Preliminary Technical Data ADuC7032

ADC Configuration Register :

Name : ADCCFG Address : 0xFFFF051C Default Value : 0x00 Access : Read/Write

Function : The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs.

Table 30: ADCCFG MMR Bit Designations

Bit Description

7 Analog Ground Switch Enable

This bit is set to ‘1’ by user software to connect the external ‘GND_SW’ pin (pin#15) to an internal analog ground reference point. This bit can be used to connect and disconnect external circuits and components to ground under program control and thereby minimize dc current consumption when the external circuit or component is not being used.

This bit is used in conjunction with ADCMDE[6] to select a 20KΩ resistor to ground.

6, 5

4, 3

1 ADC FIFO Enable

0 Current Channel ADC, Result Counter Enable

Current Channel (32-bit) Accumulator Enable 0, 0 Accumulator Disabled and reset to 0 0, 1 Accumulator Active Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535 conversions Negative current values are subtracted from accumulator total, accumulator is clamped to a minimum value of 0 1, 0 Accumulator Active Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535 conversions The absolute values of Negative current are subtracted from accumulator total, accumulator in this mode will continue to accumulate negatively, below 0 1, 1 Accumulator and Accumulator Comparator Enabled This mode is the same as Mode |1,0|, but with the Accumulator Comparator enabled. Current Channel ADC Comparator Enable 0, 0 Comparator Disabled 0, 1 Comparator Active, Interrupt asserted if absolute value of I-ADC conversion result |I| >= ADC0TH 1, 0 Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >= ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will reset the threshold counter value (ADC0THV) to 0 1, 1 Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >= ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will decrement the threshold counter value (ADC0THV) towards 0. Current Channel ADC OverRange Enable Set by user to enable a ‘coarse’ comparator on the Current Channel ADC. If the current reading is grossly (>30% approx.) over-ranged for the active gain setting, then the over range bit in the ADCSTA MMR is set. The current must be outside this range for greater than 125usecs for the flag to be set. This feature should not be used in ADC Low Power Mode

This bit is set to 1 by user code to enable ADC FIFO on Current and Voltage ADC Channels. The FIFO function allows up to 32 current and voltage ADC results to be stored in an on-chip FIFO. The current status of the FIFO is reflected by 3 bits in the ADCSTA register. If more than 32 results are stored in the FIFO, the contents of the FIFO may be corrupted.

Set by user to enable the result count mode. In this mode an I-ADC interrupt will only be generated when ADC0RCV=ADC0RCL. This allows the I-ADC to continuously monitor current but only interrupt the MCU core after a defined number of conversions. It should be noted that unless the ADC FIFO is enabled (ADCCNG[1]=1), only the last conversion value will be available (intermediate I-ADC conversion results are not stored) when the ADC counter interrupt occurs. The Voltage and Temperature ADCs will also continue to convert if enabled but again only the last conversion result will be available (intermediate V/T-ADC conversion results are not stored) when the ADC counter interrupt occurs

Rev. PrD | Page 57 of 128

Preliminary Technical Data ADuC7032

Current Channel ADC Offset Calibration Register :

Current Channel ADC Data Register :

Name : ADC0DAT Address : 0xFFFF0520 Default Value : 0x0000 Access : Read Only

Function : This ADC Data MMR holds the 16-bit

conversion result from the I-ADC. The ADC will not update this MMR if the ADC0 Conversion Result READY bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted READY flags (ADCSTA[2:0]).

Voltage Channel Data Register:

Name : ADC1DAT Address : 0xFFFF0524 Default Value : 0x0000 Access : Read Only

Function : This ADC Data MMR holds the 16-bit

conversion result from the V-ADC. The ADC will not update this MMR if the Voltage Conversion Result READY bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by the MCU clears all asserted READY flags (ADCSTA[2:1]).

Temperature Channel ADC Data Register :

Name : ADC2DAT Address : 0xFFFF0528 Default Value : 0x0000 Access : Read Only

Function : This ADC Data MMR holds the 16-bit

conversion result from the T-ADC. The ADC will not update this MMR if the Temperature Conversion Result READY bit (ADCSTA[2]) is set.

ADC FIFO Register :

Name : ADCFIFO Address : 0xFFFF052C Default Value : 0x0000 Access : Read Only

Function : This 32-bit, read-only register returns the

value of I-ADC and V-ADC conversion result held in the FIFO location currently pointed to by the FIFO read pointer. The low 16 bits [15-0] of this 32-bit word are the I-ADC result and the high 16-bits [31-16] are the V-ADC result. The FIFO function is enabled via the ADCCFG[1] bit and 3 flags available in the ADCSTA register allow user code monitor and read the FIFO contents.

Name : ADC0OF Address : 0xFFFF0530 Default Value : Part Specific, factory programmed Access : Read/Write

Function : This ADC Offset MMR holds a 16-bit offset

calibration coefficient for the I-ADC. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Voltage Channel Offset Calibration Register :

Name : ADC1OF Address : 0xFFFF0534 Default Value : Part Specific, factory programmed Access : Read/Write

Function : This Offset MMR holds a 16-bit offset

calibration coefficient for the voltage channel. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Temperature Channel Offset Calibration Register:

Name : ADC2OF Address : 0xFFFF0538 Default Value : Part Specific, factory programmed Access : Read/Write

Function : This ADC Offset MMR holds a 16-bit offset

calibration coefficient for the temperature channel. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Rev. PrD | Page 58 of 128

Preliminary Technical Data ADuC7032

Current Channel ADC Gain Calibration Register :

Name : ADC0GN Address : 0xFFFF053C Default Value : Part Specific, factory programmed Access : Read/Write

Function : This Gain MMR holds a 16-bit gain

calibration coefficient for scaling the I-ADC conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if aa gain calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Voltage Channel Gain Calibration Register :

Name : ADC1GN Address : 0xFFFF0540 Default Value : Part Specific, factory programmed Access : Read/Write

Function : This Gain MMR holds a 16-bit gain

calibration coefficient for scaling a voltage channel conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Temperature Channel Gain Calibration Register :

Name : ADC2GN Address : 0xFFFF0544 Default Value : Part Specific, factory programmed Access : Read/Write

Function : This Gain MMR holds a 16-bit gain

calibration coefficient for scaling a temperature channel conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.

Current Channel ADC Result Counter Limit Register:

Name : ADC0RCL Address : 0xFFFF0548 Default Value : 0x0001 Access : Read/Write

Function : This 16-bit MMR sets the number of

conversions required before an ADC interrupt is generated. By default this register is set to 0x01. The ADC counter function must be enabled via the ADC Result Counter Enable bit in the ADCCFG MMR.

Current Channel ADC Result Count Register:

Name : ADC0RCV Address : 0xFFFF054C Default Value : 0x0000 Access : Read Only

Function : This 16-bit, Read Only MMR holds the

current number of I-ADC conversion results. It is used in conjunction with ADC0RCL to mask I-ADC interrupts, generating a lower interrupt rate. Once ADC0RCV=ADC0RCL, the value is ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the Accumulator (ADC0ACC) to allow an average current calculation to be undertaken. The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the I-ADC is reconfigured i.e. when the ADC0CON or ADCMDE are written.

Current Channel ADC Threshold Register:

Name : ADC0TH Address : 0xFFFF0550 Default Value : 0x0000 Access : Read/Write

Function : This 16-bit MMR sets the threshold against

which the absolute value of the I-ADC conversion result is compared. In Unipolar mode ADC0TH [15:0] are compared and in 2’s compliment mode ADC0TH[14:0] are compared.

Current Channel ADC Threshold Count Limit Register:

Name : ADC0TCL Address : 0xFFFF0554 Default Value : 0x01 Access : Read/Write

Function : This 8-bit MMR determines how many

cumulative(given values below the threshold will decrement or reset the count to 0) I-ADC conversion result readings above ADC0TH must occur before the I-ADC Comparator Threshold

Rev. PrD | Page 59 of 128

Preliminary Technical Data ADuC7032

bit is set in the ADCSTA MMR generating an ADC interrupt. The I-ADC Comparator Threshold bit is asserted as soon as the ADC0THV=ADC0TCL.

Current Channel ADC Threshold Count Register:

Name : ADC0THV Address : 0xFFFF0558 Default Value : 0x00 Access : Read Only

Function : This 8-bit MMR is incremented every time

the absolute value of an I-ADC conversion result |I| >= ADC0TH. This register is decremented or reset to 0 every time the absolute value of an I-ADC conversion result |I| < ADC0TH. The configuration of this function is enabled via the Current Channel ADC Comparator bits in the ADCCFG MMR

Current Channel ADC Accumulator Register:

Name : ADC0ACC Address : 0xFFFF055C Default Value : 0x00000000 Access : Read Only

Function : This 32-bit MMR holds the current

accumulator value. The I-ADC READY bit in the ADCSTA MMR should be used to determine when it is safe to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or reconfiguring the Current Channel ADC.

Current Channel ADC Accumulator Threshold Register:

Name : ADC0ATH Address : 0xFFFF0560 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR sets the threshold against

which the accumulated value of the I-ADC results is compared. In Unipolar mode ADC0TH [15:0] are compared and in 2’s compliment mode ADC0TH[14:0] are compared.

Low Power Voltage Reference Scaling Factor

Name : ADCREF Address : 0xFFFF057C Default Value : Part Specific, factory programmed Access : Read

Function : This allows user code to correct for the

initial error of the LPM reference. The default value of 0x8000 corresponds to no error when compared to the Normal Mode Reference.

If the LPM Voltage Reference is 1% below1.200V,then the value of ADCREF will be approximately 0x7EB9

If the LPM Voltage Reference is 1% above1.200V,then the value of ADCREF will be approximately 0x8147

ADC POWER MODES OF OPERATION

The ADCs can be configured into various reduced or full ‘power’ modes of operation by configuring ADCMDE[4:3] as appropriate. The ARM7 MCU can itself also be configured in Low Power modes of operation (POWCON[5:3]). The core power modes are independently controlled and are not related to the ADC power modes described here. The ADC power modes of operation are described in more detail below.

Every I-ADC result can also compared to a pre-set threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign-independent) value of the ADC result is greater than the pre-programmed comparator threshold level. An extended function of this comparator function allows user code to configure a threshold counter (ADC0THV) which monitors the number of I-ADC results that have occurred above or below the pre-set threshold level. Again an ADC interrupt is generated once the threshold counter reaches a pre-set value (ADC0TCL).

Finally, a 32-bit accumulator(ADC0ACC) function can be configured(ADCCFG[6:5]) allowing the I-ADC to add(or subtract) multiple I-ADC sample results. User code can read the accumulated value directly( via ADC0ACC) without any further software processing.

ADC Startup Procedure

Prior to beginning converting, the following procedure should be followed.

1. Configure the Current ADC, ADC0, into Low-PowerMode (ADC0CON = 0x8007; ADCMDE = 0x09)

2. Delay for 200us.

3. Switch the Current ADC, ADC0, into Idle-Mode (ADCMDE = 0x03), keeping ADC0CON unchanged. If the Voltage or Temperature channels are to be used, they should be enabled here.

4. Delay for 1ms

5. Switch ADCMDE to desired mode, e.g. ADC0CON = 0x1.

Rev. PrD | Page 60 of 128

Preliminary Technical Data ADuC7032

digital comparator and accumulator) described earlier in

ADC Normal Power Mode

In Normal Mode, the Current and Voltage/Temperature channels are fully enabled. The ADC modulator clock is 512KHz and enables the ADCs to provide regular conversion results at a rate of between 4Hz and 8KHz (see ADCFLT). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1.0kHz

It is worth emphasizing that I-ADC and V/T-ADC channels can be configured to initiate periodic, normal power mode, high accuracy, single conversion cycles before returning to ADC full power-down mode. This flexibility is facilitated under full MCU control via the ADCMDE MMR and ensures that continuous periodic monitoring of battery current, voltage and temperature settings is feasible while ensuring the average dc current consumption is minimized.

In ADC Normal Mode, the PLL must not be powered down.

ADC Low Power Mode

In ADC Low Power mode, the I-ADC is enabled in a reduced power and reduced accuracy configuration. The ADC modulator clock is now driven directly from the on-chip 131KHz low power oscillator, which allows the ADC to be configured at update rates as low as 1Hz(ADCFLT). The gain of the ADC in this mode is fixed at 128.

All of the ADC peripheral functions (result counter, digital comparator and accumulator) described earlier in normal power mode can still be enabled in low power mode.

Typically, in Low Power Mode, the I-ADC only, is configured to run at a low update rate, continuously monitoring battery current. The MCU will be in power-down mode and will only be woken up when the I-ADC interrupts the MCU. This would happen after the I-ADC detects a current conversion or an accumulated current value has risen beyond a pre-programmed threshold, set-point or a set number of conversions.

It is also possible to select either the ADC Normal Mode Voltage Reference of the ADC Low Power Mode Voltage Reference via ADCMDE[5].

ADC Low Power-Plus Mode

In Low Power-Plus mode, the I-ADC channel is enabled in a mode almost identical to low-power mode(ADCMDE[4:3]). However, in this mode, the I-ADC gain is fixed at 512 and the ADC consumes an additional 200uA (approx.) to yield improved noise performance relative to the low-power mode setting.

normal power mode can still be enabled in Low Power-Plus mode.

As in Low Power Mode, the I-ADC only, is configured to run at a low update rate, continuously monitoring battery current. The MCU will be in power-down mode and will only be woken up when the I-ADC interrupts the MCU. This would happen after the I-ADC detects a current conversion result or an accumulated current value has risen beyond a pre-programmed threshold or set-point.

It is also possible to select either the ADC Normal Mode Voltage Reference of the ADC Low Power Mode Voltage Reference via ADCMDE[5].

ADC Sinc3 Digital Filter Response

The overall frequency response on all ADuC7032s ADCs is dominated by the low pass filter response of the on-chip Sinc3 digital filters. The Sinc3 filters are used to decimate the ADC sigma-delta modulator output data bit-stream to generate a valid 16-bit data result. The digital filter response is identical for all ADCs and is configured via the 16-bit ADC Filter (ADCFLT) register which determines the overall throughput rate of the ADCs. The noise resolution of the ADCs is determined by the programmed ADC throughput rate. In the case of the Current Channel ADC, the noise resolution will be determined by throughput rate and selected gain.

The overall frequency response and the ADC through-put is dominated by the configuration of the Sinc3 Filter Decimation Factor (SF) bits (ADCFLT[6:0]) and the Averaging Factor (AF) bits(ADCFLT[13:8]). Due to limitations on the digital filter internal data-path, there are some limitations on the allowable combinations of SF(Sinc3 Decimation Factor) and AF(Averaging Factor) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode. The calculation of the ADC through-put rate is detailed in the ADCFLT bit designations table and the restrictions on allowable combinations of AF and SF values are outlined again in Table 31

Table 31 : Allowable Combinations of SF and AF

AF Range

<= 31

127

0 1 to 7 8-63

        

Again, all of the ADC peripheral functions (result counter,

Rev. PrD | Page 61 of 128

Preliminary Technical Data ADuC7032

By default the ADCFLT = 0x07 which configures the ADCs for a through-put of 1.0KHz with all other filtering options (Chop, Running Average, Averaging Factor and Sinc3 Modify) being disabled. A typical filter response based on this default configuration is shown in Figure 19 below.

H(f) [dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Figure 19 : Typical Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0007)

An additional ‘Sinc3 Modify’ bit (ADCFLT[7]) is also available in the ADCFLT register. This bit is set by user code to modify the standard Sinc3 frequency response increasing the filter stopband rejection by 5dBs approx. This is achieved by inserting a second notch (NOTCH2) at FNOTCH2 = 1.333 X FNOTCH where FNOTCH is the location of the 1st notch in the response. There is a slight increase in ADC noise if this bit is active. Figure 20 shows the modified 1KHz filter response when the Sinc3 modify bit is active. The ‘new’ notch is clearly visible at

1.33KHz as is the improvement in stop-band rejection when compared to the standard 1KHz response above.

H(f) [dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Figure 20 : ModifiedSinc3 Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0087)

In ADC Normal Power Mode, the maximum ADC through-put rate is 8KHz which is configured by setting the SF and AF bits in the ADCFLT MMR to 0, with all other filtering options disabled. This results in 0x0000 written to ADCFLT and a typical 8KHz filter response based on these settings is shown below in Figure 21.

H(f)

[dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 22000 24000

f [Hz]

Figure 21 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x0000)

A modified version of the 8KHz filter response can be configured by setting the ‘Running Average’ bit (ADCFLT[14]). This has the effect of introducing an additional running average by 2 filter on all ADC output samples. This further reduces the ADC output noise and while maintaining an 8KHz ADC through-put rate the ADC settling time is increased by 1 full conversion period. The modified frequency response for this configuration is shown below in Figure 22.

H(f)

[dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 22000 24000

f [Hz]

Figure 22 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x4000)

At very low throughput rates, the chop bit in the ADCFLT register can be enabled to minimize offset errors and more importantly and temperature drift in the ADC DC errors. With Chop enabled, there are again 2 primary variables (Sinc3 decimation factor and averaging factor) available to allow the user select an optimum filter response trading off filter bandwidth against ADC noise.

For example, with the CHOP bit ADCFLT[15] set to 1, increasing the SF value (ADCFLT[6:0]) to 0x1F (31dec) and selecting an AF value (ADCFLT[13:8]) of 0x16 (22dec) results in an ADC through-put of 10Hz. The frequency response in this case is shown in Figure 23.

Rev. PrD | Page 62 of 128

Preliminary Technical Data ADuC7032

H(f) [dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 20 40 60 80 100 120 140 160 180 200

Figure 23 Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x961F)

Changing SF to 0x1D and setting AF to 0x3F, again with the Chop bit enabled, configures the ADC into its minimum through-put rate in Normal Mode of 4Hz. The digital filter frequency response with this configuration is shown below in Figure 24.

H(f) [dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0204060

Figure 24 : Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D)

In ADC Low Power Mode, the ADC, Sigma-Delta modulator clock no longer driven at 512KHz but is driven directly from the on-chip low power (131KHz) oscillator. Subsequently, for the same ADCFLT configurations in Normal Mode, all filter values should be scaled by a factor of approximately 4. This means that is possible to configure the ADC for 1Hz throughput is Low Power Mode. The filter frequency response for this configuration is shown below in Figure 25.

H(f)

[dB]

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 2 4 6 8 101214161820

Figure 25 : Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F

In general, it should be noted that it is possible to program different values of SF and AF in the ADCFLT register and achieve the same ADC update rate. In practical terms the tradeoff with any value of ADCFLT will be frequency response versus ADC noise. For optimum filter response and ADC noise when using combinations of SF and AF, a good rule of thumb to use would be to first choose an SF in the range of 16 – 40 (dec) or 0x10 to 0x28 and then increase the AF value to achieve the required ADC through-put. Table 32 shows some common ADCFLT configurations.

Table 32 : Common ADCFLT Configurations

ADC

Mode

Normal 0x1D 0x3F Chop On 0xBF1D 4Hz 0.5secs

Normal 0x1F 0x16 Chop On 0x961F 10Hz 0.2secs

Normal 0x07 0x00 None 0x0007 1KHz 3msecs

Normal 0x07 0x00

Normal 0x03 0x00

Normal 0x00 0x01

Low

Power

SF AF

0x10 0x03 Chop On 0x8310 20Hz 100ms

Other

Config

Sinc 3

Modifiy

Running

Average

Running

Average

ADCFLT F

ADC

0x0087 1KHz 3msec

0x4003 2KHz 2msec

0x4000 8KHz 0.5ms

SETTLE

Low

Power

Low

Power

Rev. PrD | Page 63 of 128

0x10 0x09 Chop On 0x8910 10Hz 200ms

0x1F 0x3D Chop On 0xBD1F 1Hz 2sec

Preliminary Technical Data ADuC7032

ADC Calibration

As described in detail in the top level diagrams at the start of this section, the signal flow through all ADC Channels can be described in simple terms as:

 An Input-voltage is applied through an input buffer

(and PGA in the case of the I-ADC) to the SigmaDelta Modulator.

 The Modulator-output is applied to a programmable

Digital Decimation Filter

 The filter output result is then averaged if chopping is

used.

 An Offset value (ADCxOF) is subtracted from the

result.

 This result is scaled by a Gain value (ADCxGN).

 Finally, the result is formatted as

- 2’s Complement. / Offset-Binary,

- Rounded to 16-Bit

- Clamped to +/-Full-Scale

Each ADC has a specific Offset and Gain correction or Calibration coefficient associated with it that are stored in MMR based Offset and Gain registers(ADCxOF and ADCxGN). The offset and gain registers can be used to remove offsets and gain errors arising within the part as well as Systemlevel offset and gain errors external to the part.

These registers are configured at power-on with a factory programmed calibration value. These factory calibration values will vary from part to part reflecting the manufacturing variability of internal ADC circuits . However, these registers can also be overwritten by user code (only if the ADC is in idle mode) and will be automatically overwritten if an offset or gain calibration cycle is initiated by user via the mode bits in the ADCMDE[2:0] MMR. 2 types of automatic calibration are available to the user, namely :

- Self (Offset or Gain) Calibration, where the ADC generates its calibration coefficient based on an internally generated 0V in the case of Self-Offset calibration and full-scale voltage in the case of Self-Gain calibration. It should be emphasized that ADC SelfCalibrations correct for offset and gain errors within ADC. Self calibrations cannot compensate for other external errors in the system, e.g. Shunt-Resistor tolerance/drift, external offset voltages etc.

- System (Offset or Gain) Calibration, where the ADC generates its calibration coefficient based on an externally generated zero-scale voltage in the case of System-Offset calibration and Full-scale voltage in the case of System-Gain calibration which are applied to the external ADC input for the duration of the calibration cycle.

the

The duration of an Offset calibration is 1 single conversion cycle (3/F ADC to idle mode. A Gain calibration is a 2 stage process and subsequently takes twice as long as an offset calibration cycle. Once a calibration cycle is initiated, any ongoing ADC conversion is immediately halted, the calibration is carried out automatically at an ADC update rate programmed into ADCFLT and the ADC is always returned to idle after any calibration cycle. It is strongly recommended that ADC calibration is initiated at as low an ADC update rate as possible (high SF value in ADCFLT) in order to minimize the impact of ADC noise during calibration.

NOTE: ADC0OF and ADC0GN must first contain the values for PGA = 1 before a calibration scheme is started

Chop off, 2/F

ADC

Chop on) before returning the

ADC

Using the Offset and Gain Calibration Registers

If the Chop bit (ADCFLT[15]) is enabled, then internal ADC offset errors will be minimized and an Offset calibration may not be required. If chopping is disabled however, an initial Offset calibration will be required and may need to be repeated.

A Gain calibration, particularly in the context of the I-ADC (with internal PGA) may need to be carried out at all relevant system gain ranges depending on system accuracy requirements. If it is not possible to apply an external full-scale current on all gain ranges then it is possible to apply a lower current, and scale the result produced by the calibration. e.g Apply a 50% current and then divide the ADC0GN value produced by 2 and write this value back into ADC0GN. It should be noted that there is a lower limit to the input signal that can be applied for a System-Calibration because the ADC0GN register is only 16-Bit. The input span (difference between the System Zero-Scale value and System Full-Scale value) should be greater than 40% of the nominal Full-ScaleInput range, ie > 40% of Vref/Gain.

The on-chip Flash/EE memory can be used to store multiple calibration coefficients which can be copied by user code directly into the relevant calibration registers as appropriate based on system configuration. In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes.

Rev. PrD | Page 64 of 128

Preliminary Technical Data ADuC7032

A factory or end-of-line calibration for the I-ADC would be a 2-step procedure:

1. Apply 0A current.

Configure the ADC in the required PGA setting etc. and write to ADCMDE[2:0] to perform a System Zero-Scale Calibration. This writes a new offset calibration value into ADC0OF.

2. Apply a Full-Scale current for the selected PGA setting.

Write to ADCMDE to perform a System Full-Scale Calibration. This writes a new gain calibration value into ADC0GN.

Understanding the Offset and Gain Calibration Registers

The output of the average block in the ADC signal flow described earlier after the digital filter and before the Offset and Gain scaling can be considered to be a fractional number with a span, for a +/- Full-Scale input, of approx +/-0.75. The span is less than +/-1.0 because there is attenuation in the modulator to accommodate some over-range capacity on the input signal. The exact value of the attenuation will vary slightly from partto-part, because of manufacturing tolerances.

The Offset Coefficient is read from the ADC0OF calibration register. This value is a 16-Bit 2's complement number. The range of this number, in terms of the signal chain, is effectively +/-1.0. 1 LSB of the ADC0OF register is therefore not the same as 1LSB of ADC0DAT.

A positive value of ADC0OF indicates that offset is subtracted from the output of the filter, a negative value is added. The nominal value of this register is 0x0000, indicating zero offset is to be removed. The actual offset of the ADC may vary slightly from part-to-part and at different PGA gains. The offset within the ADC is minimized if the Chopping mode is active (ADCFLT[15]=1).

The Gain Coefficient is a unitless scaling factor. The 16-Bit value in this register is divided by 16384, and then multiplied by the offset-corrected value. The nominal value of this register equals 0x5555, which corresponds to a multiplication factor of

1.3333. This scales the nominal +/-0.75 signal to produce a fullscale output signal of +/-1.0 which is checked for Overflow/ Underflow and converted to Two's Complement or Unipolar mode as appropriate, before being output to the Data register.

The actual gain, and the required scaling coefficient for zero gain error, varies slightly from part to part, and at different PGA settings and in Normal / Low-Power-Mode. The value downloaded into ADC0GN at power-on/reset represents the scaling factor for a PGA Gain=1. There will be some level of

gain error if this value is used at different PGA settings. User code can over-write the calibration coefficients or run ADC calibrations to correct the gain error at the current PGA setting.

In Summary, the simplified ADC transfer function can be described as :

VIN

ADCOUT *

This equation is valid for Voltage/Temperature channel ADC.

For the Current Channel ADC,

ADCOUT

where K is dependent on PGA gain setting and ADC mode.

Normal Mode:

For PGA gains of 1,4,8,16,32 and 64 the K factor is 1. For PGA gains of 2 and 128 the K factor is 2. For PGA gain of 256 the K Factor is 4. For PGA gain of 512, the K factor is 8.

Low Power Mode: The PGA gain is set to 128 and the K factor is 32.

Low Power Plus Mode: The K factor is 8.

In Low-Power and Low-Power-Plus Mode, the K factor doubles if (AVDD_Reg)/2 is used as the reference.

⎡ ⎢

VREF

⎣

VIN

⎡ ⎢

VREF

⎣

ADCOF

−=

ADCOFK

ADCGN

⎤ ⎥

ADCGNNOM

⎦

⎤

⎥

ADCGNNOM

⎦

ADCGN

ADC DIAGNOSTICS

The ADuC7032 features diagnostic capability on all three ADCs.

Current ADC Diagnostics

The ADuC7032 features the capability to detect Open Circuit conditions on the application board. This is accomplished using the two current sources on IIN+ and IIN-, which is controlled via ADC0CON[14,13].

The use of both the IIN+ and IIN- current sources is shown in Table 33.

To verify the current ADC is converting correctly, it is possible to select an internal test voltage via ADC0CON[7,6]. Selecting mode 10 results in the current ADC converting the Voltage Reference, e.g. The Precision 1.2V Reference, divided by 136 for PGA settings less than or equal to 128 and divided by (1.0625*Gain) for PGA settings greater than 128.

Rev. PrD | Page 65 of 128

Preliminary Technical Data ADuC7032

Temperature ADC Diagnostics

The ADuC7032 features the capability to detect Open Circuit conditions on the Temperature Channel inputs. This is accomplished using the two current sources on VTEMP+ and GND_SW, which is controlled via ADC2CON[14,13].

The use of both the VTEMP+ and GND_SW current sources is shown in Table 34.

Table 33: Current ADC Diagnostics

To verify the Temperature ADC is converting correctly, it is possible to select an internal test voltage via ADC2CON[7,6]. Selecting mode 10 results in the current ADC converting the Voltage Reference, e.g. The Precision 1.2V Reference, divided by 136.

Fault Condition

Short between IIN+ and IIN-

at pins of device

Short Between IIN+ and GND IIN+

Short Between IIN- and GND IIN-

IIN+ Open Circuit IIN+ Positive Full Scale ( 0x7FFF in Bi Polar Mode )

IIN- Open Circuit IIN- Negative Full Scale ( 0x8000 in Bi Polar Mode )

Enabled

IIN+ or IIN-

Table 34: Temperature ADC Diagnostics

No difference between ADC0DAT result prior to and after IIN+

No difference between ADC0DAT result prior to and after IIN-

ADC0DAT Result

(or IIN-) current source is enabled

current source is enabled

Current Source

Fault Condition

Short between VTEMP+ and

GND_SW at pins of device

Short Between VTEMP+ and

GND

Short Between GND_SW and

GND

Enabled

VTEMP+ or GND_SW

VTEMP+

GND_SW

No difference between reading prior to and after VTEMP+ or

No difference between reading prior to and after VTEMP+

No difference between reading prior to and after GND_SW

ADC0DAT Result

GND_SW current source is enabled

current source is enabled

VTEMP+ Open Circuit VTEMP+ Positive Full Scale ( 0x7FFF in Bi Polar Mode )

GND_SW Open Circuit GND_SW Negative Full Scale ( 0x8000 in Bi Polar Mode )

Rev. PrD | Page 66 of 128

Preliminary Technical Data ADuC7032

POWER SUPPLY SUPPORT CIRCUITS

The ADuC7032 incorporates an on-chip Low Drop-Out(LDO) regulator which is driven directly from the battery voltage to generate a 2.6V internal supply. This 2.6V supply is then used as the supply voltage for the ARM7 MCU and peripherals including the precision analog circuits on-chip.

Power on Reset(POR), Power Supply Monitor(PSM) and Low Voltage Flag (LVF) functions are also integrated to ensure safe operation of the MCU as well as continuously monitoring the battery power supply.

The POR circuit is designed to handle all battery ramp rates and guarantee full functional operation of the Flash/EE memory based MCU during power-on and power-down cycles.

As shown in Figure 26, once the supply voltage, VDD, reaches a minimum operating voltage of 3V, a POR signal keeps the ARM core in reset for 20ms. This ensures that the regulated power supply voltage. REG_DVDD, supplied to the ARM core and associated peripherals is above the minimum operational

VDD

3V TYP

voltage to guarantee full functionality. A POR flag is set in the RSTSTA MMR to indicate a POR reset event has occurred

The ADuC7032also features a PSM, or Power Supply Monitor function. Once enabled via HVCFG0[3], the PSM continuously monitors the voltage at the V

6.0V

, the PSM flag is automatically asserted and can, if the

TYP

pin. If this voltage drops below

high voltage IRQ is enabled via IRQ/FIQEN[16], generate a system interrupt. An example of this operation is shown in Figure 26.

At voltages below the POR level, an additional Low Voltage Flag can be enabled (HVCFG0[2]). It may be used to indicate that the contents of the SRAM are still valid after a reset event. The operation of the low voltage flag is shown in Figure 26. Once enabled, the status of this bit may be monitored via HVSTA[6]. If this bit is set, then the SRAM contents are valid. If this bit is cleared, then the SRAM contents may have been corrupted.

PSM TRIP 6.0V TYP

POR TRIP 3.0V TYP LVF TRIP 2.1V TYP

REG_DV

POR_TRIP

RESET_CORE

(INTERNAL SI GNAL)

ENABLE_PSM

ENABLE_LVF

2.6V

20ms TYP

05994-026

Figure 26: Typical Power-On Cycle

Rev. PrD | Page 67 of 128

Preliminary Technical Data ADuC7032

ADUC7032 SYSTEM CLOCKS

The ADuC7032 integrates a highly flexible clocking system, which may be clocked from one of three sources:

1. An integrated on-chip precision oscillator

2. An integrated on-chip low power oscillator.

3. An external watch crystal

These three options are shown in Figure 27.

Each of the internal oscillators are divided by 4 to generate a clock frequency of 32.768kHz. The PLL locks onto a multiple (625) of 32.768kHz, supplied by either of the internal oscillators or the external crystal, to provide a stable 20.48MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, which allows power saving if peak performance is not required.

By default, the PLL is driven by the Low Power oscillator which

EXTERNAL CRYSTAL

(OPTIO NAL)

CIRCUITRY

PRECISION

32.768kHz

CRYSTAL

LOW POWER

PLLCON

LOW POWER

OSCILLATOR

32.768kHz

PRECISION

OSCILLATOR

PRECISION

131kHz

DIV 4

EXTERNAL

32.768kHz

LOW POWER

generates a 20.48MHz clock source. The ARM7TDMI Core, is driven by a CD divided clock derived from the output of the PLL. By default, the CD divider is configured to divide the PLL output by 2, which generates a core clock of 10.24MHz. The divide factor may be modified to generate a binary weighted divider factor from 1 to 128, which may be altered dynamically by user code.

The ADC is driven by the output of the PLL, divided to give an ADC clock source of 512kHz. In low-power mode the ADC clock source is switched from the standard 512kHz to the Low Power 131kHz oscillator.

It should also be noted that the low power oscillator drives both the watchdog and core wake-up timers through a divide by 4 circuit. A detailed block diagram of the ADuC7032 clocking system is shown in Figure 27.

131kHz

DIV 4

PRECISION

131kHz

EXTERNAL

32.768kHz

LOW POWER OSCILLAT OR

EXTERNAL

32.768kHz

PRECISION

32.768kHz

LOW POWER

32.768kHz

CORE CLOCK

GPIO_5

HIGH ACCURCY

CALIBRATION

COUNTER

LOW POWER

CALIBRATION

COUNTER

TIMER 0

LIFE TIME

1 8

CORE

CLOCK

CORE CLOCK

PLL OUTPUT

(20.48MHz)

PLL LOCK

MCU

SPI

PLL

PLL OUTPUT

20.48MHz

FLASH

CONTROLL ER

CORE CLOCK

ECLK 2.5MHz

CLOCK

DIVIDER

ADCMDE

ADC

CLOCK

UART

ADC

Figure 27: ADuC7032 System Clock Generation

Rev. PrD | Page 68 of 128

GPIO_8

CORE CLOCK

LOW POWER

32.768kHz

CORE CLOCK

EXTERNAL

32.768kHz

PRECISION

32.768kHz

LOW POWER

32.768kHz

LOW POWER

32.768kHz

LOW POWER

32.768kHz

CORE CLOCK

LOW POWER

32.768kHz

PLL OUTPUT

(5MHz)

TIMER 1

TIMER 2

WAKE-UP

WATCHDOG

TIMER 3

TIMER 4

STI

LIN H/W

SYNCHRONIZAT ION

5994-027

Preliminary Technical Data ADuC7032

The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system while POWCON controls the core clock frequency and the powerdown mode. PLLSTA indicates the presence of an oscillator on the XTAL1 pin, the PLL Lock status, and the PLL Interrupt.

It is recommended that before the ADuC7032 is powered down, that the clock source for the PLL is switched to the Low Power 131kHz oscillator to reduce wake up time. The Low Power, Oscillator is always active.

When the ADuC7032 wakes up from power down, the MCU core will begin executing code once the PLL begins oscillating. This occurs before the PLL has locked to a frequency of

20.48MHz. To ensure the Flash memory controller is executing with a valid clock, the controller is driven with a PLL-Output/8 clock source while the PLL is locking. Once the PLL locks, the PLL’s output is switched from the PLL-Output/8 to the locked PLL-Output.

If user code requires an accurate PLL output, user code must poll the Lock bit (PLLSTA[1]) after wake-up before resuming normal code execution.

The PLL will be locked and executing user code within 2ms, if the PLL is clocked from an active clock source, e.g. Low Power 131kHz oscillator after waking up.

PLLCON is a protected MMR with two 32 bit keys PLLKEY0, a pre write key, and PLLKEY1, a post write key.

- PLLKEY0 = 0x000000AA

- PLLKEY1 = 0x00000055

POWCON is a protected MMR with two 32 bit keys POWKEY0, a pre write key, and POWKEY1, a post write key.

- POWKEY0 = 0x00000001

- POWKEY1 = 0x000000F4

An example of writing to both MMRs is shown below:

POWKEY0 = 0x01 //POWCON KEY POWCON = 0x00 //Full Power-down POWKEY1 = 0xF4 //POWCON KEY iA1*iA2 //dummy cycle

PLLKEY0 = 0xAA //PLLCON KEY PLLCON = 0x0 //Switch to Low //Power Osc. PLLKEY1 = 0x55 //PLLCON KEY iA1*iA2 //dummy cycle

PLLSTA Register :

Name : PLLSTA Address : 0xFFFF0400 Default Value : 0x02 Access : Read/Write

Function : This 8-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal.

Table 35 : PLLSTA MMR Bit Description

Bit Description

31-3

Reserved and should be written as zeros

2 XTAL Clock, Read Only

This is a live representation of the current logic level on XTAL1. This allows the user to check to see if an external clock source is present. If present this bit will alternate high and low at a frequency of 32.768kHz.

1 PLL Lock Status Bit, Read Only

Set when the PLL is locked and outputting 20.48MHz. Clear when the PLL is not locked and outputting a Fcore/8 clock source

0 PLL Interrupt:

Set if the PLL Lock status bit signal goes low. Cleared by writing 1 to this bit

Rev. PrD | Page 69 of 128

Preliminary Technical Data ADuC7032

PLLCON Pre-write Key PLLKEY1:

PLLCON Pre-write Key PLLKEY0:

Name : PLLKEY0 Address : 0xFFFF0410 Default Value : 0x00000000 Access : Write Only Key: 0x000000AA

Function : PLLCON is a keyed register that requires a

32 Bit key value to be written before and after PLLCON. PLLKEY0 is the Pre-Write Key

PLLCON Register :

Name : PLLCON Address : 0xFFFF0414 Default Value : 0x00 Access : Read/Write Function : This 8-bit register allows user code dynamically select the PLL source clock from three different oscillator sources.

Table 36: PLLCON MMR Bit description

Bit Description

31-3

If user code switches MCU clock sources, a dummy MCU cycle should be included after the clock switch is written to PLLCON.

Reserved, these bits should be written as 0 by user code

2 Not Used, must be written 0 by user software.

1-0

PLL Clock Source

00 Low Power 131kHz oscillator

01 Precision 131kHz oscillator

10 External 32.768kHz Crystal

11 Reserved

Name : PLLKEY1 Address : 0xFFFF0418 Default Value : 0x00000000 Access : Write Only Key: 0x00000055

Function : PLLCON is a keyed register that requires a

32 Bit key value to be written before and after PLLCON. PLLKEY1 is the Post-Write Key

POWCON Pre-write Key POWKEY0:

Name : POWKEY0 Address : 0xFFFF0404 Default Value : 0x00000000 Access : Write Only Key: 0x00000001

Function : POWCON is a keyed register that requires a

32 Bit key value to be written before and after POWCON. POWKEY0 is the Pre Write Key

Rev. PrD | Page 70 of 128

POWCON Pre-write Key POWKEY1:

Name : POWKEY1 Address : 0xFFFF040C Default Value : 0x00000000 Access : Write Only Key: 0x000000F4

Function : POWCON is a keyed register that requires a

32 Bit key value to be written before and after POWCON. POWKEY1 is the Post Write Key

Preliminary Technical Data ADuC7032

POWCON Register :

Name : POWCON Address : 0xFFFF0408 Default Value : 0x079 Access : Read/Write Function : This 8-bit register allows user code dynamically enter various Low Power modes and modify the CD divider which

controls the speed of the ARM7TDMI Core.

Table 37 : POWCON MMR bit designations

Bit Description

31-8 Reserved 7 Precision 131kHz Input Enable:

Cleared by the user to Power down the Precision 131kHz Input Enable. Set by the user to enable the Precision 131kHz Input Enable. The Precision 131kHz oscillator must also be enabled via

HVCFG0[6]. Setting this bit increases current consumption by approximately 50uA and should be disabled when not in use.

6 XTAL Power Down:

Cleared by the user to Power down the external crystal circuitry. Set by the user to enable the external crystal circuitry.

5 PLL Power Down1:

This bit is cleared to 0 to power down the PLL. The PLL can not be powered down if either the core or peripherals are enabled: Bits 3, 4 and 5 must be cleared simultaneously.

Set by default, and set by hardware on a wake up event

4 Peripherals

Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: bits 3 and 4 must be cleared simultaneously.

Set by default, or and by hardware on a wake up event

3 Core Power Down:

Cleared to power down the ARM Core Set by default, and set by hardware on a wake up event

2-0

CD Core clock divider bits: 000 20.48 MHz 48.83ns 001 10.24 MHz 97.66ns 010 5.12 MHz 195.31ns 011 2.56 MHz 390.63ns 100 1.28 MHz 781.25ns 101 640 kHz 1.56µs 110 320 kHz 3.125µs 111 160 kHz 6.25µs

Timer peripherals will be powered down if driven from the PLL Output clock. Timers driven from an active clock source will stay in normal power mode.

The peripherals that are powered down by this bit are as follows:

LIN can still respond to wake-up events even if this bit is cleared.

Wake-Up Timer (Timer2) can still be active if driven from low power oscillator even if this bit is set.

If user code powers down the MCU, a dummy MCU cycle should be included after the power-down command is written to POWCON.

SRAM, Flash/EE Memory and GPIO Interfaces SPI and UART Serial Ports

2,3, 4

Power Down:

Rev. PrD | Page 71 of 128

Preliminary Technical Data ADuC7032

ADUC7032 LOW POWER CLOCK CALIBRATION

The low power 131kHz oscillator may be calibrated using either the precision 131kHz oscillator, or an external 32.768KHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to implement this feature.

One counter, 9-bits wide, is clocked by the accurate clock oscillator, either the Precision oscillator or external watch crystal. The second counter, 10-bits wide, is clocked by the low power oscillator, either directly at 131kHz or via a divide by 4 block generating 32.768kHz. The source for each calibration counter should be of the same frequency. The trim register (OSC0TRM) is an 8-bit wide register, the lower 4-bits of which are user accessible trim bits. Increasing the value in OSC0TRM will decrease the frequency of the low power oscillator, decreasing the value will increase the frequency. Based on a nominal frequency of 131KHz, the typical trim range is between 127KHz to 135KHz. The OSC0TRIM bits have a resolution of typically 500Hz per LSB.

The clock calibration mode is configured and controlled by the following MMRs:

- OSC0CON: Control bits for calibration,

- OSC0STA: Calibration Status Register

- OSC0VAL0: 9Bit counter. Counter 0

- OSC0VAL1: 10Bit counter. Counter 1

- OSC0TRM: Oscillator Trim Register

An example calibration routine is shown in Figure 28. User code configures and enables the calibration sequence via OSC0CON. When the precision oscillator calibration counter, OSC0VAL0, reaches 0x1FF, both counters are disabled.

When the OSC0TRM has been changed the routine should be re-run and the new frequency checked.

Using the internal precision 131kHz oscillator, it will take approximately 4milliseconds to execute the calibration routine. If the external 32.768kHz crystal is used, this time increases to 16milliseconds.

NOTE: Prior to the clock calibration routine been started, it is required that the user switch to either the precision 131kHz oscillator or the external 32.768KHz watch crystal as the PLL Clock Source. If this is note done, it is possible that the PLL will lose lock each time OSC0TRM is modified. This will increase the length of time it takes to calibrate the Low Power, Oscillator.

BEGIN

CALIBRATION

ROUTINE

WHILE

OSCSTA[0] = 1

OSC0VAL0 < OSC0VAL1 OSC0VAL0 > OSC0VAL1

OSC0VAL0 = OSC0VAL1

INCREASE OSC0TRM

DECREASE

OSC0TRM

User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios:

- OSC0VAL0 = OSC0VAL1. No Further Action is required.

- OSC0VAL0 > OSC0VAL1. The Low Power Oscillator is running slow. OSC0TRM must be decreased.

- OSC0VAL0 < OSC0VAL1. The Low Power Oscillator is running fast. OSC0TRM must be increased.

Rev. PrD | Page 72 of 128

IS ERROR WIT HIN

DESIRED LEVEL?

YES

END

CALIBRATIO N

ROUTINE

Figure 28 : Example OSC0TRM Calibration Routine

05994-028

Preliminary Technical Data ADuC7032

OSC0TRM Register :

Name : OSC0TRM Address : 0xFFFF042C Default Value : 0x08 Access : Read/Write Function : This 8-bit register controls the Low Power Oscillator Trim

Table 38 : OSC0TRM MMR Bit Definition

Bit Description

7-4

3-0 User Trim Bits

Reserved and should be written as zeros

OSC0CON Register :

Name : OSC0CON Address : 0xFFFF0440 Default Value : 0x00 Access : Read/Write Function : This 8-bit register controls the Low Power Oscillator Calibration routine

Table 39: OSC0CON MMR Bit Definition

Bit Description

7-5 Reserved and should be written as zeros

3 Calibration Reset

2 Set to clear OSCVAL1

Calibration Source

Set to select external 32.768KHz crystal Cleared to select internal precision 131KHz Oscillator.

Set to reset the calibration counters and disable the Calibration logic

1 Set to clear OSCVAL0

Calibration Enable

Set to begin calibration Cleared to abort calibration

Rev. PrD | Page 73 of 128

Preliminary Technical Data ADuC7032

OSC0STA Register :

Name : OSC0STA Address : 0xFFFF0444 Default Value : 0x00 Access : Read Access only Function : This 8-bit register reflects the status of the Low Power Oscillator Calibration routine

Table 40 : OSC0STA MMR Bit Definition

Bit Description

31-4

3-2

Reserved

Current State of Calibration 00 Calibration Idle, device disabled or completed 01 Counter Enable state 10 Counting 11 Finished, return to Idle Calibration Enable

Set to begin calibration Cleared to abort calibration Set if calibration is in progress. Cleared if calibration completed

OSC0VAL0 Register :

Name : OSC0VAL0 Address : 0xFFFF0448 Default Value : 0x00 Access : Read Access only Function : This 9-bit counter is clocked from either the

131kHz Precision Oscillator or the 32.768kHz external crystal.

OSC0VAL1 Register :

Name : OSC0VAL1 Address : 0xFFFF044C Default Value : 0x00 Access : Read Access only Function : This 10 bit counter is clocked from the Low

Power, 131kHz oscillator..

Rev. PrD | Page 74 of 128

Preliminary Technical Data ADuC7032

PROCESSOR REFERENCE PERIPHERALS

INTERRUPT SYSTEM

There are 15 interrupt sources on the ADuC7032 which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, etc.. The ARM7TDMI CPU core will only recognize interrupts as one of two types, a normal interrupt request IRQ and a fast interrupt request FIQ. All the interrupts can be masked separately.

The control and configuration of the interrupt system is managed through nine interrupt-related registers, four dedicated to IRQ, four dedicated to FIQ. An additional MMR is used to select the programmed interrupt source. The bits in each IRQ and FIQ registers represent the same interrupt source as described in Table 41.

IRQSTA/FIQSTA should be saved immediately upon entering the ISR ( Interrupt Service Routine ) to ensure that all valid interrupt sources are serviced.

The interrupt generation route through the ARM7TDMI core is shown in Figure 29.

Table 41 : IRQ/FIQ MMRs bit description

Consider the example of Timer0 which is configured to generate a timeout every 1ms. After the first 1ms timeout, FIQSIG/IRQSIG[2] will be set and will only be cleared by writing to T0CLRI. If Timer0 is not enabled in either IRQEN or FIQEN, then FIQSTA/IRQSTA[2] will not be set and an interrupt will not occur. If Timer0 is enabled in either IRQEN or FIQEN, then either FIQSTA/IRQSTA[2] will be set and either an FIQ or an IRQ interrupt will occur.

Please note that the IRQ and FIQ interrupt bit definitions in the CPSR only control interrupt recognition by the ARM Core, not by the peripherals. For example, if Timer2 is confirgured to generate an IRQ via IRQEN, the IRQ interrupt bit is set ( Disabled ) in the CPSR and the ADuC7032 is powered down. When an interrupt occurs, the peripherals will be woken, but the ARM core will remain powered down. This is equivalent to POWCON = 0x71. The ARM Core can only be powered up by a reset event if this occurs.

Bit Description For more information please refer to:

0 All interrupts OR’ed 1 SWI:

not used in IR 2 Timer 0 Timer0 – Life-Time timer Page 78 3 Timer 1 Timer1 Page 79 4 Timer 2 - Wake Up timer Timer2 - Wake-UpTimer Page 82 5 Timer 3 - Watchdog Timer Timer3 - Watchdog Timer Page 83 6 Reserved and should be written as zero 7 LIN Hardware LIN (Local Interconnect Network ) INTERFACE Page 115 8 Flash/EE Interrupt Flash/EE memoryControl Interface Page 31 9 PLL Lock ADuC7032 System Clocks Page 68

10 ADC 11 UA RT UART SERIAL IN TERFACE Page 105 12 SPI SERIAL PERIPHERAL INTERFACE Page 112 13 XIRQ0 ( GPIO IRQ 0 ) General Purpose I/O Page 84 14 XIRQ1 ( GPIO IRQ 1 ) General Purpose I/O Page 84 15 Reserved and should be written as zero 16 IRQ3 High Voltage IRQ High Voltage Interrupt

17 XIRQ4 ( GPIO IRQ 4 ) General Purpose I/O Page 84 18 XIRQ5 ( GPIO IRQ 5 ) General Purpose I/O Page 84

EN/CLR and FIQEN/CLR

16-Bit

−∆ Analog to Digital Converters Page 44

Rev. PrD | Page 75 of 128

Preliminary Technical Data ADuC7032

FIQEN. An interrupt source can be disabled in both IRQEN

IRQ

The IRQ is the exception signal to enter the IRQ mode of the processor. It is used to service general purpose interrupt handling of internal and external events.

The four 32-bit registers dedicated to IRQ are:

- IRQSIG, reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG will be set, otherwise it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read-only. IRQSIG may be used to poll interrupt sources.

- IRQEN, provides the value of the current enable mask. When bit is set to 1, the source request is enabled to create an IRQ exception. When bit is set to 0, the source request is disabled or masked which will not

create an IRQ exception.

- IRQCLR, (write-only register) allows clearing the IRQEN

register in order to mask an interrupt source. Each bit set to 1 will clear the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers IRQEN and IRQCLR allows independent manipulation of the enable mask without requiring an atomic read-modifywrite.

- IRQSTA, (read-only register) provides the current enabled IRQ source status( effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1 that source will generate an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. All 32 bits are logically OR’ed to create a single IRQ signal to the ARM7TDMI core.

FIQ

The FIQ (Fast Interrupt reQuest) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transferor communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface providing the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA.

Bit 31 to 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and the bit 0 of both the FIQ and IRQ registers (FIQ source).

The logic for FIQEN and FIQCLR will not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to ‘1’ in FIQEN will, as a side-effect, clear the same bit in IRQEN. A bit set to ‘1’ in IRQEN will, as a side-effect, clear the same bit in

and FIQEN masks.

Programmed interrupts

As the programmed interrupts are non-maskable, they are controlled by another register, SWICFG, which write into both IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG registers at the same time.

The 32-bit register dedicated to software interrupt is SWICFG described in Table 42a. This MMR allows the control of programmed source interrupt.

Table 42 : SWICFG MMR Bit Descriptions

Bit Description

31-3

Reserved

Programmed Interrupt-FIQ Setting/clearing this bit correspond in setting/clearing bit 1 of FIQSTA and FIQSIG

Programmed Interrupt-IRQ Setting/clearing this bit correspond in setting/clearing bit 1 of IRQSTA and IRQSIG

Reserved

Note that any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by user in the IRQSTA/FIQSTA register.

TIMER0 TIMER1 TIMER2 TIMER3

LIN H/W FLASH/EE PLL LOCK

ADC

UART

SPI

XIRQ

TIMER0 TIMER1 TIMER2 TIMER3

LIN H/W FLASH/EE PLL LOCK

ADC

UART

SPI

XIRQ

FIQSIG

IRQSIG

FIQEN

IRQEN

Figure 29: Interrupt Structure

IRQSTA

IRQ

FIQ

FIQSTA

05994-029

Rev. PrD | Page 76 of 128

Preliminary Technical Data ADuC7032

)

TIMERS

The ADuC7032 features four general purpose Timer/Counters:

- Timer0, or Life-Time Timer

- Timer1,

- Timer2 or Wake-up Timer,

- Timer3 or Watchdog Timer.

The four timers in their normal mode of operation may either be free-running or periodic.

- In free-running mode the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value.

- In periodic mode the counter decrements/increments from the value in the Load Register(TxLD MMR,) until zero/full scale and starts again at the value stored in the Load Register.

Table 43 : Timer Event Capture

The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the Control register of the corresponding timer (TxCON).

In normal mode, an IRQ is generated each time the value of the counter reaches zero, if counting down, or full-scale, if counting up. An IRQ can be cleared by writing any value to Clear register of the particular timer (TxCLRI). Once TxCLRI is written to, the Timer is reloaded with TxLD within 4 clocks of the timers clock source.

Bit Description For more information please refer to:

0 Timer 0 Timer0 – Life-Time timer Page 78 1 Timer 1 Timer1 Page 79 2 Timer 2 - Wake Up timer Timer2 - Wake-UpTimer Page 82 3 Timer 3 - Watchdog Timer Timer3 - Watchdog Timer Page 83 4 Reserved Should be written as zero 5 LIN Hardware LIN (Local Interconnect Network ) INTERFACE Page 115 6 Flash/EE Interrupt Flash/EE memoryControl Interface Page 31 7 PLL Lock ADuC7032 System Clocks Page 68 8 ADC

9 UART UART SER IAL INTERFACE Page 105 10 SPI SERIAL PERIPHERAL INTERFACE Page 112 11 XIRQ0 ( GPIO IRQ 0 12 XIRQ1 ( GPIO IRQ 1 13 Reserved Should be written as zero 14 IRQ3 High Voltage IRQ High Voltage Interrupt

15 XIRQ4 ( GPIO IRQ 4 16 XIRQ5 ( GPIO IRQ 5

16-Bit

General Purpose I/O Page 84 General Purpose I/O Page 84

−∆ Analog to Digital Converters Page 44

Rev. PrD | Page 77 of 128

Preliminary Technical Data ADuC7032

TIMER0 – LIFE-TIME TIMER

Timer0 is a general purpose 48-bit count-up, or a 16-bit count up/down timer with a programmable prescalar. Timer0 may be

clocked from either the Core clock, the Low Power 32.768kHz Oscillator, the Precision 32.768kHz Oscillator or an external

32.768kHz crystal, with a prescalar of 1,16, 256 or 32768. This

gives a minimum resolution of 48.83ns when the core is operating at 20.48MHz, and with a prescalar of 1.

In 48-bit mode, Timer0 counts up from zero. The current counter value may be read from T0VAL0 and T0VAL1.

In 16-Bit mode,Timer0 may count up or count down. A 16-bit value may be written to T0LD which will be loaded into the counter. The current counter value may be read from T0VAL0. Timer0 has a capture register (T0CAP), which may be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone.

32.768kHz OSCI LLATOR

LOW POWER

PRECISION

EXTERNAL 32. 768kHz

WATCH CRYSTAL

CLOCK FREQUENCY

CORE

PRESCALER

1, 16, 256, O R 32768

Timer0 reloads the value from T0LD either when TIMER0 overflows, or immediately when T0CLRI is written.

Timer0 interface consists of six MMRS:

- T0LD is a 16-bit register which holds the 16 bit value that is loaded into the counter. Only available in 16-bit mode.

- T0CAP is a 16-bit register which holds the 16-bit value captured by an enabled IRQ event. Only available in 16-bit mode.

- T0VAL0/T0VAL1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16-bit T0VAL0 and 32-bit T0VAL1 are used.

- T0CLRI is an 8-bit register. Writing any value to this register will clear the interrupt. Only available in 16-bit mode.

- T0CON is the configuration MMR described in Table 44.

16-BIT LO AD

48-BIT UP COUNTER

16-BIT UP/DO WN COUNTER

TIMER0

VALUE

TIMER0 IR

IRQ[31:0]

Figure 30 : Timer 0 block diagram

Timer0 Value Register :

Name : T0VAL0/T0VAL1 Address : 0xFFFF0304, 0xFFFF0308 Default Value : 0x00, 0x00 Access : Read Only Function : T0VAL0 and T0VAL1 are 16-bit and 32-bit

registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16bit T0VAL0 and 32-bit T0VAL1 are used.

Rev. PrD | Page 78 of 128

CAPTURE

05994-030

Timer0 Capture Register :

Name : T0CAP Address : 0xFFFF0314 Default Value : 0x00 Access : Read Only Function : This is a 16-bit register which holds the 16-

bit value captured by an enabled IRQ event. Only available in 16-bit mode.

Preliminary Technical Data ADuC7032

Timer0 Control Register :

Name : T0CON Address : 0xFFFF030C Default Value : 0x00 Access : Read/Write Only Function : The 17-bit MMR configures the mode of operation of Timer0

Tab le 44 : T 0CO N M MR Bit Descriptions

Bit Description

31-18

16-12

10-9

3-0

Reserved This bit is reserved and should be written as 0 by user code. Event Select bit:

Set by user to enable time capture of an event Cleared by user to disable time capture of an event

Event select range, 0 to 31 The events are as described in Table 43.

Reserved This bit is reserved and should be written as 0 by user code. Clock Select: 00

01 10 11 Count up: ( Only available in 16Bit Mode )

Set by user for timer 0 to count up Cleared by user for timer 0 to count down. ( Default )

Timer0 enable bit: Set by user to enable timer 0 Cleared by user to disable timer 0. ( Default ) Timer 0 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Reserved This bit is reserved and should be written as 0 by user code. Timer0 Mode of Operation: 0 16 Bit operation ( Default ) 1 48 Bit Operation Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768

Core Clock ( Default ) Low Power 32.768kHz Oscillator External 32.768kHz Watch Crystal Precision 32.768kHz Oscillator

Timer0 Load Registers:

Name : T0LD Address : 0xFFFF0300 Default Value : 0x00 Access : Write Once Only Function : T0LD0 is a 16-bit register which holds the

16 bit value that is loaded into the counter. Only available in 16-bit mode.

Rev. PrD | Page 79 of 128

Timer0 Clear Register :

Name : T0CLRI Address : 0xFFFF0310 Default Value : 0x0FF Access : Write Only Function : This 16-bit, write-only MMR is written

(with any value) by user code to refresh(reload) Timer0.

Preliminary Technical Data ADuC7032

TIMER1

Timer1 is a 32-bit general purpose timer, count-down or countup, with a programmable pre-scalar. The pre-scalar source can be the Low Power 32.768kHz Oscillator, the core clock, or from one of two external GPIO. This source can be scaled by a factor of 1, 16, 256 or 32768. This gives a minimum resolution of

48.83ns when operating at CD zero, the core is operating at

20.48MHz, and with a pre-scalar of 1 ( Ignoring external GPIO).

The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundreths.

Timer1 has a capture register (T1CAP), which can be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy.

Timer1 interface consists of five MMRS:

- T1LD, T1VAL and T1CAP are 32-bit registers and hold 32- bit unsigned integers. T1VAL and T1CAP are read-only.

- T1CLRI is an 8-bit register. Writing any value to this register will clear the timer1 interrupt.

- T1CON is the configuration MMR described in below.

Timer1 features a post-scalar. This allows the user to count between1 and 256 the number of timer1 timeouts. To activate the post-scalar, the user sets bit 23 and writes the desired number to count into bits 24-31 of T1CON. Once that number of timeouts has reached, Timer1 will generate an interrupt if T1CON[18] is set.

NOTE: If the part is in a low power mode, and Timer1 is

clocked from the GPIO or low power oscillator source then, Timer1 will continue to be operate.

Timer1 reloads the value from T1LD either when TIMER01 overflows, or immediately when T1CLRI is written.

Timer1 Load Registers:

Name : T1LD Address : 0xFFFF0320 Default Value : 0x00000 Access : Write Only Function : T1LD is a 32 bit register which holds the 32

bit value that is loaded into the counter.

Timer1 Clear Register :

Name : T1CLRI Address : 0xFFFF032C Default Value : 0xFF Access : Write Only Function : This 32-bit, write-only MMR is written

(with any value) by user code to refresh(reload) Timer1.

Timer1 Value Register :

Name : T1VAL Address : 0xFFFF0324 Default Value : 0xFFFFFFFF Access : Read Only Function : T1VAL is a 32-bit register which holds the

current value of Timer1

32-BIT LO AD

LOW POWER

2.768kHz OSCI LLATOR

CLOCK FREQUE NCY

CORE

GPIO

PRESCALER

1, 16, 256, O R 32768

IRQ[31:0]

Figure 31 : Timer 1 Block Diagram

32-BIT

UP/DOWN COUNT ER

CAPTURE

Rev. PrD | Page 80 of 128

TIMER1 VALUE

8-BIT

POSTSCALER

TIMER1 IRQ

05994-031

Preliminary Technical Data ADuC7032

Timer1 Control Register :

Timer1 Capture Register :

Name : T1CAP Address : 0xFFFF0330 Default Value : 0x00 Access : Write Only Function : This is a 32-bit register which holds the 32-

bit value captured by an enabled IRQ event.

Table 45 : T1CON MMR Bit Descriptions

Bit Description

31-24

22-20

16-12

11-9

5-4

3-0

Timer 1 8 Bit Post-Scalar By writing to these 8 bits, a value is loaded into the post-scalar. By reading these 8 bits, the current value of the counter is loaded. Timer 1 Enable Post-Scalar: Set To enable Timer1 Post Scalar. If enabled, an interrupts will be generated after T1CON[31-24] periods as defined by T1LD. Cleared To disable Timer1 Post Scalar. Reserved This bit is reserved and should be written as 0 by user code. Post-Scalar Compare Flag.

Set if the number of Timer1 overflows is equal to the number written to the post-scalar Timer 1 Interrupt Source

Set To select interrupt generation from post-scalar counter Cleared To select interrupt generation direct from Timer1

Event Select bit:

Set by user to enable time capture of an event Cleared by user to disable time capture of an event

Event select range, 0 to 31 The events are as described in Table 43.

Clock select: 000 Core clock ( Default ) 001

010 011 Count up:

Set by user for timer 1 to count up Cleared by user for timer 1 to count down. ( Default )

Timer1 enable bit: Set by user to enable timer 1 Cleared by user to disable timer 1. ( Default ) Timer 1 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) 01 10 Hr:Min:Sec:Hundredths – 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths – 255 hours to 0 hour Pre-Scalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768

Low Power 32.768kHz Oscillator GPIO8 GPIO5

Reserved

Name : T1CON Address : 0xFFFF0328 Default Value : 0x0000 Access : Read/Write Only Function : This 32-bit MMR configures the mode of

operation of Timer1

Rev. PrD | Page 81 of 128

Preliminary Technical Data

TIMER2 - WAKE-UP TIMER

Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. The pre-scalar is clocked directly from 1 of 4 clock sources, namely, the Core Clock (default selection), the Low Power 32.768kHz Oscillator, External 32.768kHz Watch Crystal, or the Precision 32.768kHz Oscillator. The selected clock source can be scaled by a factor of 1, 16, 256 or 32768. The wake-up timer will continue to run when the core clock is disabled. This gives a minimum resolution of 48.83ns when operating at CD zero, the core is operating at 20.48MHz, and with a prescalar of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4].

The counter can be formatted as plain 32-bit value or as Hours:Minutes:Seconds:Hundreths.

Timer2 reloads the value from T2LD either when TIMER2 overflows, or immediately when T2CLRI is written.

Timer2 interface consists of four MMRS:

- T2LD and T2VAL are 32-bit registers and hold 32-bit unsigned integers. T2VAL is read-only.

- T2CLRI is an 8-bit register. Writing any value to this register will clear the timer2 interrupt.

- T2CON is the configuration MMR described in Table 36 below.

ADuC7032

Timer2 Load Registers:

Name : T2LD Address : 0xFFFF0340 Default Value : 0x00000 Access : Write Only Function : T2LD is a 32 bit register which holds the 32

bit value that is loaded into the counter.

Timer2 Clear Register :

Name : T2CLRI Address : 0xFFFF034C Default Value : 0xFF Access : Write Only Function : This 32-bit, write-only MMR is written

(with any value) by user code to refresh(reload) Timer2.

Timer2 Value Register :

Name : T2VAL Address : 0xFFFF0344 Default Value : 0xFFFFFFFF Access : Read Only Function : T2VAL is a 32-bit register which holds the current value of Timer2

32.768kHz OSCI LLATOR

EXTERNAL 32.768kHz

PRECISION

LOW POWER

CORE

CLOCK

WATCH CRY STAL

PRESCALER

1, 16, 256, O R 32768

Figure 32 : Timer 2 block diagram

32-BIT LO AD

32-BIT

UP/DOWN COUNT ER

TIMER2

VALUE

TIMER2 IRQ

5994-032

Rev. PrD | Page 82 of 128

Preliminary Technical Data ADuC7032

Timer2 Control Register :

Name : T2CON Address : 0xFFFF0348 Default Value : 0x0000 Access : Read/Write Only Function : This 32-bit MMR configures the mode of operation of Timer2

Tab le 46 : T 2CO N M MR Bit Descriptions

Bit Description

31-11

10-9

5-4

3-0

Reserved

Clock Source Select: 00

01 10 11 Count up:

Set by user for timer 2 to count up Cleared by user for timer 2 to count down. ( Default ) Timer2 enable bit: Set by user to enable timer 2 Cleared by user to disable timer 2. ( Default ) Timer 2 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) 01 10 Hr:Min:Sec:Hundredths – 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths – 255 hours to 0 hour Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 ( This setting should be used in conjunction Timer2 Formats 1,0 and 1,1 ) 1111 Source clock / 32768

Core Clock ( Default ) Low Power 32.768kHz Oscillator External 32.768kHz Watch Crystal Precision 32.768kHz Oscillator

Reserved

Rev. PrD | Page 83 of 128

Preliminary Technical Data ADuC7032

TIMER3 - WATCHDOG TIMER

Timer3 has two modes of operation, normal mode and watchdog mode. The Watchdog timer is used to recover from an illegal software state. Once enabled it requires periodic servicing to prevent it from forcing a reset of the processor.

Timer3 reloads the value from T3LD either when TIMER3 overflows, or immediately when T3CLRI is written.

Normal mode:

The Timer3 in normal mode is identical to Timer0, in 16-bit mode of operation, except for the clock source. The clock source is the Low Power 32.768kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility, which allows the capture of the current timer

value if the Timer2 interrupt is enabled via IRQEN[5].

Watchdog mode:

Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in T3LD Register until zero. The maximum timeout is 512 seconds, using the maximum pre-scalar /256 and full-scale in T3LD.

User software should only configure a minimum timeout period of 30msecs. This is to avoid any conflict with Flash/EE memory page erase cycles, which require 20ms to complete a single page erase cycle.

If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period.

Once watchdog mode is entered, T3LD and T3CON are writeprotected. These two registers can not be modified until a reset event resets the Watchdog Timer.

Timer3 is automatically halted during JTAG debug access and will only recommence counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This may be disabled by setting bit zero in T3CON. It is recommended that the default value is used, i.e. that the Watchdog Timer continues to count during power-down.

16-BIT LO AD

LOW POWER

32.768kHz

PRESCALER

1, 16, 256

Figure 33 : Timer3 Block Diagram

Timer3 Interface:

Timer3 interface consists of four MMRS:

- T3CON is the configuration MMR described in Table 37

- T3LD and T3VAL are 16-bit registers (bit 0 to 15) and hold

16-bit unsigned integers. T3VAL is read-only.

- T3CLRI is an 8-bit register. Writing any value to this register will clear the Timer3 interrupt in normal mode or will reset a new timeout period in watchdog mode

16-BIT

UP/DOWN COUNTER

TIMER3

VALUE

WATCHDOG RESET

TIMER3 IRQ

05994-033

Timer3 Load Register :

Name : T3LD Address : 0xFFFF0364 Default Value : 0x03D7 Access : Write Once Only Function : This 16-bit MMR holds the Timer3 reload

value.

Timer3 Value Register :

Name : T3VAL Address : 0xFFFF0364 Default Value : 0x03D7 Access : Read Only Function : This 16-bit, read-only MMR holds the

currentTimer3 count value.

Rev. PrD | Page 84 of 128

Preliminary Technical Data ADuC7032

Timer3 Clear Register :

Name : T3CLRI Address : 0xFFFF036C Default Value : 0x00 Access : Write Only Function : This 16-bit, write-only MMR is written

Timer3 Control Register :

Name : T3CON Address : 0xFFFF0368 Default Value : 0x00 Access : Read/Write Once Only

Function : The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 47.

Table 47 : T3CON MMR Bit Definition

Bit Description

16-9

8 Count Up/Down Enable

7 Timer3 Enable

6 Timer3 Operating Mode

5 Watchdog Timer Mode Enable

3-2 Timer3 Clock(32.768kHz) Pre-Scalar

1 Watchdog Timer IRQ Enable

0 PD_OFF

These bits are reserved and should be written as 0 by user code

Set by user code to configure Timer3 to count up Cleared by user code to configure Timer3 to count down.

Set by user code to enable Timer 3 Cleared by user code to disable Timer 3. .

Set by user code to configure Timer3 to operate in periodic mode Cleared by user to configure Timer3 to operate in free-running mode.

Set by user code to enable watchdog mode Cleared by user code to disable watchdog mode. This bit is reserved and should be written as 0 by user code

00 Source clock / 1 ( Default ) 01 Source clock / 16 10 Source clock / 256 11 Reserved

Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0 Cleared by user code to disable the IRQ option.

Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR. Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.

(with any value) by user code to refresh(reload) Timer3 in watchdog mode to prevent a watchdog timer reset event. This register must be written with a specific value (generated by user code, based on a polynomial equation) to refresh the watchdog timer and prevent a watchdog reset.

Rev. PrD | Page 85 of 128

Preliminary Technical Data

GENERAL PURPOSE I/O

The ADuC7032 features 9 General Purpose bi-directional I/O pins (GPIO). In general, many of the GPIO pins have multiple functions which can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull up resistor and their sink capability is 0.8mA and they can source 0.1mA.

The 9 GPIO are grouped into three ports, Port0, Port1 and Port2. Port0 is 5 bits wide. Port1 and Port2 are both 2 bits wide. The GPIO assignment within each port is detailed in Table 48.

A typical GPIO structure is shown Figure 34.

External Interrupts are present on GP0, GP5, GP7 and GP8. This interrupts are level triggered and are active high. These interrupts are not latched, therefore the interrupts source must be present until either IRQSTA or FIQSTA are interrogated. The Interrupt source must be active for at least 1 CD divided core clock to guarantee recognition.

OUTPUT DRIVE ENABLE

GPxDAT[31:24]

OUTPUT DATA

GPxDAT[23:16]

INPUT DATA GPxDAT[7:0]

GPIO IRQ

ONLY AVAIL ABLE ON GP0, G P5, GP7, AND GP8.

Figure 34 : ADuC7032 GPIO

ADuC7032

All port pins are configured and controlled by 4 sets (1 set for each port) of four port specific MMRs:

GPxCON: Port x Control Register GPxDAT: Port x Configuration and Data Register GPxSET: Data set port x GPxCLR: Data clear port x

where x corresponds to the port number 0,1 or 2

During normal operation, user code can control the function and state of the external GPIO pins via these general purpose registers. All GPIO pins will retain their external (high or low) during power-down (POWCON) mode.

REG_DVDD

GPIO

05994-035

Rev. PrD | Page 86 of 128

Preliminary Technical Data ADuC7032

Table 48 : External GPIO Pin to Internal Port Signal Assignments

These signals are internal signals only and do not appear on an external pin. These pins are used along with HVCON as the 2 wire

interface to the high voltage interface circuits.

These pins/signals are internal signals only and do not appear on an external pins. Both signals are used to provide external pin

diagnostic write(GPIO12) and read-back(GPIO11) capability.

GPIO PIN PORT SIGNAL Functionality ( Defined by GPxCON )

General Purpose I/O GPIO0 P0.0

IRQ0

, Slave Select I/O for SPI

General Purpose I/O GPIO1 P0.1

SCLK, Serial Clock I/O for SPI

General Purpose I/O GPIO2 P0.2

MISO, Master Input, Slave Output for SPI

Port 0

General Purpose I/O GPIO3 P0.3

MOSI, Master Output, Slave Input for SPI

General Purpose I/O GPIO4 P0.4

ECLK , a 2.56MHz clock output

P0.51 High Voltage Serial Interface

High Voltage Serial Interface

P0.6

General Purpose I/O GPIO5 P1.0

IRQ1

GPIO6 P1.1

Port 1

RxD Pin for UART

General Purpose I/O

TxD Pin for UART

General Purpose I/O GPIO7 P2.0

IRQ4

LIN Output Pin. Used to read directly from LIN PIN for conformance testing.

General Purpose I/O GPIO8 P2.1

IRQ5

LIN HV Input Pin. Used to directly drive LIN Pin for conformance testing.

General Purpose I/O GPIO112 P2.4

LIN Output Pin

General Purpose I/O GPIO122 P2.5

LIN Input Pin

Port 2

GPIO131 P2.6

Reserved

Rev. PrD | Page 87 of 128

Preliminary Technical Data ADuC7032

GPIO Port0 Control Register :

Name : GP0CON Address : 0xFFFF0D00 Default Value : 0x00000000 Access : Read/Write

Function : The 32-bit MMR selects the pin function for each Port0 pin.

Table 49 : GP0CON MMR Bit Designations

Bit Description

31-29 Reserved

These bits are reserved and should be written as 0 by user code

28 Reserved

This bit is reserved and should be written as 1 by user code

27-25 Reserved

These bits are reserved and should be written as 0 by user code

24 Internal P0.6 Enable Bit

This bit must be set to 1 by user software to enable the High Voltage Serial Interface before using the HVCON and HVDAT registered high voltage interface

23-21 Reserved

These bits are reserved and should be written as 0 by user code

20 Internal P0.5 Enable Bit

This bit must be set to 1 by user software to enable the High Voltage Serial Interface before using the HVCON and HVDAT registered high voltage interface

19-17 Reserved

These bits are reserved and should be written as 0 by user code

15-13 Reserved

11-9 Reserved

7-5 Reserved

3-1 Reserved

GPIO4 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO4 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO4 pin as ECLK enabling a 2.56MHz clock output on this pin

These bits are reserved and should be written as 0 by user code GPIO3 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO3 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO2 pin as MOSI, Master Output, Slave Input Data for the SPI Port

These bits are reserved and should be written as 0 by user code GPIO2 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO2 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO3 pin as MISO, Master Input, Slave Output Data for the SPI Port

These bits are reserved and should be written as 0 by user code GPIO1 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO1 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO1 pin as SCLK, Serial Clock I/O for the SPI Port

These bits are reserved and should be written as 0 by user code GPIO0 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO0 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO0 pin as

, Slave Select I/O for the SPI Port

Rev. PrD | Page 88 of 128

Preliminary Technical Data ADuC7032

GPIO Port1 Control Register :

Name : GP1CON Address : 0xFFFF0D04 Default Value : 0x00000000 Access : Read/Write

Function : The 32-bit MMR selects the pin function for each Port1 pin.

Table 50 : GP1CON MMR Bit Designations

Bit Description

31-5 Reserved

These bits are reserved and should be written as 0 by user code

3-1 Reserved

GPIO Port2 Control Register :

Name : GP2CON Address : 0xFFFF0D08 Default Value : 0x00000000 Access : Read/Write

Function : The 32-bit MMR selects the pin function for each Port2 pin.

GPIO6 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO6 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO6 pin as TxD, Transmit Data for UART Serial Port

These bits are reserved and should be written as 0 by user code GPIO5 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO5 pin as a General Purpose I/O (GPIO) pin This bit is set by user code to 1 to configure the GPIO5 RxD. Receive Data for UART Serial Port

Bit Description

31-21 Reserved

These bits are reserved and should be written as 0 by user code

20 GPIO12 Function Select Bit

This bit is cleared to 0 by user code to route the LIN transmit data to an internal General Purpose I/O (GPIO12) pad which can then be written via the GP2DAT MMR.

This bit is set to 1 by user code to route the UART TxD (transmit data) to the LIN data pin. This configuration is used in LIN mode.

19-17 Reserved

These bits are reserved and should be written as 0 by user code

Table 51 : GP2CON MMR Bit Designations

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Preliminary Technical Data ADuC7032

16 GPIO11 Function Select Bit

This bit is cleared to 0 by user code to internally disable the LIN input data path. In this configuration GPIO11 is used to support diagnostic read-back on all external high-voltage I/O pins (see HVCFG1[2:0])

This bit is set to 1 by user code to route input data from the LIN interface to both the LIN hardware timing/synchronization logic and to the UART RxD (receive data). This mode must be configured by user code when using LIN .

15-5 Reserved

These bits are reserved and should be written as 0 by user code

4 GPIO8 Function Select Bit

This bit is cleared by user code to 0 to configure the GPIO8 pin as a General Purpose I/O (GPIO) pin

This bit is set by user code to 1 to route the LIN input data to the GPIO8 pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART.

3-1 Reserved

These bits are reserved and should be written as 0 by user code

0 GPIO7 Function Select Bi

This bit is cleared by user code to 0 to configure the GPIO7 pin as a General Purpose I/O (GPIO) pin

This bit is set by user code to 1 to route data driven into the GPIO7 pin through the on-chip LIN transceiver to be output at the LIN pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART.

GPIO Port0 Data Register :

Name : GP0DAT Address : 0xFFFF0D20 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 48). This register also sets

the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.

Table 52 : GP0DAT MMR Bit Descriptions

Bit Description

31-29

23-21

Reserved These bits are reserved and should be written as 0 by user code

Port 0.4 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.4 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.4 as an output. Port 0.3 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.3 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.3 as an output. Port 0.2 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.2 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.2 as an output. Port 0.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.1 as an output. Port 0.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.0 as an output. Reserved These bits are reserved and should be written as 0 by user code

Rev. PrD | Page 90 of 128

Preliminary Technical Data ADuC7032

15-5

Port 0.4 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.4. Port 0.3 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.3. Port 0.2 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.2. Port 0.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.1. Port 0.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.0. Reserved These bits are reserved and should be written as 0 by user code Port 0.4 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.4. User code should write 0 to this bit.

Port 0.3 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.3. User code should write 0 to this bit.

Port 0.2 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.2. User code should write 0 to this bit.

Port 0.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.1. User code should write 0 to this bit.

Port 0.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.0. User code should write 0 to this bit.

GPIO Port1 Data Register :

Name : GP1DAT Address : 0xFFFF0D30 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 48). This register also sets

the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.

Table 53 : GP1DAT MMR Bit Descriptions

Bit Description

31-26

23-18

15-2

Reserved These bits are reserved and should be written as 0 by user code

Port 1.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P1.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P1.1 as an output. Port 1.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P1.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P1.0 as an output. Reserved These bits are reserved and should be written as 0 by user code

Port 1.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P1.1. Port 1.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P1.0. Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.1. User code should write 0 to this bit.

Port 1.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.0. User code should write 0 to this bit.

Rev. PrD | Page 91 of 128

Preliminary Technical Data ADuC7032

GPIO Port2 Data Register :

Name : GP2DAT Address : 0xFFFF0D40 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 48). This register also sets

the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.

Table 54 :GP2DAT MMR Bit Descriptions

Bit Description

30 Port 2.6 Direction Select Bit

29 Port 2.5 Direction Select Bit

28 Port 2.4 Direction Select Bit

27-26

20-18

15-7

3-2

Reserved This bit is reserved and should be written as 0 by user code

This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.6 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.6 as an output.

This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.5 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.5 as an output. This configuration is used to support diagnostic write capability to the high-voltage I/O pins.

This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.4 as an input. This configuration is used to support diagnostic read-back capability from the high-voltage I/O pins(see HVCFG1[2:0]). This bit is set to 1 by user code to configure the GPIO pin assigned to P2.4 as an output.

Reserved These bits are reserved and should be written as 0 by user code

Port 2.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.1 as an output. Port 2.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.0 as an output. Reserved This bit is reserved and should be written as 0 by user code

Port 2.6 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.6 Port 2.5 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.5. Reserved These bits are reserved and should be written as 0 by user code

Port 2.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.1. Port 2.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.0. Reserved These bits are reserved and should be written as 0 by user code Port 2.6 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.6. User code should write 0 to this bit.

Port 2.5 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.5. User code should write 0 to this bit.

Port 2.4 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.4. User code should write 0 to this bit.

Reserved These bits are reserved and should be written as 0 by user code

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Preliminary Technical Data ADuC7032

Port 2.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.1. User code should write 0 to this bit.

Port 2.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.0. User code should write 0 to this bit.

GPIO Port0 Set Register :

Name : GP0SET Address : 0xFFFF0D24 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only.

User code can do this via the GP0SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP0DAT.

Table 55 : GP0SET MMR Bit Descriptions

Bit Description

31-21 Reserved

These bits are reserved and should be written as 0 by user code

15-0 Reserved

Port 0.4 Set Bit This bit is set to 1 by user code to set the external GPIO4 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO4 pin. Port 0.3 Set Bit This bit is set to 1 by user code to set the external GPIO3 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO3 pin. Port 0.2 Set Bit This bit is set to 1 by user code to set the external GPIO2 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO2 pin. Port 0.1 Set Bit This bit is set to 1 by user code to set the external GPIO1 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO1 pin. Port 0.0 Set Bit This bit is set to 1 by user code to set the external GPIO0 pin high If user software clears this bit to 0, this will have no effect on the external GPIO0 pin.

These bits are reserved and should be written as 0 by user code

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Preliminary Technical Data ADuC7032

GPIO Port1 Set Register :

Name : GP1SET Address : 0xFFFF0D34 Default Value : 0x00000000 Access : Read/Write Function : This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only.

User code can do this via the GP1SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP1DAT.

Table 56 : GP1SET MMR Bit Descriptions

Bit Description

31-18 Reserved

These bits are reserved and should be written as 0 by user code

15-0 Reserved

Port 1.1 Set Bit This bit is set to 1 by user code to set the external GPIO6 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO6 pin. Port 1.0 Set Bit This bit is set to 1 by user code to set the external GPIO5 pin high If user software clears this bit to 0, this will have no effect on the external GPIO5 pin.

These bits are reserved and should be written as 0 by user code

GPIO Port2 Set Register :

Name : GP2SET Address : 0xFFFF0D44 Default Value : 0x00000000 Access : Read/Write Function : This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only.

User code can do this via the GP2SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP2DAT.

Table 57 : GP2SET MMR Bit Descriptions

Bit Description

31-23 Reserved

These bits are reserved and should be written as 0 by user code

20-18 Reserved

15-0 Reserved

Port 2.6 Set Bit This bit is set to 1 by user code to set the external GPIO13 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO13 pin. Port 2.5 Set Bit This bit is set to 1 by user code to set the external GPIO12 pin high If user software clears this bit to 0, this will have no effect on the external GPIO12 pin.

These bits are reserved and should be written as 0 by user code Port 2.1 Set Bit This bit is set to 1 by user code to set the external GPIO8 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.0 Set Bit This bit is set to 1 by user code to set the external GPIO7 pin high If user software clears this bit to 0, this will have no effect on the external GPIO7 pin.

These bits are reserved and should be written as 0 by user code

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Preliminary Technical Data ADuC7032

GPIO Port0 Clear Register :

Name : GP0CLR Address : 0xFFFF0D28 Default Value : 0x00000000 Access : Read/Write Function : This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only.

User code can do this via the GP0CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP0DAT.

Table 58 : GP0CLR MMR Bit Descriptions

Bit Description

31-21 Reserved

These bits are reserved and should be written as 0 by user code

15-0

Port 0.4 Clear Bit This bit is set to 1 by user code to clear the external GPIO4 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO4 pin. Port 0.3 Clear Bit This bit is set to 1 by user code to clear the external GPIO3 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO3 pin. Port 0.2 Clear Bit This bit is set to 1 by user code to clear the external GPIO2 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO2 pin. Port 0.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO1 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO1 pin. Port 0.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO0 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO0 pin.

Reserved These bits are reserved and should be written as 0 by user code

GPIO Port1 Clear Register :

Name : GP1CLR Address : 0xFFFF0D38 Default Value : 0x00000000 Access : Read/Write Function : This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only.

User code can do this via the GP1CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP1DAT.

Table 59 : GP1CLR MMR Bit Descriptions

Bit Description

31-18 Reserved

These bits are reserved and should be written as 0 by user code

15-0

Port 1.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO6 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO6 pin. Port 1.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO5 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO5 pin.

Reserved These bits are reserved and should be written as 0 by user code

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Preliminary Technical Data ADuC7032

GPIO Port2 Clear Register :

Name : GP2CLR Address : 0xFFFF0D48 Default Value : 0x00000000 Access : Read/Write

Function : This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only.

User code can do this via the GP2CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP2DAT.

Table 60 : GP2CLR MMR Bit Descriptions

Bit Description

31-23 Reserved

These bits are reserved and should be written as 0 by user code

20-18 Reserved

15-0

Port 2.6 Clear Bit This bit is set to 1 by user code to clear the external GPIO13 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.5 Clear Bit This bit is set to 1 by user code to clear the external GPIO12 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO7 pin.

These bits are reserved and should be written as 0 by user code Port 2.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO8 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO7 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO7 pin.

Reserved These bits are reserved and should be written as 0 by user code

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Preliminary Technical Data

HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE

The ADuC7032 integrates a number of high voltage circuit functions which are controlled and monitored via a registered interface consisting of 2 MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte interpreter allowing the microcontroller to indirectly read or write 8-bit data(the value in HVDAT) from/to one of 4 High voltage status/configuration registers. It should be noted that these high voltage registers are not MMRs but are so called ‘indirect’ registers that can only be accessed (as the name suggests) indirectly via the HVCON and HVDAT MMRs.

The physical interface between the HVCON register and the indirect high voltage registers is a 2 wire (data and clock) serial interface based on a 2.56MHz serial clock. Therefore, there is a finite, 10usecs(maximum) latency between the MCU core writing a command into HVCON and that command or data

HIGH-VOLTAGE

INTERFACE

MMRs

HVCON

HVDAT

SERIAL

DATA

SERIAL

CLOCK

SERIAL

INTERFACE

CONTROLL ER

ADuC7032

reaching the indirect high voltage registers. There is also a finite 10usecs latency between the MCU core writing a command into HVCON and indirect register data being read back into the HVDAT register. A busy bit (Bit0 of the HVCON when read by MCU) can be polled by the MCU to confirm when a read/write command has completed.

The following high voltage circuit functions are controlled and monitored via this interface and Figure 35 below describes the top-level architecture of the high voltage interface and related circuits.

- Precision Oscillator

- Wake-Up pin functionality

- Power Supply Monitor

- Low Voltage Flag

- LIN Operating Modes

- High Voltage Diagnostics

- High Voltage Attenuator/Buffer Circuit

- High Voltage Temperature Monitor

(INDIRECT)

HIGH-VOLTAGE

REGISTERS

HVCFG0

HVCFG1

HVSTA

HVMON

HVCFG0[6]

PRECISION

OSCILLATOR

PSMHVCFG0[ 3]

LVFHVCFG0[2]

ARM7

MCU

AND

PERIPHERALS

IRQ3 (IRQEN[16])

WU DIAGNOST IC I/P

STI DIAGNOSTIC I/P

LIN DIAGNO STIC I/P

PSM—HVSTA[5]

WU—HVSTA[4]

OVER TEMP—HVSTA[3]

LIN S-SCT—HVSTA[2]

STI S-SCT—HVSTA[1]

WU S-SCT—HVSTA[0]

WU DIAGNOST IC O/P HVMON[7]

STI DIAGNOSTIC O/P HVMON[5]

LIN DI AGNOSTI C O/P P2.4

HVCFG1[6]

HV TEMP

MONITOR

HVCFG0[4]

P2.6

P2.5

HVCFG1[3]

HVCFG1[7]

HVCFG1[5]

HIGH VO LTAGE

INTERRUPT

CONTROLL ER

HIGH VO LTAGE

DIAGNOSTI C

CONTROLL ER

ATTENUATOR

AND

BUFFER

Figure 35 : High Voltage Interface, Top Level Block Diagram

HVCFG0[5]

HVCFG0[1:0]

HVCFG0[4]

HVCFG1[4]

HVCFG1[3]

LIN

MODES

WU I/O

CONTROL

STI I/O

CONTROL

05994-036

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Preliminary Technical Data ADuC7032

High Voltage Interface Control Register :

Name : HVCON Address : 0xFFFF0804 Default Value : 0x00 Access : Read/Write

Function : This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this

register are interpreted as read or write commands to a set of 4 indirect registers related to the high voltage circuits. The HVDAT register is used to store data to be written to or read back from the indirect registers

Table 61: HVCON MMR Write Bit Designations

Bit Description

7-0

Command Byte Interpreted as

0x00 Read back high voltage register HVCFG0 into HVDAT 0x01 Read back high voltage register HVCFG1 into HVDAT 0x02 Read back high voltage status register HVSTA into HVDAT 0x03 Read back high voltage status register HVMON into HVDAT 0x08 Write the value in HVDAT to the high voltage register HVCFG0 0x09 Write the value in HVDAT to the high voltage register HVCFG1

All other command bytes are reserved and should not be written by user code

Bit Description

7-3

Reserved

Transmit Command to High Voltage Die Status:

1 Command Completed Successfully 0 Command Failed

Read Command from High Voltage Die Status:

1 Command Completed Successfully 0 Command Failed

Bit 0 (Read Only) BUSY Bit When user code reads this register, Bit0 should be interpreted as the BUSY signal for the high-voltage interface. This bit can be

used to determine if a read request has completed. High voltage (read/write) commands as described above should not be written to HVCON unless BUSY=0.

BUSY = 1, High voltage interface is busy and has not completed the previous command written to HVCON. Bit 1 and bit 2 are not valid.

BUSY = 0, High voltage interface is not busy and has completed the command written to HVCON. Bit 1 and bit 2 are valid.

Table 62: HVCON MMR Read Bit Designations

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Preliminary Technical Data ADuC7032

High Voltage Data Register:

Name : HVDAT Address : 0xFFFF080C Default Value : 0x00 Access : Read/Write

Function : HVDAT is a 12-bit register that is used to hold data to be written indirectly to and read indirectly from the following

high voltage interface registers

Tab le 63: H VDAT M MR Bit D es ign at ions

Bit Description

11-8

7-0

Command to which High Voltage Data, HVDAT[7-0], is associated with. These bits are read only and should be written as zeros.

High Voltage Data to Read/Write

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Preliminary Technical Data ADuC7032

High Voltage Configuration0 Register :

Name : HVCFG0 Address : Indirectly addressed via the HVCON high voltage interface Default Value : 0x00 Access : Read/Write

Function : This 8-bit register controls the function of high voltage circuits on the ADuC7032. This register is not an MMR and

does not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to this register is loaded via the HVDAT MMR and data is read back from this register via the HVDAT MMR.

Table 64: HVCFG0 Bit Designations

Bit Description

1-0

Wake Thermal Shutdown Disable: This bit is set to 1 to disable the automatic shutdown of the Wake driver when a thermal event occurs. This bit is cleared to 0 to enable the automatic shutdown of the Wake driver when a thermal event occurs. Precision Oscillator Enable Bit This bit is set to 1 to enable the Precision, 131kHz oscillator. The oscillator start-up time is typically 70µsecs (including HV interface latency of 10µsecs) This bit is cleared to 0 to power down the Precision, 131kHz oscillator Reserved This bit is reserved and should be written as 0 by user code. WU Assert Bit This bit is set to 1 to assert the external WU pin high.

This bit is cleared to 0 to pull the external WU pin low via an internal 10KΩ pull-down resistor. PSM Enable Bit This bit is cleared to 0 to disable the Power Supply (Voltage at the VDD pin) Monitor This bit is set to 1 to enable the Power Supply (Voltage at the VDD pin) Monitor. If IRQ3 (IRQEN[16] is enabled the PSM will generate an interrupt if the voltage at the VDD pin drops below 6.0V. Low Voltage Flag Enable Bit This bit is cleared to 0 to disable the Low Voltage Flag function This bit is set to 1 to enable the Low Voltage Flag function. The Low Voltage Flag can be interrogated via HVMON[3] after power up to determine if the REG_DVDD voltage previously dropped below 2.1V LIN Operating Mode These bits enable/disable the LIN driver. 0 0 LIN Disabled

0 1 Reserved – (not LIN V2.0 compliant)

1 0 LIN Enabled 1 1 Reserved

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Datasheet ADuC7032 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual