ANALOG DEVICES ADuC7029 Service Manual
Precision Analog Microcontroller, 12-Bit
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels
Fully differential and single-ended modes
0 V to V
analog input range
REF
12-bit voltage output DACs
Up to 4 DAC outputs available
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
1
1
Analog I/O, ARM7TDMI MCU
ADuC7019/20/21/22/24/25/26/27/28/29
On-chip peripherals
UART, 2× I
Up to 40-pin GPIO port
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator
Programmable logic array (PLA)
External memory interface, up to 512 kB
Power
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
Packages and temperature range
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP
Fully specified for –40°C to +125°C operation
Tools
Low cost QuickStart™ development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
FUNCTIONAL BLOCK DIAGRAM
2
C® and SPI serial I/O
1
1
1
1
ADC0
1MSPS
12-BIT ADC
TEMP
SENSOR
BAND GAP
REF
ARM7TDMI-BASED M CU WI TH
ADDITIONAL PERIPHERALS
PLA
31k × 16 FLASH/ EEPROM
4 GENERAL-
PURPOSE TI MERS
2k × 32 SRAM
ADC11
CMP0
CMP1
CMP
V
XCLKI
XCLKO
OUT
REF
RST
MUX
OSC
AND PLL
PSM
POR
1
Depending on part model. See Ordering Guide for more information.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADuC7026
SERIAL I/O
UART, SPI, I
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
3-PHASE
PWM
GPIO
JTAG
2
C
EXT. MEMORY
INTERFACE
DAC0
DAC1
DAC2
DAC3
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
H
L
H
L
H
L
04955-001
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005-2011 Analog Devices, Inc. All rights reserved.
ADuC7019/20/21/22/24/25/26/27/28/29
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Detailed Block Diagram .............................................................. 5
Specifications..................................................................................... 6
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17
ADuC7024/ADuC7025 .............................................................21
ADuC7026/ADuC7027 .............................................................24
ADuC7028................................................................................... 27
ADuC7029................................................................................... 29
Typical Performance Characteristics ........................................... 31
Terminology .................................................................................... 34
ADC Specifications ....................................................................34
DAC Specifications..................................................................... 34
Overview of the ARM7TDMI Core ............................................. 35
Thumb Mode (T)........................................................................ 35
Long Multiply (M)...................................................................... 35
EmbeddedICE (I) ....................................................................... 35
Exceptions ................................................................................... 35
ARM Registers ............................................................................ 35
Interrupt Latency........................................................................ 36
Memory Organization ...................................................................37
Memory Access........................................................................... 37
Flash/EE Memory....................................................................... 37
SRAM........................................................................................... 37
Memory Mapped Registers....................................................... 37
ADC Circuit Overview .................................................................. 41
Transfer Function....................................................................... 41
Typical Operation....................................................................... 42
MMRs Interface.......................................................................... 42
Converter Operation.................................................................. 44
Driving the Analog Inputs ........................................................ 45
Calibration................................................................................... 46
Temperature Sensor ................................................................... 46
Band Gap Reference................................................................... 46
Nonvolatile Flash/EE Memory ..................................................... 47
Programming.............................................................................. 47
Security ........................................................................................ 48
Flash/EE Control Interface ....................................................... 48
Execution Time from SRAM and Flash/EE............................ 50
Reset and Remap ........................................................................ 50
Other Analog Peripherals.............................................................. 52
DAC.............................................................................................. 52
Power Supply Monitor............................................................... 53
Comparator................................................................................. 53
Oscillator and PLL—Power Control........................................ 54
Digital Peripherals.......................................................................... 57
3-Phase PWM............................................................................. 57
Description of the PWM Block ................................................ 58
General-Purpose Input/Output................................................ 63
Serial Port Mux........................................................................... 65
UART Serial Interface................................................................ 65
Serial Peripheral Interface......................................................... 69
I2C-Compatible Interfaces......................................................... 71
Programmable Logic Array (PLA)........................................... 75
Processor Reference Peripherals................................................... 78
Interrupt System......................................................................... 78
Timers.......................................................................................... 79
External Memory Interfacing................................................... 83
Hardware Design Considerations ................................................ 87
Power Supplies............................................................................ 87
Grounding and Board Layout Recommendations................. 88
Clock Oscillator.......................................................................... 88
Power-On Reset Operation....................................................... 89
Typical System Configuration .................................................. 89
Development Tools......................................................................... 90
PC-Based Tools........................................................................... 90
In-Circuit Serial Downloader................................................... 90
Outline Dimensions....................................................................... 91
Ordering Guide .......................................................................... 95
Rev. D | Page 2 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
REVISION HISTORY
5/11—Rev. C to Rev. D
Changes to Table 4 ..........................................................................11
Changes to Table 105......................................................................67
Updated Outline Dimensions........................................................91
Changes to Ordering Guide...........................................................95
12/09—Rev. B to Rev. C
Added ADuC7029 Part .....................................................Universal
Added Table Numbers and Renumbered Tables............... Universal
Changes to Figure Numbers .............................................Universal
Changes to Table 1 ............................................................................6
Changes to Figure 3 ..........................................................................9
Changes to Table 3 and Figure 4 ...................................................10
Changes to Table 10 ........................................................................16
Changes to Figure 55 ......................................................................53
Changes to Serial Peripheral Interface Section ...........................69
Changes to Table 137......................................................................73
Changes to Figure 71 and Figure 72 .............................................85
Changes to Figure 73 and Figure 74 .............................................86
Updated Outline Dimensions........................................................91
Changes to Ordering Guide...........................................................94
3/07—Rev. A to Rev. B
Added ADuC7028 Part .....................................................Universal
Updated Format.................................................................. Universal
Changes to Figure 2...........................................................................5
Changes to Table 1 ............................................................................6
Changes to ADuC7026/ADuC7027 Section ...............................23
Changes to Figure 21 ......................................................................28
Changes to Figure 32 Caption ....................................................... 30
Changes to Table 14........................................................................35
Changes to ADC Circuit Overview Section................................38
Changes to Programming Section................................................44
Changes to Flash/EE Control Interface Section..........................45
Changes to Table 24........................................................................47
Changes to RSTCLR Register Section..........................................48
Changes to Figure 52 ......................................................................49
Changes to Figure 53 ......................................................................50
Changes to Comparator Section ...................................................50
Changes to Oscillator and PLL—Power Control Section..........51
Changes to Digital Peripherals Section........................................54
Changes to Interrupt System Section ...........................................75
Changes to Timers Section ............................................................76
Changes to External Memory Interfacing Section .....................80
Added IOV
Changes to Ordering Guide...........................................................90
1/06—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 6
Added the Flash/EE Memory Reliability Section ....................... 43
Changes to Table 30........................................................................52
Changes to Serial Peripheral Interface .........................................66
Changes to Ordering Guide...........................................................90
10/05—Revision 0: Initial Version
Supply Sensitivity Section..................................... 84
DD
Rev. D | Page 3 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
GENERAL DESCRIPTION
The ADuC7019/20/21/22/24/25/26/27/28/29 are fully integrated,
1 MSPS, 12-bit data acquisition systems incorporating high
performance multichannel ADCs, 16-bit/32-bit MCUs, and
Flash®/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional
four inputs are available but are multiplexed with the four DAC
output pins. The four DAC outputs are available only on certain
models (ADuC7020, ADuC7026, ADuC7028, and ADuC7029).
However, in many cases where the DAC outputs are not present,
these pins can still be used as additional ADC inputs, giving a
maximum of 16 ADC input channels. The ADC can operate in
single-ended or differential input mode. The ADC input voltage
is 0 V to V
and voltage comparator complete the ADC peripheral set.
Depending on the part model, up to four buffered voltage
output DACs are available on-chip. The DAC output range is
programmable to one of three voltage ranges.
. A low drift band gap reference, temperature sensor,
REF
The devices operate from an on-chip oscillator and a PLL
generating an internal high frequency clock of 41.78 MHz
(UCLK). This clock is routed through a programmable clock
divider from which the MCU core clock operating frequency
is generated. The microcontroller core is an ARM7TDMI®,
16-bit/32-bit RISC machine, which offers up to 41 MIPS peak
performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on-chip. The
ARM7TDMI core views all memory and registers as a single
linear array.
On-chip factory firmware supports in-circuit serial download
via the UART or I
2
C serial interface port; nonintrusive emulation
is also supported via the JTAG interface. These features are
incorporated into a low cost QuickStart™ development system
supporting this MicroConverter® family.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. When
operating at 41.78 MHz, the power dissipation is typically
120 mW. The ADuC7019/20/21/22/24/25/26/27/28/29 are
available in a variety of memory models and packages (see
Ordering Guide).
Rev. D | Page 4 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
DETAILED BLOCK DIAGRAM
DD
DACGND75DACV
70
12-BIT
12-BIT
12-BIT
12-BIT
3-PHASE
PWM
PLL
INTERRUPT
CONTROLLER
17
33
35
36
48
/MS1
/MS2
L
/MS00
H
H
P2.3/AE
/PLAO[7]
L
P2.5/PWM0
P2.6/PWM1
P2.4/PWM0
P2.2/RS/ PWM0
*SEE ORDERI NG GUIDE FO R
FEATURE AVAILAB ILITY ON
DIFFERENT M ODELS.
69
BUF
BUF
BUF
BUF
REF
DAC
10
DAC0*/ADC1 2
11
DAC1*/ADC1 3
12
DAC2*/ADC1 4
13
DAC3*/ADC1 5
29
P3.0/AD0/PWM0H/PLAI[8]
30
P3.1/AD1/PWM0L/PLAI[9]
31
P3.2/AD2/PWM1H/PLAI[10]
32
P3.3/AD3/PWM1L/PLAI[11]
38
P3.4/AD4/PWM2H/PLAI[12]
39
P3.5/AD5/PWM2L/PLAI[13]
46
P3.6/AD6/PWM
47
P3.7/AD7/PWM
OSC
44
XCLKO
45
XCLKI
43
P0.7/ECLK/XCLK/ SPM8/PLAO[4]
40
IRQ0/P0.4/PWM
41
IRQ1/P0.5/ADC
24
16
/BLE
/MS3
/BHE
L
H
L
P2.7/PWM1
P0.1/PWM2
P0.2/PWM2
/PLAI[14]
TRIP
/PLAI[15]
SYNC
/PLAO[1]/MS1
TRIP
/PLAO[2]/MS2
BUSY
04955-002
BM/P0.0/CMP
P4.6/AD14/PLAO[14]
P4.7/AD15/PLAO[15]
ADC2/CMP 0
ADC3/CMP 1
/PLAI[7]/MS0
OUT
ADC0
ADC1
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
ADCNEG
V
REF
77
78
79
80
1
2
3
4
5
6
7
76
9
DAC
20
68
18
PROG. LO GIC
19
55
P4.0/AD8/PLAO[8]56P4.1/AD9/PLAO[9]
REF
ARRAY
REFGND71AGND72AGND8GND
67
MUX
MUX
BAND GAP
REFERENCE
63
P4.2/AD10/PLAO[10]64P4.3/AD11/ PLAO[11]65P4.4/AD12/PLAO[12]66P4.5/AD13/ PLAO[13]
DD
DD
AV
AV
74
73
12-BIT SAR
ADC 1MSPS
TEMP
SENSOR
8192 BYTES USER RAM
/IRQ
OUT
SPI/I2C SERIAL
INTERFACE
V
CMP
REF
SERIAL PORT MULTI PLEXER
62
61
P1.1/SPM 1/PLAI[1]60P1.2/SPM 2/PLAI[2]59P1.3/SPM 3/PLAI[3]
P1.0/T1/SPM0/PLAI[0]
DD
IOGND
25
53
ADuC7026*
ADC
CONTROL
62kB FLASH/EE
(31k × 16 BITS)
(2k × 32 BITS)
DOWNLO ADER
UART
SERIAL PORT
58
52
P1.6/SPM 6/PLAI[6]
P1.4/SPM 4/PLAI[4]/I RQ257P1.5/SPM 5/PLAI[5]/I RQ3
IOGND26IOV
51
DD
IOV
54
P1.7/SPM7/PLAO[0]
ARM7TDMI
14
42
TMS
START
P2.0/SPM9/PLAO[5]/CONV
Figure 2.
15
MCU
CORE
JTAG
EMULATO R
23
TDI
DD
RST27LV
DGND
37
28
VOLTAGE
OUTPUT DAC
VOLTAGE
DAC
CONTROL
OUTPUT DAC
VOLTAGE
OUTPUT DAC
VOLTAGE
OUTPUT DAC
WAKE-UP/
RTC TIMER
POWER SUPPLY
MONITOR
PROG. CLOCK
DIVIDER
POR
22
21
49
34
TCK
TDO
BUSY
P0.3/TRST/A16/ADC
50
/PLAO[6]
H
P0.6/T1/MRST/PLAO[3]
P2.1/W S/PWM0
Rev. D | Page 5 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, V
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2
ADC Power-Up Time 5 s
DC Accuracy
1, 2
Resolution 12 Bits
Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference
±1.0 LSB 1.0 V external reference
Differential Nonlinearity
3, 4
+0.7/−0.6 LSB 1.0 V external reference
DC Code Distribution 1 LSB ADC input is a dc voltage
ENDPOINT ERRORS
5
Offset Error ±1 ±2 LSB
Offset Error Match ±1 LSB
Gain Error ±2 ±5 LSB
Gain Error Match ±1 LSB
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, f
Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components
Total Harmonic Distortion (THD) −78 dB
Peak Harmonic or Spurious Noise
(PHSN)
Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels
ANALOG INPUT
Input Voltage Ranges
Differential Mode V
Single-Ended Mode 0 to V
Leakage Current ±1 ±6 µA
Input Capacitance 20 pF During ADC acquisition
ON-CHIP VOLTAGE REFERENCE 0.47 µF from V
Output Voltage 2.5 V
Accuracy ±5 mV TA = 25°C
Reference Temperature Coefficient ±40 ppm/ °C
Power Supply Rejection Ratio 75 dB
Output Impedance 70 Ω TA = 25°C
Internal V
Power-On Time 1 ms
REF
EXTERNAL REFERENCE INPUT
Input Voltage Range 0.625
DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF
DC Accuracy7
Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Offset Error ±15 mV 2.5 V internal reference
Gain Error8 ±1 %
Gain Error Mismatch 0.1 % % of full scale on DAC0
ANALOG OUTPUTS
Output Voltage Range_0 0 to DAC
Output Voltage Range_1 0 to 2.5 V
Output Voltage Range_2 0 to DACVDD V
Output Impedance 2 Ω
= 2.5 V internal reference, f
REF
= 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.
CORE
±0.5 +1/−0.9 LSB 2.5 V internal reference
−75 dB
6
± V
CM
AVDD V
V DAC
REF
/2 V
REF
V
REF
to AGND
REF
range: DACGND to DACVDD
REF
SAMPLE
= 1 MSPS
Rev. D | Page 6 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Parameter Min Typ Max Unit Test Conditions/Comments
DAC AC CHARACTERISTICS
Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch Energy ±20 nV-sec
COMPARATOR
Input Offset Voltage ±15 mV
Input Bias Current 1 µA
Input Voltage Range AGND AVDD − 1.2 V
Input Capacitance 7 pF
Hysteresis
4, 6
2 15 mV
Response Time 3 µs
TEMPERATURE SENSOR
Voltage Output at 25°C 780 mV
Voltage TC −1.3 mV/°C
Accuracy ±3 °C
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection 2.79 V Two selectable trip points
3.07 V
Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage
POWER-ON-RESET 2.36 V
GLITCH IMMUNITY ON RESET PIN3 50 µs
WATCHD OG T IME R ( WDT )
Timeout Period
0 512 sec
FLASH/EE MEMORY
Endurance9 10,000 Cycles
Data Retention10 20 Years TJ = 85°C
DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO
Logic 1 Input Current ±0.2 ±1 µA VIH = IOVDD or VIH = 5 V
Logic 0 Input Current −40 −60 µA
−80 −120 µA VIL = 0 V; TDI on ADuC7019/20/21/22/24/25/29
Input Capacitance 10 pF
LOGIC INPUTS3 All logic inputs excluding XCLKI
V
, Input Low Voltage 0.8 V
INL
V
, Input High Voltage 2.0 V
INH
LOGIC OUTPUTS All digital outputs excluding XCLKO
VOH, Output High Voltage 2.4 V I
VOL, Output Low Voltage11 0.4 V I
CRYSTAL INPUTS XCLKI and XCLKO
Logic Inputs, XCLKI Only
V
, Input Low Voltage 1.1 V
INL
V
, Input High Voltage 1.7 V
INH
XCLKI Input Capacitance 20 pF
XCLKO Output Capacitance 20 pF
INTERNAL OSCILLATOR 32.768 kHz
±3 %
±24 % TA = 0°C to 85°C range
1 LSB change at major carry (where maximum
number of bits simultaneously changes in the
DACxDAT register)
Hysteresis turned on or off via the CMPHYST bit
in the CMPCON register
100 mV overdrive and configured with CMPRES =
11
= 0 V; except TDI on
V
IL
ADuC7019/20/21/22/24/25/29
= 1.6 mA
SOURCE
= 1.6 mA
SINK
Rev. D | Page 7 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Parameter Min Typ Max Unit Test Conditions/Comments
MCU CLOCK RATE
From 32 kHz Internal Oscillator 326 kHz CD12 = 7
From 32 kHz External Crystal 41.78 MHz CD12 = 0
Using an External Clock 0.05 44 MHz TA = 85°C
0.05 41.78 MHz TA = 125°C
START-UP TIME Core clock = 41.78 MHz
At Power-On 130 ms
From Pause/Nap Mode 24 ns CD12 = 0
3.06 µs CD12 = 7
From Sleep Mode 1.58 ms
From Stop Mode 1.7 ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay 12 ns From input pin to output pin
Element Propagation Delay 2.5 ns
POWER REQUIREMENTS
Power Supply Voltage Range
AVDD to AGND and IOVDD to IOGND 2.7 3.6 V
Analog Power Supply Currents
AVDD Current 200 µA ADC in idle mode; all parts except ADuC7019
400 µA ADC in idle mode; ADuC7019 only
DACVDD Current15 3 25 µA
Digital Power Supply Current
IOVDD Current in Normal Mode Code executing from Flash/EE
7 10 mA CD12 = 7
11 15 mA CD12 = 3
40 45 mA CD12 = 0 (41.78 MHz clock)
IOVDD Current in Pause Mode 25 30 mA CD12 = 0 (41.78 MHz clock)
IOVDD Current in Sleep Mode 250 400 µA TA = 85°C
600 1000 µA TA = 125°C
Additional Power Supply Currents
ADC 2 mA @ 1 MSPS
0.7 mA @ 62.5 kSPS
DAC 700 µA per DAC
ESD TESTS 2.5 V reference, TA = 25°C
HBM Passed Up To 4 kV
FCIDM Passed Up To 0.5 kV
1
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 49. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V
9
Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11
Test carried out with a maximum of eight I/Os set to a low output level.
12
See the POWCON register.
13
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14
IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15
On the ADuC7019/20/21/22, this current must be added to the AVDD current.
13, 14
.
REF
Rev. D | Page 8 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter Min Typ Max Unit
CLK1 UCLK
t
MS_AFTER_CLKH
t
ADDR_AFTER_CLKH
t
AE_H_AFTER_MS
tAE (XMxPAR[14:12] + 1) × CLK
t
HOLD_ADDR_AFTER_AE_L
t
HOLD_ADDR_BEFORE_WR_L
t
WR_L_AFTER_AE_L
t
DATA_AFTER_WR_L
tWR (XMxPAR[7:4] + 1) × CLK
t
WR_H_AFTER_CLKH
t
HOLD_DATA_AFTER_WR_H
t
BEN_AFTER_AE_L
t
RELEASE_MS_AFTER_WR_H
1
See Table 78.
0 4 ns
4 8 ns
½ CLK
½ CLK + (!XMxPAR[10]) × CLK
(!XMxPAR[8]) × CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
8 12 ns
0 4 ns
(!XMxPAR[8]) × CLK
½ CLK
(!XMxPAR[8] + 1) × CLK
CLK
CLK
t
MS_AFTER_ CLKH
MSx
t
t
AE
WS
RS
AD[16:1] FFFF 9ABC 5678 9ABE 1234
BLE
BHE
A16
AE_H_AFTER_M S
t
AE
t
HOLD_ADDR_A FTER_AE_L
t
HOLD_ADDR_B EFORE_WR_L
t
ADDR_AFTER_CLKH
WR_L_AFTER_AE_L
t
WR
t
WR_H_AFTER_ CLKH
t
HOLD_DATA_A FTER_WR_H
t
DATA_AFTER_WR_L
t
BEN_AFTER_AE_L
Figure 3. External Memory Write Cycle (See Table 78)
t
RELEASE_MS_AFTER_WR_H
04955-052
Rev. D | Page 9 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 3. External Memory Read Cycle
Parameter Min Typ Max Unit
CLK1 1/MD clock ns typ × (POWCON[2:0] + 1)
t
MS_AFTER_CLKH
t
ADDR_AFTER_CLKH
t
AE_H_AFTER_MS
tAE (XMxPAR[14:12] + 1) × CLK
t
HOLD_ADDR_AFTER_AE_L
t
RD_L_AFTER_AE_L
t
RD_H_AFTER_CLKH
tRD (XMxPAR[3:0] + 1) × CLK
t
DATA_BEFORE_RD_H
t
DATA_AFTER_RD_H
t
RELEASE_MS_AFTER_RD_H
1
See Table 78.
4 8 ns
4 16 ns
½ CLK
½ CLK + (! XMxPAR[10] ) × CLK
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
0 4
16 ns
8 + (! XMxPAR[9]) × CLK
1 × CLK
CLK
ECLK
t
MSx
AE
WS
RS
MS_AFTER_CL KH
t
AE_H_AFTER_MS
t
AE
t
RD_L_AFTER_AE _L
t
RD
t
RD_H_AFTER_CLK H
t
RELEASE_MS _AFTER_RD_H
AD[16:1]
BHE
BLE
A16
t
t
ADDR_AFTER_CLKH
FFFF 2348 XXXX CDEF XX 234A XX 89AB
t
HOLD_ADDR_A FTER_AE_L
DATA_BEFOR E_RD_H
t
DATA_AFTER_RD_H
Figure 4. External Memory Read Cycle (See Table 78)
04955-053
Rev. D | Page 10 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
S
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave Master
Parameter Description Min Max Typ Unit
tL SCLOCK low pulse width1 200 1360 ns
tH SCLOCK high pulse width1 100 1140 ns
t
Start condition hold time 300 ns
SHD
t
Data setup time 100 740 ns
DSU
t
Data hold time 0 400 ns
DHD
t
Setup time for repeated start 100 ns
RSU
t
Stop condition setup time 100 400 ns
PSU
t
Bus-free time between a stop condition and a start condition 1.3
BUF
tR Rise time for both CLOCK and SDATA 300 200 ns
tF Fall time for both CLOCK and SDATA 300 ns
t
Pulse width of spike suppressed 50 ns
SUP
1
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
HCLK
= t
/2CD; see Figure 57.
UCLK
Table 5. I
2
C Timing in Standard Mode (100 kHz)
Slave Master
Parameter Description Min Max Typ Unit
tL SCLOCK low pulse width1 4.7 µs
tH SCLOCK high pulse width1 4.0 ns
t
Start condition hold time 4.0 µs
SHD
t
Data setup time 250 ns
DSU
t
Data hold time 0 3.45 µs
DHD
t
Setup time for repeated start 4.7 µs
RSU
t
Stop condition setup time 4.0 µs
PSU
t
Bus-free time between a stop condition and a start condition 4.7 µs
BUF
tR Rise time for both CLOCK and SDATA 1 µs
tF Fall time for both CLOCK and SDATA 300 ns
1
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
HCLK
= t
/2CD; see Figure 57.
UCLK
DATA (I/O)
SCLK (I)
t
PSU
t
BUF
PS
STOP
CONDITIO N
CONDITION
START
MSB LSB ACK MSB
t
DSU
t
SHD
t
DHD
Figure 5. I
2
C Compatible Interface Timing
t
SUP
t
DSU
t
H
t
L
t
SUP
t
RSU
t
DHD
REPEATED
S(R)
START
t
R
t
F
t
R
1982–71
t
F
μs
4955-054
Rev. D | Page 11 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 6. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
tSL SCLOCK low pulse width1 (SPIDIV + 1) × t
tSH SCLOCK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLOCK edge 25 ns
DAV
t
Data input setup time before SCLOCK edge2 1 × t
DSU
t
Data input hold time after SCLOCK edge2 2 × t
DHD
ns
UCLK
ns
UCLK
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLOCK rise time 5 12.5 ns
tSF SCLOCK fall time 5 12.5 ns
1
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
2
t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
UCLK
HCLK
= t
UCLK
/2CD; see Figure 57.
ns
HCLK
ns
HCLK
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
DAV
t
SH
t
DSU
t
DHD
t
SL
t
DF
t
DR
t
SR
t
SF
4955-055
Figure 6. SPI Master Mode Timing (Phase Mode = 1)
Rev. D | Page 12 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tSL SCLOCK low pulse width1 (SPIDIV + 1) × t
tSH SCLOCK high pulse width1 (SPIDIV + 1) × t
t
Data output valid after SCLOCK edge 25 ns
DAV
t
Data output setup before SCLOCK edge 75 ns
DOSU
t
Data input setup time before SCLOCK edge2 1 × t
DSU
t
Data input hold time after SCLOCK edge2 2 × t
DHD
ns
UCLK
ns
UCLK
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLOCK rise time 5 12.5 ns
tSF SCLOCK fall time 5 12.5 ns
1
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
2
t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
UCLK
HCLK
= t
/2CD; see Figure 57.
UCLK
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
t
DOSU
MOSI MSB BITS 6 T O 1 LSB
t
SH
t
SL
t
DAV
t
DF
t
DR
t
SR
ns
HCLK
ns
HCLK
t
SF
MISO MSB IN BITS 6 TO 1 LSB IN
t
DSU
t
DHD
Figure 7. SPI Master Mode Timing (Phase Mode = 0)
04955-056
Rev. D | Page 13 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 8. SPI Slave Mode Timing (Phsae Mode = 1)
Parameter Description Min Typ Max Unit
tCS
to SCLOCK edge
CS
tSL SCLOCK low pulse width2 (SPIDIV + 1) × t
tSH SCLOCK high pulse width2 (SPIDIV + 1) × t
t
Data output valid after SCLOCK edge 25 ns
DAV
t
Data input setup time before SCLOCK edge1 1 × t
DSU
t
Data input hold time after SCLOCK edge1 2 × t
DHD
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLOCK rise time 5 12.5 ns
tSF SCLOCK fall time 5 12.5 ns
t
SFS
1
t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
UCLK
2
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
high after SCLOCK edge
CS
CS
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MISO MSB BITS 6 TO 1 LSB
1
(2 × t
) + (2 × t
HCLK
ns
UCLK
ns
UCLK
) ns
UCLK
ns
HCLK
ns
HCLK
0 ns
= t
/2CD; see Figure 57.
HCLK
UCLK
t
t
CS
t
t
SH
DAV
t
SL
t
DF
t
DR
t
SR
SFS
t
SF
MOSI MSB I N BITS 6 TO 1 LSB IN
t
DSU
t
DHD
Figure 8. SPI Slave Mode Timing (Phase Mode = 1)
04955-057
Rev. D | Page 14 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tCS
to SCLOCK edge
CS
tSL SCLOCK low pulse width2 (SPIDIV + 1) × t
tSH SCLOCK high pulse width2 (SPIDIV + 1) × t
t
Data output valid after SCLOCK edge 25 ns
DAV
t
Data input setup time before SCLOCK edge1 1 × t
DSU
t
Data input hold time after SCLOCK edge1 2 × t
DHD
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLOCK rise time 5 12.5 ns
tSF SCLOCK fall time 5 12.5 ns
t
DOCS
t
SFS
1
t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
UCLK
2
t
depends on the clock divider or CD bits in the PLLCON MMR. t
HCLK
Data output valid after CS
high after SCLOCK edge
CS
CS
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MISO
t
DOCS
1
edge
(2 × t
) + (2 × t
HCLK
ns
UCLK
ns
UCLK
) ns
UCLK
ns
HCLK
ns
HCLK
25 ns
0 ns
= t
HCLK
t
CS
t
SH
t
DAV
t
DF
MSB BITS 6 TO 1 LSB
/2CD; see Figure 57.
UCLK
t
SL
t
DR
t
SFS
t
SR
t
SF
MOSI
MSB IN BITS 6 TO 1 LSB IN
t
DSU
t
DHD
Figure 9. SPI Slave Mode Timing (Phase Mode = 0)
Rev. D | Page 15 of 96
04955-058
ADuC7019/20/21/22/24/25/26/27/28/29
ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GND
otherwise noted.
Table 10.
Parameter Rating
AVDD to IOVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
IOVDD to IOGND, AVDD to AGND −0.3 V to +6 V
Digital Input Voltage to IOGND −0.3 V to +5.3 V
Digital Output Voltage to IOGND −0.3 V to IOVDD + 0.3 V
V
to AGND −0.3 V to AVDD + 0.3 V
REF
Analog Inputs to AGND −0.3 V to AV
Analog Outputs to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range, Industrial –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
40-Lead LFCSP 26°C/W
49-Ball CSP_BGA 80°C/W
64-Lead LFCSP 24°C/W
64-Ball CSP_BGA 75°C/W
64-Lead LQFP 47°C/W
80-Lead LQFP 38°C/W
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS Compliant Assemblies
(20 sec to 40 sec)
, TA = 25°C, unless
REF
DD
260°C
+ 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Rev. D | Page 16 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADuC7019/ADuC7020/ADuC7021/ADuC7022
DD
REF
AGND
V
P4.2/PLAO[10]
P1.0/T1/ SPM0/PLAI[0]
P1.1/SPM 1/PLAI[1]
P1.2/SPM 2/PLAI[2]
31
P1.3/SPM 3/PLAI[3]
30
P1.4/SPM 4/PLAI[4]/I RQ2
29
P1.5/SPM 5/PLAI[5]/I RQ3
28
P1.6/SPM 6/PLAI[6]
27
P1.7/SPM 7/PLAO[0]
26
XCLKI
25
XCLKO
24
P0.7/ECLK/ XCLK/SPM8/PLAO[4]
23
P2.0/SPM 9/PLAO[5]/CONV
22
IRQ1/P0.5/ADC
21
BUSY
/PLAO[2]
START
BM/P0.0/CMP
ADC3/CM P1
ADC4
GND
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
/PLAI[7]
OUT
REF
TDI
ADC2/CMP 0
ADC1
ADC0
AV
403938373635343332
1
PIN 1
2
INDICATO R
3
4
5
6
7
8
9
10
ADuC7019/
ADuC7020
TOP VIEW
(Not to Scale)
111213141516171819
DDLVDD
TCK
TDO
IOV
IOGND
P0.6/T1/MRST/PLAO[3]
NOTES
1. THE EXPOSED PADDLE M UST BE LEFT UNCONNECTED.
20
RST
BUSY
DGND
/PLAO[1]
TRIP
P0.3/TRST/ADC
IRQ0/P0.4/PWM
04955-064
Figure 10. 40-Lead LFCSP_VQ Pin Configuration (ADuC7019/ADuC7020)
DD
REF
AGND
V
P1.0/T1/ SPM0/PLAI[0]
P1.1/SPM 1/PLAI[1]
P1.2/SPM 2/PLAI[2]
31
P1.3/SPM3/PLAI[3]
30
P1.4/SPM4/PLAI[4]/IRQ2
29
P1.5/SPM5/PLAI[5]/IRQ3
28
P1.6/SPM6/PLAI[6]
27
P1.7/SPM7/PLAO[0]
26
XCLKI
25
XCLKO
24
P0.7/ECLK/ XCLK/SPM8/PLAO[ 4]
23
P2.0/SPM9/PLAO[5]/CONV
22
IRQ1/P0.5/ADC
21
BUSY
/PLAO[2]
START
BM/P0.0/CMP
ADC4
ADC5
ADC6
ADC7
GND
DAC0/ADC12
DAC1/ADC13
TMS
/PLAI[7]
OUT
REF
TDI
ADC3/CMP 1
ADC2/CMP 0
ADC1
ADC0
AV
403938373635343332
1
PIN 1
2
INDICATO R
3
4
5
6
7
8
9
10
ADuC7021
TOP VIEW
(Not to Scale)
111213141516171819
DDLVDD
TCK
TDO
IOV
IOGND
P0.6/T1/MRST/PLAO[3]
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED.
20
RST
BUSY
DGND
/PLAO[1]
TRIP
P0.3/TRST/ADC
IRQ0/P0.4/PWM
04955-065
Figure 11. 40-Lead LFCSP_VQ Pin Configuration (ADuC7021)
Rev. D | Page 17 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
ADC4
ADC3/CMP1
ADC2/CMP0
403938373635343332
DD
REF
AGND
V
P1.0/T1/ SPM0/PLAI[0]
ADC1
ADC0
P1.1/SPM 1/PLAI[1]
AV
31
1
ADC5
ADC6
ADC7
ADC8
ADC9
GND
REF
TMS
TDI
BM/P0.0/CMP
P0.6/T1/MRST/PLAO[3]
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED.
OUT
/PLAI[7]
PIN 1
2
INDICAT OR
3
4
5
6
7
8
9
10
ADuC7022
TOP VIEW
(Not to Scale)
111213141516171819
DDLVDD
TCK
TDO
IOV
DGND
IOGND
BUSY
P0.3/ TRST/ADC
RST
/PLAO[1]
TRIP
IRQ0/P0.4/PWM
20
/PLAO[2]
BUSY
IRQ1/P0.5/ADC
30
P1.2/SPM2/PLAI[2]
29
P1.3/SPM3/PLAI[3]
28
P1.4/SPM4/PLAI[4]/IRQ2
27
P1.5/SPM5/PLAI[5]/IRQ3
26
P1.6/SPM6/PLAI[6]
25
P1.7/SPM7/PLAO[0]
24
XCLKI
23
XCLKO
22
P0.7/ECLK/XCLK/SPM8/PLAO[4]
21
P2.0/ SPM9/PLAO[ 5]/CONV
START
04955-066
Figure 12. 40-Lead LFCSP_VQ Pin Configuration (ADuC7022)
Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic Description
38 37 36 ADC0 Single-Ended or Differential Analog Input 0.
39 38 37 ADC1 Single-Ended or Differential Analog Input 1.
40 39 38 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
1 40 39 ADC3/CMP1
Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2 1 40 ADC4 Single-Ended or Differential Analog Input 4.
‒
‒
‒
‒ ‒
‒ ‒
3 5 6 GND
2 1 ADC5 Single-Ended or Differential Analog Input 5.
3 2 ADC6 Single-Ended or Differential Analog Input 6.
4 3 ADC7 Single-Ended or Differential Analog Input 7.
4 ADC8 Single-Ended or Differential Analog Input 8.
5 ADC9 Single-Ended or Differential Analog Input 9.
REF
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4 6 ‒ DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
5 7 ‒ DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
6
7
‒ ‒
‒ ‒
DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
DAC3/ADC15
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
must be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15 (see Figure 43).
8 8 7 TMS Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOV
. In some cases, an external
DD
pull-up resistor (~100K) is also required to ensure that the part does not
enter an erroneous state.
9 9 8 TDI Test Data In, JTAG Test Port Input. Debug and download access.
Rev. D | Page 18 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No.
7019/7020 7021 7022 Mnemonic Description
10 10 9 BM/P0.0/CMP
11 11 10 P0.6/T1/MRST/PLAO[3]
12 12 11 TCK
13 13 12 TDO Test Data Out, JTAG Test Port Output. Debug and download access.
14 14 13 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
15 15 14 IOVDD
16 16 15 LVDD
17 17 16 DGND Ground for Core Logic.
18 18 17 P0.3/TRST/ADC
19 19 18
RST
20 20 19 IRQ0/P0.4/PWM
21 21 20 IRQ1/P0.5/ADC
22 22 21
P2.0/SPM9/PLAO[5]/CONV
23 23 22 P0.7/ECLK/XCLK/SPM8/PLAO[4]
24 24 23 XCLKO Output from the Crystal Oscillator Inverter.
25 25 24 XCLKI
26 26 25 P1.7/SPM7/PLAO[0]
27 27 26 P1.6/SPM6/PLAI[6]
28 28 27 P1.5/SPM5/PLAI[5]/IRQ3
29 29 28 P1.4/SPM4/PLAI[4]/IRQ2
30 30 29 P1.3/SPM3/PLAI[3]
31 31 30 P1.2/SPM2/PLAI[2]
32 32 31 P1.1/SPM1/PLAI[1]
33 33 32 P1.0/T1/SPM0/PLAI[0]
34
‒ ‒
P4.2/PLAO[10]
/PLAI[7]
OUT
BUSY
TRIP
BUSY
/PLAO[1]
/PLAO[2]
Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 kΩ resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
Test Clock, JTAG Test Port Input. Debug and download access. This pin has
an internal pull-up resistor to IOV
. In some cases an external pull-up
DD
resistor (~100K) is also required to ensure that the part does not enter an
erroneous state.
3.3 V Supply for GPIO (see Tabl e 78) and Input of the On-Chip Voltage
Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
Signal Output.
ADC
BUSY
Reset Input, Active Low.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/GeneralPurpose Input and Output Port 0.5/ADC
Signal Output/Programmable
BUSY
Logic Array Output Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
START
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/
Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.
Rev. D | Page 19 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No.
7019/7020 7021 7022 Mnemonic Description
35 34 33 V
36 35 34 AGND Analog Ground. Ground reference point for the analog circuitry.
37 36 35 AVDD 3.3 V Analog Power.
0 0 0 EP
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor
when using the internal reference.
Exposed Paddle. The pin configuration for the ADuC7019/ADuC7020/
ADuC7021/ADuC7022 has an exposed paddle that must be left
unconnected.
Rev. D | Page 20 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
ADuC7024/ADuC7025
REF
REF
64 ADC3/CMP1
63 ADC2/CMP0
62 ADC1
61 ADC0
60 DACVDD59 AVDD58 AGND
57 DACGND
56 DAC
55 V
54 P4.5/PLAO[13]
53 P4.4/PLAO[12]
52 P4.3/PLAO[11]
51 P4.2/PLAO[10]
50 P1 .0/T1/SPM0/PLAI [0]
49 P1 .1/SPM1/PLAI[ 1]
1ADC4
PIN 1
2ADC5
INDICATO R
3ADC6
4ADC7
5ADC8
6ADC9
7GND
REF
8ADCNEG
9DAC0 /ADC12
10DAC 1/ADC13
11TMS
12TDI
13P4.6/PLAO[14]
14P4.7/PLAO[15]
15BM/P0.0/CMP
/PLAI[7]
OUT
NOTES
1. THE EXPOSED PADDLE M UST BE LEFT UNCONNECTED.
Figure 13.
16P0.6/T1/MRST/PLAO[3]
64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025)
17TCK
18TDO
19IOGND
20IOVDD21LVDD22DGND
ADuC7024/
ADuC7025
TOP VIEW
(Not to Scale)
26P3.3/PWM1
23P3.0/PWM0
24P3.1/PWM0
25P3.2/PWM1
/PLAI[8]
/PLAI[9]
L
/PLAI[10]
/PLAI[11]
H
L
H
27P0.3/TRST/ADC
BUSY
28
RST
48 P1.2/SPM 2/PLAI[2]
47 P1.3/SPM 3/PLAI[3]
46 P1.4/SPM 4/PLAI[4]/I RQ2
45 P1.5/SPM 5/PLAI[5]/I RQ3
44 P4.1/PLAO[9]
43 P4.0/PLAO[8]
42 I OV
DD
41 I OGND
40 P1.6/SPM 6/PLAI[6]
39 P1.7/SPM 7/PLAO[0]
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
35 XCLKO
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
33 P2.0/SPM 9/PLAO[5]/CONV
30P3.5/PWM2
31IRQ0/P0.4/PWM
32IRQ1/P0.5/ADC
29P3.4/PWM2
/PLAO[1]
/PLAO[2]
/PLAI[12]
/PLAI[13]
L
H
TRIP
BUSY
SYNC
TRIP
/PLAI[15]
/PLAI[14]
START
04955-067
DD
REF
REF
64 ADC3/CMP1
63 ADC2/CMP0
62 ADC1
61 ADC0
60 DACV
59 AVDD58 AGND
57 DACGND
56 DAC
55 V
54 P4.5/PLAO[13]
53 P4.4/PLAO[12]
52 P4.3/PLAO[11]
51 P4.2/PLAO[10]
50 P1. 0/T1/SPM0/PLAI[ 0]
49 P1. 1/SPM1/PLAI[1]
48 P1 .2/SPM2/PLAI[ 2]
47 P1 .3/SPM3/PLAI[ 3]
46 P1.4/SPM4/PLAI[4]/IRQ2
45 P1.5/SPM5/PLAI[5]/IRQ3
44 P4.1/PLAO[9]
43 P4.0/PLAO[8]
42 IO V
DD
41 IO GND
40 P1 .6/SPM6/PLAI[ 6]
39 P1 .7/SPM7/PLAO[ 0]
38 P3.7/PWM
37 P3.6/PWM
36 XCLKI
35 XCLKO
34 P0 .7/ECLK/XCLK/SPM8/ PLAO[4]
33 P2 .0/SPM9/PLAO[ 5]/CONV
32IRQ1/P0.5/ADC
30P3.5/PWM2
31IRQ0/P0.4/PWM
/PLAO[1]
/PLAO[2]
/PLAI[13]
L
TRIP
BUSY
SYNC
TRIP
/PLAI[15]
/PLAI[14]
OUT
REF
/PLAI[7]
1ADC4
PIN 1
2ADC5
INDICATO R
3ADC6
4ADC7
5ADC8
6ADC9
7GND
8ADCNEG
9DAC0/ADC12
10DAC1/ADC13
11TMS
12TDI
13P4.6/PLAO[14]
14P4.7/PLAO[15]
15BM/P0.0/CMP
16P0.6/T1/MRST/PLAO[3]
17TCK
18TDO
19IOGND
ADuC7024/
ADuC7025
TOP VIEW
(Not to Scale)
20IOVDD21LVDD22DGND
23P3.0/PWM 0
24P3.1/PWM0
25P3.2/PWM1
/PLAI[8]
/PLAI[9]
L
/PLAI[10]
H
H
26P3.3/PWM1
27P0. 3/TRST/ADC
28
29P3.4/PWM2
RST
BUSY
/PLAI[11]
/PLAI[12]
L
H
Figure 14. 64-Lead LQFP Pin Configuration (ADuC7024/ADuC7025)
START
04955-068
Rev. D | Page 21 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP)
Pin No. Mnemonic Description
1 ADC4 Single-Ended or Differential Analog Input 4.
2 ADC5 Single-Ended or Differential Analog Input 5.
3 ADC6 Single-Ended or Differential Analog Input 6.
4 ADC7 Single-Ended or Differential Analog Input 7.
5 ADC8 Single-Ended or Differential Analog Input 8.
6 ADC9 Single-Ended or Differential Analog Input 9.
7 GND
8 ADCNEG
9 DAC0/ADC12
10 DAC1/ADC13
11 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
12 TDI JTAG Test Port Input, Test Data In. Debug and download access
13 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
14 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
15 BM/P0.0/CMP
16 P0.6/T1/MRST/PLAO[3]
17 TCK JTAG Test Port Input, Test Clock. Debug and download access.
18 TDO JTAG Test Port Output, Test Data Out. Debug and download access.
19 IOGND Ground for GPIO (see Table 7 8). Typically connected to DGND.
20 IOVDD 3.3 V Supply for GPIO (see Tab le 78) and Input of the On-Chip Voltage Regulator.
21 LVDD
22 DGND Ground for Core Logic.
23 P3.0/PWM0H/PLAI[8]
24 P3.1/PWM0L/PLAI[9]
25 P3.2/PWM1H/PLAI[10]
26 P3.3/PWM1L/PLAI[11]
27 P0.3/TRST/ADC
28
29 P3.4/PWM2H/PLAI[12]
30 P3.5/PWM2L/PLAI[13]
31 IRQ0/P0.4/PWM
32 IRQ1/P0.5/ADC
33
34 P0.7/ECLK/XCLK/SPM8/PLAO[4]
35 XCLKO Output from the Crystal Oscillator Inverter.
36 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
REF
/PLAI[7]
OUT
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
RST
/PLAO[1]
TRIP
/PLAO[2]
BUSY
P2.0/SPM9/PLAO[5]/CONV
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present
on the ADuC7025.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present
on the ADuC7025.
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/PowerOn Reset Output/Programmable Logic Array Output Element 3.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic
Array Input Element 8.
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic
Array Input Element 9.
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic
Array Input Element 10.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic
Array Input Element 11.
Signal Output.
BUSY
Reset Input, Active Low.
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic
Array Input 12.
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic
Array Input Element 13.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
START
Signal Output/Programmable Logic Array Output Element 2.
BUSY
Array Output Element 5/Start Conversion Input Signal for ADC.
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
Rev. D | Page 22 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic Description
37 P3.6/PWM
38 P3.7/PWM
39 P1.7/SPM7/PLAO[0]
40 P1.6/SPM6/PLAI[6]
41 IOGND Ground for GPIO (see Table 7 8). Typically connected to DGND.
42 IOVDD 3.3 V Supply for GPIO (see Tab le 78) and Input of the On-Chip Voltage Regulator.
43 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
44 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
45 P1.5/SPM5/PLAI[5]/IRQ3
46 P1.4/SPM4/PLAI[4]/IRQ2
47 P1.3/SPM3/PLAI[3]
48 P1.2/SPM2/PLAI[2]
49 P1.1/SPM1/PLAI[1]
50 P1.0/T1/SPM0/PLAI[0]
51 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
52 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
53 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
54 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
55 V
56 DAC
REF
REF
57 DACGND Ground for the DAC. Typically connected to AGND.
58 AGND Analog Ground. Ground reference point for the analog circuitry.
59 AVDD 3.3 V Analog Power.
60 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD.
61 ADC0 Single-Ended or Differential Analog Input 0.
62 ADC1 Single-Ended or Differential Analog Input 1.
63 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
64 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
0 EP
/PLAI[14]
TRIP
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input
Element 14.
/PLAI[15]
SYNC
General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/
Programmable Logic Array Input Element 15.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic
Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Exposed Paddle. The pin configuration for the ADuC7024/ADuC7025 LFCSP_VQ has an exposed
paddle that must be left unconnected.
Rev. D | Page 23 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
ADuC7026/ADuC7027
/PLAI[7]/MS0
OUT
H
REF
/BLE
DD
78 ADC1
77 ADC0
23TDO
24P0.2/PWM2
/BHE
L
74 AVDD73 AVDD72 AGND
76 ADC11
75 DACV
ADuC7026/
ADuC7027
(Not to Scale)
25IOGND
26IOV
27LVDD28DGND
DD
80 ADC3/CMP1
79 ADC2/CMP0
1ADC4
2ADC5
3ADC6
4ADC7
5ADC8
6ADC9
7ADC10
8GND
9ADCNEG
10DAC0/ADC12
11DAC1/ADC13
12DAC2/ADC14
13DAC3/ADC15
14TMS
15TDI
16P0.1/PWM2
17P2.3/AE
18P4.6/AD14/PLAO[14]
19P4.7/AD15/PLAO[15]
20BM/P0.0/ CMP
PIN 1
INDICATO R
21P0.6/T1/MRST/PLAO[3]
22TCK
71 AGND
70 DACGND
TOP VIEW
30P3.1/AD1/PWM0
31P3.2/AD2/PWM1
29P3.0/AD0/PWM0
/PLAI[8]
/PLAI[9]
L
/PLAI[10]
H
H
REF
69 DAC
32P3.3/AD3/PWM1
/PLAI[11]
L
REF
68 V
67 REFGND
66 P4.5/ AD13/PLAO[13]
65 P4.4/ AD12/PLAO[12]
64 P4.3/ AD11/PLAO[11]
63 P4.2/ AD10/PLAO[10]
62 P1.0/T1/SPM0/PLAI[0]
61 P1.1/SPM1/PL AI[1]
60 P1.2/SPM2/PLAI[2]
59 P1.3/SPM3/PLAI[3]
58 P1.4/SPM4/PLAI[4]/IRQ2
57 P1.5/SPM5/PLAI[5]/IRQ3
56 P4.1/AD9/PLAO[9]
55 P4.0/AD8/PLAO[8]
54 IOV
DD
53 IOGND
52 P1.6/SPM6/PLAI[6]
51 P1.7/SPM7/PLAO[0]
50 P2.2/RS/PWM0
49 P2.1/WS/PWM0
48 P2.7/PWM1
47 P3.7/AD7/PWM
46 P3.6/AD6/PWM
45 XCLKI
44 XCLKO
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
42 P2.0/SPM9/PLAO[5]/CONV
41 IRQ1/P0.5/ADC
34P0.3/TRS T/A16/ADC
36P2.6/PWM1
37RST
38P3.4/AD4/PWM2
35P2.5/PWM0
33P2.4/PWM0
BUSY
/MS0
H
39P3.5/AD5/PWM2
40IRQ0/P0.4/P WM
/MS1
/MS2
L
H
/PLAI[12]
/PLAI[13]
L
H
/PLAO[1]/MS1
TRIP
/MS3
L
/PLAO[7]
L
/PLAO[6]
H
/PLAI[15]
SYNC
/PLAI[14]
TRIP
/PLAO[2]/MS2
BUSY
START
Figure 15. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027)
Table 13. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No. Mnemonic Description
1 ADC4 Single-Ended or Differential Analog Input 4.
2 ADC5 Single-Ended or Differential Analog Input 5.
3 ADC6 Single-Ended or Differential Analog Input 6.
4 ADC7 Single-Ended or Differential Analog Input 7.
5 ADC8 Single-Ended or Differential Analog Input 8.
6 ADC9 Single-Ended or Differential Analog Input 9.
7 ADC10 Single-Ended or Differential Analog Input 10.
8 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9 ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10 DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
11 DAC1/ADC13
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
12 DAC2/ADC14
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
13 DAC3/ADC15
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
14 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
Rev. D | Page 24 of 96
04955-069
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic Description
15 TDI JTAG Test Port Input, Test Data In. Debug and download access.
16
P0.1/PWM2
17 P2.3/AE General-Purpose Input and Output Port 2.3/External Memory Access Enable.
18 P4.6/AD14/PLAO[14]
19 P4.7/AD15/PLAO[15]
20 BM/P0.0/CMP
21 P0.6/T1/MRST/PLAO[3]
22 TCK JTAG Test Port Input, Test Clock. Debug and download access.
23 TDO JTAG Test Port Output, Test Data Out. Debug and download access.
24
P0.2/PWM2
25 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
26 IOVDD 3.3 V Supply for GPIO (see Table 7 8) and Input of the On-Chip Voltage Regulator.
27 LVDD
28 DGND Ground for Core Logic.
29 P3.0/AD0/PWM0H/PLAI[8]
30 P3.1/AD1/PWM0L/PLAI[9]
31 P3.2/AD2/PWM1H/PLAI[10]
32 P3.3/AD3/PWM1L/PLAI[11]
33 P2.4/PWM0H/MS0
34 P0.3/TRST/A16/ADC
35 P2.5/PWM0L/MS1
36 P2.6/PWM1H/MS2
37
RST
38 P3.4/AD4/PWM2H/PLAI[12]
39 P3.5/AD5/PWM2L/PLAI[13]
40 IRQ0/P0.4/PWM
41 IRQ1/P0.5/ADC
42
P2.0/SPM9/PLAO[5]/
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
44 XCLKO Output from the Crystal Oscillator Inverter.
45 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
/BLE General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
H
Byte Low Enable.
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
/PLAI[7]/MS0
OUT
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM
is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/GeneralPurpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7/External Memory Select 0.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
/BHE General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
L
Byte High Enable.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-Side
Output/Programmable Logic Array Input Element 8.
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-Side
Output/Programmable Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-Side
Output/Programmable Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-Side
Output/Programmable Logic Array Input Element 11.
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
Signal Output.
BUSY
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
Reset Input, Active Low.
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-Side
Output/Programmable Logic Array Input 12.
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-Side
Output/Programmable Logic Array Input Element 13.
/PLAO[1]/MS1
TRIP
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/
External Memory Select 1.
/PLAO[2]/MS2
BUSY
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
Signal Output/Programmable Logic Array Output Element 2/External
BUSY
Memory Select 2.
CONV
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
START
Array Output Element 5/Start Conversion Input Signal for ADC.
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
Rev. D | Page 25 of 96
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic Description
46 P3.6/AD6/PWM
47 P3.7/AD7/PWM
48 P2.7/PWM1L/MS3
49
50
P2.1/WS
P2.2/RS
/PWM0H/PLAO[6] General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-
/PWM0L/PLAO[7] General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 Low-
51 P1.7/SPM7/PLAO[0]
52 P1.6/SPM6/PLAI[6]
53 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
54 IOVDD 3.3 V Supply for GPIO (see Table 7 8) and Input of the On-Chip Voltage Regulator.
55 P4.0/AD8/PLAO[8]
56 P4.1/AD9/PLAO[9]
57 P1.5/SPM5/PLAI[5]/IRQ3
58 P1.4/SPM4/PLAI[4]/IRQ2
59 P1.3/SPM3/PLAI[3]
60 P1.2/SPM2/PLAI[2]
61 P1.1/SPM1/PLAI[1]
62 P1.0/T1/SPM0/PLAI[0]
63 P4.2/AD10/PLAO[10]
64 P4.3/AD11/PLAO[11]
65 P4.4/AD12/PLAO[12]
66 P4.5/AD13/PLAO[13]
67 REFGND Ground for the Reference. Typically connected to AGND.
68 V
69 DAC
REF
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
REF
70 DACGND Ground for the DAC. Typically connected to AGND.
71, 72 AGND Analog Ground. Ground reference point for the analog circuitry.
73, 74 AVDD 3.3 V Analog Power.
75 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD.
76 ADC11 Single-Ended or Differential Analog Input 11.
77 ADC0 Single-Ended or Differential Analog Input 0.
78 ADC1 Single-Ended or Differential Analog Input 1.
79 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
80 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
/PLAI[14]
TRIP
/PLAI[15]
SYNC
General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cutoff/
Programmable Logic Array Input Element 14.
General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/
Programmable Logic Array Input Element 15.
General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory
Select 3.
Side Output/Programmable Logic Array Output Element 6.
Side Output/Programmable Logic Array Output Element 7.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic
Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic
Array Input Element 6.
General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic
Array Output Element 8.
General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic
Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic
Array Input Element 5/External Interrupt Request 3, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic
Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic
Array Output Element 10.
General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic
Array Output Element 11.
General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic
Array Output Element 12.
General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic
Array Output Element 13.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
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ADUC7028
87654321
A
B
C
D
E
F
G
H
BOTTOM VIEW
(Not to Scale)
Figure 16. 64-Ball BGA Pin Configuration (ADuC7028)
Table 14. Pin Function Descriptions (ADuC7028)
Ball No. Mnemonic Description
A1 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
A2 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD.
A3 AVDD 3.3 V Analog Power.
A4 AGND Analog Ground. Ground reference point for the analog circuitry.
A5 DACGND Ground for the DAC. Typically connected to AGND.
A6 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
A7 P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
A8 P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
B1 ADC4 Single-Ended or Differential Analog Input 4.
B2 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
B3 ADC1 Single-Ended or Differential Analog Input 1.
B4 DAC
B5 V
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
REF
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
B6 P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
B7 P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
B8 P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
C1 ADC6 Single-Ended or Differential Analog Input 6.
C2 ADC5 Single-Ended or Differential Analog Input 5.
C3 ADC0 Single-Ended or Differential Analog Input 0.
C4 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
C5 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
C6 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
C7 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
C8 IOGND Ground for GPIO (see Tabl e 78). Typically connected to DGND.
D1 ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
D2 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
D3 ADC7 Single-Ended or Differential Analog Input 7.
D4 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
D5 P3.6/PWM
/PLAI[14]
TRIP
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
D6 P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
04955-086
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Ball No. Mnemonic Description
D7 P1.6/SPM6/PLAI[6]
D8 IOVDD 3.3 V Supply for GPIO (see Table 7 8) and Input of the On-Chip Voltage Regulator.
E1 DAC3 DAC3 Voltage Output.
E2 DAC2 DAC2 Voltage Output.
E3 DAC1 DAC1 Voltage Output.
E4 P3.0/PWM0H/PLAI[8]
E5 P3.2/PWM1H/PLAI[10]
E6 P1.5/SPM5/PLAI[5]/IRQ3
E7 P3.7/PWM
/PLAI[15]
SYNC
E8 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
F1 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
F2 TDI JTAG Test Port Input, Test Data In. Debug and download access.
F3 DAC0s DAC0 Voltage Output.
F4 P3.1/PWM0L/PLAI[9]
F5 P3.3/PWM1L/PLAI[11]
F6
RST
F7 P0.7/ECLK/XCLK/SPM8/PLAO[4]
F8 XCLKO Output from the Crystal Oscillator Inverter.
G1 BM/P0.0/CMP
/PLAI[7]
OUT
G2 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
G3 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
G4 TDO JTAG Test Port Output, Test Data Out. Debug and download access.
G5 P0.3/TRST/ADC
BUSY
G6 P3.4/PWM2H/PLAI[12]
G7 P3.5/PWM2L/PLAI[13]
G8
P2.0/SPM9/PLAO[5]/CONV
START
H1 P0.6/T1/MRST/PLAO[3]
H2 TCK JTAG Test Port Input, Test Clock. Debug and download access.
H3 IOGND Ground for GPIO (see Tabl e 78). Typically connected to DGND.
H4 IOVDD 3.3 V Supply for GPIO (see Table 7 8) and Input of the On-Chip Voltage Regulator.
H5 LVDD
H6 DGND Ground for Core Logic.
H7 IRQ0/P0.4/PWM
H8 IRQ1/P0.5/ADC
/PLAO[1]
TRIP
/PLAO[2]
BUSY
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
General-Purpose Input and Output Port 3.7/PWM Synchronization/Programmable Logic
Array Input Element 15.
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
Reset Input, Active Low.
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
Multifunction I/O Pin. Boot mode. The ADuC7028 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/GeneralPurpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
Signal
Output.
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
Signal Output/Programmable Logic Array Output Element 2.
BUSY
Rev. D | Page 28 of 96
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ADUC7029
Figure 17. 49-Ball BGA Pin Configuration (ADuC7029)
Table 15. Pin Function Descriptions (ADuC7029)
Ball No. Mnemonic Description
A1 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
A2 ADC1 Single-Ended or Differential Analog Input 1.
A3 ADC0 Single-Ended or Differential Analog Input 0.
A4 AVDD 3.3 V Analog Power.
A5 V
A6 P1.0/T1/SPM0/PLAI[0]
A7 P1.1/SPM1/PLAI[1]
B1 ADC6 Single-Ended or Differential Analog Input 6.
B2 ADC5 Single-Ended or Differential Analog Input 5.
B3 ADC4 Single-Ended or Differential Analog Input 4.
B4 AGND Analog Ground. Ground reference point for the analog circuitry.
B5 DAC
B6 P1.4/SPM4/PLAI[4]/IRQ2
B7 P1.3/SPM3/PLAI[3]
C1 GND
C2 AGND Analog Ground. Ground reference point for the analog circuitry.
C3 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
C4 IOGND Ground for GPIO (see Tab le 78). Typically connected to DGND.
C5 P1.2/SPM2/PLAI[2]
C6 P1.6/SPM6/PLAI[6]
C7 P1.5/SPM5/PLAI[5]/IRQ3
D1 DAC0 DAC0 Voltage Output.
D2 DAC3 DAC3 Voltage Output.
D3 DAC1 DAC1 Voltage Output.
D4 P3.3/PWM1L/PLAI[11]
D5 P3.4/PWM2H/PLAI[12]
D6 P3.6/PWM
D7 P1.7/SPM7/PLAO[0]
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
REF
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
/PLAI[14]
TRIP
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
63
745
BOTTOM VIEW
(Not to Scale)
2
1
A
B
C
D
E
F
G
04955-088
Rev. D | Page 29 of 96
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