ANALOG DEVICES ADuC7026 Service Manual

Precision Analog Microcontroller

www.BDTIC.com/ADI

Preliminary Technical Data

FEATURES

Analog I/O
Multi-Channel, 12-bit, 1MSPS ADC

- Up to 16 ADC channels *
Fully differential and single-ended modes
0 to V
12-bit Voltage Output DACs

- Up to 4 DAC outputs available*
On-Chip 20ppm/°C Voltage Reference
On-Chip Temperature Sensor (±3°C)
Uncommitted Voltage Comparator

Microcontroller

ARM7TDMI Core, 16/32-bit RISC architecture
JTAG Port supports code download and debug

Clocking options: - Trimmed On-Chip Oscillator (± 3%)

45MHz PLL with Programmable Divider

Memory

62k Bytes Flash/EE Memory, 8k Bytes SRAM
In-Circuit Download, JTAG based Debug
Software triggered in-circuit re-programmability

On-Chip Peripherals

UART, 2 I
Up to 40-Pin GPIO Port*

Analog Input Range

REF

- External Watch crystal

- External clock source

2

C and SPI Serial I/O

12-bit Analog I/O,

ARM7TDMI® MCU

ADuC702x Series

2 X General Purpose Timers
Wake-up and Watchdog Timers
Power Supply Monitor
Three-phase 16-bit PWM generator*
PLA – Programmable Logic (Array)

Power

Specified for 3V operation
Active Mode: 3mA (@1MHz)

50mA (@45MHz)
Packages and Temperature Range
From 40 lead 6x6mm LFCSP to 80 pin LQFP*

Fully specified for –40°C to 85°C operation

Tools

Low-Cost QuickStart Development System
Full Third-Party Support

* Package, PWM, GPIO availability and number of Analog I/O
depend on part model. See page 9.

APPLICATIONS

Industrial Control and Automation Systems
Smart Sensors, Precision Instrumentation
Base Station Systems, Optical Networking

(See general description on page 11)

FUNCTIONAL BLOCK DIAGRAM

ADC0

...

...

MUX

ADC11

CMP0
CMP1

CMP

OUT

V

REF

XCLKI

XCLKO

RST

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

+

-

OSC

&PLL

PSM

POR

1MSPS

12-BIT ADC

TEMP

SENSOR

BANDGAP

REF

ARM7TDMI-BASED MCU WITH

ADDITIONAL PERIPHERALS

PLA

4 GEN. PUR-

POSE TIMERS

2kX32 SRAM

31kX16 FLASH/EEPROM

UART, SPI, I2C

SERIAL I/O

Figure 1

DAC012-BIT DAC

ADuC7026*

GPIO

JTAG

Three­phase

PWM

EXT. MEMORY

INTERFACE

DAC112-BIT DAC

DAC212-BIT DAC

DAC312-BIT DAC

PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

ADuC702x—Specifications ............................................................ 3

Reset and Remap........................................................................ 35

Terminology ...................................................................................... 6

Absolute Maximum Ratings............................................................ 7

Ordering Guide............................................................................. 9

Pin function descriptions ..............................................................10

General Description ....................................................................... 19

Overview of the ARM7TDMI core.......................................... 19

Memory organisation................................................................. 20

ADC circuit information............................................................... 25

General Overview....................................................................... 25

ADC Transfer Function............................................................. 25

Typical Operation....................................................................... 26

Converter operation................................................................... 28

Driving the analog inputs.......................................................... 29

ADC Calibration ........................................................................ 29

Temperature Sensor ...................................................................29

Other analog peripherals............................................................... 36

DAC.............................................................................................. 36

Power Supply Monitor............................................................... 38

Comparator................................................................................. 38

Oscillator and PLL - Power control ......................................... 39

Digital peripherals.......................................................................... 41

Three-phase PWM..................................................................... 41

General Purpose I/O.................................................................. 48

Serial Port Mux........................................................................... 50

Programmable Logic Array (PLA)........................................... 60

Processor reference peripherals.................................................... 63

Interrupt System ......................................................................... 63

Timers.......................................................................................... 65

ADuC702x Hardware Design considerations ............................ 73

Power supplies ............................................................................ 73

Bandgap Reference..................................................................... 29

Nonvolatile Flash/EE Memory ..................................................... 31

Flash/EE memory overview ...................................................... 31

Flash/EE Memory and the ADuC702x.................................... 31

Flash/EE memory security ........................................................ 31

Flash/EE Control Interface........................................................ 32

Execution time from SRAM and FLASH/EE .........................33

Grounding and Board Layout Recommendations................. 73

Clock Oscillator.......................................................................... 74

Power-on reset operation .......................................................... 74

Typical sysem configuration ..................................................... 75

Development Tools ........................................................................ 76

In-Circuit Serial Downloader................................................... 76

Outline Dimensions....................................................................... 77

Rev. PrA | Page 2 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

ADUC702X—SPECIFICATIONS

Table 1. (AV
unless otherwise noted.)

Parameter ADuC702x Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS

ADC Powerup Time 500 uS
DC Accuracy

Resolution 12 Bits
Integral Nonlinearity

Integral Nonlinearity
Differential Nonlinearity

Differential Nonlinearity
DC Code Distribution

CALIBRATED ENDPOINT ERRORS

Offset Error
Offset Error Match
Gain Error
Gain Error Match

DYNAMIC PERFORMANCE Fin = 10kHz Sine Wave, f

Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD) -78 dB typ
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk

ANALOG INPUT

Input Voltage Ranges

Differential mode V

Single-ended mode 0 to V
Leakage Current ±5 µA max
Input Capacitance 20 pF typ During ADC Acquisition

ON-CHIP VOLTAGE REFERENCE

Output Voltage
Accuracy ±10 mV max Measured at TA = 25°C
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal V

EXTERNAL REFERENCE INPUT9

Input Voltage Range

Input Impedance

DAC CHANNEL SPECIFICATIONS

DC ACCURACY

Resolution 12 Bits
Relative Accuracy ±2 LSB typ
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Offset Error

Gain Error
Gain Error Mismatch

= IOVDD = 2.7 V to 3.6 V, V

DD

2, 3

4

4

5

6

7

Power-On Time

REF

1

= 2.5 V Internal Reference, f

REF

f

±1.5
±0.5
±2.0
+1/-0.9
±0.5
+1/-0.9
1

±5
±1
±5
±1

LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ

LSB max
LSB typ
LSB max
LSB typ

71 dB typ

-78

-80

8

±V

/2 Volts

CM

REF

Volts

REF

2.5

±10
80
10
1

0.625
AV

DD

TBD

dB typ
dB typ

V

ppm/°C typ
dB typ

Ω typ
ms typ

V min
V max
KΩ typ

±2
±5
±0.5
TBD

mV max
mV max
% max
% typ

= 45MHz, All specifications TA = T

CORE

= 1MSPS

SAMPLE

2.5V internal reference

2.5V internal reference

1.0V external reference

2.5V internal reference

2.5V internal reference

1.0V external reference
ADC input is a dc voltage

SAMPLE

0.47µF from V

to AGND

REF

= 5kΩ, CL = 100pF

R

L

DAC output unbuffered
DAC output buffered

% of fullscale on DAC0

MAX

= 1MSPS

to T

MIN

,

Rev. PrA | Page 3 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

Parameter ADuC702x Unit Test Conditions/Comments

ANALOG OUTPUTS

Output Voltage Range_0
Ouput Voltage Range_1
Output Voltage Range_2
Output Impedance 10

DAC AC CHARACTERISTICS

Voltage Output Settling Time
Voltage Output Settling Time
Digital to Analog Glitch Energy

COMPARATOR

Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis

Response Time

TEMPERATURE SENSOR

Voltage Output at 25°C
Voltage TC
Accuracy ±3 °C typ

POWER SUPPLY MONITOR (PSM)

IOVDD Trip Point Selection 2.79 V Two selectable Trip Points

3.07 V
Power Supply Trip Point Accuracy ±2.5 % max Of the selected nominal Trip Point Voltage

Watchdog Timer (WDT)

Timeout Period

Flash/EE MEMORY

Endurance10 10,000 Cycles min
Data Retention11 30 Years min TJ = 55°C

Digital Inputs

Input Leakage Current

Input Capacitance

Logic Inputs4

VINL, Input Low Voltage
VINH, Input High Voltage

Logic Outputs

VOH, Output High Voltage IOVDD – 400mV V min I
VOL, Output Low Voltage12 0.4 V max I

MCU CLOCK RATE 355.5

STARTUP TIME

At Power-On
From Idle Mode
From Power-Down Mode

Programmable Logic Array (PLA)

Propagation Delay

4

0 to DACREF
0 to 2.5V
0 to DACV

10
15
TBD

±10
5
AGND to AV
7
5
10
1
10

TBD

-2.0

0
TBD

±10
±1
10

0.4

2.0

45.5

TBD
TBD
TBD

TBD

DD

DD

-1.2

V typ
V typ

V typ

Ω typ

µs typ
µs typ
nV-sec typ

mV
nA typ
Vmin/Vmax
pF typ
mV min
mv max
µs min
µs max

mV typ
mV/°C typ

ms min
ms max

µA max
µA typ
pF typ

V max
V min

kHz min
MHz max

ns typ

DACREF range: DACGND to DACV

DD

DAC Output buffered
DAC Output unbuffered
I LSB change at major carry

Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register

Response time may be modified via the CMPRES
bits in the CMPCON register

All digital inputs including XTAL1 and XTAL2

All Logic inputs including XTAL1 and XTAL2

= 1.6mA

SOURCE

= 1.6mA

SINK

8 programmable core clock selections within this
range

Core Clock = TBD MHz

From input pin to output pin

Rev. PrA | Page 4 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Parameter ADuC702x Unit Test Conditions/Comments

POWER REQUIREMENTS 13, 14

Power Supply Voltage Range
AVDD – AGND and IOVDD - IOGND 2.7 V min

3.6 V max

Power Supply Current Normal Mode 3mA

Power Supply Current Idle Mode

Power Supply Current Power Down
Mode

1

Temperature Range -40° to +85°C

2

All ADC Channel Specifications are guaranteed during normal MicroConverter core operation.

3

These specification apply to all ADC input channels.

4

These numbers are not production tested but are supported by design and/or characterization data on production release.

5

Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and achieve these specifications..

6

SNR calculation includes distortion and noise components.

7

Channel-to-channel crosstalk is measured on adjacent channels.

8

The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.

9

When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON Memeory Mapped Register to 0.

10

Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +85°C. Typical endurance at 25°C is 70,000 cycles.

11

Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature.

12

Test carried out with a maximum of 20 I/O set to a low output level.

13

Power supply current consumption is measured in normal, idle and power-down modes under the following conditions:
Normal Mode: TBD
Idle Mode: TBD
Power-Down: TBD

14

DVDD power supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle.

1MHz clock
1MHz clock
45MHz clock

5
50

mA typ
mA max
mA typ

60 mA max 45MHz clock

1

30
100

mA max

µA typ
µA max

External Crystal or Internal Osc ON
External Crystal or Internal Osc ON

Rev. PrA | Page 5 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

TERMINOLOGY

ADC Specifications

Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point 1/2
LSB below the first code transition and full scale, a point 1/2
LSB above the last code transition.

fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitisation process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Gain Error

This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has been
adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.

DAC SPECIFICATIONS

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to
within a 1 LSB level for a full-scale input change..

Rev. PrA | Page 6 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings (TA = 25°C unless otherwise noted)

Parameter Rating

AVDD to DVDD TBD
AGND to DGND TBD
DVDD to DGND, AVDD to AGND TBD
Digital Input Voltage to DGND TBD
Digital Output Voltage to DGND TBD
VREF to AGND TBD
Analog Inputs to AGND TBD
Operating Temperature Range

Industrial ADuC702x
Storage Temperature Range TBD
Junction Temperature TBD

θJA Thermal Impedance (CSP)

θJA Thermal Impedance (LQFP)

Lead Temperature, Soldering

Vapor Phase (60 sec) TBD
Infrared (15 sec) TBD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

–40°C to +85°C

TBD
TBD

ESD Caution

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrA | Page 7 of 78

ADuC702x Series Preliminary Technical Data

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PIN CONFIGURATION

40-Lead CSP

40

1

PIN 1

IDENTIFIER

31

30

64

1

64-Lead LQFP

PIN 1
IDENTIFIER

49

48

TOP VIE W

(Not to Scale)

10

11

21

20

16

64-Lead CSP

64

IDENTIFIER

17

PIN 1

ADuC7024/A D u C7025

TOP V IEW

(Not to Scale)

1

16

49

48

33

32

80

1

ADuC7024/ADuC7025

64-LEAD L QFP

17

80-Lead LQFP

PIN 1
IDENTIFIER

ADuC7026 80-LEAD LQFP

TOP VIEW

(Not to Scale)

TOP VIEW

(No t to S cale )

33

32

61

60

20

21

41

40

Rev. PrA | Page 8 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

ORDERING GUIDE

Model ADC

Channels

DAC
Channels

FLASH /
RAM

PWM Ext

Memory

GPIO Temp

Range

Package
Description

Package
Option

ADuC7020BCP62 5 4 62kB/8kB 14

ADuC7021BCP62 8 2 62kB/8kB 13

ADuC7021BCP32 8 2 32kB/4kB 13

ADuC7021ACP32

ADuC7022BCP62 10 62kB/8kB 13

ADuC7022BCP32 10 32kB/4kB 13

ADuC7022ACP32

ADuC7024BCP62 10 2 62kB/8kB Yes 30

ADuC7024BST62 10 2 62kB/8kB Yes 30

ADuC7025BCP62 12 62kB/8kB Yes 30

ADuC7025BCP32 12 32kB/4kB Yes 30

ADuC7026BST62 12 4 62kB/8kB Yes Yes 40

ADuC7027BST62 16 62kB/8kB Yes Yes 40

ADuC7027AST62

EVAL-ADuC7020QS

EVAL-ADuC7024QS

EVAL-ADuC7026QS

8 (10 Bit
NMC)

10 (10 Bit
NMC)

16 (10 Bit
NMC)

2 32kB/4kB 13

62kB/8kB 13

62kB/8kB Yes Yes 40

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

–40°C to +
85°C

Contact the factory for chip availability.

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

40-Lead Chip
Scale Package

64-Lead Chip
Scale Package

64 Lead
Plastic Quad
Flatpack

64-Lead Chip
Scale Package

64-Lead Chip
Scale Package

80 Lead
Plastic Quad
Flatpack

80 Lead
Plastic Quad
Flatpack

80 Lead
Plastic Quad
Flatpack

Development
System

Development
System

Development
System

CP-40

CP-40

CP-40

CP-40

CP-40

CP-40

CP-40

CP-64-1

ST-64

CP-64-1

CP-64-1

ST-80

ST-80

ST-80

Rev. PrA | Page 9 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

PIN FUNCTION DESCRIPTIONS – ADUC7020/ADUC7021/ADUC7022

Table 3. Pin Function Descriptions

Pin# ADuC702X

7020 7021 7022

38 37 36 ADC0 I Single-ended or differential Analog input 0
39 38 37 ADC1 I Single-ended or differential Analog input 1
40 39 38 ADC2/CMP0 I Single-ended or differential Analog input 2 / Comparator Positive Input

1 40 39 ADC3/CMP1 I Single-ended or differential Analog input 3 / Comparator Negative Input
2 1 40 ADC4 I Single-ended or differential Analog input 4

- 2 1 ADC5 I Single-ended or differential Analog input 5

- 3 2 ADC6 I Single-ended or differential Analog input 6

- 4 3 ADC7 I Single-ended or differential Analog input 7

- - 4 ADC8 I Single-ended or differential Analog input 8

- - 5 ADC9 I Single-ended or differential Analog input 9

3 5 6 GND

4 6 - DAC0/ADC12 I/O DAC0 Voltage Output / Single-ended or differential Analog input 12
5 7 - DAC1/ADC13 I/O DAC1 Voltage Output / Single-ended or differential Analog input 13
6 - - DAC2/ADC14 I/O DAC2 Voltage Output / Single-ended or differential Analog input 14
7 - - DAC3/ADC15 I/O DAC3 Voltage Output / Single-ended or differential Analog input 15
8 8 7 TMS I JTAG Test Port Input - Test Mode Select. Debug and download access
9 9 8 TDI I JTAG Test Port Input – Test Data In. Debug and download access

10 10 9

11 11 10

12 12 11 TCK/XCLK I

13 13 12 TDO O JTAG Test Port Output - Test Data Out. Debug and download access
14 14 13 IOGND S Ground for GPIO. Typically connected to DGND
15 15 14 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator.

16 16 15 LVDD S

17 17 16 DGND S Ground for core logic.
18 18 17 TRST I JTAG Test Port Output - Test Reset. Debug and download access
19 19 18 RST I Reset Input. (active low)

20 20 19

21 21 20

22 22 21

23 23 22

Mnemonic Type* Function

S

REF

BM/P0.0/CMP
LAI[7]

P0.6/T1/MRST/PLA
O[3]

IRQ0/P0.4/CONV

/PLAO[1]

ART

IRQ1/P0.5/ADC
/PLAO[2]

P2.0/SPM9/PLAO[
5]/CONV

P0.7/ECLK/SPM8/P
LAO[4]

START

/P

OUT

ST

BUSY

Ground voltage reference for the ADC. For optimal performance the
analog power supply should be separated from IOGND and DGND

Multifunction I/O pin:
Boot Mode. The ADuC702X will enter UART serial download mode if BM

I/O

is low at reset and will execute code if BM is pulled high at reset through
a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage
Comparator Output/ Programmable Logic Array Input Element 7

Multifunction pin: driven low after reset

O

General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output
/ Programmable Logic Array Output Element 3

JTAG Test Port Input - Test Clock. Debug and download access / Input to
the internal clock generator circuits

2.5V. Output of the on-chip voltage regulator. Must be connected to a

0.47µF capacitor to DGND

Multifunction I/O pin:
External Interrupt Request 0, active high / General Purpose Input-Output

I/O

Port 0.4 / Start conversion input signal for ADC / Programmable Logic
Array Output Element 1

Multifunction I/O pin:

I/O

External Interrupt Request 1, active high / General Purpose Input-Output
Port 0.5 / ADC

Serial Port Multiplexed:

I/O

General Purpose Input-Output Port 2.0 / UART / Programmable Logic
Array Output Element 5/ Start conversion input signal for ADC

Serial Port Multiplexed:

I/O

General Purpose Input-Output Port 0.7 / Output for External Clock signal
/ UART / Programmable Logic Array Output Element 4

signal / Programmable Logic Array Output Element 2

BUSY

Rev. PrA | Page 10 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Pin# ADuC702X

7020 7021 7022

24 24 23 XCLKO O Output to the crystal oscillator inverter

25 24 24 XCLKI I

26 26 25

27 27 26 P1.6/SPM6/PLAI[6] I/O

28 28 27 P1.5/SPM5/PLAI[5] I/O

29 29 28 P1.4/SPM4/PLAI[4] I/O

30 30 29 P1.3/SPM3/PLAI[3] I/O

31 31 30 P1.2/SPM2/PLAI[2] I/O

32 32 31 P1.1/SPM1/PLAI[1] I/O

33 33 32

34 - - P4.2/PLAO[10] I/O

35 34 33 V

36 35 34 AGND S Analog Ground. Ground reference point for the analog circuitry
37 36 35 AVDD S 3.3V Analog Power

*

I = Input, O = Output, S = Supply.

- No pin assigned.

Mnemonic Type* Function

Input to the crystal oscillator inverter and input to the internal clock
generator circuits

P1.7/SPM7/PLAO[
0]

P1.0/T1/SPM0/PLA
I[0]

I/O

REF

Serial Port Multiplexed:

I/O

General Purpose Input-Output Port 1.7 / UART / SPI / Programmable
Logic Array Output Element 0

Serial Port Multiplexed:
General Purpose Input-Output Port 1.6 / UART / SPI / Programmable

Logic Array Input Element 6
Serial Port Multiplexed:
General Purpose Input-Output Port 1.5 / UART / SPI / Programmable

Logic Array Input Element 5
Serial Port Multiplexed:
General Purpose Input-Output Port 1.4 / UART / SPI / Programmable

Logic Array Input Element 4
Serial Port Multiplexed:
General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable

Logic Array Input Element 3
Serial Port Multiplexed:
General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable

Logic Array Input Element 2
Serial Port Multiplexed:
General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable

Logic Array Input Element 1
Serial Port Multiplexed:

I/O

General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 /
Programmable Logic Array Input Element 0

General Purpose Input-Output Port 4.2 / Programmable Logic Array
Output Element 10

2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor
when using the internal reference.

Rev. PrA | Page 11 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

PIN FUNCTION DESCRIPTIONS – ADUC7024/ADUC7025

Table 4. Pin Function Descriptions

Pin# Mnemonic Type* Function

1 ADC4 I Single-ended or differential Analog input 4
2 ADC5 I Single-ended or differential Analog input 5
3 ADC6 I Single-ended or differential Analog input 6
4 ADC7 I Single-ended or differential Analog input 7
5 ADC8 I Single-ended or differential Analog input 8
6 ADC9 I Single-ended or differential Analog input 9

7 GND

8 ADCNEG I

9 DAC0**/ADC12 I/O DAC0 Voltage Output / Single-ended or differential Analog input 12
10 DAC1**/ADC13 I/O DAC1 Voltage Output / Single-ended or differential Analog input 13
11 TMS I JTAG Test Port Input - Test Mode Select. Debug and download access
12 TDI I JTAG Test Port Input – Test Data In. Debug and download access

13 P4.6/PLAO[14] I/O

14 P4.7/PLAO[15] I/O

15 BM/P0.0/CMP

16 P0.6/T1/MRST/PLAO[3] O

17 TCK I JTAG Test Port Input - Test Clock. Debug and download access
18 TDO O JTAG Test Port Output - Test Data Out. Debug and download access
19 IOGND S Ground for GPIO. Typically connected to DGND
20 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator.

21 LVDD S

22 DGND S Ground for core logic.

23 P3.0/PWM0H/PLAI[8] I/O

24 P3.1/PWM0L/PLAI[9] I/O

25 P3.2/PWM1H/PLAI[10] I/O

26 P3.3/PWM1L/PLAI[11] I/O

27 P0.3/TRST/ADC

28 RST I Reset Input. (active low)

29 P3.4/PWM2H/PLAI[12] I/O

30 P3.5/PWM2L/PLAI[13] I/O

S

REF

/PLAI[7] I/O

OUT

I/O

BUSY

Ground voltage reference for the ADC. For optimal performance the analog
power supply should be separated from IOGND and DGND

Bias point or Negative Analog Input of the ADC in pseudo differential mode.
Must be connected to the ground of the signal to convert. This bias point
must be between 0V and 1V

General Purpose Input-Output Port 4.6/ Programmable Logic Array Output
Element 14

General Purpose Input-Output Port 4.7/ Programmable Logic Array Output
Element 15

Multifunction I/O pin:
Boot Mode. The ADuC7024/ADuC7025 will enter UART serial download mode

if BM is low at reset and will execute code if BM is pulled high at reset through
a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage
Comparator Output/ Programmable Logic Array Input Element 7

Multifunction pin: driven low after reset
General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output /

Programmable Logic Array Output Element 3

2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF
capacitor to DGND

General Purpose Input-Output Port 3.0/ PWM phase 0 high side output /
Programmable Logic Array Input Element 8

General Purpose Input-Output Port 3.1/ PWM phase 0 low side output /
Programmable Logic Array Input Element 9

General Purpose Input-Output Port 3.2/ PWM phase 1 high side output /
Programmable Logic Array Input Element 10

General Purpose Input-Output Port 3.3/ PWM phase 1 low side output /
Programmable Logic Array Input Element 11

General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset.
Debug and download access / ADC

General Purpose Input-Output Port 3.4 / PWM phase 2 high side output /
Programmable Logic Array Input 12

General Purpose Input-Output Port 3.5 / PWM phase 2 low side output /
Programmable Logic Array Input Element 13

signal output

BUSY

Rev. PrA | Page 12 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Pin# Mnemonic Type* Function

Multifunction I/O pin:

31 IRQ0/P0.4/CONV

32 IRQ1/P0.5/ADC

33 P2.0/PWM

34 P0.7/ECLK/SPM8/PLAO[4] I/O

35 XCLKO O Output to the crystal oscillator inverter

36 XCLKI I

37 P3.6/PWM

38 P3.7/PWMSYNC/PLAI[15] I/O

39 P1.7/SPM7/PLAO[0] I/O

40 P1.6/SPM6/PLAI[6] I/O

41 IOGND S Ground for GPIO. Typically connected to DGND
42 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator.

43 P4.0/PLAO[8] I/O

44 P4.1/PLAO[9] I/O

45 P1.5/SPM5/PLAI[5] I/O

46 P1.4/SPM4/PLAI[4] I/O

47 P1.3/SPM3/PLAI[3] I/O

48 P1.2/SPM2/PLAI[2] I/O

49 P1.1/SPM1/PLAI[1] I/O

50 P1.0/T1/SPM0/PLAI[0] I/O

51 P4.2/PLAO[10] I/O

TRIP

TRIP

/PLAO[1] I/O

START

/PLAO[2] I/O

BUSY

/SPM9/PLAO[5]/CONV

/PLAI[14] I/O

I/O

START

External Interrupt Request 0, active high / General Purpose Input-Output Port

0.4 / Start conversion input signal for ADC / Programmable Logic Array
Output Element 1

Multifunction I/O pin:
External Interrupt Request 1, active high / General Purpose Input-Output Port

0.5 / ADC
Serial Port Multiplexed:
General Purpose Input-Output Port 2.0 / PWM safety cut off / UART /

Programmable Logic Array Output Element 5/ Start conversion input signal
for ADC

Serial Port Multiplexed:
General Purpose Input-Output Port 0.7 / Output for External Clock signal /

UART / Programmable Logic Array Output Element 4

Input to the crystal oscillator inverter and input to the internal clock
generator circuits

General Purpose Input-Output Port 3.6/ PWM safety cut off / Programmable
Logic Array Input Element 14

General Purpose Input-Output Port 3.7/ PWM synchronisation input output
/Programmable Logic Array Input Element 15

Serial Port Multiplexed:
General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic

Array Output Element 0
Serial Port Multiplexed:
General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic

Array Input Element 6

General Purpose Input-Output Port 4.0 / Programmable Logic Array Output
Element 8

General Purpose Input-Output Port 4.1 / Programmable Logic Array Output
Element 9

Serial Port Multiplexed:
General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic

Array Input Element 5
Serial Port Multiplexed:
General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic

Array Input Element 4
Serial Port Multiplexed:
General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic

Array Input Element 3
Serial Port Multiplexed:
General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic

Array Input Element 2
Serial Port Multiplexed:
General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic

Array Input Element 1
Serial Port Multiplexed:
General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I

Programmable Logic Array Input Element 0
General Purpose Input-Output Port 4.2 / Programmable Logic Array Output

Element 10

signal / Programmable Logic Array Output Element 2

BUSY

2

C0 /

Rev. PrA | Page 13 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

Pin# Mnemonic Type* Function

52 P4.3/PLAO[11] I/O

53 P4.4/PLAO[12] I/O

54 P4.5/PLAO[13] I/O

55 V

56 DAC
57 DACGND S Ground for the DAC. Typically connected to AGND
58 AGND S Analog Ground. Ground reference point for the analog circuitry
59 AVDD S 3.3V Analog Power
60 DACVDD S 3.3V Power Supply for the DACs. Typically connected to AVDD
61 ADC0 I Single-ended or differential Analog input 0
62 ADC1 I Single-ended or differential Analog input 1
63 ADC2/CMP0 I Single-ended or differential Analog input 2/ Comparator positive input
64 ADC3/CMP1 I Single-ended or differential Analog input 3/ Comparator negative input

*

I = Input, O = Output, S = Supply.

** DAC outputs not present on ADuC7025

I/O

REF

I External Voltage Reference for the DACs. Range: DACGND to DACVDD

REF

General Purpose Input-Output Port 4.3 / Programmable Logic Array Output
Element 11

General Purpose Input-Output Port 4.4 / Programmable Logic Array Output
Element 12

General Purpose Input-Output Port 4.5 / Programmable Logic Array Output
Element 13

2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor
when using the internal reference.

Rev. PrA | Page 14 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

PIN FUNCTION DESCRIPTIONS – ADUC7026/ADUC7027

Table 5. Pin Function Descriptions

Pin# Mnemonic Type* Function

1 ADC4 I Single-ended or differential Analog input 4
2 ADC5 I Single-ended or differential Analog input 5
3 ADC6 I Single-ended or differential Analog input 6
4 ADC7 I Single-ended or differential Analog input 7
5 ADC8 I Single-ended or differential Analog input 8
6 ADC9 I Single-ended or differential Analog input 9
7 ADC10 I Single-ended or differential Analog input 10

8 GND

9 ADCNEG I

10 DAC0/ADC12 I/O DAC0 Voltage Output / Single-ended or differential Analog input 12
11 DAC1/ADC13 I/O DAC1 Voltage Output / Single-ended or differential Analog input 13
12 DAC1/ADC14 I/O DAC2 Voltage Output / Single-ended or differential Analog input 14
13 DAC1/ADC15 I/O DAC3 Voltage Output / Single-ended or differential Analog input 15
14 TMS I JTAG Test Port Input - Test Mode Select. Debug and download access
15 TDI I JTAG Test Port Input – Test Data In. Debug and download access
16
17 P2.3/AE

18 P4.6/AD14/PLAO[14] I/O

19 P4.7/AD15/PLAO[15] I/O

20 BM/P0.0/CMP

21 P0.6/T1/MRST/PLAO[3]/AE O

22 TCK I JTAG Test Port Input - Test Clock. Debug and download access
23 TDO O JTAG Test Port Output - Test Data Out. Debug and download access
24
25 IOGND S Ground for GPIO. Typically connected to DGND
26 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator.

27 LVDD S

28 DGND S Ground for core logic.

29 P3.0/AD0/PWM0H/PLAI[8] I/O

30 P3.1/AD1/PWM0L/PLAI[9] I/O

31 P3.2/AD2/PWM1H/PLAI[10] I/O

32 P3.3/AD3/PWM1L/PLAI[11] I/O

33 P2.4/MS0 I/O General Purpose Input-Output Port 2.4 / External Memory select 0

S

REF

BLE

P0.1/

P0.2/

BHE

/PLAI[7] I/O

OUT

Ground voltage reference for the ADC. For optimal performance the analog
power supply should be separated from IOGND and DGND

Bias point or Negative Analog Input of the ADC in pseudo differential mode.
Must be connected to the ground of the signal to convert. This bias point
must be between 0V and 1V

I/O General Purpose Input-Output Port 0.1

General Purpose Input-Output Port 4.6/ External Memory
Interface/Programmable Logic Array Output Element 14

General Purpose Input-Output Port 4.7/ External Memory Interface /
Programmable Logic Array Output Element 15

Multifunction I/O pin:
Boot Mode. The ADuC7026 will enter UART serial download mode if BM is low

at reset and will execute code if BM is pulled high at reset through a 1kOhm
resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator
Output/ Programmable Logic Array Input Element 7

Multifunction pin: driven low after reset
General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output /

Programmable Logic Array Output Element 3

I/O General Purpose Input-Output Port 0.2

2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF
capacitor to DGND

General Purpose Input-Output Port 3.0 / External Memory Interface/ PWM
phase 0 high side output / Programmable Logic Array Input Element 8

General Purpose Input-Output Port 3.1 / External Memory Interface / PWM
phase 0 low side output / Programmable Logic Array Input Element 9

General Purpose Input-Output Port 3.2 / External Memory Interface / PWM
phase 1 high side output / Programmable Logic Array Input Element 10

General Purpose Input-Output Port 3.3 / External Memory Interface / PWM
phase 1 low side output / Programmable Logic Array Input Element 11

Rev. PrA | Page 15 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

Pin# Mnemonic Type* Function

34 P0.3/TRST/A16/ADC

35 P2.5/MS1 I/O General Purpose Input-Output Port 2.5 / External Memory select 1
36 P2.6/MS2 I/O General Purpose Input-Output Port 2.6 / External Memory select 2
37 RST I Reset Input. (active low)

38 P3.4/AD4/PWM2H/PLAI[12] I/O

39 P3.5/AD5/PWM2L/PLAI[13] I/O

40 IRQ0/P0.4/CONV

41 IRQ1/P0.5/ADC

42 P2.0/PWM

43 P0.7/ECLK/SPM8/PLAO[4] I/O

44 XCLKO O Output to the crystal oscillator inverter

45 XCLKI I

46 P3.6/AD6/PWM

47 P3.7/AD7/ECLK/PLAI[15] I/O

48 P2.7/MS3 I/O General Purpose Input-Output Port 2.7 / External Memory select 3
49 P2.1/WS I/O General Purpose Input-Output Port 2.1 / External Memory Write Strobe
50 P2.2/RS I/O General Purpose Input-Output Port 2.2 / External Memory Read Strobe

51 P1.7/SPM7/PLAO[0] I/O

52 P1.6/SPM6/PLAI[6] I/O

53 IOGND S Ground for GPIO. Typically connected to DGND
54 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator.

55 P4.0/AD8/PLAO[8] I/O

56 P4.1/AD9/PLAO[9] I/O

57 P1.5/SPM5/PLAI[5] I/O

58 P1.4/SPM4/PLAI[4] I/O

59 P1.3/SPM3/PLAI[3] I/O Serial Port Multiplexed:

BUSY

/SPM9/PLAO[5]/CONV

TRIP

I/O

BUSY

/PLAO[1] I/O

START

/PLAO[2] I/O

I/O

START

/PLAI[14] I/O

TRIP

General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset.
Debug and download access / ADC

General Purpose Input-Output Port 3.4 / External Memory Interface / PWM
phase 2 high side output / Programmable Logic Array Input 12

General Purpose Input-Output Port 3.5 / External Memory Interface /PWM
phase 2 low side output / Programmable Logic Array Input Element 13

Multifunction I/O pin:
External Interrupt Request 0, active high / General Purpose Input-Output Port

0.4 / Start conversion input signal for ADC / Programmable Logic Array
Output Element 1

Multifunction I/O pin:
External Interrupt Request 1, active high / General Purpose Input-Output Port

0.5 / ADC
Serial Port Multiplexed:
General Purpose Input-Output Port 2.0 / PWM safety cut off / UART /

Programmable Logic Array Output Element 5/ Start conversion input signal
for ADC

Serial Port Multiplexed:
General Purpose Input-Output Port 0.7 / Output for External Clock signal /

UART / Programmable Logic Array Output Element 4

Input to the crystal oscillator inverter and input to the internal clock
generator circuits

General Purpose Input-Output Port 3.6 / External Memory Interface / PWM
safety cut off / Programmable Logic Array Input Element 14

General Purpose Input-Output Port 3.7/ / External Memory Interface / Output
for External Clock signal /Programmable Logic Array Input Element 15

Serial Port Multiplexed:
General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic

Array Output Element 0
Serial Port Multiplexed:
General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic

Array Input Element 6

General Purpose Input-Output Port 4.0 / External Memory Interface /
Programmable Logic Array Output Element 8

General Purpose Input-Output Port 4.1 / External Memory Interface
/Programmable Logic Array Output Element 9

Serial Port Multiplexed:
General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic

Array Input Element 5
Serial Port Multiplexed:
General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic

Array Input Element 4

signal / Programmable Logic Array Output Element 2

BUSY

signal output

BUSY

Rev. PrA | Page 16 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Pin# Mnemonic Type* Function

General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic
Array Input Element 3

Serial Port Multiplexed:

60 P1.2/SPM2/PLAI[2] I/O

61 P1.1/SPM1/PLAI[1] I/O

62 P1.0/T1/SPM0/PLAI[0] I/O

63 P4.2/AD10/PLAO[10] I/O

64 P4.3/AD11/PLAO[11] I/O

65 P4.4/AD12/PLAO[12] I/O

66 P4.5/AD13/PLAO[13] I/O

67 REFGND S Ground for the reference. Typically connected to AGND

68 V

69 DAC
70 DACGND S Ground for the DAC. Typically connected to AGND
71 AGND S Analog Ground. Ground reference point for the analog circuitry
72 AGND S Analog Ground. Ground reference point for the analog circuitry
73 AVDD S 3.3V Analog Power
74 AVDD S 3.3V Analog Power
75 DACVDD S 3.3V Power Supply for the DACs. Typically connected to AVDD
76 ADC11 I Single-ended or differential Analog input 11
77 ADC0 I Single-ended or differential Analog input 0
78 ADC1 I Single-ended or differential Analog input 1
79 ADC2/CMP0 I Single-ended or differential Analog input 2/ Comparator positive input
80 ADC3/CMP1 I Single-ended or differential Analog input 3/ Comparator negative input

*

I = Input, O = Output, S = Supply.

I/O

REF

I External Voltage Reference for the DACs. Range: DACGND to DACVDD

REF

General Purpose Input-Output Port 1.2 / UART / I
Array Input Element 2

Serial Port Multiplexed:
General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic

Array Input Element 1
Serial Port Multiplexed:
General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I

Programmable Logic Array Input Element 0
General Purpose Input-Output Port 4.2 / External Memory Interface /

Programmable Logic Array Output Element 10

General Purpose Input-Output Port 4.3 / External Memory Interface
/Programmable Logic Array Output Element 11

General Purpose Input-Output Port 4.4 / External Memory Interface
/Programmable Logic Array Output Element 12

General Purpose Input-Output Port 4.5 / External Memory Interface
/Programmable Logic Array Output Element 13

2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor
when using the internal reference.

2

C1 /Programmable Logic

2

C0 /

Rev. PrA | Page 17 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

D

F
E

N

R

D

D

D

G

N

D

D
N

G

G

A

D

F

V

V

E

A

A

R

D

D

D

N
G
O

I

D

N

D

D

V

V

G

O

O

O

I

I

I

T

D

E

D

N

S

D

E

V

G

R

L

D

D

D

F

N

D

E
R

V

G

C

C

C

A

A

A

D

D

D

BM/P0.0/CMP

P4.6/PLAO/AD14
P4.7/PLAO/AD15

ADC0

ADC1
ADC2/CMP0
ADC3/CMP1

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

ADC10

ADC11

ADC

NEG

/PLAO

OUT

V

REF

DAC

DAC

PROG. LOGIC

MUX

MUX

MUX

BAND GAP

REFERENCE

ARRAY

12-BIT SAR

ADC 1MSPS

TEMP

SENSOR

62 KBYTES FLASH/EE

/IRQ

CMP

OUT

V

REF

SPI/I2CSERIAL

INTERFACE

SERIAL PORT MULTIPLEXER

8192 BYTES USER RAM

ADC

CONTROL

(31k X 16 bits)

(2k X 32 bits)

DOWNLOADER

UART

SERIAL PORT

ADuC7026*

ARM7TDMI

MCU

CORE

R
O

T

G

A

A

L

T

U

J

M
E

DAC

CONTROL

WAKEUP/

RTC TIMER

POWER SUPPLY

MONITOR

PROG. CLOCK

DIVIDER

POR

12-BIT

VOLTAGE

OUTPUT DAC

12-BIT

VOLTAGE

OUTPUT DAC

12-BIT

VOLTAGE

OUTPUT DAC

12-BIT

VOLTAGE

OUTPUT DAC

CONTROLLER

BUF

BUF

BUF

BUF

Three-

phase

PWM

OSC

PLL

INTERRUPT

DAC0*/ADC12

DAC1*/ADC13

DAC2*/ADC14

DAC3*/ADC15

P3.0/PWM0H/PLAI/AD0
P3.1/PWM0L/PLAI/AD1
P3.2/PWM1H/PLAI/AD2
P3.3/PWM1H/PLAI/AD3
P3.4/PWM2H/PLAI/AD4
P3.5/PWM2H/PLAI/AD5
P3.6/PWM

XCLKO
XCLKI

P3.7/ECLK/PLAI/AD7

IRQ0/P0.4/CONV
IRQ1/P0.5/ADC
P0.0

TRIP

/PLAI/AD6

START

/PLAO

BUSY

/PLAO

0

8
D
A

/
O
A
L
P

/

0

.

4
P

1

9

1

1

D

D

D

A

/

A

A

/

/

O

O

O

A

A

A

L

L

L

P

/

P

P

/

/

1

.

2

3

.

.

4

4

4

P

P

P

I

3

2

A

1

1

L

D

D

A

A

/P

/

/

0

O

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M

A

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P

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S

P

P

/

/

/

0

.

5

4

.

.

1

4

4

P

P

P

I

I

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L

L

P

P

P

P

/

/

/

/

3

2

1

4

M

M

M

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P

P

P

P

S

S

S

S

/

/

/

/

3

2

1

4

.

.

.

.

1

1

1

1

P

P

P

P

I

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A

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L

L

P

P

/

/

6

5

M

M

P

P

S

S

/

/

6

5

.

.

1

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P

P

T

O

A

R

A

L

A

L

T

P

/

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S

/

7

V

8

M

M

M

P

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P

S

/

S

C

/

/

7

.

K

O

1

L

A

P

C

L

E

P

/

/

7

9

.

0

M

P

P
/S

P

I
R
T

M
W

P

/

0

.

2
P

I

S

D

M

T

T

Y

O

K
L

D
T

C
X

/
K
C
T

E

S

A

U

/

B

O

C

A

D

L

A

P

/

/

6

T

1

S

A

R

/
T

M

/

S

6

.

R

0

T

/

P

3

.

0
P

E

S

S

A

R

W

/

/

/

3

2

1

.

.

.

2

2

2

P

P

P

3

0

1

2

E

S

S

M

M

/

/

4

5

.

.

2

2

P

P

* See selection table for
feature availabilityon
different models.

E

S

S

L

H

B

B

M

M

/

/

/

/

1

2

6

7

.

.

.

.

0

0

2

2

P

P

P

P

Figure 2: Detailed Block Diagram

Rev. PrA | Page 18 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

GENERAL DESCRIPTION

The ADuC702x is fully integrated, 1MSPS, 12-bit data
acquisition system incorporating a high performance multi­channel ADC, a 16/32-bit MCU and Flash/EE Memory on a
single chip.

The ADC consists of up to 12 single-ended inputs. An
additional 4 inputs are available but are multiplexed with the 4
DAC output pins. The 4 DAC outputs are only available on
certain models of the ADuC702x, though in many cases where
the DAC is not present this pin can still be used as an additional
ADC input, giving a maximum of 16 ADC input channels. The
ADC can operate in single-ended or differential input modes.
The ADC input voltage is 0 to V
reference, temperature sensor and voltage comparator complete
the ADC peripheral set.

The ADuC702x also integrates 4 buffered voltage output DACs
on-chip. The DAC output range is programmable to one of
three voltage ranges.

The device operates from an on-chip oscillator and PLL
generating an internal high-frequency clock of 45 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16/32-bit RISC
machine, offering up to 45 MIPS peak performance. 62k Bytes
of non-volatile Flash/EE are provided on-chip as well as 8k
Bytes of SRAM. Both the Flash/EE and SRAM memory arrays
are mapped into a single linear array.

. Low drift bandgap

REF

system debugging.

Thumb mode (T)

An ARM instruction is 32-bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16-bits, the Thumb instruction set. Faster
execution from 16-bit memory and greater code density can
usually be achieved by using the Thumb instruction set instead
of the ARM instruction set, which makes the ARM7TDMI core
particularly suitable for embedded applications.

However the Thumb mode has two limitations:

- Thumb code usually uses more instructions for the same job,

so ARM code is usually best for maximising the performance
of the time-critical code.

- The Thumb instruction set does not include some

instructions that are needed for exception handling, so ARM
code needs to be used for exception handling.

See ARM7TDMI User Guide for details on the core
architecture, the programming model and both the ARM and
ARM Thumb instruction sets.

Long Multiply (M)

The ARM7TDMI instruction set includes four extra
instructions which perform 32-bit by 32-bit multiplication with
64-bit result and 32-bit by 32-bit multiplication-accumulation
(MAC) with 64-bit result.

On-chip factory firmware supports in-circuit serial download
via the UART and JTAG serial interface ports while non­intrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low-cost QuickStart
Development System supporting this MicroConverter family.

The parts operate from 2.7V to 3.6V and are specified over an
industrial temperature range of -40°C to 85°C. When operating
at 45MHz the power dissipation is 300mW. The ADuC702x is
available in a variety of memory models and packages. These
are detailed on page 9.

OVERVIEW OF THE ARM7TDMI CORE

The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8, 16 or 32 bits and the length of the
instruction word is 32 bits.

The ARM7TDMI is an ARM7 core with 4 additional features:

- T support for the Thumb (16 bit) instruction set.

- D support for debug

- M support for long multiplies

- I include the EmbeddedICE module to support embedded

EmbeddedICE (I)

EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers which allow code to be halted for
debugging purposes. These registers are controlled through the
JTAG test port.

When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be inspected as well as the Flash/EE, the
SRAM and the Memory Mapped Registers.

Exceptions

ARM supports five types of exceptions, and a privileged
processing mode for each type. The five type of exceptions are:

- Normal interrupt or IRQ. It is provided to service general-

purpose interrupt handling of internal and external events

- Fast interrupt or FIQ. It is provided to service data transfer or

communication channel with low latency. FIQ has priority
over IRQ

- Memory abort

- Attempted execution of an undefined instruction

Rev. PrA | Page 19 of 78

ADuC702x Series Preliminary Technical Data

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- Software interrupt (SWI) instruction which can be used to

make a call to an operating system.

Typically the programmer will define interrupts as IRQ but for
higher priority interrupt, i.e. faster response time, the
programmer can define interrupt as FIQ.

ARM Registers

ARM7TDMI has a total of 37 registers, of which 31 are general
purpose registers and six are status registers. Each operating
mode has dedicated banked registers.

When writing user-level programs, 15 general purpose 32-bit
registers (r0 to r14), the program counter (r15) and the current
program status register (CPSR) are usable. The remaining
registers are used only for system-level programming and for
exception handling.

When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (r13) and the link register (r14) as represented in
Figure 3. The fast interrupt mode has more registers (8 to 12)
for fast interrupt processing, so that the interrupt processing
can begin without the need to save or restore these registers and
thus save critical time in the interrupt handling process.

r0
r1
r2
r3
r4

r5
r6
r7

r8
r9
r10
r11
r12
r13
r14
r15 (PC)

CPSR

r8_fiq

r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq

SPSR_fiq

r13_svc
r14_svc

SPSR_svc

r13_abt
r14_abt

SPSR_abt

usable in user mode

system modes only

r13_irq
r14_irq

SPSR_irq

r13_und
r14_und

SPSR_und

Interrupt latency

The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 41 processor cycles, which
is just over 909 nanoseconds in a system using a continuous 45
MHz processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time.

The minimum latency for FIQ or IRQ interrupts is five cycles in
total which consists of the shortest time the request can take
through the synchronizer plus the time to enter the exception
mode.

Note that the ARM7TDMI will always be run in ARM (32-bit)
mode when in privileged modes, i.e. when executing interrupt
service routines.

MEMORY ORGANISATION

The part incorporates two separate blocks of memory, 8kByte of
SRAM and 64kByte of On-Chip Flash/EE memory. 62kByte of
On-Chip Flash/EE memory are available to the user, and the
remaining 2kBytes are reserved for the factory configured boot
page. These two blocks are mapped as shown in

Figure 4

.

Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0x00000000. It is possible to remap the
SRAM at address 0x00000000 by clearing bit 0 of the REMAP
MMR. This remap function is described in more details in the
Flash/EE memory chapter.

FFFFFFFFh

FFFF0000h

0008FFFFh

MMRs

Reserved

user mode fiq

mode

svc

mode

abord
mode

irq

mode

undefined

mode

Figure 3: register organisation

More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents from ARM:

- DDI0029G, ARM7TDMI Technical Reference Manual.

- DDI0100E, ARM Architecture Reference Manual.

Rev. PrA | Page 20 of 78

00080000h

00010000h

00000000h

Flash/EE

Reserved

00011FFFh

0000FFFFh

SRAM

Re-mappableMemory Space
(Flash/EE or SRAM)

Figure 4: Physical memory map

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Memory Access

The ARM7 core sees memory as a linear array of 232 byte
location where the different blocks of memory are mapped as
outlined in

Figure 4

.

The ADuC702x memory organisation is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.

Byte0

...

89AB
4567
01

bit0

0xFFFFFFFFh

0x00000004h

0x00000000h

bit31

Byte3

...

Byte1Byte2

...

...

23

32 bits

Figure 5: little endian format

Flash/EE Memory

The total 64kBytes of Flash/EE are organised as 32k X 16 bits.
31k X 16 bits are user space and 1k X 16 bits is reserved for boot
loader. The page size of this Flash/EE memory is 256Bytes.

62kBytes of Flash/EE are available to the user as code and non­volatile data memory. There is no distinction between data and
program as ARM code shares the same space. The real width of
the Flash/EE memory is 16 bits, which means that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary for each instruction fetch. It is therefore
recommended to use Thumb mode when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 45MHz in Thumb
mode and 22.5MHz in full ARM mode. More details on
Flash/EE access time are outlined later in ‘Execution from
SRAM and Flash/EE’ section of this datasheet.

SRAM

8kBytes of SRAM are available to the user, organized as 2k X 32
bits, i.e. 2kWords. ARM code can run directly from SRAM at
45MHz , given that the SRAM array is configured as a 32-bit
wide memory array. More details on SRAM access time are
outlined later in ‘Execution from SRAM and Flash/EE’ section
of this datasheet.

Memory Mapped Registers

The Memory Mapped Register (MMR) space is mapped into
the upper 2 pages of the Flash/EE space and accessed by
indirect addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 6
are unoccupied or reserved locations and should not be
accessed by user software. Table 6 shows a full MMR memory
map.

0xFFFFFFFF

0xFFFFFC3C

0xFFFFFC00

0xFFFFF820

0xFFFFF800

0xFFFFF46C

0xFFFFF400

0xFFFF0B54

0xFFFF0B00

0xFFFF0A14

0xFFFF0A00

0xFFFF0948

0xFFFF0900

0xFFFF0848

0xFFFF0800

0xFFFF0730

0xFFFF0700

0xFFFF0620

0xFFFF0600

0xFFFF0538

0xFFFF0500

0xFFFF0490

0xFFFF048C

0xFFFF0448

0xFFFF0440

0xFFFF0420

0xFFFF0404

0xFFFF0370

0xFFFF0360

0xFFFF0350

0xFFFF0340

0xFFFF0334

0xFFFF0320

0xFFFF0310

0xFFFF0300

0xFFFF0238

0xFFFF0220

0xFFFF0110

0xFFFF0000

PWM

Flash Control

Interface

GPIO

PLA

SPI

I2C1

I2C0

UART

DAC

ADC

Bandgap

Reference

Power Supply

Monitor

PLL &

Oscillator Control

Watchdog

Timer

Wake Up

Timer

General Purpose

Timer

Timer 0

Remap &

System Control

Interrupt

Controller

Figure 6: Memory Mapped

Rev. PrA | Page 21 of 78

ADuC702x Series Preliminary Technical Data

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Table 6. Complete MMRs list

Access Address Name Byte

Type Cycle

IRQ address base = 0xFFFF0000

0x0000 IRQSTA 4 R 1 63

0x0004 IRQSIG 4 R 1 63

0x0008 IRQEN 4 RW 1 63

0x000C IRQCLR 4 W 1 63

0x0010 SWICFG 4 W 1 64

0x0100 FIQSTA 4 R 1 63

0x0104 FIQSIG 4 R 1 63

0x0108 FIQEN 4 RW 1 63

0x010C FIQCLR 4 W 1 63

System Control address base = 0xFFFF0200

0x0220 REMAP 1 RW 1 35

0x0230 RSTSTA 1 R 1 35

0x0234 RSTCLR 1 W 1 35

Timer address base = 0xFFFF0300

0x0300 T0LD 2 RW 2 65

0x0304 T0VAL 2 R 2 65

0x0308 T0CON 2 RW 2 65

0x030C T0CLRI 1 W 2 65

0x0320 T1LD 4 RW 2 66

0x0324 T1VAL 4 R 2 66

0x0328 T1CON 2 RW 2 66

0x032C T1CLRI 1 W 2 66

0x0330 T1CAP 4 RW 2 66

0x0340 T2LD 4 RW 2 67

0x0344 T2VAL 4 R 2 67

0x0348 T2CON 2 RW 2 67

0x034C T2CLRI 1 W 2 67

0x0360 T3LD 2 RW 2 68

0x0364 T3VAL 2 R 2 68

0x0368 T3CON 2 RW 2 68

0x036C T3CLRI 1 W 2 68

PLL base address = 0xFFFF0400

0x0404 POWKY1 1 W 2 40

0x0408 POWCON 1 RW 2 40

0x040C POWKY2 1 W 2 40

0x0410 PLLKY1 1 W 2 40

Page

Address Name Byte

0x0414 PLLCON 1 RW 2 40

0x0418 PLLKY2 1 W 2 40

PSM address base = 0xFFFF0440

0x0440 PSMCON 2 RW 2 38

0x0444 CMPCON 2 RW 2 38

Reference address base = 0xFFFF0480

0x048C REFCON 1 RW 2 30

ADC address base = 0xFFFF0500

0x0500 ADCCON 1 RW 2 26

0x0504 ADCCP 1 RW 2 27

0x0508 ADCCN 1 RW 2 27

0x050C ADCSTA 1 RW 2 26

0x0510 ADCDAT 4 R 2 26

0x0514 ADCRST 1 RW 2 26

0x0530 ADCGN 2 RW 2 29

0x0534 ADCOF 2 RW 2 29

DAC address base = 0xFFFF0600

0x0600 DAC0CON 1 RW 2 36

0x0604 DAC0DAT 4 RW 2 36

0x0608 DAC1CON 1 RW 2 36

0x060C DAC1DAT 4 RW 2 36

UART base address = 0xFFFF0700

0x0700 COMTX 1 RW 2 51

COMRX 1 R 2 51

COMDIV0 1 RW 2 51

0x0704 COMIEN0 1 RW 2 52

COMDIV1 1 R/W 2 51

0x0708 COMIID0 1 R 2 52

0x070C COMCON0 1 RW 2 51

0x0710 COMCON1 1 RW 2 53

0x0714 COMSTA0 1 R 2 52

0x0718 COMSTA1 1 R 2 53

0x071C COMSCR 1 RW 2 51

0x0720 COMIEN1 1 RW 2 54

0x0724 COMIID1 1 R 2 54

0x0728 COMADR 1 RW 2 51

0X072C COMDIV2 2 RW 2 53

Access

Type Cycle

Page

Rev. PrA | Page 22 of 78

Preliminary Technical Data ADuC702x Series

www.BDTIC.com/ADI

Access Address Name Byte

Type Cycle

I2C0 base address = 0xFFFF0800

0x0800 I2C0MSTA 1 R 2 58

0x0804 I2C0SSTA 1 R 2 58

0x0808 I2C0SRX 1 R 2 57

0x080C I2C0STX 1 W 2 57

0x0810 I2C0MRX 1 R 2 57

0x0814 I2C0MTX 1 W 2 57

0x0818 I2C0CNT 1 RW 2 57

0x081C I2C0ADR 1 RW 2 57

0x0824 I2C0BYTE 1 RW 2 57

0x0828 I2C0ALT 1 RW 2 57

0x082C I2C0CFG 1 RW 2 57

0x0830 I2C0DIVH 1 RW 2 57

0x0834 I2C0DIVL 1 RW 2 57

0x0838 I2C0ID0 1 RW 2 57

0x083C I2C0ID1 1 RW 2 57

0x0840 I2C0ID2 1 RW 2 57

0x0844 I2C0ID3 1 RW 2 57

I2C1 base address = 0xFFFF0900

0x0900 I2C1MSTA 1 R 2 58

0x0904 I2C1SSTA 1 R 2 58

0x0908 I2C1SRX 1 R 2 57

0x090C I2C1STX 1 W 2 57

0x0910 I2C1MRX 1 R 2 57

0x0914 I2C1MTX 1 W 2 57

0x0918 I2C1CNT 1 RW 2 57

0x091C I2C1ADR 1 RW 2 57

0x0924 I2C1BYTE 1 RW 2 57

0x0928 I2C1ALT 1 RW 2 57

0x092C I2C1CFG 1 RW 2 57

0x0930 I2C1DIVH 1 RW 2 57

0x0934 I2C1DIVL 1 RW 2 57

0x0938 I2C1ID0 1 RW 2 57

0x093C I2C1ID1 1 RW 2 57

0x0940 I2C1ID2 1 RW 2 57

0x0944 I2C1ID3 1 RW 2 57

SPI base address = 0xFFFF0A00

0x0A00 SPISTA 1 R 2 55

Page

0x0A04 SPIRX 1 R 2 55

Access Address Name Byte

Type Cycle

0x0A08 SPITX 1 W 2 55

0x0A0C SPIDIV 1 RW 2 55

0x0A10 SPICON 2 RW 2 55

PLA base address = 0xFFFF0B00

0x0B00 PLAELM0 2 RW 2 60

0x0B04 PLAELM1 2 RW 2 60

0x0B08 PLAELM2 2 RW 2 60

0x0B0C PLAELM3 2 RW 2 60

0x0B10 PLAELM4 2 RW 2 60

0x0B14 PLAELM5 2 RW 2 60

0x0B18 PLAELM6 2 RW 2 60

0x0B1C PLAELM7 2 RW 2 60

0x0B20 PLAELM8 2 RW 2 60

0x0B24 PLAELM9 2 RW 2 60

0x0B28 PLAELM10 2 RW 2 60

0x0B2C PLAELM11 2 RW 2 60

0x0B30 PLAELM12 2 RW 2 60

0x0B34 PLAELM13 2 RW 2 60

0x0B38 PLAELM14 2 RW 2 60

0x0B3C PLAELM15 2 RW 2 60

0x0B40 PLACLK 1 RW 2 61

0x0B44 PLAIRQ 4 RW 2 61

0x0B48 PLAADC 4 RW 2 62

0x0B4C PLADIN 4 R 2 62

0x0B50 PLADOUT 4 RW 2 62

External Memory base address = 0xFFFFF000

0xF000 XMCFG 1 RW 2

0xF010 XM0CON 1 RW 2

0xF014 XM1CON 1 RW 2

0xF018 XM2CON 1 RW 2

0xF01C XM3CON 1 RW 2

0xF020 XM0PAR 2 RW 2

0xF024 XM1PAR 2 RW 2

0xF028 XM2PAR 2 RW 2

0xF02C XM3PAR 2 RW 2

GPIO base address = 0xFFFFF400

0xF400 GP0CON 4 RW 1 48

Page

Rev. PrA | Page 23 of 78

ADuC702x Series Preliminary Technical Data

www.BDTIC.com/ADI

0xF404 GP1CON 4 RW 1 48

0xF408 GP2CON 4 RW 1 48

0xF40C GP3CON 4 RW 1 48

0xF410 GP4CON 4 RW 1 48

0xF420 GP0DAT 4 RW 1 49

0xF424 GP0SET 1 W 1 49

0xF428 GP0CLR 1 W 1 49

0xF430 GP1DAT 4 RW 1 49

0xF434 GP1SET 1 W 1 49

0xF438 GP1CLR 1 W 1 49

0xF440 GP2DAT 4 RW 1 49

0xF444 GP2SET 1 W 1 49

0xFC24 PWMDAT2 2 RW 1

The ‘Access’ column corresponds to the access time reading or
writing a MMR. It depends on the AMBA (Advanced
Microcontroller Bus Architecture) bus used to access the
peripheral. The processor has two AMBA busses, AHB
(Advanced High-performance Bus) used for system modules
and APB (Advanced Peripheral Bus) used for lower
performance peripheral.

Access Address Name Byte

Type Cycle

0xF448 GP2CLR 1 W 1 49

0xF450 GP3DAT 4 RW 1 49

0xF454 GP3SET 1 W 1 49

0xF458 GP3CLR 1 W 1 49

0xF460 GP4DAT 4 RW 1 49

0xF464 GP4SET 1 W 1 49

0xF468 GP4CLR 1 W 1 49

Flash/EE base address = 0xFFFFF800

0xF800 FEESTA 1 R 1 32

0xF804 FEEMOD 1 RW 1 32

0xF808 FEECON 1 RW 1 32

0xF80C FEEDAT 2 RW 1 32

0xF810 FEEADR 2 RW 1 32

0xF818 FEESIGN 3 R 1 32

0xF81C FEEPRO 4 RW 1 33

0xF820 FEEHIDE 4 RW 1 33

PWM base address= 0xFFFFFC00

0xFC00 PWMCON 2 RW 1 46

0xFC04 PWMSTA 2 RW 1

0xFC08 PWMDAT0 2 RW 1

0xFC0C PWMDAT1 2 RW 1

0xFC10 PWMCFG 2 RW 1

0xFC14 PWMCH0 2 RW 1 46

0xFC18 PWMCH1 2 RW 1 46

0xFC1C PWMCH2 2 RW 1 46

0xFC20 PWMEN 2 RW 1 47

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Rev. PrA | Page 24 of 78