ANALOG DEVICES ADuC7023 Service Manual

Precision Analog Microcontroller, 12-Bit Analog

I/O, ARM7TDMI MCU with Enhanced IRQ Handler

ADuC7023

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2010-2012 Analog Devices, Inc. All rights reserved.

Data Sheet

FEATURES

Analog I/O

Multichannel, 12-bit, 1 MSPS ADC

Up to 12 ADC channels
Fully differential and single-ended modes
0 V to V
12-bit voltage output DACs

On-chip voltage reference
On-chip temperature sensor
Voltage comparator

Microcontroller

ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug

Clocking options

Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz

41.78 MHz PLL with programmable divider

Memory

62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs

On-chip peripherals

2× fully I
SPI (20 Mbps in master mode, 10 Mbps in slave mode)

With 4-byte FIFO on input and output stages

Up to 20 GPIO pins

All GPIOs are 5 V tolerant

3× general-purpose timers

Programmable logic array (PLA)

16 PLA elements

16-bit, 5-channel PWM

Power

Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz

Packages and temperature range

32-lead 5 mm × 5 mm LFCSP
40-lead LFCSP

Fully specified for −40°C to +125°C operation
Tools

Low cost QuickStart development system
Full third-party support

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

analog input range

REF

4 DAC outputs available

2

C-compatible channels

Watchdog timer (WDT)

APPLICATIONS

Optical networking
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems

GENERAL DESCRIPTION

The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data
acquisition system, incorporating high performance multichannel
ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip.

The ADC consists of up to 12 single-ended inputs. An additional four
inputs are available but are multiplexed with the four DAC output
pins. The ADC can operate in single-ended or differential input modes.
The ADC input voltage is 0 V to V

temperature sensor, and voltage comparator complete the ADC
peripheral set.

The DAC output range is programmable to one of two voltage ranges.
The DAC outputs have an enhanced feature of being able to retain
their output voltage during a watchdog or software reset sequence.

The devices operate from an on-chip oscillator and a PLL,
generating an internal high frequency clock of 41.78 MHz. This
clock is routed through a programmable clock divider from which
the MCU core clock operating frequency is generated. The
microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC
machine that offers up to 41 MIPS peak performance. Eight
kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE
memory are provided on chip. The ARM7TDMI core views all
memory and registers as a single linear array.

The ADuC7023 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt levels
are supported.

On-chip factory firmware supports in-circuit download via the I
serial interface port, and nonintrusive emulation is supported via
the JTAG interface. These features are incorporated into a low cost
QuickStart™ development system supporting this MicroConverter®
family. The part contains a 16-bit PWM with five output signals.

For communication purposes, the part contains 2 × I2C channels that
can be individually configured for master or slave mode. An SPI
interface supporting both master and slave modes is also provided.

The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. The ADuC7023 is
available in either a 32-lead or 40-lead LFCSP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

. A low drift band gap reference,

REF

www.analog.com

2

C

ADuC7023 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Timing Specifications .................................................................. 8

Absolute Maximum Ratings .......................................................... 13

ESD Caution ................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 17

Terminology .................................................................................... 18

ADC Specifications .................................................................... 18

DAC Specifications..................................................................... 18

Overview of the ARM7TDMI Core ............................................. 19

Thumb Mode (T) ........................................................................ 19

Long Multiply (M) ...................................................................... 19

EmbeddedICE (I) ....................................................................... 19

Exceptions ................................................................................... 19

ARM Registers ............................................................................ 19

Interrupt Latency ........................................................................ 20

Memory Organization ................................................................... 21

Memory Access ........................................................................... 21

Flash/EE Memory ....................................................................... 21

SRAM ........................................................................................... 21

Memory Mapped Registers ....................................................... 21

ADC Circuit Overview .................................................................. 28

Transfer Function ....................................................................... 28

Typ i cal O p e ration ....................................................................... 29

MMR Interface ............................................................................ 29

Converter Operation .................................................................. 32

Driving the Analog Inputs ........................................................ 33

Calibration ................................................................................... 33

Temperature Sensor ................................................................... 34

Band Gap Reference ................................................................... 35

Nonvolatile Flash/EE Memory ..................................................... 36

Programming .............................................................................. 36

Security ........................................................................................ 37

Rev. C | Page 2 of 96

Flash/EE Control Interface ....................................................... 37

Execution Time from SRAM and Flash/EE ............................ 40

Reset and Remap ........................................................................ 40

Other Analog Peripherals .............................................................. 43

DAC .............................................................................................. 43

Power Supply Monitor ............................................................... 45

Comparator ................................................................................. 45

Oscillator and PLL—Power Control ........................................ 47

Digital Peripherals .......................................................................... 50

General-Purpose Input/Output................................................ 50

Serial Peripheral Interface ......................................................... 53

I2C ..................................................................................................... 58

Configuring External Pins for I2C Functionality ................... 58

Serial Clock Generation ............................................................ 58

I2C Bus Addresses ....................................................................... 58

I2C Registers ................................................................................ 59

Programmable Logic Array (PLA)........................................... 66

Pulse-Width Modulator ................................................................. 70

Pulse-Width Modulator General Overview ........................... 70

Processor Reference Peripherals ................................................... 75

Interrupt System ......................................................................... 75

IRQ ............................................................................................... 75

Fast Interrupt Request (FIQ) .................................................... 76

Vectored Interrupt Controller (VIC) ....................................... 77

Timers .......................................................................................... 82

Hardware Design Considerations ................................................... 87

Power Supplies ............................................................................. 87

Grounding and Board Layout Recommendations ................. 88

Clock Oscillator .......................................................................... 88

Power-On Reset Operation ....................................................... 89

Typical System Configuration .................................................. 90

Development Tools......................................................................... 91

PC-Based Tools ........................................................................... 91

In-Circuit I2C Downloader ....................................................... 91

Outline Dimensions ....................................................................... 92

Ordering Guide .......................................................................... 93

Data Sheet ADuC7023

REVISION HISTORY

5/12—Rev. B to Rev. C

Changed SDATA to SDA and SCLK to SCL, Table 2; SDATA to
SDA and SCLK to SCL, Table 3; and SDATA to SDA and SCLK

to SCL, Figure 2 ................................................................................. 8

Changes to Figure 7, Figure 8, and Table 9 .................................. 14

Changed SCLK to SCL, Table 17 ................................................... 25

Changed SCLK to SCL, Table 18 ................................................... 26

Changes to Bit 6, Table 24 and 4 to 0, Description Column,

Tabl e 25 ............................................................................................. 30

Changed Reference in REFCON Register Section from Table 22

to Table 30 ........................................................................................ 35

Added Note 1 to Table 5 3 ............................................................... 49

Changes to Note 1, Table 55 ........................................................... 50

Changed SPICLK (Serial Clock I/O) Pin Section to SCLK

(Serial Clock I/O) Pin Section ....................................................... 53

Changed SPICLK to SCLK in Serial Peripheral Interface Section

and in SCLK (Serial Clock I/O) Pin Section ............................... 53

Changes to Table 79 ........................................................................ 68

Changes to Timers Section ............................................................ 82

Added Hours, Minutes, Seconds, and 1/128 Format Section and

Table 101 ........................................................................................... 82

Changes to T0LD Register Section and T1LD Register Section .... 83

Changes to T2LD Register Section ........................................................ 85

Updated Outline Dimensions ........................................................ 92

Changes to Ordering Guide ........................................................... 93

7/10—Rev. A to Rev. B

Changes to Temperature Sensor Parameter in Table 1................. 6

Change to Table 10 and changes to Table 11 ............................... 23

Changes to Table 12 and Table 13 ................................................. 24

Changes to Table 16 and Table 17 ................................................. 25

Changes to Table 18 ........................................................................ 26

Change to Table 21 and changes to Table 22 ............................... 27

Changes to Table 24 ........................................................................ 29

Changes to ADCGN Register and ADCOF Register Sections . 32

Changes to Temperature Sensor Section ..................................... 34

Changes to Table 29 ........................................................................ 35

Change to REMAP Register and RSTCLR Register Sections ... 41
Change to RSTKEY1 Register and RSTKEY2 Register

Sections ............................................................................................. 42

Changes to Oscillator and PLL—Power Control Section .......... 48

Changes to General-Purpose Input/Output Section .................. 51

Changes to Serial Peripheral Interface Section ........................... 53

Changes to Table 75 ........................................................................ 67

Changes to Table 83 and Pulse-Width Modulator General

Overview Section ............................................................................ 70

Changes to Table 84 ........................................................................ 71

Change to Table 85 .......................................................................... 72

Change to FIQSTAN Register Section ......................................... 81

Change to T2CLRI Register Section ............................................. 85

6/10—Rev. 0 to Rev. A

Changes to Temperature Sensor Parameter in Table 1 ................ 6

Changes to Table 24 ........................................................................ 29

Changes to Temperature Sensor Section ..................................... 34

Changes to DACBKEY0 Register Section and to Table 43 ........ 47

Changes to Ordering Guide ........................................................... 93

1/10—Revision 0: Initial Version

Rev. C | Page 3 of 96

ADuC7023 Data Sheet

08675-001

ADuC7023

40-LEAD LFCSP

DAC0

DAC1

DAC2

DAC3

ADC0

XCLKI

XCLKO

RST

V

REF

ADC12

ADC2/CMP0

ADC3/CMP1

CMP

OUT

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

VECTORED
INTERRUPT

CONTROLLER

1MSPS

12-BIT ADC

TEMP

SENSOR

BAND GAP

REF

MUX

OSC

AND PLL

PSM

POR

ARM7TDMI-BAS E D M CU WITH

ADDITIO NAL PERIPHERAL S

PLA

3 GENERAL-

PURPOSE TIMERS

2k × 32 SRAM

31k × 16 FLASH/E E P ROM

SPI, 2 × I

2

C

GPIO

PWM

JTAG

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. C | Page 4 of 96

Data Sheet ADuC7023

3, 4

ON-CHIP VOLTAGE REFERENCE

0.47 µF from V

to AGND

Offset Error

±15 mV

2.5 V internal reference

Gain Error10

±1 %

Gain Error Mismatch

0.1 %

% of full scale on DAC0

SPECIFICATIONS

AVDD = IOVDD = 2.7 V to 3.6 V, V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and f

ADC Power-Up Time 5 μs
DC Accuracy

Resolution 12 Bits
Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference
±1.0 LSB 1.0 V external reference

Differential Nonlinearity
+0.7/−0.6 LSB 1.0 V external reference
DC Code Distribution 1 LSB ADC input is a dc voltage

ENDPOINT ERRORS

Offset Error ±1 ±2 LSB
Offset Error Match ±1 LSB
Gain Error ±2 LSB
Gain Error Match ±1 LSB

DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, f

Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components
Total Harmonic Distortion (THD) −78 dB
Peak Harmonic or Spurious Noise −75 dB
Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels

ANALOG INPUT

Input Voltage Ranges

Differential Mode VCM ± V

Single-Ended Mode 0 to V
Leakage Current ±1 ±6 µA
Input Capacitance 20 pF During ADC acquisition

Output Voltage 2.5 V
Accuracy ±4 mV TA = 25°C
Reference Temperature Coefficient ±15 ppm/°C
Power Supply Rejection Ratio 75 dB
Output Impedance 51 Ω TA = 25°C
Internal V

EXTERNAL REFERENCE INPUT

Input Voltage Range 0.625 AVDD V

DAC CHANNEL SPECIFICATIONS

DC Accuracy7 RL = 5 kΩ, CL = 100 pF

Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Offset Error ±15 mV 2.5 V internal reference
Gain Error8 ±1 %
Gain Error Mismatch 0.1 % % of full scale on DAC0

DC Accuracy9 RL = 1 kΩ, CL = 100 pF

Resolution 12 Bits
Relative Accuracy ±2.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

1, 2

5

Power-On Time 1 ms

REF

= 2.5 V internal reference, f

REF

= 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.

CORE

±0.5 +1/−0.9 LSB 2.5 V internal reference

/26 V

REF

V

REF

REF

SAMPLE

/2

ADC

= 1 MSPS

ANALOG OUTPUTS

Output Voltage Range 1 0 to 2.5 V V
Output Voltage Range 2 0 to AVDD V
Output Impedance 2 Ω

range: AGND to AVDD

REF

Rev. C | Page 5 of 96

ADuC7023 Data Sheet

Input Bias Current

1

µA

Input Capacitance

7

pF

4, 6

Hysteresis can be turned on or off via the CMPHYST bit

V

, Input High Voltage

2.0 V

Parameter Min Typ Max Unit Test Conditions/Comments

DAC IN OP AMP MODE

DAC Output Buffer in Op Amp Mode
Input Offset Voltage ±0.25 mV
Input Offset Voltage Drift 8 µV/°C
Input offset Current 0.3 nA
Input Bias Current 0.4 nA
Gain 80 dB 5 kΩ load
Unity-Gain Frequency 5 MHz RL = 5 kΩ, CL = 100 pF
CMRR 80 dB
Settling Time 10 µs RL = 5 kΩ, CL = 100 pF
Output Slew Rate 1.5 V/µs RL = 5 kΩ, CL = 100 pF
PSRR 75 dB

DAC AC CHARACTERISTICS

Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch Energy ±20 nV-sec

COMPARATOR

Input Offset Voltage ±10 mV

Input Voltage Range AGND AVDD – 1.2 V

1 LSB change at major carry (where maximum number of
bits simultaneously change in the DACxDAT register)

Hysteresis

2 15 mV

in the CMPCON register

Response Time 3 µs 100 mV overdrive and configured with CMPRES = 11

TEMPERATURE SENSOR Indicates die temperature

Voltage Output at 25°C 1.369 V
Voltage TC 4.42 mV/°C
Accuracy with No Calibration ±3 °C
Accuracy with One Point Calibration

±1.5 °C

Using Contents of TEMPREF Register

θJA Thermal Impedance

40-Lead LFCSP 26 °C/W
32-Lead LFCSP 32.5 °C/W

POWER SUPPLY MONITOR (PSM)

IOVDD Trip Point Selection 2.79 V One trip point

Power Supply Trip Point Accuracy ±2 % Of the selected nominal trip point voltage
POWER-ON RESET 2.41 V
WATCHDOG TIMER (WDT)

Timeout Period

0 512 sec

FLASH/EE MEMORY

Endurance11 10,000 Cycles

Data Retention12 20 Years TJ = 85°C
DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO

Logic 1 Input Current ±0.2 ±1 µA VIH = VDD or VIH = 5 V

Logic 0 Input Current −40 −60 µA VIL = 0 V; except TDI

−80 −120 µA VIL = 0 V; TDI

Input Capacitance 10 pF
LOGIC INPUTS4 All logic inputs excluding XCLKI

V

, Input Low Voltage 0.8 V

INL

INH

LOGIC OUTPUTS All digital outputs excluding XCLKO

VOH, Output High Voltage 2.4 V I

VOL, Output Low Voltage13 0.4 V I

SOUR CE

= 1.6 mA

SINK

= 1.6 mA

CRYSTAL INPUTS XCLKI AND XCLKO

Logic Inputs, XCLKI Only

V

, Input Low Voltage 1.1 V

INL

V

, Input High Voltage 1.7 V

INH

XCLKI Input Capacitance 20 pF

XCLKO Output Capacitance 20 pF

Rev. C | Page 6 of 96

Data Sheet ADuC7023

Analog Power Supply Currents

AVDD Current

200 µA

ADC in idle mode

Parameter Min Typ Max Unit Test Conditions/Comments

INTERNAL OSCILLATOR 32.768 kHz
±3 %
MCU CLOCK RATE

From 32 kHz Internal Oscillator 326 kHz CD = 7
From 32 kHz External Crystal 41.78 MHz CD = 0
Using an External Clock 0.05 44 MHz TA = 85°C

0.05 41.78 MHz TA = 125°C

START-UP TIME Core clock = 41.78 MHz

At Power-On 66 ms
From Pause/Nap Mode 24 ns CD = 0

3.07 µs CD = 7
From Sleep Mode 1.58 ms
From Stop Mode 1.7 ms

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay 12 ns From input pin to output pin
Element Propagation Delay 2.5 ns

POWER REQUIREMENTS

Power Supply Voltage Range

AVDD to AGND and IOVDD to DGND 2.7 3.6 V

Digital Power Supply Current

IOVDD Current in Normal Mode Code executing from Flash/EE

8.5 10 mA CD = 7
11 15 mA CD = 3
28 35 mA CD = 0 (41.78 MHz clock)

IOVDD Current in Pause Mode 14 20 mA CD = 0 (41.78 MHz clock)
IOVDD Current in Sleep Mode
230 650 µA TA = 125°C

Additional Power Supply Currents

ADC 1.4 mA At 1 MSPS

0.7 mA At 62.5 kSPS
DAC 400 µA Per DAC

ESD TESTS 2.5 V reference, TA = 25°C

HBM Passed 3 kV
FICDM Passed 1.0 kV

1

All ADC channel specifications are guaranteed during normal microcontroller core operation.

2

Apply to all ADC input channels.

3

Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).

4

Not production tested but supported by design and/or characterization data on production release.

5

Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC

system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).

6

The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.

7

DAC linearity is calculated using a reduced code range of 100 to 3995.

8

DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V

9

DAC linearity is calculated using a reduced code range of 100 to 3995.

10

DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V

11

Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

12

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

13

Test carried out with a maximum of eight I/Os set to a low output level.

14

Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with

3.6 V supply, and sleep mode with 3.6 V supply.

15

IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.

14, 15

.

REF

.

REF

Rev. C | Page 7 of 96

ADuC7023 Data Sheet

Parameter

Description

Min

Max

Typ

Unit

tH

SCL high pulse width

100 1140

ns

Parameter

Description

Min

Max

Unit

08675-002

SDA (I/O)

MSB LSB ACK MSB

1982–71

P S S(R)

t

R

t

F

t

RSU

t

DSU

t

DSU

t

PSU

t

BUF

t

H

t

F

t

R

t

DHD

t

DHD

t

SHD

t

SUP

t

L

t

SUP

REPEATED

START

START

CONDITION

STOP

CONDITION

SCL (I)

TIMING SPECIFICATIONS

Table 2. I2C Timing in Fast Mode (400 kHz)

Slave Master

tL SCL low pulse width 200 1360 ns

t

Start condition hold time 300 ns

SHD

t

Data setup time 100 740 ns

DSU

t

Data hold time 0 400 ns

DHD

t

Setup time for repeated start 100 ns

RSU

t

Stop condition setup time 100 800 ns

PSU

t

Bus-free time between a stop condition and a start condition 1.3 µs

BUF

tR Rise time for both SCL and SDA 300 200 ns
tF Fall time for both SCL and SDA 300 ns

2

Table 3. I

Slave

tL SCL low pulse width 4.7 µs
tH SCL high pulse width 4.0 ns
t

SHD

t

DSU

t

DHD

t

RSU

t

PSU

t

BUF

tR Rise time for both SCL and SDA 1 µs
tF Fall time for both SCL and SDA 300 ns

C Timing in Standard Mode (100 kHz)

Start condition hold time 4.0 µs
Data setup time 250 ns

Data hold time 0 3.45 µs
Setup time for repeated start 4.7 µs
Stop condition setup time 4.0 µs
Bus-free time between a stop condition and a start condition 4.7 µs

2

Figure 2. I

C-Compatible Interface Timing

Rev. C | Page 8 of 96

Data Sheet ADuC7023

08675-003

MOSI

MSB BIT 6 TO BIT 1 LSB

MISO MSB IN BIT 6 TO BIT 1 LSB IN

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

t

SF

t

SR

t

SL

t

SH

t

DAV

t

DSU

t

DHD

t

DF

t

DR

Table 4. SPI Master Mode Timing (Phase Mode = 1)

Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge1 1 × t

DSU

t

Data input hold time after SCLK edge1 2 × t

DHD

ns

UCLK

ns

UCLK

tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

ns

UCLK

ns

UCLK

Figure 3. SPI Master Mode Timing (Phase Mode = 1)

Rev. C | Page 9 of 96

ADuC7023 Data Sheet

tSF

SCLK fall time

5 12.5

ns

08675-004

MSB BIT 6 TO BIT 1 LSB

MSB IN BIT 6 TO BIT 1 LSB IN

MOSI

MISO

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

t

SF

t

SR

t

SL

t

DAV

t

SH

t

DF

t

DR

t

DOSU

t

DSU

t

DHD

Table 5. SPI Master Mode Timing (Phase Mode = 0)

Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data output setup before SCLK edge 75 ns

DOSU

t

Data input setup time before SCLK edge1 1 × t

DSU

t

Data input hold time after SCLK edge1 2 × t

DHD

ns

UCLK

ns

UCLK

tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

ns

UCLK

ns

UCLK

Figure 4. SPI Master Mode Timing (Phase Mode = 0)

Rev. C | Page 10 of 96

Data Sheet ADuC7023

tDF

Data output fall time

5 12.5

ns

08675-005

MOSI

MISO

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

t

SF

t

SFS

t

SR

t

SL

t

DAV

t

SH

t

DF

t

DR

t

DSU

t

DHD

SS

MSB BIT 6 TO BIT 1 LSB

MSB IN BIT 6 TO BIT 1 LSB IN

t

SS

Table 6. SPI Slave Mode Timing (Phase Mode = 1)

Parameter Description Min Typ Max Unit
tSS

tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge1 1 × t

DSU

t

Data input hold time after SCLK edge1 2 × t

DHD

tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
t

SFS

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

to SCLK edge 200 ns

SS

ns

UCLK

ns

UCLK

ns

UCLK

ns

UCLK

high after SCLK edge 0 ns

SS

Figure 5. SPI Slave Mode Timing (Phase Mode = 1)

Rev. C | Page 11 of 96

ADuC7023 Data Sheet

tDF

Data output fall time

5 12.5

ns

08675-006

MSB IN BIT 6 TO BIT 1 LSB IN

MSB BIT 6 TO BIT 1 LSB

MOSI

MISO

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

t

SF

t

SFS

t

SR

t

SL

t

DAV

t

SH

t

DF

t

DR

t

DSU

t

DOCS

t

DHD

SS

t

SS

Table 7. SPI Slave Mode Timing (Phase Mode = 0)

Parameter Description Min Typ Max Unit

tSS

tSL SCLK low pulse width1 (SPIDIV + 1) × t
tSH SCLK high pulse width1 (SPIDIV + 1) × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge1 1 × t

DSU

t

Data input hold time after SCLK edge1 2 × t

DHD

tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
t

Data output valid after SS edge 25 ns

DOCS

t

SFS

1

t

= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

UCLK

to SCLK edge 200 ns

SS

ns

UCLK

ns

UCLK

ns

UCLK

ns

UCLK

high after SCLK edge 0 ns

SS

Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Rev. C | Page 12 of 96

Data Sheet ADuC7023

Analog Inputs to AGND

−0.3 V to AVDD + 0.3 V

θJA Thermal Impedance

ABSOLUTE MAXIMUM RATINGS

AGND = GND

Table 8.

Parameter Rating

AVDD to IOVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
IOVDD to DGND, AVDD to AGND −0.3 V to +6 V
Digital Input Voltage to DGND −0.3 V to +5.3 V
Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V
V

to AGND −0.3 V to AVDD + 0.3 V

REF

Analog Outputs to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C

40-Lead LFCSP 26°C/W
32-Lead LFCSP 32.5°C/W

Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS Compliant Assemblies

(20 sec to 40 sec)

, TA = 25°C, unless otherwise noted.

REF

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Rev. C | Page 13 of 96

ADuC7023 Data Sheet

NOTES

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECT E D TO AGND OR LEFT FLOATING.

08675-048

1

AV

DD

2

GND

REF

3DAC0
4DAC1
5DAC2
6DAC3
7P1.4/ADC10/PLAO[3]
8

P2.0/ADC12/PWM4/PLAI[7]

9

10

P0.5/SDA0/PLAI[1]/COMP

OUT

23 RTCK

24

TMS

25 P0.0/nTRST/ADC

BUSY

PLAI[8]/BM

26

P0.1/PLAI[9]/TDO

27 P0.2/PLAO[8]/TDI

28 P0.3/PLAO[9]/TCK

29

P1.5/ADC6/PWM

TRIPINPUT

/PLAO[4]

30

P2.2/ADC7/SYNC/PLAO[6]

22 XCLKO
21 XCLKI

11

P0.6/MISO/SCL1/PLAI[2]

12

P0.7/MOSI/SDA1/PLAO[0]

13

P1.0/SPICLK/PWM0/PLAO[1]

15

P1.6/PWM2/SCL1/PLAI[5]

17

DGND

16

P1.7/PWM3/SDA1/PLAI[6]

18

IOV

DD

19

LV

DD

20

33

P1.2/ADC4/IRQ2/PLAI[3]/ECLK

34

P1.3/ADC5/IRQ3/PLAI[4]

35

V

REF

36

ADC0

37

ADC1

38

ADC2/CMP0

39

ADC3/CMP1

40

AGND

32

P2.4/ADC9/PLAI[10]

31

P2.3/ADC8/PLAO[7]

ADuC7023

TOP VIEW

(Not to Scale)

RST

14

P1.1/SS/IRQ1/PWM1/PLAO[2]/TI

P0.4/IRQ0/SCL0/PLAI[0]/CONV

START

08675-007

AV

DD

GND

REF

DAC0
DAC1
DAC2
DAC3

P0.5/SDA0/PLAI[1]/COMP

OUT

P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADC

BUSY

/PLAI[8]/BM
TMS
RTCK
XCLKO
XCLKI

P0.6/MISO/SCL1/PLAI[2]

P0.7/MOSI/SDA1/PLAO[0]

P1.0/SPICLK/PWM0/PLAO[1]

DGND

IOV

DD

LV

DD

AGND

ADC3/CMP1

ADC2/CMP0

ADC1

ADC0

V

REF

P1.3/ADC5/IRQ3/PLAI[4]

P1.2/ADC4/IRQ2/PLAI[3]/ECLK

RST

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

9

10111213141516

32313029282726

25

ADuC7023

TOP VIEW

(Not to Scal e)

NOTES

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.

P1.1/SS/IRQ1/PWM1/PLAO[2]/T1

P0.4/IRQ0/SCL0/PLAI[0]/CONV

START

32

N/A

P2.4/ADC9/PLAI[10]

General-Purpose Input and Output Port 2.4/ADC Single-Ended or

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions

40-LFCSP 32-LFCSP Mnemonic Description

0 0 Exposed Paddle Exposed Pad. The paddle needs to be soldered and either connected to

36 28 ADC0 Single-Ended or Differential Analog Input 0.
37 29 ADC1 Single-Ended or Differential Analog Input 1.
38 30 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
39 31 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.

31 N/A P2.3/ADC8/PLAO[7] General-Purpose Input and Output Port 2.3/ADC Single-Ended or

30 N/A P2.2/ADC7/SYNC/PLAO[6] General-Purpose Input and Output Port 2.2/ADC Single-Ended or

8 N/A P2.0/ADC12/PWM4/PLAI[7] General-Purpose Input and Output Port 2.0/ADC Single-Ended or

2 2 GND

3 3 DAC0 DAC0 Voltage Output or ADC Input.
4 4 DAC1 DAC1 Voltage Output or ADC Input.

Figure 7. 40-Lead Pin Configuration

Pin No.

Ground Voltage Reference for the ADC. For optimal performance, the

REF

Figure 8. 32-Lead Pin Configuration

AGND or left floating.

Differential Analog Input/Programmable Logic Array Input Element 10.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.

Differential Analog Input 8/Programmable Logic Array Output Element 7.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, pull-up resistor should be
disabled manually.

Differential Analog Input 7/PWM Sync /Programmable Logic Array Output
Element 6. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, pull-up resistor should
be disabled manually.

Differential Analog Input 12/PWM Output 4/Programmable Logic Array
Input Element 7. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled. When used as an ADC input, it is not
possible to disable the internal pull-up resister. This means that this pin
has a higher leakage current value than other analog input pins.

analog power supply should be separated from DGND.

Rev. C | Page 14 of 96

Data Sheet ADuC7023

Pin No.

40-LFCSP 32-LFCSP Mnemonic Description

5 5 DAC2 DAC2 Voltage Output
6 6 DAC3 DAC3 Voltage Output
24 20 TMS Test Mode Select, JTAG Test Port Input. Debug and download access.

This pin has an internal pull-up resistor to IOV
pull-up resistor is also required to ensure the part does not enter an
erroneous state.

25 21 P0.0/nTRST/ADC

/PLAI[8]/BM This is a multifunction pin as follows:

BUSY

General-Purpose Input and Output Port 0.0. By default, this pin is
configured as GPIO.
JTAG Reset Input. Debug and download access. If this pin is held low, JTAG
access is not possible because the JTAG interface is held in reset and
P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC Busy Signal.

Programmable Logic Array Input Element 8.
Boot Mode Entry Pin. The ADuC7023 enters I2C download mode if BM is
low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023
executes code if BM is pulled high at reset or if BM is low at reset with a
flash address 0x80014 not equal to 0xFFFFFFFFF.

26 22 P0.1/PLAI[9]/TDO The default value of this pin depends on the level of P0.0/BM. If P0.0/

BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data output pin. This is a multifunction pin as
follows:
General-Purpose Input and Output Port 0.1.
Programmable Logic Array Input Element 9.
Test Data Out, JTAG Test Port Output. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin can not be
changed.

27 23 P0.2/PLAO[8]/TDI The default value of this pin depends on the level of P0.0/BM. If P0.0/

BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data input pin. This is a multifunction pin as
follows:
General-Purpose Input and Output Port 0.2.
Programmable Logic Array Output Element 8.
Test Data In, JTAG Test Port Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed.

28 24 P0.3/PLAO[9]/TCK The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =

0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data clock pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.3.
Programmable Logic Array Output Element 9.
Test Clock, JTAG Test Port Clock Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code
and the GP0CON/GP0DAT register bits affecting this pin must not be

changed.
17 13 DGND Digital Ground.
18 14 IOVDD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
19 15 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be

connected to a 0.47 µF capacitor to DGND only.
20 16

Reset Input, Active Low.

RST

23 19 RTCK Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is an

output signal from the JTAG controller. If using a 20-lead JTAG header,

connect to Pin 11.

. In some cases an external

DD

Rev. C | Page 15 of 96

ADuC7023 Data Sheet

13

11

P1.0/SCLK/PWM0/PLAO[1]

General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/

Pin No.

40-LFCSP 32-LFCSP Mnemonic Description

9 7 P0.4/IRQ0/SCL0/PLAI[0]/CONV General-Purpose Input and Output Port 0.4/External Interrupt Request

0//I2C0 Clock Signal/Programmable Logic Array Input Element 0/ADC
External Convert Start. By default, this pin is configured as a digital input
with a weak pull-up resistor enabled.

10 8 P0.5/SDA0/PLAI[1]/COMP

11 9 P0.6/MISO/SCL1/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On

12 10 P0.7/MOSI/SDA1/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data

21 17 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock

22 18 XCLKO Output from the Crystal Oscillator Inverter. Leave unconnected if unused.
16 N/A P1.7/PWM3/SDA1/PLAI[6] General-Purpose Input and Output Port 1.7/PWM Output 3/I2C Data

15 N/A P1.6/PWM2/SCL1/PLAI[5] General-Purpose Input and Output Port 1.6/PWM Output 2/I2C Clock

29 N/A P1.5/ADC6/PWM

TRIPINPUT

7 N/A P1.4/ADC10/PLAO[3] General-Purpose Input and Output Port 1.4/ADC Single-Ended or

34 26 P1.3/ADC5/IRQ3/PLAI[4] General-Purpose Input and Output Port 1.3/ADC Single-Ended or

33 25 P1.2/ADC4/IRQ2/PLAI[3]/ECLK/ General-Purpose Input and Output Port 1.2/ADC Single-Ended or

14 12 P1.1/SS/IRQ1/PWM1/PLAO[2]/T1 General-Purpose Input and Output Port 1.1/SPI Interface Slave Select

General-Purpose Input and Output Port 0.5/I2C0 Data Signal/Programmable

OUT

Logic Array Input Element 1/Voltage Comparator Output. By default, this
pin is configured as a digital input with a weak pull-up resistor enabled.

32-Lead Package/Programmable Logic Array Input Element 2. By default,
this pin is configured as a digital input with a weak pull-up resistor
enabled.

Signal On 32-Lead Package/Programmable Logic Array Output Element 0.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.

Generator Circuits. Connect to DGND if unused.

Signal/Programmable Logic Array Input Element 6. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.

Signal/Programmable Logic Array Input Element 5. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.

/PLAO[4] General-Purpose Input and Output Port 1.5/ADC Single-Ended or

Differential Analog Input 6/PWM

/Programmable Logic Array Output

TRIPINPUT

Element 4. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, the pull-up resistor
should be disabled manually.

Differential Analog Input 10/Programmable Logic Array Output Element 3.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.

Differential Analog Input 5/External Interrupt Request 3/Programmable
Logic Array Input Element 4.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.

Differential Analog Input 4/External Interrupt Request 2/Programmable
Logic Array Input Element 3/Input-Output for External Clock.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.

(Active Low)/External Interrupt Request 1/PWM Output 1/Programmable
Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.

35 27 V

2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor

REF

40 32 AGND Analog Ground. Ground reference point for the analog circuitry.
1 1 AVDD 3.3 V Analog Power.

PWM Output 0/Programmable Logic Array Output Element 1. By default,
this pin is configured as a digital input with a weak pull-up resistor
enabled.

when using the internal reference.

Rev. C | Page 16 of 96

Data Sheet ADuC7023

0.5

0.6

0.4

0.3

0.2

0.1
0

–0.1
–0.2
–0.3
–0.4

0 500 1000 1500 2000 2500 3000 3500 4095

ADC CODES

DNL (LSB)

08675-049

SAMPLING RATE = 950kSPS
WORST CAS E P OSITIV E = 0.63, CODE = 2364
WORST CAS E NE GATIVE = –0.46, CODE = 2363

0.6

0.4

0.2

0

–0.2

–0.6

–0.4

–0.8

–1.0

0 500 1000

1500 2000 2500 3000 3500 4095

ADC CODES

INL (LSB)

08675-050

SAMPLING RATE = 950kSPS
WORST CAS E P OSITIV E = 0.57, CODE = 4063
WORST CAS E NE GATIVE = –0.90, CODE = 3356

0.6

0.5

0.4

0.3

0.2

0.1

–0.1

0

–0.2
–0.3
–0.4
–0.5
–0.6

0 500 1000 1500 2000 2500 3000 3500 4095

ADC CODES

DNL (LSB)

08675-051

SAMPLING RATE = 950kSPS
WORST CAS E P OSITIV E = 0.64, CODE = 3583
WORST CAS E NE GATIVE = –0.61, CODE = 1830

1.2

1.0

0.8

0.6

0.4

0.2

–0.2

0

–0.4
–0.6

–0.8
–1.0

0 500 1000 1500 2000 2500 3000 3500 4095

ADC CODES

INL (LSB)

08675-052

SAMPLING RATE = 950kSPS
WORST CAS E P OSITIV E = 1.09, CODE = 4032
WORST CAS E NE GATIVE = –0.98, CODE = 3422

20

0

–20

–40

–60

–80

–100

–200

–400

0 20,000 40,000 60,000 80,000 104,400

FREQUENCY ( Hz )

SINAD, THD AND P HS N OF ADC (dB)

08675-053

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. Typical DNL, f

Figure 10. Typical INL, f

= 950 kSPS, Internal Reference Used

ADC

= 950 kSPS, Internal Reference Used

ADC

Figure 12. Typical INL, f

= 950 kSPS, External 1.0 V Reference Used

ADC

Figure 13. SINAD, THD, and PHSN of ADC , Internal 2.5 V Reference Used

Figure 11. Typical DNL, f

ADC

= 950 kSPS, External 1.0 V Reference Used

Rev. C | Page 17 of 96

ADuC7023 Data Sheet

TERMINOLOGY

ADC SPECIFICATIONS

Integral Nonlinearity (INL)

The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition, and full scale, a point
½ LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.

Gain Error

The deviation of the last code transition from the ideal AIN
voltage (full scale − 1.5 LSB) after the offset error has been
adjusted out.

Signal to (Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.

The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

The ratio of the rms sum of the harmonics to the fundamental.

DAC SPECIFICATIONS

Relative Accuracy

Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.

Voltage Output Settling Time

The amount of time it takes the output to settle to within a
1 LSB level for a full-scale input change.

Rev. C | Page 18 of 96

08675-008

USABLE IN USER M ODE
SYSTEM MODES ONLY

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

R8_FIQ

R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ

R13_UND
R14_UND

R0
R1
R2
R3
R4
R5
R6
R7
R8

R9
R10
R11
R12
R13
R14

R15 (PC)

R13_IRQ
R14_IRQ

R13_ABT
R14_ABT

R13_SVC
R14_SVC

SPSR_FIQ

CPSR

USER MODE

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

Data Sheet ADuC7023

OVERVIEW OF THE ARM7TDMI CORE

The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.

The ARM7TDMI is an ARM7 core with four additional features: T
support for the thumb (16-bit) instruction set, D support for
debug, M support for long multiplications, and I includes the
EmbeddedICE module to support embedded system debugging

THUMB MODE (T)

An ARM instruction is 32 bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16 bits, called the Thumb® instruction set.
Faster execution from 16-bit memory and greater code density
can usually be achieved by using the Thumb instruction set
instead of the ARM instruction set, which makes the
ARM7TDMI core particularly suitable for embedded
applications.

However, the Thumb mode has two limitations. Thumb code
typically requires more instructions for the same job. As a
result, ARM code is usually best for maximizing the
performance of time critical code. Also, the Thumb instruction
set does not include some of the instructions needed for
exception handling, which automatically switches the core to
ARM code for exception handling.

See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM Thumb instruction sets.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instruc­tions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with a 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.

EmbeddedICE (I)

EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and watch­point registers that allow code to be halted for debugging purposes.
These registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers can be inspected as well as the Flash/EE,
SRAM, and memory mapped registers.

Rev. C | Page 19 of 96

EXCEPTIONS

ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are:

• Normal interrupt or IRQ. This is provided to service

general-purpose interrupt handling of internal and
external events.

• Fast interrupt or FIQ. This is provided to service data

transfers or communication channels with low latency. FIQ
has priority over IRQ.

• Memory abort.

• Attempted execution of an undefined instruction.

• Software interrupt instruction (SWI). This can be used to

make a call to an operating system.

Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.

When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the
current program status register (CPSR) are usable. The
remaining registers are only used for system-level programming
and exception handling.

When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All excep­tion modes have replacement banked registers for the stack
pointer (R13) and the link register (R14) as represented in
Figure 14. The fast interrupt mode has more registers (R8 to R12)
for fast interrupt processing. This means the interrupt processing
can begin without the need to save or restore these registers,
and thus save critical time in the interrupt handling process.

Figure 14. Register Organization

ADuC7023 Data Sheet

More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ)
consists of the following: the longest time the request can take
to pass through the synchronizer, the time for the longest
instruction to complete (the longest instruction is an LDM) that
loads all the registers including the PC, and the time for the
data abort and FIQ entry.

At the end of this time, the ARM7TDMI executes the instruc­tion at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 µs in a
system using a continuous 41.78 MHz processor clock.

The maximum interrupt request (IRQ) latency calculation is
similar but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in thumb mode where the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.

The ARM7TDMI always runs in ARM (32-bit) mode when in
privileged modes, for example, when executing interrupt
service routines.

Rev. C | Page 20 of 96

RESERVED

MMRs

0xFFFFFFFF

0x0008FFFF

0x00011FFF

0x0000FFFF

0x00000000

0x00010000

0x00080000

0xFFFF0000

RESERVED

FLASH/EE

(FLASH/EE OR SRAM)

REMAPPABLE MEMORY SPACE

SRAM

08675-009

08675-010

BIT 31

BYTE 2

A

6
2

.
.
.

BYTE 3

B
7
3

.
.
.

BYTE 1

9
5
1

.
.
.

BYTE 0

8
4
0

.
.
.

BIT 0

32 BITS

0xFFFFFFFF

0x00000004
0x00000000

Data Sheet ADuC7023

MEMORY ORGANIZATION

The ADuC7023 incorporates two separate blocks of memory:
8 kB of SRAM and 64 kB of on-chip Flash/EE memory; 62 kB of
on-chip Flash/EE memory is available to the user, and the
remaining 2 kB are reserved for the factory configured boot
page. These two blocks are mapped as shown in Figure 15.

Figure 15. Physical Memory Map

By default, after a reset, the Flash/EE memory is mirrored at
Address 0x00000000. It is possible to remap the SRAM at
Address 0x00000000 by clearing Bit 0 of the Remap MMR.
This remap function is described in more detail in the Flash/EE
Memory section.

MEMORY ACCESS

The ARM7 core sees memory as a linear array of the 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 15.

The ADuC7023 memory organizations are configured in little
endian format, which means that the least significant byte is
located in the lowest byte address, and the most significant byte
is in the highest byte address.

Figure 16. Little Endian Format

FLASH/EE MEMORY

The total 64 kB of Flash/EE memory is organized as 32k × 16 bits;
31k × 16 bits is user space and 1 k × 16 bits is reserved for the
on-chip kernel. The page size of this Flash/EE memory is 512 bytes.

62 kilobytes of Flash/EE memory are available to the user as
code and nonvolatile data memory. There is no distinction
between data and program because ARM code shares the same
space. The real width of the Flash/EE memory is 16 bits, which
means that in ARM mode (32-bit instruction), two accesses to
the Flash/EE are necessary for each instruction fetch. It is,
therefore, recommended to use Thumb mode when executing
from Flash/EE memory for optimum access speed. The
maximum access speed for the Flash/EE memory is 41.78 MHz
in Thumb mode and 20.89 MHz in full ARM mode. More
details about Flash/EE access time are outlined later in the
Execution Time from SRAM and Flash/EE section.

SRAM

Eight kilobytes of SRAM are available to the user, organized as
2k × 32 bits, that is, two words. ARM code can run directly from
SRAM at 41.78 MHz, given that the SRAM array is configured
as a 32-bit wide memory array. More details about SRAM access
time are outlined later in the Execution Time from SRAM and
Flash/EE section.

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in Figure 17
are unoccupied or reserved locations and should not be
accessed by user software. Tabl e 10 to Ta b l e 23 show the full
MMR memory map.

The access time for reading from or writing to an MMR depends
on the advanced microcontroller bus architecture (AMBA) bus
used to access the peripheral. The processor has two AMBA
buses: advanced high performance bus (AHB) used for system
modules and advanced peripheral bus (APB) used for lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the ADuC7023
are on the APB except the Flash/EE memory and the GPIOs.

Rev. C | Page 21 of 96

FLASH CONTROL

INTERFACE

GPIO

PLA

SPI

I2C1

I2C0

DAC

ADC

BAND GAP

REFERENCE

POWER SUPPLY

MONITOR

PLL AND

OSCILLATOR CONTROL

WATCHDOG

TIMER

GENERAL-PURPOSE

TIMER

TIMER0

REMAP AND

SYSTEM CONTROL

INTERRUPT

CONTROLLER

0xFFFFFFFF

0xFFFFF820

0xFFFFF800

0xFFFFF46C

0xFFFFF400

0xFFFF0FBF

0xFFFF0F80

0xFFFF0B54

0xFFFF0B00
0xFFFF0A14
0xFFFF0A00

0xFFFF0948

0xFFFF0900
0xFFFF0848

0xFFFF0800
0xFFFF0620
0xFFFF0600
0xFFFF0538
0xFFFF0500
0xFFFF0490

0xFFFF048C

0xFFFF0448
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0370
0xFFFF0360
0xFFFF0334
0xFFFF0320
0xFFFF0310
0xFFFF0300
0xFFFF0238

0xFFFF0220

0xFFFF0140

0xFFFF0000

08675-011

PWM

ADuC7023 Data Sheet

Figure 17. Memory Mapped Registers

Rev. C | Page 22 of 96

Data Sheet ADuC7023

This register contains the subroutine address for the currently active IRQ
0x002C

RESERVED

4

R/W

0x00000000

Reserved.

0x011C

FIQVEC

4 R 0x00000000

FIQ interrupt vector.

Table 10. IRQ Address Base = 0xFFFF0000

Address Name Byte Access Type Default Value Description

0x0000 IR Q S TA 4 R 0x00000000 Active IRQ source.
0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled).
0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources.
0x000C IRQCLR 4 W MMR to disable IRQ sources.
0x0010 SWICFG 4 W Software interrupt configuration MMR.
0x0014 IRQBASE 4 R/W 0x00000000 Base address of all vectors. Points to start of a 64-byte memory block

which can contain up to 32 pointers to separate subroutine handlers.

0x001C IRQVEC 4 R 0x00000000

source.

0x0020 IRQP0 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 1

to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.

0x0024 IRQP1 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 8

to Interrupt Source 15.

0x0028 IRQP2 4 R/W 0x00000000 This register contains the interrupt priority setting for Interrupt Source 16 to

Interrupt Source 21.

0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting.
0x0034 IRQCONE 4 R/W 0x00000000 This register configures the external interrupt sources as rising edge,

falling edge, or level triggered.
0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge level triggered interrupt source.
0x003C IRQSTAN 4 R/W 0x00000000 This register indicates the priority level of an interrupt that has just

caused an interrupt exception.
0x0100 FI QSTA 4 R 0x00000000 Active FIQ source.
0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled).
0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources.
0x010C FIQCLR 4 W MMR to disable FIQ sources.

0x013C FIQSTAN 4 RW 0x00000000 This register indicates the priority level of an FIQ that has just caused an

FIQ exception.

Table 11. System Control Address Base = 0xFFFF0200

Address Name Byte Access Type Default Value1 Description

0x0220 Remap2 1 R/W 0x00 Remap control register.
0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR.
0x0234 RSTCLR 1 W 0x00 RSTCLR MMR for clearing RSTSTA register.
0x0248 RSTKEY1 1 W 0xXX 0x76 should be written to this register before writing to RSTCFG.
0x024C RSTCFG 1 R/W 0x00 This register allows the DAC and GPIO outputs to retain state after a

watchdog or software reset.

0x0250 RSTKEY2 1 W 0xXX 0xB1 should be written to this register after writing to RSTCFG.

1

N/A means not applicable.

2

Updated by kernel.

Rev. C | Page 23 of 96

ADuC7023 Data Sheet

0x0360

T2LD

2

R/W

0x0000

Timer2 load register.

0x040C

POWKEY2

2 W 0xXXXX

POWCON0 postwrite key.

Table 12. Timer Address Base = 0xFFFF0300

Address Name Byte Access Type Default Value1 Description

0x0300 T0LD 2 R/W 0x0000 Timer0 load register.
0x0304 T0VAL 2 R 0xFFFF Timer0 value register.
0x0308 T0CON 2 R/W 0x0000 Timer0 control MMR.
0x030C T0CLRI 1 W 0xXX Timer0 interrupt clear register.
0x0320 T1LD 4 R/W 0x00000000 Timer1 load register.
0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 value register
0x0328 T1CON 4 R/W 0x00000000 Timer1 control MMR.
0x032C T1CLRI 1 W 0xXX Timer1 interrupt clear register.
0x0330 T1CAP 4 R 0x00000000 Timer1 capture register.

0x0364 T2VAL 2 R 0xFFFF Timer2 value register.
0x0368 T2CON 2 R/W 0x0000 Timer2 control MMR.
0x036C T2CLRI 1 W 0xXX Timer2 interrupt clear register.

1

N/A means not applicable.

Table 13. PLL/PSM Base Address = 0xFFFF0400

Address Name Byte Access Type Default Value1 Description

0x0404 POWKEY1 2 W 0xXXXX POWCON0 prewrite key.
0x0408 POWCON0 1 R/W 0x00 Power control and core speed control register.

0x0410 PLLKEY1 2 W 0xXXXX PLLCON prewrite key.
0x0414 PLLCON 1 R/W 0x21 PLL clock source selection MMR.
0x0418 PLLKEY2 2 W 0xXXXX PLLCON postwrite key.
0x0434 POWKEY3 2 W 0xXXXX POWCON1 prewrite key.
0x0438 POWCON1 2 R/W 0x0004 Power control and core speed control register.
0x043C POWKEY4 2 W 0xXXXX POWCON1 postwrite key.
0x0440 PSMCON 2 R/W 0x0008 Power supply monitor control register.
0x0444 CMPCON 2 R/W 0x0000 Comparator control register.

1

N/A means not applicable.

Table 14. Reference Base Address = 0xFFFF0480

Address: 0x048c

Name: REFCON

Byte: 1

Access type: Read/write

Default value: 0x00

Description: Reference control register.

Table 15. ADC Address Base = 0xFFFF0500

Address Name Byte Access Type Default Value Description

0x0500 ADCCON 2 R/W 0x0600 ADC control MMR.
0x0504 ADCCP 1 R/W 0x00 ADC positive channel selection register.
0x0508 ADCCN 1 R/W 0x01 ADC negative channel selection register.
0x050C ADCSTA 1 R 0x00 ADC status MMR.
0x0510 ADCDAT 4 R 0x00000000 ADC data output MMR.
0x0514 ADCRST 1 R/W 0x00 ADC reset MMR.

Rev. C | Page 24 of 96

Data Sheet ADuC7023

0x0618

DAC3CON

1

R/W

0x00

DAC3 control MMR.

Address Name Byte Access Type Default Value Description

0x0530 ADCGN 2 R/W Factory configured ADC gain calibration MMR.
0x0534 ADCOF 2 R/W Factory configured ADC offset calibration MMR.
0x0544 TSCON 1 R/W 0x00 Temperature sensor chopping enable register.
0x0548 TEMPREF 2 R/W Factory configured Temperature sensor reference value.

Table 16. DAC Address Base = 0xFFFF0600

Address Name Byte Access Type Default Value Description

0x0600 DAC0CON 1 R/W 0x00 DAC0 control MMR.
0x0604 DAC0DAT 4 R/W 0x00000000 DAC0 data MMR.
0x0608 DAC1CON 1 R/W 0x00 DAC1 control MMR.
0x060C DAC1DAT 4 R/W 0x00000000 DAC1 data MMR.
0x0610 DAC2CON 1 R/W 0x00 DAC2 control MMR.
0x0614 DAC2DAT 4 R/W 0x00000000 DAC2 data MMR.

0x061C DAC3DAT 4 R/W 0x00000000 DAC3 data MMR.
0x0654 DACBCFG 1 R/W 0x00 DAC Configuration MMR
0x0650 DACBKEY0 2 W 0x0000 DAC Key0 MMR
0x0658 DACBKEY1 2 W 0x0000 DAC Key1 MMR

Table 17. I2C0 Base Address = 0XFFFF0800

Access

Address Name Byte

0x0800 I2C0MCON 2 R/W 0x0000 I2C0 master control register.
0x0804 I2C0MS TA 2 R 0x0000 I2C0 master status register.
0x0808 I2C0MRX 1 R 0x00 I2C0 master receive register.
0x080C I2C0MTX 1 W 0x00 I2C0 master transmit register.
0x0810 I2C0MCNT0 2 R/W 0x0000 I2C0 master read count register. Write the number of required bytes into this

0x0814 I2C0MCNT1 1 R 0x00 I2C0 master current read count register. This register contains the number of

0x0818 I2C0ADR0 1 R/W 0x00 I2C0 address byte register. Write the required slave address in here prior to

0x081C I2C0ADR1 1 R/W 0x00 I2C0 address byte register. Write the required slave address in here prior to

0x0824 I2C0DIV 2 R/W 0x1F1F I2C0 clock control register. Used to configure the SCL frequency.
0x0828 I2C0SCON 2 R/W 0x0000 I2C0 slave control register.
0x082C I2C0SSTA 2 R/W 0x0000 I2C0 slave status register.
0x0830 I2C0SRX 1 R 0x00 I2C0 slave receive register.
0x0834 I2C0STX 1 W 0x00 I2C0 slave transmit register.
0x0838 I2C0ALT 1 R/W 0x00 I2C0 hardware general call recognition register.
0x083C I2C0ID0 1 R/W 0x00 I2C0 slave ID0 register. Slave bus ID register.
0x0840 I2C0ID1 1 R/W 0x00 I2C0 slave ID1 register. Slave bus ID register.
0x0844 I2C0ID2 1 R/W 0x00 I2C0 slave ID2 register. Slave bus ID register.
0x0848 I2C0ID3 1 R/W 0x00 I2C0 slave ID3 register. Slave bus ID register.
0x084C I2C0FSTA 2 R/W 0x0000 I2C0 FIFO status register. Used in both master and slave modes.

Type

Default
Value Description

register prior to reading from a slave device.

bytes already received during a read from slave sequence.

communications.

communications. Used in 10-bit mode only.

Table 18. I2C1 Base Address = 0XFFFF0900

Address Name Byte Access Type Default Value Description

0x0900 I2C1MCON 2 R/W 0x0000 I2C1 master control register.
0x0904 I2C1MS TA 2 R 0x0000 I2C1 master status register.
0x0908 I2C1MRX 1 R 0x00 I2C1 master receive register.
0x090C I2C1MTX 1 W 0x00 I2C1 master transmit register.
0x0910 I2C1MCNT0 2 R/W 0x0000 I2C1 master read count register. Write the number of required bytes

into this register prior to reading from a slave device.

Rev. C | Page 25 of 96

ADuC7023 Data Sheet

0x091C

I2C1ADR1

1

R/W

0x00

I2C1 address byte register. Write the required slave address in here
0x0A10

SPICON

2

R/W

0x0000

SPI control MMR.

0x0B14

PLAELM5

2

R/W

0x0000

PLA Element 5 control register.

Address Name Byte Access Type Default Value Description

0x0914 I2C1MCNT1 1 R 0x00 I2C1 master current read count register. This register contains the

number of bytes already received during a read from slave sequence.

0x0918 I2C1ADR0 1 R/W 0x00 I2C1 address byte register. Write the required slave address in here

prior to communications.

prior to communications. Used in 10-bit mode only.
0x0924 I2C1DIV 2 R/W 0x1F1F I2C1 clock control register. Used to configure the SCL frequency.
0x0928 I2C1SCON 2 R/W 0x0000 I2C1 slave control register.
0x092C I2C1SSTA 2 R/W 0x0000 I2C1 slave status register.
0x0930 I2C1SRX 1 R 0x00 I2C1 slave receive register.
0x0934 I2C1STX 1 W 0x00 I2C1 slave transmit register.
0x0938 I2C1ALT 1 R/W 0x00 I2C1 hardware general call recognition register.
0x093C I2C1ID0 1 R/W 0x00 I2C1 slave ID0 register. Slave bus ID register.
0x0940 I2C1ID1 1 R/W 0x00 I2C1 slave ID1 register. Slave bus ID register.
0x0944 I2C1ID2 1 R/W 0x00 I2C1 slave ID2 register. Slave bus ID register.
0x0948 I2C1ID3 1 R/W 0x00 I2C1 slave ID3 register. Slave bus ID register.
0x094C I2C1F S TA 2 R/W 0x0000 I2C1 FIFO status register. Used in both master and slave modes.

Table 19. SPI Base Address = 0xFFFF0A00

Address Name Byte Access Type Default Value Description

0x0A00 SPISTA 2 R 0x0000 SPI status MMR.
0x0A04 SPIRX 1 R 0x00 SPI receive MMR.
0x0A08 SPITX 1 W 0xXX SPI transmit MMR.
0x0A0C SPIDIV 1 R/W 0x00 SPI baud rate select MMR.

Table 20. PLA Base Address = 0XFFFF0B00

Address Name Byte Access Type Default Value Description

0x0B00 PLAELM0 2 R/W 0x0000 PLA Element 0 control register.
0x0B04 PLAELM1 2 R/W 0x0000 PLA Element 1 control register.
0x0B08 PLAELM2 2 R/W 0x0000 PLA Element 2 control register.
0x0B0C PLAELM3 2 R/W 0x0000 PLA Element 3 control register.
0x0B10 PLAELM4 2 R/W 0x0000 PLA Element 4 control register.

0x0B18 PLAELM6 2 R/W 0x0000 PLA Element 6 control register.
0x0B1C PLAELM7 2 R/W 0x0000 PLA Element 7 control register.
0x0B20 PLAELM8 2 R/W 0x0000 PLA Element 8 control register.
0x0B24 PLAELM9 2 R/W 0x0000 PLA Element 9 control register.
0x0B28 PLAELM10 2 R/W 0x0000 PLA Element 10 control register.
0x0B2C PLAELM11 2 R/W 0x0000 PLA Element 11 control register.
0x0B30 PLAELM12 2 R/W 0x0000 PLA Element 12 control register.
0x0B34 PLAELM13 2 R/W 0x0000 PLA Element 13 control register.
0x0B38 PLAELM14 2 R/W 0x0000 PLA Element 14 control register.
0x0B3C PLAELM15 2 R/W 0x0000 PLA Element 15 control register.
0x0B40 PLACLK 1 R/W 0x00 PLA clock select register.
0x0B44 PLAIRQ 4 R/W 0x00000000 PLA interrupt control register.
0x0B48 PLAADC 4 R/W 0x00000000 PLA ADC trigger control register.
0x0B4C PLADIN 4 R/W 0x00000000 PLA data in register.
0x0B50 PLADOUT 4 R 0x00000000 PLA data out register.
0x0B54 PLALCK 1 W 0x00 PLA lock register.

Rev. C | Page 26 of 96

Data Sheet ADuC7023

PWM Control Register 1. See the

0xF404

GP1CON

4

R/W

0x00000000

GPIO Port1 control MMR.

Table 21. PWM Base Address = 0xFFFF0F80

Address Name Byte Access Type Default Value Description

0x0F80 PWMCON1 2 R/W 0x0012

Pulse-Width Modulator section for full details.
0x0F84 PWM0COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 0 and PWM Output 1.
0x0F88 PWM0COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 0 and PWM Output 1.
0x0F8C PWM0COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 0 and PWM Output 1.
0x0F90 PWM0LEN 2 R/W 0x0000 Frequency control for PWM Output 0 and PWM Output 1.
0x0F94 PWM1COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 2 and PWM Output 3.
0x0F98 PWM1COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 2 and PWM Output 3.
0x0F9C PWM1COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 2 and PWM Output 3.
0x0FA0 PWM1LEN 2 R/W 0x0000 Frequency control for PWM Output 2 and PWM Output 3.
0x0FA4 PWM2COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 4 and PWM Output 5.
0x0FA8 PWM2COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 4 and PWM Output 5.
0x0FB8 PWMCLRI 2 W 0x0000 PWM interrupt clear register. Writing any value to this register

clears a PWM interrupt source.

Table 22. GPIO Base Address = 0xFFFFF400

Address Name Byte Access Type Default Value Description

0xF400 GP0CON 4 R/W 0x00001111 GPIO Port0 control MMR.

0xF408 GP2CON 4 R/W 0x00000000 GPIO Port2 control MMR.
0xF420 GP0DAT 4 R/W 0x000000XX GPIO Port0 data control MMR.
0xF424 GP0SET 4 W 0x000000XX GPIO Port0 data set MMR.
0xF428 GP0CLR 4 W 0x000000XX GPIO Port0 data clear MMR.
0xF42C GP0PAR 4 R/W 0x22220000 GPIO Port0 pull-up disable MMR.
0xF430 GP1DAT 4 R/W 0x000000XX GPIO Port1 data control MMR.
0xF434 GP1SET 4 W 0x000000XX GPIO Port1 data set MMR.
0xF438 GP1CLR 4 W 0x000000XX GPIO Port1 data clear MMR.
0xF43C GP1PAR 4 R/W 0x22000022 GPIO Port1 pull-up disable MMR.
0xF440 GP2DAT 4 R/W 0x000000XX GPIO Port2 data control MMR.
0xF444 GP2SET 4 W 0x000000XX GPIO Port2 data set MMR.
0xF448 GP2CLR 4 W 0x000000XX GPIO Port2 data clear MMR.
0xF44C GP2PAR 4 R/W 0x00000000 GPIO Port2 pull-up disable MMR.

Table 23. Flash/EE Base Address = 0xFFFFF800

Address Name Byte Access Type Default Value Description

0xF800 FEESTA 1 R 0x20 Flash/EE status MMR.
0xF804 FEEMOD 2 R/W 0x0000 Flash/EE control MMR.
0xF808 FEECON 1 R/W 0x07 Flash/EE control MMR.
0xF80C FEEDAT 2 R/W 0xXXXX Flash/EE data MMR.
0xF810 FEEADR 2 R/W 0x0000 Flash/EE address MMR.
0xF818 FEESIGN 3 R 0xFFFFFF Flash/EE LFSR MMR.
0xF81C FEEPRO 4 R/W 0x00000000 Flash/EE protection MMR.
0xF820 FEEHIDE 4 R/W 0xFFFFFFFF Flash/EE protection MMR.

Rev. C | Page 27 of 96

ADuC7023 Data Sheet

08675-012

AV

DD

V

CM

V

CM

V

CM

0

2V

REF

2V

REF

2V

REF

08675-013

OUTPUT CODE

VOLTAGE INPUT

1111 1111 1111
1111 1111 1110
1111 1111 1101

1111 1111 1100

0000 0000 0011

1LSB0V +FS – 1LSB

0000 0000 0010
0000 0000 0001
0000 0000 0000

1LSB =

FS

4096

08675-014

OUTPUT CODE

VOLTAGE INPUT (VIN+ – VIN–)

0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010

0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110

1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000

–V

REF

+ 1LSB +V

REF

– 1LSB0LSB

1LSB =

2 × V

REF

4096

SIGN

BIT

ADC CIRCUIT OVERVIEW

The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.

The ADC consists of a 12-bit successive approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of three
different modes: fully differential mode (for small and balanced
signals), single-ended mode (for any single-ended signals), or
pseudo differential mode (for any single-ended signals), taking
advantage of the common-mode rejection offered by the
pseudo differential input.

The converter accepts an analog input range of 0 V to V

REF

when
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (V
maximum amplitude of 2 V

Figure 18. Examples of Balanced Signals in Fully Differential Mode

) in the 0 V t o AVDD range with a

CM

(see Figure 18).

REF

A high precision, low drift, factory calibrated, 2.5 V reference is
provided on chip. An external reference can also be connected as
described later in the Band Gap Reference section.

Single or continuous conversion modes can be initiated in the
software. An external

CONV

STA RT pin, an output generated from

the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.

A voltage output from an on-chip band gap reference propor­tional to absolute temperature can also be routed through the
front-end ADC multiplexer. This temperature channel can be
selected as an ADC input. This facilitates an internal temperature
sensor channel that measures die temperature.

The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 19.

Figure 19. ADC Trans fer Function in Ps eudo Differential o r Single-Ended Mode

Fully Differential Mode

The amplitude of the differential signal is the difference between
the signals applied to the V
V

). The maximum amplitude of the differential signal is,

IN−

therefore, −V

REF

to +V

REF

and V

IN+

IN–

p-p (that is, 2 × V

pins (that is, V

). This is regardless of

REF

IN+

−

the common mode (CM). The common mode is the average of
the two signals, for example, (V

IN+

+ V

)/2, and is, therefore,

IN–

the voltage on which the two inputs are centered. This results in
the span of each input being CM ±V
set up externally, and its range varies with V

/2. This voltage has to be

REF

(see the Driving

REF

the Analog Inputs section).

The output coding is twos complement in fully differential mode
with 1 LSB = 2 V
V

= 2.5 V. The output result is ±11 bits, but this is shifted by

REF

/4096 or 2 × 2.5 V/4096 = 1.22 mV when

REF

one to the right. This allows the result in the ADCDAT MMR to
be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS −
3/2 LSB). The ideal input/output transfer characteristic is shown
in Figure 20.

TRANSFER FUNCTION

Pseudo Differential and Single-Ended Modes

In pseudo differential or single-ended mode, the input range is
0 V to V
differential and single-ended modes with

. The output coding is straight binary in pseudo

REF

1 LSB = FS/4096, or

2.5 V/4096 = 0.61 mV, or
610 µV when V

= 2.5 V

REF

Rev. C | Page 28 of 96

Figure 20. ADC Transfer Function in Differential Mode

Data Sheet ADuC7023

08675-015

SIGN BITS 12- BIT ADC RESULT

31 27

16

15 0

08675-016

ADC CLOCK

ACQ BIT TRIAL

DATA

ADCSTA = 0 ADCSTA = 1

ADC INTERRUPT

WRITE

CONV

START

ADC

BUSY

ADCDAT

TYPICAL OPERATION

When configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.

The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27 as shown in Figure 21. Note that in fully
differential mode, the result is represented in twos complement
format. In pseudo differential and single-ended modes, the
result is represented in straight binary format.

Figure 21. ADC Result Format

The same format is used in DACxDAT, simplifying the software.

Current Consumption

The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 µA. The internal reference
adds 140 µA. During conversion, the extra current is 0.3 µA
multiplied by the sampling frequency (in kHz).

Timing

Figure 22 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight
clocks, and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on the temperature sensor, set
ADCCON = 0x37A3. When using multiple channels including
the temperature sensor, the timing settings revert to the user­defined settings after reading the temperature sensor channel.

Figure 22. ADC Timing

MMR INTERFACE

The ADC is controlled and configured via the eight MMRs
described in this section.

ADCCON Register

Name: ADCCON

Address: 0xFFFF0500

Default value: 0x0600

Access: Read/write

Function: ADCCON is an ADC control register

that allows the programmer to enable the
ADC peripheral, select the mode of
operation of the ADC (either in single­ended mode, pseudo differential mode, or
fully differential mode), and select the
conversion type. This MMR is described
in Tabl e 24.

Table 24. ADCCON MMR Bit Designations

Bit Value Description

15 to 14 Reserved.
13 Temperature sensor conversion enable. Set to 1 for temperature sensor conversions. Set to 0 for

12 to 10 ADC clock speed.

000 f
001 f
010 f
011 f
100 f
101 f

9 to 8 ADC acquisition time.

00 2 clocks.
01 4 clocks.
10 8 clocks (default value).
11 16 clocks.

normal ADC conversions.

/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.

ADC

/2 (default value).

ADC

/4.

ADC

/8.

ADC

/16.

ADC

/32.

ADC

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