ANALOG DEVICES ADT7516 Service Manual

SPI-/I2C-Compatible, Temperature Sensor,

www.BDTIC.com/ADI

4-Channel ADC and Quad Voltage Output

FEATURES

ADT7516: four 12-bit DACs ADT7517: four 10-bit DACs ADT7519: four 8-bit DACs Buffered voltage output Guaranteed monotonic by design over all codes 10-bit temperature-to-digital converter 10-bit 4-channel ADC DC input bandwidth Input range: 0 V to 2.28 V Temperature range: −40°C to +120°C Temperature sensor accuracy: ±0.5°C typ Supply range: 2.7 V to 5.5 V DAC output range: 0 V to 2 V

REF

Power-down current: <10 μA Internal 2.28 V

option

REF

Double-buffered input logic Buffered reference input Power-on reset to 0 V DAC output Simultaneous update of outputs (LDAC function) On-chip, rail-to-rail output buffer amplifier

®

SPI

, I2C®, QSPI™, MICROWIRE™, and DSP compatible 4-wire serial interface SMBus packet error checking (PEC) compatible 16-lead QSOP package

APPLICATIONS

Portable battery-powered instruments Personal computers Smart battery chargers Telecommunications systems Electronic text equipment Domestic appliances Process control

1

Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; and 5,764,174. Other patents pending.

GENERAL DESCRIPTION

The ADT7516/ADT7517/ADT75191 combine a 10-bit temperature-to-digital converter, a 10-bit 4-channel ADC, and a quad 12-/10-/8-bit DAC, respectively, in a 16-lead QSOP package. The parts also include a band gap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25°C.

The ADT7516/ADT7517/ADT7519 operate from a single 2.7 V

o 5.5 V supply. The input voltage range on the ADC channels is

t 0 V to 2.28 V, and the input bandwidth is dc. The reference for the ADC channels is derived internally. The output voltage of the DAC ranges from 0 V to V time of 7 s typical.

The ADT7516/ADT7517/ADT7519 provide two serial interface o

ptions: a 4-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, and a 2-wire SMBus/I controlled through the serial interface.

The reference for the four DACs is derived either internally or f

rom a reference pin. The outputs of all DACs can be updated simultaneously using the software LDAC function or the external incorporate a power-on reset circuit, ensuring that the DAC output powers up to 0 V and remains there until a valid write takes place.

The wide supply voltage range, low supply current, and SPI-/

2

I

C-compatible interface of the ADT7516/ADT7517/ADT7519 make them ideal for a variety of applications, including personal computers, office equipment, and domestic appliances.

ADT7516/ADT7517/ADT7519

PIN CONFIGURATION

1

V

-B

OUT

V

-A

2

OUT

V

REF

D+/AIN1

D–/AIN2

2

C interface. They feature a standby mode that is

LDAC

pin. The ADT7516/ADT7517/ADT7519

-IN

CS

GND

V

DD

ADT7516/

3

ADT7517/

ADT7519

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

V

-C

OUT

V

-D

15

OUT

AIN4

14

SCL/SCLK

13

SDA/DIN

12

11

DOUT/ADD

INT/INT

10

LDAC/AIN3

9

Figure 1.

, with an output voltage settling

DD

02883-006

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADT7516/ADT7517/ADT7519

www.BDTIC.com/ADI

REVISION HISTORY

10/06—Rev. A to Rev. B

Updated Format..................................................................Universal

hanges to Features..........................................................................1

C

Changes to General Description.....................................................1

Changes to Specifications.................................................................3

Changes to Absolute Maximum Ratings........................................9

Changes to Table 10........................................................................28

Changes to ADT7516/ADT7517/ADT7519 Registers Section......28

Changes to Serial Interface Section...............................................37

Changes to Ordering Guide...........................................................44

Terminology.................................................................................... 17

Theory of Operation ...................................................................... 19

Power-Up Calibration................................................................ 19

Conversion Speed....................................................................... 19

Function Description—Voltage Output.................................. 20

Functional Description—Analog Inputs................................. 23

ADC Transfer Function............................................................. 23

Functional Description—Measurement.................................. 25

ADT7516/ADT7517/ADT7519 Registers............................... 28

Serial Interface............................................................................ 37

SMBus Alert Response .............................................................. 42

Outline Dimensions....................................................................... 43

Ordering Guide .......................................................................... 43

8/04—Rev. 0 to Rev. A

Updated Format...................................................................... Universal

leted ADT7518

De

Added ADT7519..................................................................... Universal

Change to Internal V

Change to Equation.............................................................................26

7/03—Initial Version: Rev. 0

Value .............................................................5

REF

Rev. B | Page 2 of 44

ADT7516/ADT7517/ADT7519

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SPECIFICATIONS

Temperature range is as follows: A version: −40°C to +120°C, VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.

Table 1.

Parameter

DAC DC PERFORMANCE

ADT7519

ADT7517

ADT7516

Offset Error ±0.4 ±2 % of FSR Gain Error ±0.3 ±2 % of FSR Lower Deadband 20 65 mV

Upper Deadband 60 100 mV

Offset Error Drift Gain Error Drift DC Power Supply Rejection Ratio4 –60 dB ∆VDD = ±10% DC Crosstalk

ADC DC ACCURACY Maximum VDD = 5 V

Resolution 10 Bits Total Unadjusted Error (TUE) 2 3 % of FSR VDD = 2.7 V to 5.5 V Total Unadjusted Error (TUE) 2 % of FSR VDD = 3.3 V ±10% Offset Error ±0.5 % of FSR

Gain Error ±2 % of FSR ADC BANDWIDTH DC Hz ANALOG INPUTS

Input Voltage Range 0 2.28 V AIN1 to AIN4, C4 = 0 in Control Configuration 3 0 VDD V AIN1 to AIN4, C4 = 0 in Control Configuration 3

DC Leakage Current ±1 μA

Input Capacitance 5 20 pF

Input Resistance 10 MΩ THERMAL CHARACTERISTICS

Internal Temperature Sensor Internal reference used, averaging on

±0.5 ±3 °C TA = 0°C to +85°C ±2 ±5 °C TA = –40°C to +120°C

±3 ±5 °C TA = –40°C to +120°C

1

2, 3

Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic over all codes

Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic over all codes

Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed monotonic over all codes

4

Accuracy @ VDD = 3.3 V ±10% ±1.5 °C TA = 85°C

Accuracy @ VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C

Resolution 10 Bits Equivalent to 0.25°C Long-Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C

Min Typ Max Unit Conditions/Comments

Lower deadband exists only if offset error is

tive, see Figure 40

nega Upper deadband exists if V

plus gain error is positive, see Figure 41 –12 ppm of FSR/°C –5 ppm of FSR/°C

200 μV See Figure 5

= VDD and off-set

REF

Rev. B | Page 3 of 44

ADT7516/ADT7517/ADT7519

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Parameter

1

Min Typ Max Unit Conditions/Comments

External Temperature Sensor External transistor = 2N3906

Accuracy @ VDD = 3.3 V ±10% ±1.5 °C TA = 85°C ±3 °C T ±5 °C T

= 0°C to +85°C

A

= −40°C to +120°C

A

Accuracy @ VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C ±3 ±5 °C TA = −40°C to +120°C Resolution 10 Bits Equivalent to 0.25°C Output Source Current 180 μA High level 11 μA Low level Thermal Voltage Output

8-Bit DAC Output

Resolution 1 °C

Scale Factor 8.97 mV/°C 0 V to V

17.58 mV/°C 0 V to 2 V

output, TA = −40°C to +120°C

REF

output, TA = −40°C to +120°C

REF

10-Bit DAC Output

Resolution 0.25 °C

Scale Factor 2.2 mV/°C 0 V to V

4.39 mV/°C 0 V to 2 V

output, TA = −40°C to +120°C

REF

output, TA = −40°C to +120°C

REF

CONVERSION TIMES Single channel mode

Slow ADC

VDD/AIN 11.4 ms Averaging (16 samples) on

712 μs Averaging off

Internal Temperature 11.4 ms Averaging (16 samples) on

712 μs Averaging off

External Temperature 24.22 ms Averaging (16 samples) on

1.51 ms Averaging off Fast ADC

VDD/AIN 712 μs Averaging (16 samples) on

44.5 μs Averaging off

Internal Temperature 2.14 ms Averaging (16 samples) on

134 μs Averaging off

External Temperature 14.25 ms Averaging (16 samples) on 890 μs Averaging off ROUND ROBIN UPDATE RATE

5

Time to complete one measurement cycle through all channels

Slow ADC @ 25°C

Averaging On 79.8 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8

Averaging Off 4.99 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8

Averaging On 94.76 ms D+ and D– are selected on Pin 7 and Pin 8

Averaging Off 9.26 ms D+ and D– are selected on Pin 7 and Pin 8

Fast ADC @ 25°C

Averaging On 6.41 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8

Averaging Off 400.84 μs AIN1 and AIN2 are selected on Pin 7 and Pin 8

Averaging On 21.77 ms D+ and D– are selected on Pin 7 and Pin 8

Averaging Off 3.07 ms D+ and D– are selected on Pin 7 and Pin 8 DAC EXTERNAL REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference

REF

V

Input Impedance >10 MΩ Buffered reference and power-down mode

REF

4

Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –75 dB Frequency = 10 kHz

Rev. B | Page 4 of 44

ADT7516/ADT7517/ADT7519

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Parameter

1

Min Typ Max Unit Conditions/Comments

ON-CHIP REFERENCE

Reference Voltage Temperature Coefficient

OUTPUT CHARACTERISTICS

Output Voltage

4

6

2.2662 2.28 2.2938 V 80 ppm/°C

0.001 VDD − 0.1 V

This is a measure of the minimum and maximum

ive capability of the output amplifier

dr DC Output Impedance 0.5 Ω Short Circuit Current 25 mA VDD = 5 V

16 mA VDD = 3 V

Power-Up Time 2.5 μs Coming out of power-down mode, VDD = 5 V

5 μs Coming out of power-down mode, VDD = 3.3 V DIGITAL INPUTS

4

Input Current ±1 μA VIN = 0 V to VDD VIL, Input Low Voltage 0.8 V VIH, Input High Voltage 1.89 V Pin Capacitance 3 10 pF All digital inputs SCL, SDA Glitch Rejection 50 ns

Input filtering suppresses n

oise spikes of less

than 50 ns LDAC Pulse Width

20 ns Edge triggered input

DIGITAL OUTPUT

Digital High Voltage, VOH 2.4 V I

SOURCE

= I

= 200 μA

SINK

Output Low Voltage, VOL 0.4 V IOL = 3 mA Output High Current, IOH 1 mA V Output Capacitance, C INT/INT Output Saturation Voltage

I2C TIMING CHARACTERISTICS7,

50 pF

OUT

0.8 V I

8

= 5 V

OH

= 4 mA

OUT

Serial Clock Period, t1 2.5 μs Fast mode I2C, see Figure 2 Data In Setup Time to SCL High, t2 50 ns Data Out Stable after SCL Low, t3 0 ns See Figure 2 SDA Low Setup Time to SCL

Low (Start Condition), t

4

SDA High Hold Time after SCL

High (Stop Condition), t

5

50 ns See Figure 2

SDA and SCL Fall Time, t6 300 ns See Figure 2 SDA and SCL Rise Time, t7 300

SPI TIMING CHARACTERISTICS

CS to SCLK Setup Time, t1

4, 10

0 ns See Figure 3

9

ns See Figure 2

SCLK High Pulse Width, t2 50 ns See Figure 3 SCLK Low Pulse Width, t3 50 ns See Figure 3 Data Access Time after SCLK

Falling Edge, t

11

4

Data Setup Time Prior to SCLK

Rising Edge, t

5

Data Hold Time after SCLK

Rising Edge, t

6

CS to SCLK Hold Time, t7 CS to DOUT High Impedance, t8

35 ns

20 ns See Figure 3

0 ns See Figure 3

0 μs See Figure 3 40 ns See Figure 3

POWER REQUIREMENTS

VDD 2.7 5.5 V VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level IDD (Normal Mode)

12

3 mA V

= 3.3 V, VIH = VDD, and VIL = GND

DD

2.2 3 mA VDD = 5 V, VIH = VDD, and VIL = GND

Rev. B | Page 5 of 44

ADT7516/ADT7517/ADT7519

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Parameter

1

Min Typ Max Unit Conditions/Comments

IDD (Power-Down Mode) 10 μA VDD = 3.3 V, VIH = VDD, and VIL = GND

10 μA VDD = 5 V, VIH = VDD, and VIL = GND

Power Dissipation 10 mW VDD = 3.3 V, normal mode

33 μW VDD = 3.3 V, shutdown mode

1

See the Terminology section.

2

DC specifications are tested with the outputs unloaded.

3

Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).

4

Guaranteed by design and characterization, not production tested.

5

Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.

6

For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (V

plus gain error must be positive.

7

The SDA and SCL timing is measured with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate

but has a negative effect on the EMC behavior of the part.

8

Guaranteed by design, not production tested. All I2C timing specifications are for fast mode operation but the interface is still capable of handling the slower standard

rate specifications.

9

The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.

10

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.

11

Measured with the load circuit shown in Figure 4.

12

The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.

= VDD), the offset

REF

DAC AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND, CL = 200 pF to GND, 4.7 kΩ to VDD, all specifications T

Table 2.

Parameter

1, 2

Min Typ

Output Voltage Settling Time V

3

Max Unit Conditions/Comments

= VDD = 5 V

REF

ADT7519 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) ADT7517 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)

ADT7516 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion –70 dB V

1

See the Terminology section.

2

Guaranteed by design and characterization, not production tested.

3

At 25°C.

= 2 V ±0.1 V p-p

REF

= 2.5 V ±0.1 V p-p; frequency = 10 kHz

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. B | Page 6 of 44

ADT7516/ADT7517/ADT7519

V

O

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TIMING DIAGRAMS

t

1

SCL

t

Figure 2. I

2

t

3

2

C Bus Timing Diagram

SDA

DATA IN

SDA

DATA OUT

t

4

CS

SCLK

DIN

DOUT

t

1

D7

XXXXXXXXD7D6D5D4D3D2D1 D0

t

2

t

3

D6D5D4D3D2D1D0X X XXXXX X

t

6

5

t

4

Figure 3. SPI Bus Timing Diagram

t

5

t

6

02883-002

t

7

t

8

02883-003

TO OUTPUT

50pF

C

200µA I

L

200µA I

OL

1.6V

OH

2883-004

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

DD

TO DAC

UTPUT

4.7kΩ

200pF

02883-005

Figure 5. Load Circuit for DAC Outputs

Rev. B | Page 7 of 44

ADT7516/ADT7517/ADT7519

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FUNCTIONAL BLOCK DIAGRAM

INTERNAL

D+/AIN1

D–/AIN2

LDAC/AIN3

AIN4

7

8

9

14

ON-CHIP

TEMPERATURE

SENSOR

ANALOG

MUX

V

DD

SENSOR

TEMPERATURE

VALUE REGISTER

EXTERNAL

TEMPERATURE

VALUE REGISTER

A-TO-D

CONVERTER

V

DD

VALUE REGISTER

AIN1

VALUE REGISTER

AIN2

VALUE REGISTER

AIN3

VALUE REGISTER

AIN4

VALUE REGISTER

DIGITAL MUX

LIMIT

COMPARATOR

STATUS

REGISTERS

ADDRESS POI NTER

REGIST ER

T

HIGH

REGISTERS T

LOW

REGISTERS

VCCLIMIT

REGISTERS

AIN

DIGITAL MUX

SPI/SMBus INTERFACE

HIGH

REGISTERS

AIN

LOW

REGISTERS

CONTROL CO NFIG. 1

REGIST ER

CONTROL CO NFIG. 2

REGIST ER

CONTROL CO NFIG. 3

REGIST ER

DAC CONFIGU RATION

REGISTERS

LDAC CONFIG URATION

REGISTERS

INTERRUPT MASK

REGISTERS

LIMIT

ADT7516/ADT7517/ADT7519

DAC A

REGISTERS

DAC B

REGISTERS

DAC C

REGISTERS

DAC D

REGISTERS

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN

SELECT

LOGIC

INTERNAL

REFERENCE

POWER-

DOWN LOGIC

2

1

16

15

10

V

OUT

V

OUT

V

OUT

V

OUT

INT/INT

-A

-B

-C

-D

12

5

6

GND

V

DD

Figure 6. Functional Block Diagram

13

4

SCL

CS

SDA

11

ADD

for the ADT7516/ADT7517/ADT7519

9

LDAC/AIN33V

REF

-IN

02883-001

Rev. B | Page 8 of 44

ADT7516/ADT7517/ADT7519

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V Analog Input Voltage to GND –0.3 V to VDD + 0.3 V Digital Input Voltage to GND –0.3 V to VDD + 0.3 V Digital Output Voltage to GND –0.3 V to VDD + 0.3 V Reference Input Voltage to GND –0.3 V to VDD + 0.3 V Operating Temperature Range –40°C to +120°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C Power Dissipation1 (TJ max – TA)/θJA Thermal Impedance2

θ

Junction-to-Ambient 105.44°C/W

JA

θ

Junction-to-Case 38.8°C/W

JC

IR Reflow Soldering

Peak Temperature 220°C (0°C/5°C) Time at Peak Temperature 10 sec to 20 sec Ramp-Up Rate 3°C/sec maximum Ramp-Down Rate –6°C/sec maximum Time 25°C to Peak Temperature 6 min maximum

IR Reflow Soldering (Pb-Free Package)

Peak Temperature 260°C (+0°C) Time at Peak Temperature 20 sec to 40 sec Ramp-Up Rate 3°C/sec maximum Ramp-Down Rate –6°C/sec maximum Time 25°C to Peak Temperature 8 min maximum

1

Values relate to the package being used on a 4-layer board.

2

Junction-to-case resistance is applicable to components featuring a

preferential flow direction, for example, components mounted on a heat sink. Junction-to-ambient resistance is more useful for air cooled PCBmounted components.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2

Table 4. I

ADD Pin I2C Address

Low 1001 000 Float 1001 010 High 1001 011

C Address Selection

ESD CAUTION

Rev. B | Page 9 of 44

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PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

V

OUT

V

OUT

V

-IN

REF

CS

GND

V

D+/AIN1

D–/AIN2

-B

-A

DD

1

2

ADT7516/

3

ADT7517/

ADT7519

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

V

15

V

14

AIN4

13

SCL/SCLK

SDA/DIN

12

DOUT/ADD

11

INT/INT

10

LDAC/AIN3

9

OUT

-C

-D

02883-006

Figure 7. Pin Configuration (QSOP Package)

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V 3 V 4

-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

-IN Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to VDD.

REF

SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables

CS

the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to V

when operating the serial interface in I2C mode.

DD

5 GND Ground Reference Point. Ground reference point for all circuitry on the part. Analog and digital ground. 6 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 7 D+/AIN1 D+: Positive Connection to External Temperature Sensor.

AIN1: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V

.

DD

8 D–/AIN2 D–: Negative Connection to External Temperature Sensor.

.

DD

9

AIN2: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V

/AIN3 LDAC: Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A

LDAC

falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is

10

Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when

INT/INT

11 DOUT/ADD

with the LDAC AIN3: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V

temperature, V DOUT: SPI Serial Data Output. Log

pin controlling the loading of the DAC registers.

.

DD

, or AIN limits are exceeded. The default is active low. Open-drain output, needs a pull-up resistor.

DD

ic output. Data is clocked out of any register at this pin. Data is clocked out on the

falling edge of SCLK. Open-drain output, needs a pull-up resistor.

2

ADD: I

C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the Address 1001 000; leaving it floating

gives the Address 1001 010; and setting it high gives the address 1001 011. The I

2

C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent change on this pin has no effect on the I2C serial bus address.

12 SDA/DIN

2

C Serial Data Input/Output. I2C serial data to be loaded into the registers of the part and read from these

SDA: I registers is provided on this pin. Open-drain configuration, needs a pull-up resistor.

DIN: SPI Serial Data Input. S

erial data to be loaded into the part’s registers is provided on this pin. Data is clocked into

a register on the rising edge of SCLK. Open-drain configuration, needs a pull-up resistor.

13 SCL/SCLK

Serial Clock Input. This is the clock input for the serial port. The serial clock is used t

o clock data out of any register of the ADT7516/ADT7517/ADT7519, and also to clock data into any register that can be written to. Open-drain configuration, needs a pull-up resistor.

14 AIN4 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD. 15 V 16 V

-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

Rev. B | Page 10 of 44

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TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

0

–0.05

INL ERROR (LSB)

–0.10

–0.15

–0.20

0 50 100 150 200 250

DAC CODE

Figure 8. ADT7519 Typical DAC INL Plot

02883-009

0.10

0.08

0.06

0.04

0.02

0

–0.02

DNL ERROR (LSB)

–0.04

–0.06

–0.08

–0.10

0 50 100 150 200 250

DAC CODE

Figure 11. ADT7519 Typical

DAC DNL Plot

02883-012

0.6

0.4

0.2

0

INL ERROR (LSB)

–0.2

–0.4

–0.6

0 200 400 600

Figure 9. ADT7517 Typical DAC INL Plot

2.5

2.0

1.5

1.0

0.5

0

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

–2.5

Figure 10. ADT7516 Typical DAC INL Plot

DAC CODE

800 1000

20001500500 10000 2500 3000 3500 4000

DAC CODE

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

02883-010

02883-011

–0.3

0 200 400 600 800 1000

DAC CODE

Figure 12. ADT7517 Typical

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

DAC CODE

Figure 13. ADT7516 Typical

DAC DNL Plot

20001500500 10000 2500 3000 3500 4000

DAC DNL Plot

02883-013

02883-014

Rev. B | Page 11 of 44

ADT7516/ADT7517/ADT7519

www.BDTIC.com/ADI

0.30

10

0.25

0.20

0.15

0.10

0.05

ERROR (LSB)

0

–0.05

–0.10

1.01.52.02.53.03.54.04.5 5.0

Figure 14. ADT7519 DAC INL and DNL Error vs. V

0.14

0.12

0.10

0.08

0.06

0.04

0.02

ERROR (LSB)

0

–0.02

–0.04

–0.06

–40 110805020–10

INL WCP

INL WCN

DNL WCP

DNL WCN

TEMPERATURE ( °C)

INL WCP

DNL WCP

DNL WCN

INL WCN

(V)

V

REF

Figure 15. ADT7519 DAC INL Error and DNL Error vs. Temperature

5

0

–5

ERROR (LSB)

–10

–15

02883-015

–20

2.7 3.3 3.6 4. 0

GAIN ERROR

Figure 17. DAC Offset Error and Gain Error vs. V

2.505

2.500

2.495

2.490

2.485

2.480

DAC OUTPUT (V)

2.475 VDD = 5V

V

= 5V

REF

DAC OUTPUT

2.470

02883-016

LOADED TO MI DSCALE

2.465

0123

Figure 18. DAC V

Source and Sink Current Capability

OUT

OFFSET ERROR

(V)

V

DD

SOURCE CURRENT

CURRENT (mA)

V

= 2.25V

REF

4.5 5.0

SINK CURRENT

45

02883-018

5.5

DD

02883-019

6

0

–0.2

–0.4

–0.6

–0.8

–1.0

ERROR (LSB)

–1.2

–1.4

–1.6

–1.8

–40 120100806040200–20

OFFSET ERROR

GAIN ERROR

TEMPERATURE ( °C)

02883-017

Figure 16. DAC Offset Error and Gain Error vs. Temperature

Rev. B | Page 12 of 44

(mA)

CC

I

1.98

1.96

1.94

1.92

1.90

1.88

1.86

DAC OUTPUT UNLOADED

DAC OUTPUT LOADED

04350030002500200015001000500

DAC CODE

Figure 19. Supply Current vs. DAC Code

02883-020

000

ADT7516/ADT7517/ADT7519

www.BDTIC.com/ADI

2.00

ADC OFF DAC OUTPUTS AT 0V

1.95

1.90

(mA)

CC

I

1.85

1.80

1.75

2.7 3.1 3.5 3.9 4.3 4.7 5.12.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5 V

(V)

CC

Figure 20. Supply Current vs. Supply Voltage @ 25°C

7

6

5

4

(mA)

CC

I

3

2

1

0

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4. 5 4.7 4. 9 5.1 5. 3 5.5 (V)

V

CC

Figure 21. Power-Down Current vs. Supply Voltage @ 25°C

02883-021

02883-022

1.8

1.6

1.4

1.2

1.0

0.8

DAC OUTPUT (V)

0.6

0.4

0.2

0

024

Figure 23. Exiting Powe

0.4700

0.4695

0.4690

0.4685

0.4680

0.4675

0.4670

DAC OUTPUT (V )

0.4665

0.4660

0.4655

0.4650 02 4681

68

TIME (µs)

r-Down to Midscale

TIME (µs)

Figure 24. ADT7516 DAC Major Code Transition Glitch Energy;

01

1…11 to 100...00

02883-024

10

02883-025

0

4.0

3.5

3.0

2.5

2.0

1.5

DAC OUTPUT (V)

1.0

0.5

0

02 4681

Figure 22. DAC Half-Scale Settling (

TIME (µs)

1/4 to 3/4 Scale Code Change)

02883-023

0

Rev. B | Page 13 of 44

0.4730

0.4725

0.4720

0.4715

0.4710

0.4705

DAC OUTPUT (V)

0.4700

0.4695

0.4690

0.4685 02 4681

TIME (µs)

Figure 25. ADT7516 DAC Major Code Transition Glitch Energy;

0…00 to 011…11

10

02883-026

0

ADT7516/ADT7517/ADT7519

www.BDTIC.com/ADI

0

–2

–4

VDD= 5V T

= 25°C

A

0

±100mV RIPPLE ON V V

= 2.25V

REF

–10

= 3.3V

V

DD

TEMPERATURE = 25°C

–20

CC

–6

–8

FULL-SCAL E ERROR (mV)

–10

–12

2.329

2.328

2.327

2.326

2.325

DAC OUTPUT (V)

2.324

2.323

2.322

12 3

V

(V)

REF

Figure 26. DAC Full-Scale Error vs. V

VDD= 5V

= 5V

V

REF

DAC OUTPUT LO ADED TO MIDSCALE

012 345

TIME (µs)

45

REF

–30

AC PSRR (dB)

–40

–50

02883-027

–60

110

FREQUENCY (kHz)

02883-030

100

Figure 29. PSRR vs. Supply Ripple Frequency

1.5

EXTERNAL T EMPERATURE @ 5V

1.0

0.5

0

TEMPERATURE ERRO R (°C)

–0.5

02883-028

–1.0

INTERNAL T EMPERATURE @ 3.3V

INTERNAL T EMPERATURE @ 5V

–30 0 40 85 120

EXTERNAL T EMPERATURE @ 3.3V

TEMPERATURE ( °C)

02883-031

Figure 27. DAC-to-

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 800 1000

Figure 28. ADC INL with V

DAC Crosstalk

ADC CODE

= VDD (3.3 V)

REF

02883-029

Rev. B | Page 14 of 44

Figure 30. Internal Temperature Error @ 3.3 V and 5 V

3

V

= 3.3V

DD

2

1

0

–1

ERROR (LSB)

–2

–3

–4

–40 –20 0

OFFSET ERROR

GAIN ERROR

20 40 60 80 100 120

TEMPERATURE (°C)

Figure 31. ADC Offset Error and Gain Error vs. Temperature

02883-032

ANALOG DEVICES ADT7516 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PIN CONFIGURATION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DAC AC CHARACTERISTICS

TIMING DIAGRAMS

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS