ANALOG DEVICES ADT7473 Service Manual

Cool® Remote Thermal

FEATURES

Controls and monitors up to 4 fans High and low frequency fan drive signal

1 on-chip and 2 remote temperature sensors Series resistance cancellation on the remote channel Extended temperature measurement range, up to 191°C Dynamic T

intelligently

Automatic fan speed control mode controls system cooling

based on measured temperature

Enhanced acoustic mode dramatically reduces user

perception of changing fan speeds Thermal protection feature via

Monitors performance impact of Intel® Pentium®4 processor Thermal control circuit via

3-wire and 4-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications

(fully SMBus 1.1 compliant) Fully ROHS compliant

control mode optimizes system acoustics

MIN

output

THERM

input

THERM

FUNCTIONAL BLOCK DIAGRAM

Monitor and Fan Controller

ADT7473

GENERAL DESCRIPTION

The ADT7473 dBCool controller is a thermal monitor and multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The ADT7473 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans so they operate at the lowest possible speed for minimum acoustic noise.

The automatic fan speed control loop optimizes fan speed for a given temperature. A unique dynamic T enables the system thermals/acoustics to be intelligently managed. The effectiveness of the system’s thermal solution can be monitored using the

THERM

input. The ADT7473 also

provides critical thermal protection to the system using the bidirectional

THERM

pin as an output to prevent system or

component overheating.

SCL

SDA SMBALERT

control mode

MIN

ADT7473

PWM1 PWM2 PWM3

TACH1 TACH2 TACH3 TACH4

THERM

D1+ D1– D2+ D2–

CCP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

PWM

REGISTERS

AND

CONTROLLERS

(HF AND LF)

TO ADT7473

SRC

BAND GAP

TEMP. SENSOR

ACOUSTIC

ENHANCEMENT

CONTROL

FAN

SPEED

COUNTER

PERFORMANCE

MONITORING

THERMAL

PROTECTION

INPUT

SIGNAL

CONDITIONING

AND

ANALOG

MULTIPLEXER

GND

Figure 1.

SERIAL BUS

INTERFACE

AUTOMATIC

FAN SPEED

CONTROL

ADDRESS

POINTER

DYNAMIC

MIN

CONTROL

10-BIT

ADC

BAND GAP

REFERENCE

PWM

CONFIGURATION

REGISTERS

INTERRUPT

MASKING

INTERRUPT

STATUS

REGISTERS

LIMIT

COMPARATORS

VALUE AND

LIMIT

REGISTERS

04686-001

ADT7473

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Product Description......................................................................... 9

Comparison Between ADT7467 and ADT7473 ...................... 9

Recommended Implementation................................................. 9

Serial Bus Interface..................................................................... 10

Write Operations ........................................................................ 11

Read Operations ......................................................................... 12

SMBus Timeout.......................................................................... 12

THERM

Timer ........................................................................... 22

Fan Drive Using PWM Control ............................................... 25

Fan Presence Detect................................................................... 30

Sleep States .................................................................................. 30

XNOR Tree Test Mode .............................................................. 31

Power-On Default ...................................................................... 31

Programming the Automatic Fan Speed Control Loop............ 32

Automatic Fan Control Overview............................................ 32

Step 1: Hardware Configuration .............................................. 33

Step 2: Configuring the Mux .................................................... 35

Step 3: T

Step 4: PWM

Step 5: PWM

Settings for Thermal Calibration Channels ...... 37

MIN

for Each PWM (Fan) Output ...................... 38

MIN

for PWM (Fan) Outputs.............................. 38

MAX

Voltage Measurement Input...................................................... 12

Analog-to-Digital Converter ....................................................12

Input Circuitry............................................................................ 12

Voltage Measurement Registers................................................ 12

Limit Registers ...................................................................13

CCP

Additional ADC Functions for Voltage Measurements........ 13

Temperature Measurement Method ........................................ 14

Series Resistance Cancellation.................................................. 16

Factors Affecting Diode Accuracy ........................................... 16

Additional ADC Functions for Temperature Measurement 18

Limits, Status Registers, and Interrupts....................................... 19

Limit Values................................................................................. 19

Status Registers ........................................................................... 20

REVISION HISTORY

6/05—Revision 0: Initial Version

Step 6: T

Step 7: T

Step 8: T

Dynamic T

for Temperature Channels................................ 39

RANGE

for Temperature Channels ............................... 42

THERM

for Temperature Channels.................................. 43

HYST

Control Mode ................................................... 45

MIN

Step 9: Operating Points for Temperature Channels............. 47

Step 10: High and Low Limits for Temperature Channels ... 48

Step 11: Monitoring

THERM

................................................... 50

Enhancing System Acoustics .................................................... 51

Step 12: Ramp Rate for Acoustic Enhancement..................... 53

Outline Dimensions....................................................................... 74

Ordering Guide .......................................................................... 74

Rev. 0 | Page 2 of 76

ADT7473

SPECIFICATIONS

TA = T All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T norm. Logic inputs accept input high voltages up to V logic levels of V guaranteed by design and are not production tested.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

TEMP-TO-DIGITAL CONVERTER

36 μA Second current 96 μΑ Third current ANALOG-TO-DIGITAL CONVERTER

(INCLUDING MUX AND ATTENTUATORS)

FAN RPM-TO-DIGITAL CONVERTER

OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

SMBus DIGITAL INPUTS (SCL, SDA)

MIN

to T

, VCC = V

MAX

= 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. Serial management bus (SMBus) timing specifications are

MIN

to V

, unless otherwise specified.

MAX

, even when device is operating down to V

MAX

= 25°C and represent most likely parametric

. Timing specifications are tested at

MIN

Supply Voltage 3.0 3.3 3.6 V

Supply Current, ICC 1.5 3 mA Interface inactive, ADC active

Local Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA ≤ 85°C

±2.5 °C −40°C ≤ TA ≤ 125°C

Resolution 0.25 °C

Remote Diode Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA ≤ 85°C

±2.5 °C −40°C ≤ TA ≤ 125°C

Resolution 0.25 °C

Remote Sensor Source Current 6 μA First current

Total Unadjusted Error (TUE) ±1.5 %

Differential Nonlinearity (DNL) ±1 LSB 8 bits

Power Supply Sensitivity ±0.1 %/V

Conversion Time (Voltage Input) 11 ms Averaging enabled

Conversion Time (Local Temperature) 12 ms Averaging enabled

Conversion Time (Remote Temperature) 38 ms Averaging enabled

Total Monitoring Cycle Time 145 ms Averaging enabled

19 ms Averaging disabled

Input Resistance 90 120 kΩ For V

channel

CCP

Accuracy ±6 % 0°C ≤ TA ≤ 70°C

±10 % −40°C ≤ TA ≤ +120°C

Full-Scale Count 65,535

Nominal Input RPM 109 RPM Fan count = 0xBFFF

329 RPM Fan count = 0x3FFF

5,000 RPM Fan count = 0x0438

10,000 RPM Fan count = 0x021C

Current Sink, IOL 8.0 mA

Output Low Voltage, VOL 0.4 V I

High Level Output Current, IOH 0.1 20 μA V

Output Low Voltage, VOL 0.4 V I

High Level Output Current, IOH 0.1 1.0 μA V

= −8.0 mA

OUT

= VCC

OUT

= −4.0 mA

OUT

= VCC

OUT

Input High Voltage, VIH 2.0 V

Input Low Voltage, V

0.4 V

Hysteresis 500 mV

Rev. 0 | Page 3 of 76

ADT7473

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, VIH 2.0 V

3.6 V Maximum input voltage

Input Low Voltage, VIL 0.8 V

−0.3 V Minimum input voltage Hysteresis 0.5 V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, V Input Low Voltage, V

0.75 × V

0.4 V

DIGITAL INPUT CURRENT

Input High Current, IIH ±1 μA VIN = VCC Input Low Current, IIL ±1 μA VIN = 0 Input Capacitance, CIN 5 pF

SERIAL BUS TIMING See Figure 2

Clock Frequency, f Glitch Immunity, t Bus Free Time, t SCL Low Time, t SCL High Time, t SCL, SDA Rise Time, t SCL, SDA Fall Time, t Data Setup Time, t Detect Clock Low Timeout, t

10 400 kHz

SCLK

50 ns

4.7 μs

BUF

4.7 μs

LOW

4.0 50 μs

HIGH

1,000 ns

300 μs

250 ns

SU;DAT

15 35 ms Can be optionally disabled

TIMEOUT

HIGH

SU; DAT

Figure 2. Serial Bus Timing Diagram

SU; STA

HD; STA

SU; STO

04686-002

SCL

BUF

HD; STA

LOW

HD; DAT

Rev. 0 | Page 4 of 76

ADT7473

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 3.6 V Voltage on Any Input or Output Pin −0.3 V to +3.6 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering

IR Reflow Peak Temperature 260°C

Lead Temperature (Soldering, 10 sec) 300°C ESD Rating 1,500 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

16-lead QSOP package:

θJA = 150°C/W θ

= 39°C/W

Rev. 0 | Page 5 of 76

ADT7473

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCL

GND

TACH3

PWM2/SMBALERT

TACH1 TACH2

PWM3

ADT7473

TOP VIEW

(Not to Scale)

SDA

PWM1/XTO

CCP

D1+ D1–

D2+

D2–

TACH4/GPIO/THERM/SMBALERT

04686-003

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Mnemonic Description

No.

1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. 2 GND Ground Pin for the ADT7473. 3 VCC Power Supply. Powered by 3.3 V. 4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. 5 PWM2

Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed. Can be configured as a high or low frequency drive.

SMBALERT Digital Output (Open Drain). Can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. 6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. 7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.

8 PWM3

Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ

typical pull-up. Can be configured as a high or low frequency drive. 9 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. GPIO General-Purpose Open Drain Digital I/O.

THERM Can be configured as a bidirectional THERM pin, which can be used to time and monitor assertions on the THERM

input as well as to assert when an ADT7473

THERM overtemperature limit is exceeded. For example, the pin can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions.

SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit

conditions.

10 D2− Cathode Connection to Second Thermal Diode. 11 D2+ Anode Connection to Second Thermal Diode. 12 D1− Cathode Connection to First Thermal Diode. 13 D1+ Anode Connection to First Thermal Diode. 14 V

Analog Input. Monitors processor core voltage (0 V − 3 V).

CCP

15 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up. XTO Also functions as the output from the XNOR tree in XNOR test mode. 16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.

Rev. 0 | Page 6 of 76

ADT7473

TYPICAL PERFORMANCE CHARACTERISTICS

D+ TO GND

D+ TO V

–20

TEMPERATURE ERROR (°C)

–40

–60

0 204060

80 10010 30 50 70 90

LEAKAGE RESISTANCE (MΩ)

Figure 4. Remote Temperature Error vs. PCB Resistance

–10

–20

–30

–40

TEMPERATURE ERROR (°C)

–50

–60

024681012

CAPACITANCE (nF)

14 16 18 20 22

Figure 5. Temperature Error vs. Capacitance Between D+ and D−

04686-004

04686-006

TEMPERATURE ERROR (°C)

–10

0 100M 200M 300M 400M 500M 600M

40mV

NOISE FREQUENCY (Hz)

100mV

60mV

04686-008

Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency

1.20

1.18

1.16

1.14

1.12

1.10

(mA)

1.08

1.06

1.04

1.02

1.00

0.98

3.0 3.1 3.2 3.3 3.4

Figure 8. Normal I

(V)

vs. Power Supply

3.5 3.6

04686-009

TEMPERATURE ERROR (°C)

–5

0 100M 200M 300M 400M 500M 600M

NOISE FREQUENCY (Hz)

100mV

60mV

40mV

04686-007

Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency

Rev. 0 | Page 7 of 76

100mV

–5

TEMPERATURE ERROR (

–10

–15

0 100M 200M 300M 400M 500M 600M

250mV

FREQUENCY (Hz)

Figure 9. Internal Temperature Error vs. Frequency

04686-010

ADT7473

–2

–4

–6

–8

TEMPERATURE ERROR (

–10

–12

0 100M 200M 300M

Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency

3.0

2.5

2.0

1.5

1.0

0.5

TEMPERATURE ERROR (°C)

–0.5

–1.0

–1.5

Figure 11. Internal Temperature Error vs. ADT7473 Temperature

250mV

100mV

400M 500M 600M

FREQUENCY (Hz)

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (°C)

105 125

04686-011

04686-012

3.0

2.5

2.0

1.5

1.0

0.5 0

–0.5

TEMPERATURE ERROR (°C)

–1.0 –1.5 –2.0

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (°C)

105 125

04686-013

Figure 12. Remote Temperature Error vs. Temperature

Rev. 0 | Page 8 of 76

ADT7473

PRODUCT DESCRIPTION

The ADT7473 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 16), and an input line for the serial clock (Pin 1). All control and programming functions for the ADT7473 are performed over the serial bus. Additionally, a pin can be reconfigured as an SMBALERT

output to signal out-of-limit conditions.

COMPARISON BETWEEN ADT7467 AND ADT7473

The ADT7473 can only be powered via a 3.3 V supply, and does not support 5 V operation like the ADT7467.

High frequency PWM drive can be independently selected for each PWM channel on the ADT7473. This is not available on the ADT7467.

The range and resolution of the temperature offset register can now be changed from a ±64°C range at 0.5°C resolution to a ±128°C range at 1°C resolution. This is not available on the ADT7467.

THERM individually on each temperature channel. This is not available

on the ADT7467.

Bit 7 of Configuration Register 1 is no longer supported because the ADT7473 cannot be powered via a 5 V supply.

Bit 0 of Configuration Register 1 (0x40) remains writable after the lock bit is set. This bit enables monitoring.

2-wire fan speed measurement is no longer supported on the ADT7473.

overtemperature events can be disabled/enabled

How to Set the Functionality of Pin 9

Pin 9 on the ADT7473 has four possible functions:

THERM

, GPIO, and TACH4. The user chooses the required

SMBALERT

functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.

Table 4. Pin 9 Settings

Bit 0 Bit 1 Function

0 0 TACH4 0 1

1 0

THERM SMBALERT

1 1 GPIO

RECOMMENDED IMPLEMENTATION

Configuring the ADT7473, as shown in Figure 13, allows the system designer to use the following features:

• Two PWM outputs for fan control of up to three fans (the

front and rear chassis fans are connected in parallel).

• Three TACH fan speed measurement inputs.

• V

• CPU temperature measured using Remote 1 temperature

• Ambient temperature measured through Remote 2

• Bidirectional

measured internally through Pin 3.

channel.

temperature channel.

THERM

Pentium 4

PROCHOT overtemperature

programmed as an

pin. This feature allows Intel

monitoring and can function as an

THERM

output. It can alternatively be

SMBALERT

system interrupt output.

FRONT CHASSIS FAN

REAR CHASSIS FAN

AMBIENT TEMPERATURE

Figure 13. ADT7473 Configuration

ADT7473

TACH2

PWM3 TACH3

D1+ D1–

Rev. 0 | Page 9 of 76

PWM1

TACH1

THERM

SMBALERT

GND

D2+ D2–

SDA SCL

PROCHOT

CPU FAN

ICH

CPU

04686-015

ADT7473

SERIAL BUS INTERFACE

On PCs and servers, control of the ADT7473 is carried out using the SMBus. The ADT7473 is connected to this bus as a slave device, under the control of a master controller, which is usually (but not necessarily) the ICH.

The ADT7473 has a fixed 7-bit serial bus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address (01011100 or 0x5C). Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle.

When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

SCL

In the ADT7473, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register.

This write operation is shown in is sent over the bus, and then R/

Figure 14. The device address

is set to 0. This is followed

by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two possibilities:

• If the ADT7473’s address pointer register value is unknown

or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7473 as before, but only the data byte containing the register address is sent, because no data is written to the register. This is shown in

Figure 15.

A read operation is then performed consisting of the serial bus address, R/

read from the data register. This is shown in

bit set to 1, followed by the data byte

Figure 16.

• If the address pointer register is known to be already at the

desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in

Figure 16.

SDA

START BY

MASTER

1011

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

R/W

ACK. BY ADT7473

Rev. 0 | Page 10 of 76

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

FRAME 2

ACK. BY

ADT7473

ACK. BY ADT7473

STOP BY MASTER

04686-016

ADT7473

SDA

SCL

START BY

MASTER

1011

SERIAL BUS ADDRESS BYTE

FRAME 1

R/W

ACK. BY

ADT7473

Figure 15. Writing to the Address Pointer Register Only

SCL

SDA

START BY

MASTER

SERIAL BUS ADDRESS BYTE

FRAME 1

R/W

ACK. BY

ADT7473

Figure 16. Reading Data from a Previously Selected Register

It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register.

In addition to supporting the send byte and receive byte protocols, the ADT7473 also supports the read byte protocol. (See System Management Bus Specifications Rev. 2 for more information; this document is available from Intel.)

If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.

WRITE OPERATIONS

The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7473 are discussed below. The following abbreviations are used in the diagrams: S – START P – STOP R – READ W – WRITE A – ACKNOWLEDGE

– NO ACKNOWLEDGE

A The ADT7473 uses the following SMBus write protocols.

Send Byte

In this operation, the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

ADDRESS POINTER REGISTER BYTE

DATA BYTE FROM ADT743

FRAME 2

ACK. BY

ADT7473

NO ACK. BY

MASTER

STOP BY MASTER

For the ADT7473, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This operation is illustrated in

23154

SLAVE

ADDRESS

Figure 17. Setting a Register Address for Subsequent Read

WASA

ADDRESS

Figure 17.

04686-019

If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition.

Write Byte

In this operation, the master device sends a command byte and one data byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA, and the

transaction ends.

The byte write operation is illustrated in

23154

SLAVE

ADDRESS

Figure 18. Single Byte Write to a Register

W A DATASA

ADDRESS

Figure 18.

678

04686-017

04686-018

04686-020

Rev. 0 | Page 11 of 76

ADT7473

READ OPERATIONS

The ADT7473 uses the following SMBus read protocols.

Receive Byte

This operation is useful when repeatedly reading a single register. The register address must have been previously set up. In this operation, the master device receives a single byte from a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

5. The master asserts NO ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADT7473, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in

Alert Response Address

Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus.

The

SMBALERT output or an

connected to a common

master. If a device’s events occur:

Figure 19.

24315

SLAVE

ADDRESS

Figure 19. Single-Byte Read from a Register

DATAARSA

04686-021

output can be used as either an interrupt

SMBALERT

. One or more outputs can be

SMBALERT

line connected to the

line goes low, the following

SMBus TIMEOUT

The ADT7473 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7473 assumes the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot work with the SMBus timeout feature, so it can be disabled.

Configuration Register 1 (Reg. 0x40)

<6> TODIS = 0, SMBus timeout enabled (default).

<6> TODIS = 1, SMBus timeout disabled.

VOLTAGE MEASUREMENT INPUT

The ADT7473 has one external voltage measurement channel and can also measure its own supply voltage, V measure V out through the V

. The VCC supply voltage measurement is carried

CCP

pin (Pin 3). The V

CCP

. Pin 14 can

input can be used to

monitor a chipset supply voltage in computer systems.

ANALOG-TO-DIGITAL CONVERTER

All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the input has built-in attenuators to allow measurement of V

CCP

without any external components. To allow for the tolerance of the supply voltage, the ADC produces an output of 3/4 full-scale (768 decimal or 300 hex) for the nominal input voltage and thus has adequate headroom to deal with overvoltages.

INPUT CIRCUITRY

The internal structure for the V Figure 20. The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low-pass filter that gives the input immunity to high frequency noise.

CCP

17.5k

analog input is shown in

CCP

52.5kΩ 35pF

SMBALERT

2. The master initiates a read operation and sends the alert

response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address.

3. The device whose

the alert response address, and the master reads its device

is pulled low.

SMBALERT

output is low responds to

Figure 20. Structure of Analog Inputs

VOLTAGE MEASUREMENT REGISTERS

Reg. 0x21 V

Reg. 0x22 V

Reading = 0x00 default

CCP

Reading = 0x00 default

04686-022

address. The address of the device is now known and can be interrogated in the usual way.

4. If more than one device’s

SMBALERT

output is low, the

one with the lowest device address has priority in accordance with normal SMBus arbitration.

5. Once the ADT7473 has responded to the alert response

address, the master must read the status registers, and the SMBALERT

is cleared only if the error condition is gone.

Rev. 0 | Page 12 of 76

ADT7473

LIMIT REGISTERS

CCP

Associated with the V

measurement channel is a high and

CCP

low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate

Reg. 0x46 V

Reg. 0x47 V

Low Limit = 0x00 default

CCP

High Limit = 0xFF default

CCP

SMBALERT

interrupts.

Tabl e 5 shows the input ranges of the analog inputs and output codes of the 10-bit ADC.

When the ADC is running, it samples and converts a voltage input in 711 μs and averages 16 conversions to reduce noise; a measurement takes nominally 11.38 ms.

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS

A number of other functions are available on the ADT7473 to offer the system designer increased flexibility.

Turn-Off Averaging

For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. When faster conversions are needed, setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This effectively gives a reading 16 times faster (711 μs), but the reading may be noisier.

Bypass Voltage Input Attenuator

Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes the attenuation circuitry from the V

input. This allows the

CCP

user to directly connect external sensors or to rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V.

Single-Channel ADC Conversion

Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7473 into single-channel ADC conversion mode. In this mode, the ADT7473 can be made to read a single voltage channel only. If the internal ADT7473 clock is used, the selected input is read every 711 μs. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55).

Bits <7:5> Reg. 0x55 Channel Selected

001 V 010 V 101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature

CCP

Configuration Register 2 (Reg. 0x73)

<4> = 1, averaging off.

<5> = 1, bypass input attenuators.

<6> = 1, single-channel convert mode.

TACH1 Minimum High Byte (Reg. 0x55)

<7:5> selects ADC channel for single-channel convert mode.

Rev. 0 | Page 13 of 76

ADT7473

Table 5. 10-Bit ADC Output Code vs. VIN

(3.3 VIN)

Decimal Binary (10 Bits)

CCP

<0.0042 <0.00293 0 00000000 00

0.0042 to 0.0085 0.0293 to 0.0058 1 00000000 01

0.0085 to 0.0128 0.0058 to 0.0087 2 00000000 10

0.0128 to 0.0171 0.0087 to 0.0117 3 00000000 11

0.0171 to 0.0214 0.0117 to 0.0146 4 00000001 00

0.0214 to 0.0257 0.0146 to 0.0175 5 00000001 01

0.0257 to 0.0300 0.0175 to 0.0205 6 00000001 10

0.0300 to 0.0343 0.0205 to 0.0234 7 00000001 11

0.0343 to 0.0386 0.0234 to 0.0263 8 00000010 00

•

1.100 to 1.1042 0.7500 to 0.7529 256 (1/4-scale) 01000000 00

•

2.200 to 2.2042 1.5000 to 1.5029 512 (1/2-scale) 10000000 00

•

3.300 to 3.3042 2.2500 to 2.2529 768 (3/4 scale) 11000000 00

•

4.3527 to 4.3570 2.9677 to 2.9707 1013 11111101 01

4.3570 to 4.3613 2.9707 to 2.9736 1014 11111101 10

4.3613 to 4.3656 2.9736 to 2.9765 1015 11111101 11

4.3656 to 4.3699 2.9765 to 2.9794 1016 11111110 00

4.3699 to 4.3742 2.9794 to 2.9824 1017 11111110 01

4.3742 to 4.3785 2.9824 to 2.9853 1018 11111110 10

4.3785 to 4.3828 2.9853 to 2.9882 1019 11111110 11

4.3828 to 4.3871 2.9882 to 2.9912 1020 11111111 00

4.3871 to 4.3914 2.9912 to 2.9941 1021 11111111 01

4.3914 to 4.3957 2.9941 to 2.9970 1022 11111111 10 >4.3957 >2.9970 1023 11111111 11

The VCC output codes listed assume that VCC is 3.3 V.

ADC Output

TEMPERATURE MEASUREMENT METHOD

A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the baseemitter voltage (V current. Unfortunately, this technique requires calibration to null out the effect of the absolute value of V from device to device.

The technique used in the ADT7473 is to measure the change

when the device is operated at three different currents.

in V

Previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor.

) of a transistor operated at constant

, which varies

Rev. 0 | Page 14 of 76

Figure 21 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D− input. C1 can optionally be added as a noise filter (recommended maximum value 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Filtering

section.

Noise

ADT7473

Local Temperature Measurement

The ADT7473 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Tabl e 6 and Tab l e 7. Theoretically, the temperature sensor and ADC can measure temperatures from −63°C to +127°C (or

−63°C to +191°C in the extended temperature range) with a resolution of 0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7473 operating temperature range are not possible.

Remote Temperature Measurement

The ADT7473 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pins 10 and 11, or Pins 12 and 13.

The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about –2 mV/°C. Unfortunately, the absolute value of V

varies from device to device and individual

calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADT7473 is to measure the change in V

when the device is

operated at three different currents. This is given by

()

NnqKTV

1/ ×=Δ

where:

K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents.

Figure 21 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. It could also be a discrete transistor such as a 2N3904/2N3906.

If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D– input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D– input and the base to the D+ input.

Figure 23 and Figure 24 show how to connect the ADT7473 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D– input.

∆V

To me as u re

, the operating current through the sensor is

switched among three related currents. N1 × I and N2 × I are different multiples of the current I, as shown in

Figure 21. The

currents through the temperature diode are switched between

∆V

I and N1 × I, giving

∆V

giving two

∆V

. The temperature can then be calculated using the

BE2

measurements. This method can also cancel the effect

, and then between I and N2 × I,

BE1

of any series resistance on the temperature measurement.

The resulting ΔV

waveforms are passed through a 65 kHz

low-pass filter to remove noise and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to ΔV

. The ADC digitizes this

voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles.

The results of remote temperature measurements are stored in 10-bit, twos complement format, as listed in

Table 6 . The extra resolution for the temperature measurements is held in the extended resolution register 2 (Reg. 0x77). This gives temperature readings with a resolution of 0.25°C.

BIAS

LPF

= 65kHz

OUT+

OUT–

TO ADC

04686-023

REMOTE

SENSING

TRANSISTOR

I N1× IN2× I

D+

D–

Figure 21. Signal Conditioning for Remote Diode Temperature Sensors

Rev. 0 | Page 15 of 76

ADT7473

Noise Filtering

For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ pin and the D− pin to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. This capacitor reduces the noise, but does not eliminate it, making use of the sensor difficult in a very noisy environment.

The ADT7473 has a major advantage over other devices for eliminating the effects of noise on the external sensor. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. The effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result.

The construction of a filter allows the ADT7473 and the remote temperature sensor to operate in noisy environments. shows a low-pass R-C filter with the following values:

R = 100 Ω, C = 1 nF

This filtering reduces both common-mode noise and differential noise.

100Ω

REMOTE

EMPERATURE

SENSOR

Figure 22. Filter Between Remote Sensor and ADT7473

100Ω

1nF

SERIES RESISTANCE CANCELLATION

Parasitic resistance to the ADT7473 D+ and D− inputs (seen in series with the remote diode) is caused by a variety of factors including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.5°C offset per Ω of parasitic resistance in series with the remote diode.

The ADT7473 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of this resistance. The ADT7473 is designed to automatically cancel, typically, up to 3 kΩ of resistance. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. See the

Noise Filtering section for details.

D+

D–

Figure 22

04686-024

FACTORS AFFECTING DIODE ACCURACY

Remote Sensing Diode

The ADT7473 is designed to work with either substrate transistors built into processors or discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D−. If a PNP transistor is used, the collector and base are connected to D− and the emitter is connected to D+.

To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration:

•

The ideality factor, n

deviation of the thermal diode from ideal behavior. The ADT7473 is trimmed for an n following equation to calculate the error introduced at a temperature T (°C), when using a transistor whose n not equal 1.008. Refer to the data sheet for the related CPU to obtain the n

ΔT = (n

To factor this in, the user can write the ΔT value to the offset register. The ADT7473 then automatically adds it to or subtracts it from the temperature measurement.

•

Some CPU manufacturers specify the high and low current

levels of the substrate transistors. The high current level of the ADT7473, I

, is 6 μA. If the ADT7473 current levels do not match

LOW

the current levels specified by the CPU manufacturer, it might be necessary to remove an offset. The CPU’s data sheet advises whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. It is important to note that, if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register.

If a discrete transistor is used with the ADT7473, the best accuracy is obtained by choosing devices according to the following criteria:

•

Base-emitter voltage greater than 0.25 V at 6 μA, at the

highest operating temperature.

• Base-emitter voltage less than 0.95 V at 100 μA, at the

lowest operating temperature.

Base resistance less than 100 Ω.

•

Small variation in h

•

tight control of V

, of the transistor is a measure of the

value of 1.008. Use the

values.

− 1.008)/1.008 × (273.15 K + T)

, is 96 μA and the low level current,

HIGH

(such as 50 to 150) that indicates

characteristics.

does

Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23 packages, are suitable devices to use.

Rev. 0 | Page 16 of 76

ADT7473

Table 6. Twos Complement Temperature Data Format

Temperature Digital Output (10-Bit)1

–128°C –63°C –50°C –25°C –10°C 0°C

10.25°C

25.5°C

50.75°C 75°C 100°C 125°C 127°C

Bold numbers denote 2 LSB of measurement in extended resolution Register 2 (Reg. 0x77) with 0.25°C resolution.

1000 0000 00 (diode fault) 1100 0001 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00

Table 7. Extended Range, Temperature Data Format

Temperature Digital Output (10-Bit)1

–64°C –63°C –1°C 0°C 1°C 10°C 25°C 50°C 75°C 100°C 125°C 191°C

Bold numbers denote 2 LSB of measurement in extended resolution

N3904

NPN

Figure 23. Measuring Temperature Using an NPN Transistor

0000 0000 00 (diode fault) 0000 0001 00 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00

ADT7473

D+

D–

04686-025

Nulling Out Temperature Errors

As CPUs run faster, it becomes more difficult to avoid high frequency clocks when routing the D+/D– traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the D+/D– lines. Constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value.

The ADT7473 has temperature offset registers at addresses 0x70 and 0x72 for the Remote 1 and Remote 2 temperature channels. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The LSBs add 0.5°C offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to ±64°C with a resolution of 0.5°C. This ensures that the readings in the temperature measurement registers are as accurate as possible.

Temperature Offset Registers

Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0°C default)

Reg. 0x71 Local Temperature Offset = 0x00 (0°C default)

Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0°C default)

ADT7460/ADT7473 Backwards-Compatible Mode

By setting Bit 1 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value registers (0x25, 0x26, and 0x27) in twos complement in the range −63°C to +127°C. (The ADT7473 still makes calculations based on the Offset 64 extended range and clamps the results, if necessary.) The temperature limits must be reprogrammed in twos complement. If a twos complement temperature below

−63°C is entered, the temperature is clamped to −63°C. In this mode, the diode fault condition remains −128°C = 1000 0000, while in the extended temperature range (−64°C to +191°C), the fault condition is represented by −64°C = 0000 0000.

Temperature Measurement Registers

Reg. 0x25 Remote 1 Temperature

Reg. 0x26 Local Temperature

ADT7473

Reg. 0x27 Remote 2 Temperature

Reg. 0x77 Extended Resolution 2 = 0x00 default

D+

N3906

PNP

Figure 24. Measuring Temperature Using a PNP Transistor

D–

04686-026

Rev. 0 | Page 17 of 76

<7:6> TDM2, Remote 2 temperature LSBs.

<5:4> LTMP, Local temperature LSBs.

<3:2> TDM1, Remote 1 temperature LSBs.

ADT7473

Temperature Measurement Limit Registers

Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate

SMBALERT

interrupts.

Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default

Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default

Reg. 0x50 Local Temperature Low Limit = 0x01 default

Reg. 0x51 Local Temperature High Limit = 0x7F default

Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default

Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default

Reading Temperature from the ADT7473

It is important to note that the temperature can be read from the ADT7473 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order.

If the 10-bit measurement is required, a 2-register read for each measurement is used. The extended resolution register (Reg. 0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read, and vice versa.

ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT

A number of other functions are available on the ADT7473 to offer the system designer increased flexibility.

Turn-Off Averaging

For each temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off.

Table 8. Conversion Time with Averaging Disabled

Channel Measurement Time

Voltage Channel 0.7 ms Remote Temperature 1 7 ms Remote Temperature 2 7 ms Local Temperature 1.3 ms

Table 9. Conversion Time with Averaging Enabled

Channel Measurement Time

Voltage Channels 11 ms Remote Temperature 39 ms Local Temperature 12 ms

Single-Channel ADC Conversions

Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7473 into single-channel ADC conversion mode. In this mode, the ADT7473 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55).

Table 10. Programming Single-Channel ADC Mode for Temperatures

Bits <7:5> Reg. 0x55 Channel Selected

101 Remote 1 Temperature 110 Local Temperature 111 Remote 2 Temperature

Configuration Register 2 (Reg. 0x73)

<4> = 1, averaging off.

<6> = 1, single-channel convert mode.

TACH1 Minimum High Byte (Reg. 0x55)

<7:5> selects ADC channel for single-channel convert mode.

Overtemperature Events

Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Reg. 0x6A to Reg. 0x6C are the

When a temperature exceeds its

outputs run at 100% duty cycle or the maximum PWM duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A) if bit 3 of Configuration Register 4, Reg. 0x7D is set. The fans remain running at this speed until the temperature drops below THERM boost bit in Configuration Register 3, Bit 2, Reg. 0x78. The hysteresis value for that

into the hysteresis registers (Reg. 0x6D and Reg. 0x6E). The default hysteresis value is 4°C.

THERM LIMIT

TEMPERATURE

FANS

limits.

THERM

limit, all PWM

minus hysteresis; this can be disabled by setting the

THERM

Figure 25.

limit is the value programmed

HYSTERESIS (°C)

100%

THERM

Limit Operation

04686-027

Rev. 0 | Page 18 of 76

ADT7473

LIMITS, STATUS REGISTERS, AND INTERRUPTS

LIMIT VALUES

Associated with each measurement channel on the ADT7473 are high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and is detected by polling the device. Alternatively, SMBALERT microcontroller of out-of-limit conditions.

interrupts can be generated to flag a processor or

Fan Limit Registers

Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default

Reg. 0x55 TACH1 Minimum High Byte = 0xFF default

Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default

Reg. 0x57 TACH2 Minimum High Byte = 0xFF default

8-Bit Limits

The following is a list of 8-bit limits on the ADT7473.

Voltage Limit Registers

Reg. 0x46 V

Reg. 0x47 V

Reg. 0x48 V

Reg. 0x49 V

Low Limit = 0x00 default

CCP

High Limit = 0xFF default

CCP

Low Limit = 0x00 default

High Limit = 0xFF default

Temperature Limit Registers

Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default

Reg. 0x4F Remote 1 Temperature High Limit = 0xFF default

Reg. 0x6A Remote 1

THERM

Limit = 0xA4 default

Reg. 0x50 Local Temperature Low Limit = 0x01 default

Reg. 0x51 Local Temperature High Limit = 0xFF default

Reg. 0x6B Local

THERM

Limit = 0xA4 default

Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default

Reg. 0x53 Remote 2 Temperature High Limit = 0xFF default

Reg. 0x6C Remote 2

THERM

Reg. 0x7A

Limit Register

THERM

Limit = 0x00 default

Limit = 0xA4 default

16-Bit Limits

The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Because fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan TACHs. Because the fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan.

Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default

Reg. 0x59 TACH3 Minimum High Byte = 0xFF default

Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default

Reg. 0x5B TACH4 Minimum High Byte = 0xFF default

Out-of-Limit Comparisons

Once all limits have been programmed, the ADT7473 can be enabled for monitoring. The ADT7473 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit.

High Limit: > Comparison Performed Low Limit: ≤ Comparison Performed

Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit. This fan limit is needed only in manual fan control mode.

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). By default, the ADT7473 powers up with this bit set. The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1.

As the ADC is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time.

For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is

•

Rev. 0 | Page 19 of 76

One dedicated supply voltage input (V

•

Supply voltage (V

•

Local temperature

•

Two remote temperatures

pin)

CCP

)

ADT7473

As mentioned previously, the ADC performs round-robin conversions. The total monitoring cycle time for averaged voltage and temperature monitoring is 146 ms. The total monitoring cycle time for voltage and temperature monitoring with averaging disabled is 19 ms. The ADT7473 is a derivative of the ADT7467. As a result, the total conversion time in the ADT7473 is the same as the total conversion time of the ADT7467, even though the ADT7473 has fewer monitored channels.

Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way.

STATUS REGISTERS

The results of limit comparisons are stored in Status Register 1 and Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out of limits, the corresponding status register bit is set to 1.

The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Status Register 1 (Reg. 0x41), 1 means an out-of-limit event has been flagged in Status Register 2. This means the user needs only to read Status Register 2 when this bit is set. Alternatively, Pin 5 or Pin 9 can be configured as an

SMBALERT

automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are sticky. Whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone away. Interrupt status mask registers (Reg. 0x74, 0x75) allow individual interrupt sources to be masked from causing an

SMBALERT

. However, if one of these masked

interrupt sources goes out of limit, its associated status bit is set in the interrupt status registers.

Status Register 1 (Reg. 0x41)

Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read.

Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has been exceeded.

Bit 5 (LT) = 1, Local temperature high or low limit has been exceeded.

Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has been exceeded.

output. This

Status Register 2 (Reg. 0x42)

Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.

Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.

Bit 5 (F4P) = 1, indicates Fan 4 has dropped below the minimum speed. Alternatively, indicates the

been exceeded, if the

THERM

function is used.

THERM

limit has

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below the minimum speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below the minimum speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below the minimum speed.

Bit 1 (OVT) = 1, indicates a

THERM

overtemperature limit has

been exceeded.

SMBALERT

The ADT7473 can be polled for status, or an

Interrupt Behavior

SMBALERT

interrupt can be generated for out-of-limit conditions. It is important to note how the

SMBALERT

output and status bits

behave when writing interrupt handler software.

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

STICKY

STATUS BIT

TEMP BACK IN LIMIT

SMBALERT

(STATUS BIT STAYS SET)

Figure 26.

SMBALERT

Figure 26 shows how the

and Status Bit Behavior

SMBALERT

(TEMP BELOW LIMIT)

output and sticky status

bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky because they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. Note that the

SMBALERT

output remains low for the entire duration that

a reading is out of limit and until the status register has been read. This has implications on how software handles the interrupt.

04686-028

Bit 2 (V

Bit 1 (V

) = 1, VCC high or low limit has been exceeded.

CCP

) = 1, V

high or low limit has been exceeded.

CCP

Rev. 0 | Page 20 of 76

ADT7473

Handling

SMBALERT

Interrupts

To prevent the system from being tied up servicing interrupts, it is recommend handling the

Detect the

Enter the interrupt handler. Read the status registers to identify the interrupt source.

Mask the interrupt source by setting the appropriate mask

SMBALERT

assertion.

interrupt as follows:

bit in the interrupt mask registers (Reg. 0x74, Reg. 0x75).

Take the appropriate action for a given interrupt source. Exit the interrupt handler.

Periodically poll the status registers. If the interrupt status

7. bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the

behave as shown in

HIGH LIMIT

TEMPERATURE

STICKY

TATUS BI

SMBALERT

Figure 27. How Masking the Interrupt Source Affects

SMBALERT

Figure 27.

TEMP BACK IN LIMIT (STATUS BIT STAYS SET)

INTERRUPT MASK BIT SET

output and status bits to

CLEARED ON READ

(TEMP BELOW LIMIT)

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

SMBALERT

Output

Masking Interrupt Sources

Interrupt Mask Register 1 is located at Address 0x74; Interrupt Mask Register 2 is located at Address 0x75. These allow individual interrupt sources to be masked out to prevent SMBALERT only the

interrupts. Masking an interrupt source prevents

SMBALERT

output from being asserted; the

appropriate status bit is set normally.

Interrupt Mask Register 1 (Reg. 0x74)

Bit 7 (OOL) = 1, masks

SMBALERT

for any alert condition

flagged in Status Register 2.

Bit 6 (R2T) = 1, masks

Bit 5 (LT) = 1, masks

Bit 4 (R1T) = 1, masks

Bit 2 (V

) = 1, masks

SMBALERT

for Remote 2 temperature.

for local temperature.

for Remote 1 temperature.

for VCC channel.

04686-029

Interrupt Mask Register 2 (Reg. 0x75)

Bit 7 (D2) = 1, masks

Bit 6 (D1) = 1, masks

Bit 5 (FAN4) = 1, masks

SMBALERT

If the TACH4 pin is being used as the masks

SMBALERT

Bit 4 (FAN3) = 1, masks

Bit 3 (FAN2) = 1, masks

Bit 2 (FAN1) = 1, masks

Bit 1 (OVT) = 1, masks (exceeding

Enabling the

The

SMBALERT

for a

THERM

SMBALERT

THERM

limits).

SMBALERT

interrupt function is disabled by default. Pin 5

or Pin 9 can be reconfigured as an

for Diode 2 errors.

for Diode 1 errors.

for Fan 4 failure.

THERM

event.

for Fan 3.

for Fan 2.

for Fan 1.

for overtemperature

Interrupt Output

SMBALERT

input, this bit

output to signal

out-of-limit conditions.

Table 11. Configuring Pin 5 as

Configuration Register 3 (Reg. 0x78) <0> ALERT = 1

Assigning

THERM

Functionality to a Pin

SMBALERT

Output

Pin 9 on the ADT7473 has four possible functions: SMBus ALERT,

THERM

, GPIO, and TACH4. The user chooses the

required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.

Bit 0 Bit 1 Function

00 TACH4 01

10 SMBus ALERT 11 GPIO

Once Pin 9 is configured as

THERM

, it must be enabled (Bit 1,

Configuration Register 3 at Address 0x78).

THERM

When time assertions on the connecting to the

performance. See the

as an Input

THERM

is configured as an input, the ADT7473 can

THERM

PROCHOT

THERM

pin. This can be useful for

output of a CPU to gauge system

Timer section for more

information.

Bit 0 (V

) = 1, masks

CCP

SMBALERT

for V

channel.

CCP

Rev. 0 | Page 21 of 76

ADT7473

The user can also set up the ADT7473 so that, when the THERM fans run at 100% for the duration of the time the

pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (Address 0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above T T pulling the

for more information.

pin is driven low externally, the fans run at 100%. The

THERM

. If the temperature is below

MIN

or if the duty cycle in manual mode is set to 0x00, then

MIN

THERM

MIN

low externally has no effect. See Figure 28

pin is

When using the

After a

THERM

The contents of the timer are cleared on read.

The F4P bit (Bit 5) of Status Register 2 needs to be cleared

THERM

timer read (Reg. 0x79):

(assuming that the

timer, be aware of the following.

THERM

timer limit has been

exceeded).

If the

THERM

timer is read during a

THERM

assertion, then

the following happens:

The contents of the timer are cleared.

Bit 0 of the

THERM

timer is set to 1 (because a

THERM

assertion is occurring).

THERM

THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100 % BECAUS E TEMPERATURE IS BEL OW T

Figure 28. Asserting

in Automatic Fan Speed Control Mode

MIN

THERM ASSERTED TO LOWAS AN INPUT: FANS DO NOT GO TO 1 00% BE CAUSE TEMPERATURE IS ABOVE T ARE ALREAD Y RUNNI NG.

THERM

Low as an Input

AND FANS

MIN

THERM TIMER

The ADT7473 has an internal timer to measure assertion time. For example, the connected to the

PROCHOT

measure system performance. The

THERM

output of a Pentium 4 CPU to

THERM

input can be

input can also be

connected to the output of a trip point temperature sensor.

The timer is started on the assertion of the ADT7473’s input and stopped when counts

THERM

counting on the next

times cumulatively; that is, the timer resumes

THERM

continues to accumulate

THERM

is deasserted. The timer

assertion. The

THERM

assertion times until the

timer is read (it is cleared on read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared.

The 8-bit

THERM Bit 0 is set to 1 on the first tive

THERM

timer is set and Bit 0 now becomes the LSB of the

timer with a resolution of 22.76 ms (see

timer register (Reg. 0x79) is designed so that

THERM

assertion. Once the cumula-

assertion time has exceeded 45.52 ms, Bit 1 of the

Figure 29).

THERM

timer

3. The

If the

THERM

timer increments from 0.

THERM

timer limit (Reg. 0x7A) = 0x00, the F4P bit

is set.

THERM

TIMER

(REG. 0x79)

04686-030

THERM

TIMER

(REG. 0x79)

THERM

TIMER

(REG. 0x79)

Generating

000 00010 765 32104

ACCUMULATE THERM LOW

ASSERTION TIMES

000 00100 765 32104

ACCUMULATE THERM LOW

ASSERTION TIMES

000 01010 765 32104

Figure 29.Understanding the

SMBALERT

Interrupts from

THERM ASSERTED

≤ 22.76ms

THERM ASSERTED

≥ 45.52ms

THERM ASSERTED ≥ 113.8ms

(91.04ms + 22.76ms)

THERM

Timer

THERM

Timer

04686-031

Events

The ADT7473 can generate ble

THERM

timer limit is exceeded. This allows the system

SMBALERT

designer to ignore brief, infrequent capturing longer

THERM

timer limit register. This 8-bit register allows a limit from 0 sec (first an

SMBALERT

THERM

is generated. The

timer events. Register 0x7A is the

assertion) to 5.825 sec to be set before

compared with the contents of the

s when a programma-

THERM

assertions, while

timer value is

timer limit register.

Rev. 0 | Page 22 of 76

ADT7473

If the

THERM value, the F4P bit (Bit 5) of Status Register 2 is set and an SMBALERT (Reg. 0x75) masks out

however, the F4P bit of Interrupt Status Register 2 still is set if the

THERM

Figure 30 is a functional block diagram of the limit, and associated circuitry. Writing a value of 0x00 to the

THERM to be generated on the first limit value of 0x01 generates an

THERM

Configuring the

1. Configure Pin 9 as a

Setting Bit 1 ( Register 3 (Reg. 0x78) enables the monitoring functionality. This is disabled on Pin 9 by

default.

Setting Bits 0 and 1 (PIN9FUNC) of Configuration Register 4 (Reg. 0x7D) enables

functionality on Pin 9 (Bit 1 of Configuration Register 3, THERM TACH4.

Setting Bits 5, 6, and 7 of Configuration Register 5 (0x7C) makes

appropriate temperature channel exceeds the temperature limit, the ADT7473 is not pulling

pulled low by an external device (such as a CPU overtemperature signal), the

THERM

If Bits 5, 6, and 7 of Configuration Register 5 (0x7C) are 0, THERM

timer value exceeds the

is generated. The F4P bit (Bit 5) of Mask Register 2

SMBALERT

timer limit is exceeded.

timer limit register (Reg. 0x7A) causes an

THERM

assertions exceed 45.52 ms.

THERM

, must also be set). Pin 9 can also be used as

THERM

assertions.

is set as a timer input only.

Behavior

THERM

timer enable) of Configuration

bidirectional. This means that if the

THERM

s if this bit is set to 1;

assertion. A

SMBALERT

timer input.

THERM

output asserts. If the

low, but

THERM

timer limit

THERM

once cumulative

timer/output

THERM

timer also times

timer,

SMBALERT

THERM

timer

THERM

timer

Select the desired fan behavior for

Assuming the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (Reg. 0x78) causes all fans to run at 100% duty cycle whenever

allows fail-safe system cooling. If this bit is 0, the fans run at their current settings and are not affected by

events. If the fans are not already running when

asserted, the fans do not run at full speed.

Select whether

SMBALERT

Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks out

SMBALERT exceeded. This bit should be cleared if on

THERM

Select a suitable

This value determines whether an on the first

THERM causes an assertion.

Select a

This value specifies how often OS or BIOS level software checks the

THERM

the

THERM

tive

If, for example, the total <22.76 ms in Hour 1, >182.08 ms in Hour 2, and >5.825

sec in Hour 3, this can indicate that system performance is degrading significantly because

frequently on an hourly basis.

Alternatively, OS- or BIOS-level software can timestamp when the system is powered on. If an

generated due to the

another timestamp can be taken. The difference in time can be calculated for a fixed

example, if it takes one week for a

2.914 sec to be exceeded and the next time it takes only one hour, this is an indication of a serious degradation in system performance.

THERM

interrupts.

events are required.

THERM

assertion time limit is exceeded. A value of 0x00

SMBALERT

THERM

timer once an hour to determine the cumula-

assertion time.

timer events should generate

s when the

THERM

monitoring time.

limit value.

assertion, or only if a cumulative

to be generated on the first

timer. For example, BIOS could read

THERM

SMBALERT

assertion time is

THERM

timer limit being exceeded,

THERM

timer events.

is asserted. This

THERM

timer limit value is

SMBALERT

is asserting more

SMBALERT

timer limit time. For

timer limit of

s based

is generated

THERM

Rev. 0 | Page 23 of 76

+ 53 hidden pages

ANALOG DEVICES ADT7473 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

THERMAL CHARACTERISTICS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

PRODUCT DESCRIPTION

COMPARISON BETWEEN ADT7467 AND ADT7473

RECOMMENDED IMPLEMENTATION

SERIAL BUS INTERFACE

WRITE OPERATIONS

READ OPERATIONS

SMBus TIMEOUT

VOLTAGE MEASUREMENT INPUT

ANALOG-TO-DIGITAL CONVERTER

INPUT CIRCUITRY

VOLTAGE MEASUREMENT REGISTERS

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS

TEMPERATURE MEASUREMENT METHOD

SERIES RESISTANCE CANCELLATION

FACTORS AFFECTING DIODE ACCURACY

ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT

LIMITS, STATUS REGISTERS, AND INTERRUPTS

LIMIT VALUES

STATUS REGISTERS