Analog Devices ADT7463 c Datasheet
dB
COOL™ Remote Thermal
a
FEATURES
Monitors up to 5 Supply Voltages
Controls and Monitors up to 4 Fan Speeds
1 On-Chip and 2 Remote Temperature Sensors
Monitors up to 6 Processor VID Bits
Dynamic T
Acoustics Intelligently
Automatic Fan Speed Control Mode Controls System
Cooling Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User
Perception of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel
Processor Thermal Control Circuit via THERM Input
2-Wire and 3-Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
APPLICATIONS
Low Acoustic Noise PCs
Networking and Telecommunications Equipment
Control Mode Optimizes System
MIN
®
Pentium® 4
FUNCTIONAL BLOCK DIAGRAM
VID5
VID4
VID3
VID2
VID1
VID0
PWM1
PWM2
PWM3
TACH1
TACH2
TACH3
TACH4
THERM
V
D1+
D1–
D2+
D2–
V
+5V
+12V
+2.5V
V
CCP
CC
CC
IN
IN
IN
PWM
REGISTERS
AND
CONTROLLERS
VCC TO ADT7463
BAND GAP
TEMP. SENSOR
ENHANCEMENT
FAN SPEED
PERFORMANCE
MONITORING
PROTECTION
CONDITIONING
MULTIPLEXER
VID
REGISTER
ACOUSTIC
CONTROL
COUNTER
THERMAL
INPUT
SIGNAL
AND
ANALOG
Controller and Voltage Monitor
ADT7463
GENERAL DESCRIPTION
The ADT7463 dBCOOL controller is a complete systems
monitor and multiple PWM fan controller for noise-sensitive
applications requiring active system cooling. It can monitor
12 V, 5 V, and 2.5 V CPU supply voltages, plus its own supply
voltage. It can monitor the temperature of up to two remote
sensor diodes, plus its own internal temperature. It can measure
and control the speed of up to four fans so that they operate at the
lowest possible speed for minimum acoustic noise. The automatic
fan speed control loop optimizes fan speed for a given temperature.
A unique dynamic T
thermals/acoustics to be intelligently managed. The effectiveness
of the system’s thermal solution can be monitored using the
THERM input. The ADT7463 also provides critical thermal
protection to the system using the bidirectional THERM pin
as an output to prevent system or component overheating.
ADDR
SELECT
ADDRESS
SELECTION
GND
SMBUS
ADT7463
ADDR EN
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
10-BIT
ADC
BAND GAP
REFERENCE
SCL
SDA
SERIAL BUS
INTERFACE
control mode enables the system
MIN
SMBALERT
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
INTERRUPT
STATUS
REGISTERS
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
*
*Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
ADT7463–SPECIFICATIONS
1, 2, 3, 4
(TA = T
MIN
to T
, VCC = V
MAX
MIN
to V
, unless otherwise noted.)
MAX
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 5.0 5.5 V
Supply Current, I
CC
3mAInterface Inactive, ADC Active
20 µA Standby Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy ± 0.5 ±1.5 ⬚C0⬚C ⱕ TA ⱕ 70⬚C
± 3 ⬚C –40⬚C ⱕ T
ⱕ +120⬚C
A
Resolution 0.25 ⬚C
Remote Diode Sensor Accuracy ± 0.5 ±1.5 ⬚C
± 2.5 ⬚C
± 3 ⬚C
0⬚C ⱕ TA ⱕ 70⬚C; 0⬚C ⱕ TD ⱕ 120⬚C
0⬚C ⱕ TA ⱕ 105⬚C; 0⬚C ⱕ TD ⱕ 120⬚C
0⬚C ⱕ TA ⱕ 120⬚C; 0⬚C ⱕ TD ⱕ 120⬚C
Resolution 0.25 ⬚C
Remote Sensor Source Current 180 µAHigh Level
11 µALow Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE ± 1.5 %
Differential Nonlinearity, DNL ± 1 LSB
Power Supply Sensitivity ± 0.1 %/V
Conversion Time (Voltage Input) 11.38 13 ms Averaging Enabled
Conversion Time (Local Temperature) 12.09 13.50 ms Averaging Enabled
Conversion Time (Remote Temperature) 25.59 28 ms Averaging Enabled
Total Monitoring Cycle Time 120.17 134.50 ms Averaging Enabled
Total Monitoring Cycle Time 13.51 15 ms Averaging Disabled
Input Resistance 100 140 200 kΩ
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ± 7%0⬚C ⱕ TA ⱕ 70⬚C
± 11 % 0⬚C ⱕ T
± 13 % –40⬚C ⱕ T
ⱕ 105⬚C
A
ⱕ +120⬚C
A
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan Count = 0xBFFF
329 RPM Fan Count = 0x3FFF
5,000 RPM Fan Count = 0x0438
10,000 RPM Fan Count = 0x021C
Internal Clock Frequency 82.8 90.0 97.2 kHz
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 to PWM3, XTO
Current Sink, I
Output Low Voltage, V
High Level Output Current, I
OL
OL
OH
0.1 1 µAV
8.0 mA
0.4 V I
= –8.0 mA, VCC = 3.3 V
OUT
= V
OUT
CC
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, V
High Level Output Current, I
OL
OH
0.4 V I
0.1 1 µAV
= –4.0 mA, VCC = 3.3 V
OUT
= V
OUT
CC
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
Input Low Voltage, V
IL
IH
2.0 V
0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS
(VID0 to VID5)
Input High Voltage, V
Input Low Voltage, V
IL
Input High Voltage, V
Input Low Voltage, V
IL
IH
IH
1.7 V Bit 6 (THLD) Reg. 0x43 = 0
0.8 V (VID Threshold = 1 V)
0.8 V Bit 6 (THLD) Reg. 0x43 = 1
0.4 V (VID Threshold = 0.6 V)
REV. C–2–
ADT7463
Parameter Min Typ Max Unit Test Conditions/Comment
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, V
Input Low Voltage, V
IH
IL
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS
(THERM) AGTL+
Input High Voltage, V
Input Low Voltage, V
IH
IL
DIGITAL INPUT CURRENT
Input High Current, I
Input Low Current, I
Input Capacitance, C
SERIAL BUS TIMING
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Detect Clock Low Timeout, t
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at TA = 25°C and represent the most likely parametric norm.
3
Logic inputs accept input high voltages up to V
4
Timing specifications are tested at logic levels of V
5
Guaranteed by design, not production tested.
Specifications subject to change without notice.
SCLK
SW
BUF
SU;STA
HD;STA
LOW
HIGH
SU;DAT
HD;DAT
IH
IL
IN
5
R
F
TIMEOUT
even when the device is operating down to V
MAX
= 0.8 V for a falling edge and V
IL
2.0 V
5.5 V Maximum Input Voltage
+0.8 V
–0.3 V Minimum Input Voltage
0.75 ⫻ V
CCP
V
0.4 V
–1 µAV
+1 µAV
IN
IN
= V
= 0
CC
5pF
400 kHz See Figure 1
50 ns See Figure 1
1.3 µsSee Figure 1
0.6 µsSee Figure 1
0.6 µsSee Figure 1
1.3 µsSee Figure 1
0.6 50 µsSee Figure 1
1000 ns See Figure 1
300 µsSee Figure 1
100 ns See Figure 1
300 ns See Figure 1
15 35 ms Can Be Optionally Disabled
.
= 2.0 V for a rising edge.
IH
MIN
REV. C
SCL
SDA
t
BUF
PS
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
HD;STA
t
SU;STA
S
t
SU;STO
P
Figure 1. Diagram for Serial Bus Timing
–3–
ADT7463
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on +12V
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
IN
Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
IR Reflow Peak Temperature for Pb-free . . . . . . . . . . 260°C
Lead Temperature (soldering 10 sec) . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
24-Lead QSOP Package:
= 105°C/W, θ
θ
JA
= 39°C/W.
JC
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADT7463ARQ
ADT7463ARQ-REEL
ADT7463ARQ-REEL7
ADT7463ARQZ*
ADT7463ARQZ-REEL*
ADT7463ARQZ-REEL7*
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
–40⬚C to +120⬚C 24-Lead QSOP RQ-24
EVAL-ADT7463EB
*Z = Pb-free part.
SDA
SCL
GND
V
CC
VID0
VID1
VID2
VID3
TACH3
PWM2/SMBALERT
TACH1
TACH2
Evaluation Board
PIN CONFIGURATION
1
2
3
4
5
ADT7463
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
24
PWM1/XTO
23
V
CCP
22
+2.5VIN/SMBALERT
21
+12V
/VID5
IN
20
+5V
/THERM
IN
19
VID4
18
D1+
17
D1–
16
D2+
15
D2–
14
TACH4/ADDRESS SELECT/THERM
13
PWM3/ADDRESS ENABLE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADT7463 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C–4–
ADT7463
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus.
2 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
3 GND Ground Pin for the ADT7463.
4V
CC
5 VID0 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
6 VID1 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
7 VID2 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
8 VID3 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog
10 PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control FAN 2
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog
12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog
13 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/Fan 4 speed. Requires 10 kΩ typical
ADDRESS ENABLE If pulled low on power-up, this places the ADT7463 into address select mode, and the state of Pin 14 will determine
14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog
ADDRESS If in address select mode, this pin determines the SMBus device address.
SELECT
THERM Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
15 D2– Cathode Connection to Second Thermal Diode.
16 D2+ Anode Connection to Second Thermal Diode.
17 D1– Cathode Connection to First Thermal Diode.
18 D1+ Anode Connection to First Thermal Diode.
19 VID4 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
20 +5V
IN
THERM Alternatively, this pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
21 +12V
IN
VID5 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
22 +2.5V
IN
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
23 V
CCP
24 PWM1/ Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
XTO Also functions as the output from the XOR tree in XOR test mode.
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also
monitored through this pin. The ADT7463 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the V
input attenuators to correctly measure a 5 V supply.
CC
input (AIN3) to measure the speed of 2-wire fans.
speed.
out-of-limit conditions.
input (AIN1) to measure the speed of 2-wire fans.
input (AIN2) to measure the speed of 2-wire fans.
pull-up.
the ADT7463’s slave address.
input (AIN4) to measure the speed of 2-wire fans.
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
Analog Input. Monitors 5 V power supply.
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
Analog Input. Monitors 12 V power supply.
Supports VRM10 solutions.
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
out-of-limit conditions.
Analog Input. Monitors processor core voltage (0 V to 3 V).
REV. C
–5–
ADT7463
FUNCTIONAL DESCRIPTION
General Description
The ADT7463 is a complete systems monitor and multiple fan
controller for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The serial bus controller has an optional
address line for device selection (Pin 14), a serial data line
for reading and writing addresses and data (Pin 1), and an input
line for the serial clock (Pin 2). All control and programming
functions of the ADT7463 are performed over the serial bus. In
addition, two of the pins can be reconfigured as an SMBALERT
output to indicate out-of-limit conditions.
Measurement Inputs
The device has six measurement inputs, four for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip temperature sensor.
Pins 20 through 23 are analog inputs with on-chip attenuators,
configured to monitor 5 V, 12 V, 2.5 V, and the processor core
voltage (2.25 V input), respectively.
Power is supplied to the chip via Pin 4, and the system also
monitors V
through this pin. In PCs, this pin is normally
CC
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1⫾ and D2⫾
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature.
Sequential Measurement
When the ADT7463 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are stored
in the status registers, which can be read over the serial bus to
flag out-of-limit conditions.
Processor Voltage ID
Five digital inputs (VID0 to VID5—Pins 5 to 8, 19, and 21) read
the processor voltage ID code and store it in the VID register,
from which it can be read out by the management system over
the serial bus. The VID code monitoring function is compatible
with both VRM9.x and future VRM10 solutions. Additionally,
an SMBALERT can be generated to flag a change in VID code.
ADT7463 Address Selection
Pin 13 is the dual-function PWM3/ADDRESS ENABLE pin.
If Pin 13 is pulled low on power-up, the ADT7463 reads the
state of Pin 14 (TACH4/ADDRESS SELECT/ THERM pin) to
determine the ADT7463’s slave address. If Pin 13 is high on
power-up, then the ADT7463 defaults to the SMBus slave
Address 0x2E. This function is described in more detail later.
INTERNAL REGISTERS OF THE ADT7463
A brief description of the ADT7463’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables IV to XLII.
Configuration Registers
The configuration registers provide control and configuration of
the ADT7463, including alternate pinout functionality.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7463, the first byte
of data is always a register address, which is written to the
address pointer register.
Status Registers
These registers provide the status of each limit comparison and
are used to signal out-of-limit conditions on the temperature,
voltage, or fan speed channels. If Pin 10 or Pin 22 is configured as SMBALERT, then this pin asserts low whenever a
status bit gets set.
Interrupt Mask Registers
These registers allow each interrupt status event to be masked
when Pin 10 or Pin 22 is configured as an SMBALERT output.
VID Register
The status of the VID0 to VID5 pins of the processor can read
from this register. VID code changes can also generate
SMBALERT interrupts.
Value and Limit Registers
The results of analog voltage inputs, temperature, and fan speed
measurements are stored in these registers, along with their
limit values.
Offset Registers
These registers allow each temperature channel reading to be
offset by a twos complement value written to these registers.
T
Registers
MIN
These registers program the starting temperature for each fan
under automatic fan speed control.
T
Registers
RANGE
These registers program the temperature-to-fan speed control
slope in automatic fan speed control mode for each PWM output.
Operating Point Registers
These registers define the target operating temperatures for each
thermal zone when running under dynamic T
control. This
MIN
function allows the cooling solution to adjust dynamically in
response to measured temperature and system performance.
Enhance Acoustics Registers
These registers allow each PWM output controlling fan to be
tweaked to enhance the system’s acoustics.
REV. C–6–
Typical Performance Characteristics–ADT7463
15
10
5
0
–5
–10
–15
REMOTE TEMPERATURE ERROR (ⴗC)
–20
1.0 3.3 100.0
DXP TO GND
DXP TO VCC (3.3V)
LEAKAGE RESISTANCE (M⍀)
10.0 30.0
TPC 1. Remote Temperature Error
vs. Leakage Resistance
3
2
1
0
–1
–2
LOCAL TEMPERATURE ERROR ( C)
–3
–40 10 110
HIGH LIMIT
+3 SIGMA
–3 SIGMA
LOW LIMIT
60
TEMPERATURE ( C)
TPC 4. Local Temperature Error
vs. Actual Temperature
3
0
–3
REMOTE TEMPERATURE
–6
–9
–12
–15
–18
–21
–24
–27
–30
REMOTE TEMPERATURE ERROR (ⴗC)
–33
–36
1.0 10.0
ERROR (ⴗC)
2.2 3.3 4.7 22.0 47.0
DXP TO DXN CAPACITANCE (nF)
TPC 2. Remote Temperature Error
vs. Capacitance between D+ and D–
14
12
10
8
6
4
2
0
REMOTE TEMPERATURE ERROR (ⴗC)
–2
100k 550k 50M
250mV
100mV
5M
FREQUENCY (Hz)
TPC 5. Remote Temperature Error
vs. Power Supply Noise Frequency
3
2
1
0
–1
–2
REMOTE TEMPERATURE ERROR ( C)
–3
–40
HIGH LIMIT
+3 SIGMA
–3 SIGMA
LOW LIMIT
10 60 110
TEMPERATURE ( C)
TPC 3. Remote Temperature Error
vs. Actual Temperature
12.5
10.0
7.5
5.0
2.5
0
–2.5
LOCAL TEMPERATURE ERROR (ⴗC)
–5.0
100k 550k 50M
250mV
100mV
5M
FREQUENCY (Hz)
TPC 6. Local Temperature Error vs.
Power Supply Noise Frequency
1.9
1.8
1.7
1.6
SUPPLY CURRENT (mA)
1.5
1.4
2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
SUPPLY VOLTAGE (V)
TPC 7. Supply Voltage vs.
Supply Current
REV. C
16
14
12
10
8
6
4
2
0
REMOTE TEMPERATURE ERROR (ⴗC)
–2
60k
110k 1M 10M 50M
20mV
10mV
FREQUENCY (Hz)
TPC 8. Remote Temperature Error vs.
Differential Mode Noise Frequency
–7–
40
35
30
25
20
15
10
5
0
–5
REMOTE TEMPERATURE ERROR (ⴗC)
–10
10k
100mV
40mV
20mV
100k 1M 10M
FREQUENCY (Hz)
TPC 9. Remote Temperature Error vs.
Common-Mode Noise Frequency
ADT7463
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
CONTROLLER
ADP316x
VRM
V
COMP
TACH2
PWM3
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
Figure 2. Recommended Implementation
RECOMMENDED IMPLEMENTATION
Configuring the ADT7463 as in Figure 2 allows the systems
designer the following features:
•
Six VID inputs (VID0 to VID5) for VRM10 support.
•
Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (V
•
2.5 V measurement input used to monitor CPU current
(connected to V
output of ADP316x VRM controller).
COMP
CORE
).
This is used to determine CPU power consumption.
•
5 V measurement input.
ADT7463
PWM1
TACH1
VID[0:4]/VID[0:5]
THERM
SMBALERT
GND
•
VRM temperature uses local temperature sensor.
•
CPU temperature measured using Remote 1 temperature
5(VRM9)/6(VRM10)
D2+
D2–
PROCHOT
SDA
SCL
channel.
•
Ambient temperature measured through Remote 2 temperature
channel.
•
If not using VID5, this pin can be reconfigured as the 12 V
monitoring input.
•
Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT
monitoring and can function as an overtemperature THERM
output.
•
SMBALERT system interrupt output.
See the AN-612 ADT7463 Configuration application note for more
information and register settings for all possible configurations
(www.analog.com/UploadedFiles/Application_Notes/408599520AN612_0.pdf).
REV. C–8–
ADT7463
SERIAL BUS INTERFACE
Control of the ADT7463 is carried out using the serial system
management bus (SMBus). The ADT7463 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7463 has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high,
the ADT7463 has a default SMBus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address. If
more than one ADT7463 is used in a system, then each ADT7463
should be placed in address select mode by strapping Pin 13 low on
power-up. The logic state of Pin 14 then determines the device’s
SMBus address. The logic of these pins is sampled upon power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely on the low-to-high transition
at the beginning of the 8th SCL pulse, when the serial bus address
byte matches the selected slave address. The selected slave address
is chosen using the address enable/address select pins. Any
attempted changes in the address will have no effect after this.
Table I. Address Select Mode
Pin 13 State Pin 14 State Address
0Low (10 kΩ to GND) 0101100 (0x2C)
0High (10 kΩ Pull-Up) 0101101 (0x2D)
1Don’t Care 0101110 (0x2E)
(Default)
V
ADT7463
ADDR_SEL
PWM3/ADDR_EN
CC
14
10k⍀
13
ADDRESS = 0x2E
Figure 3. Default SMBus Address = 0x2E
ADT7463
10k⍀
ADDR_SEL
PWM3/ADDR_EN
14
13
ADDRESS = 0x2C
Figure 4. SMBus Address = 0x2C (Pin 14 = 0)
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices sharing
the same serial bus, for example, if more than one ADT7463 is
used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
V
CC
ADT7463
ADDR_SEL
PWM3/ADDR_EN
10k⍀
14
13
ADDRESS = 0x2D
Figure 5. SMBus Address = 0x2D (Pin 14 = 1)
V
CC
ADT7463
ADDR_SEL
PWM3/ADDR_EN
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM 3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7463 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7463 IS PLACED INTO ADDRESS SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATE
FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME.
10k⍀
14
13
NC
DO NOT LEAVE ADDR_EN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
Figure 6. Unpredictable SMBus Address if Pin 13
Is Unconnected
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, then the master writes to the
slave device. If the R/W bit is a 1, the master reads from
the slave device.
REV. C
–9–
ADT7463
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master pulls the data line
high during the tenth clock pulse to assert a STOP condition.
In READ mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse. This is known as No Acknowledge.
The master then takes the data line low during the low period before the 10th clock pulse, and then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
19
SCL
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7463, write operations contain either one
or two bytes, and read operations contain one byte and perform
the following functions.
To write data to one of the device data registers or read data from
it, the address pointer register must be set so that the correct data
register is addressed, then data can be written into that register
or read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data
is to be written to the device, then the write operation contains
a second data byte that is written to the register selected by the
address pointer register.
This is illustrated in Figure 7. The device address is sent over
the bus followed by R/W being set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
1
9
SDA
START BY
MASTER
0
10
SERIAL BUS ADDRESS
1
1
FRAME 1
BYTE
SCL (CONTINUED)
SDA (CONTINUED)
A0
A1
R/W
ACK. BY
ADT7463
1
D7
D7
D6
D6
ADDRESS POINTER REGISTER BYTE
D5
D5
D4
D4
FRAME 2
D3
FRAME 3
DATA
BYTE
D3
D2
D2
D1
D1
D0
D0
9
ACK. BY
ADT7463
ACK. BY
ADT7463
STOP BY
MASTER
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
REV. C–10–
ADT7463
19
SCL
0
SDA
START BY
MASTER
10
SERIAL BUS ADDRESS
1
FRAME 1
BYTE
1
A0
A1
R/W
ACK. BY
ADT7463
Figure 8. Writing to the Address Pointer Register Only
19
SCL
0
SDA
START BY
MASTER
1011
FRAME 1
SERIAL BUS ADDRESS
BYTE
A0
A1
R/W
ACK. BY
ADT7463
Figure 9. Reading Data from a Previously Selected Register
When reading data from a register, there are two possibilities:
1. If the ADT7463’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7463
as before, however, only the data byte is sent and this contains the register address. This is shown in Figure 8.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.
2. If the address pointer register is already at the desired address,
data can be read from the corresponding data register without
first writing to the address pointer register, so Figure 8 can
be omitted.
D0
ACK. BY
ADT7463
D0
NO ACK. BY
MASTER
9
STOP BY
MASTER
9
STOP BY
MASTER
1
D6
D7
1
D6
D7
D4
D5
ADDRESS POINTER REGISTER BYTE
D4
D5
DATA BYTE FROM ADT7463
D3
FRAME 2
D3
FRAME 2
D2
D2
D1
D1
Notes
1. It is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.
2. In Figures 7 to 9, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.
3. In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7463 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).
4. If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
REV. C
–11–
ADT7463
S
SLAVE
ADDRESS
RA
DATA
A
P
12 3456
ADT7463 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7463
are discussed below. The following abbreviations are used in the
diagrams:
S – START
P– STOP
R– READ
W – WRITE
A– ACKNOWLEDGE
A – NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7463, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
12 3 4 56
S
ADDRESS
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
12 3 4 56
SLAVE
S
ADDRESS
Figure 11. Single Byte Write to a Registe
SLAVE
WA AP
REGISTER
WA
ADDRESS
REGISTER
ADDRESS
A
DATA
78
AP
ADT7463 READ OPERATIONS
The ADT7463 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the transaction ends.
In the ADT7463, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address
that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the one
with the lowest device address will have priority in accordance
with normal SMBus arbitration.
5. Once the ADT7463 has responded to the alert response
address, the master must read the status registers and the
SMBALERT will only be cleared if the error condition has
gone away.
SMBUS TIMEOUT
The ADT7463 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
r
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
CONFIGURATION REGISTER 1 – Register 0x40
<6> TODIS = 0; SMBus Timeout ENABLED (Default)
<6> TODIS = 1; SMBus Timeout DISABLED
REV. C–12–
ADT7463
VOLTAGE MEASUREMENT INPUTS
The ADT7463 has four external voltage measurement channels.
It can also measure its own supply voltage, V
CC
.
Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V
supplies and the processor core voltage V
The V
the V
supply voltage measurement is carried out through
CC
pin (Pin 4). Setting Bit 7 of Configuration Register 1
CC
(0 V to 3 V input).
CCP
(Reg. 0x40) allows a 5 V supply to power the ADT7463 and be
measured without overranging the V
measurement channel.
CC
The 2.5 V input can be used to monitor a chipset supply voltage
in computer systems.
ANALOG-TO-DIGITAL CONVERTER (ADC)
All analog inputs are multiplexed into the on-chip, successive
approximation, ADC. This has a resolution of 10 bits. The basic
input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the
processor core voltage V
without any external components. To
CCP
allow for the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (decimal 768 or 300 hex) for
the nominal input voltage and so has adequate headroom to
cope with overvoltages.
INPUT CIRCUITRY
The internal structure for the analog inputs is shown in Figure 13.
Each input circuit consists of an input protection diode, an
attenuator, plus a capacitor to form a first-order, low-pass filter
that gives the input immunity to high frequency noise.
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x20 2.5 V Reading = 0x00 Default
Reg. 0x21 V
Reg. 0x22 V
Reading = 0x00 Default
CCP
Reading = 0x00 Default
CC
Reg. 0x23 5 V Reading = 0x00 Default
Reg. 0x24 12 V Reading = 0x00 Default
VOLTAGE MEASUREMENT LIMIT REGISTERS
Associated with each voltage measurement channel are high and
low limit registers. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x46 V
Reg. 0x47 V
Reg. 0x48 V
Reg. 0x49 V
Low Limit = 0x00 Default
CCP
High Limit = 0xFF Default
CCP
Low Limit = 0x00 Default
CC
High Limit = 0xFF Default
CC
Reg. 0x4A 5 V Low Limit = 0x00 Default
Reg. 0x4B 5 V High Limit = 0xFF Default
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
12V
3.3V
2.5V
V
5V
CCP
IN
IN
IN
IN
120k⍀
93k⍀
68k⍀
45k⍀
17.5k⍀
52.5k⍀
20k⍀
47k⍀
71k⍀
94k⍀
30pF
30pF
30pF
30pF
35pF
MUX
REV. C
Figure 13. Structure of Analog Inputs
Table II shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise;
a measurement on each input takes nominally 11.38 ms.
–13–
ADT7463
Table II. 10-Bit A/D Output Code vs. V
IN
Input Voltage A/D Output
+12V
IN
+5V
IN
VCC (3.3VIN)* +2.5V
IN
+V
CCP
Decimal Binary (10 Bits)
<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00
0.0156–0.0312 0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 0.0293–0.0058 1 00000000 01
0.0312–0.0469 0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 0.0058–0.0087 2 00000000 10
0.0469–0.0625 0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 0.0087–0.0117 3 00000000 11
0.0625–0.0781 0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 0.0117–0.0146 4 00000001 00
0.0781–0.0937 0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 0.0146–0.0175 5 00000001 01
0.0937–0.1093 0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 0.0175–0.0205 6 00000001 10
0.1093–0.1250 0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 0.0205–0.0234 7 00000001 11
0.1250–0.14060 0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 0.0234–0.0263 8 00000010 00
•
•
•
4.0000–4.0156 1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 0.7500–0.7529 256 (1/4 scale) 01000000 00
•
•
•
8.0000–8.0156 3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 1.5000–1.5029 512 (1/2 scale) 10000000 00
•
•
•
12.0000–12.0156 5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 2.2500–2.2529 768 (3/4 scale) 11000000 00
•
•
•
15.8281–15.8437 6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 2.9677–2.9707 1013 11111101 01
15.8437–15.8593 6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 2.9707–2.9736 1014 11111101 10
15.8593–15.8750 6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 2.9736–2.9765 1015 11111101 11
15.8750–15.8906 6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 2.9765–2.9794 1016 11111110 00
15.8906–15.9062 6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 2.9794–2.9824 1017 11111110 01
15.9062–15.9218 6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 2.9824–2.9853 1018 11111110 10
15.9218–15.9375 6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 2.9853–2.9882 1019 11111110 11
15.9375–15.9531 6.6439–6.6504 4.3828–4.3871 3.3169–3.3202 2.9882–2.9912 1020 11111111 00
15.9531–15.9687 6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 2.9912–2.9941 1021 11111111 01
15.9687–15.9843 6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 2.9941–2.9970 1022 11111111 10
>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11
*The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the V
output codes are the same as for the +5VIN column.
CC
REV. C–14–
ADT7463
VID CODE MONITORING
The ADT7463 has five dedicated voltage ID (VID code) inputs.
These are digital inputs that can be read back through the
VID register (Reg. 0x43) to determine the processor voltage
required/being used in the system. Five VID code inputs support
VRM9.x solutions. In addition, Pin 21 (12 V input) can be reconfigured as a sixth VID input to satisfy future VRM requirements.
VID CODE REGISTER – Register 0x43
<0> = VID0 (reflects logic state of Pin 5)
<1> = VID1 (reflects logic state of Pin 6)
<2> = VID2 (reflects logic state of Pin 7)
<3> = VID3 (reflects logic state of Pin 8)
<4> = VID4 (reflects logic state of Pin 19)
<5> = VID5 (reconfigurable 12 V input). This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of VID register
(Reg. 0x43) controls the VID input threshold voltage.
VID CODE REGISTER – Register 0x43
<6> THLD = 0; VID Switching Threshold = 1 V,
< 0.8 V, VIH > 1.7 V, V
V
OL
MAX
= 3.3 V
THLD = 1; VID Switching Threshold = 0.6 V,
V
< 0.4 V, VIH > 0.8 V, V
OL
RECONFIGURING PIN 21 (+12V/VID5) AS VID5 INPUT
MAX
= 3.3 V
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Since the pin is configured as
VID5, it is no longer possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
VID CODE REGISTER – Register 0x43
<7> VIDSEL = 0; Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1; Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7463 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7463. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12V/VC bit and denotes a VID
change when set. The VID code change bit gets set when the
logic states on the VID inputs are different than they were 11 µs
previously. The change of VID code can be used to generate
an SMBALERT interrupt. If an SMBALERT interrupt is
not required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VID code
changes.
STATUS REGISTER 2 – Register 0x42
<0> 12V/VC = 0; If Pin 21 is configured as VID5, then a
Logic 0 denotes no change in VID code within last 11 µs.
<0> 12V/VC = 1; If Pin 21 is configured as VID5, then a Logic 1
means that a change has occurred on the VID code inputs within
the last 11 µs. An SMBALERT generates if this function is en-
abled.
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility, including:
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This effectively gives a reading 16 times faster
(711 µs), but the reading may be noisier.
Bypass Voltage Input Attenuators
Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes
the attenuation circuitry from the 2.5 V, V
, VCC, 5 V, and
CCP
12 V inputs. This allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this mode,
the ADT7463 can be made to read a single voltage channel
only. If the internal ADT7463 clock is used, the selected input
is read every 711 µs. The appropriate ADC channel is selected
by writing to Bits <7:5> of the TACH1 Minimum High Byte
Register (0x55).
Bits <7:5> Channel
Reg 0x55 Selected
000 2.5 V
001 V
010 V
CCP
CC
011 5 V
100 12 V
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<5> = 1 Bypass Input Attenuators
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
REV. C
–15–
ADT7463
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7463 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip 10-bit ADC. The 8-bit
MSB temperature data is stored in the local temperature register
(Address 26h). As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table III. Theoretically, the temperature sensor
and ADC can measure temperatures from –128⬚C to +127⬚C
with a resolution of 0.25⬚C. However, this exceeds the operating
temperature range of the device, so local temperature measurements outside this range are not possible.
Remote Temperature Measurement
The ADT7463 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pins 15 and
16, or 17 and 18.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/⬚C. Unfortunately, the absolute
IN ⴛ I I
CPU
BIAS
value of V
varies from device to device and individual calibra-
BE
tion is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7463 is to
measure the change in V
when the device is operated at two
BE
different currents.
This is given by
∆VKTq N
=×ln( )
BE
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 14 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could equally well be a
discrete transistor, such as a 2N3904.
V
DD
REMOTE
SENSING
TRANSISTOR
THERMDA
THERMDC
D+
D–
BIAS
DIODE
LOW-PASS
FILTER
f
= 65kHz
C
V
V
Figure 14. Signal Conditioning for Remote Diode Temperature Sensors
OUT+
TO ADC
OUT–
REV. C–16–
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