Analog Devices ADT7460 c Datasheet
dB
COOL™ Remote Thermal
FEATURES
Controls and monitors up to 4 fan speeds
1 on-chip and 2 remote temperature sensors
Dynamic T
intelligently
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via
Monitors performance impact of Intel®
Processor thermal control circuit via
2-wire and 3-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications (fully
SMBus 1.1-compliant)
APPLICATIONS
Low acoustic noise PCs
Networking and telecommunications equipment
control mode optimizes system acoustics
MIN
output
THERM
Pentium® 4
input
THERM
FUNCTIONAL BLOCK DIAGRAM
ADDR
SELECT
Controller and Fan Controller
ADT7460
GENERAL DESCRIPTION
The ADT74601 dBCOOL controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive applications
requiring active system cooling. It can monitor the temperature
of up to two remote sensor diodes plus its own internal temperature. It can measure and control the speed of up to four fans
so that they operate at the lowest possible speed for minimum
acoustic noise. The automatic fan speed control loop optimizes
fan speed for a given temperature. A unique dynamic T
control mode enables the system thermals/acoustics to be
intelligently managed. The effectiveness of the system’s thermal
solution can be monitored using the
THERM
ADT7460 also provides critical thermal protection to the
system by using the bidirectional
THERM
to prevent system or component overheating.
ADDR_EN
SCL
SDA
SMBALERT
input. The
pin as an output
MIN
PWM1
PWM2
PWM3
TACH1
TACH2
TACH3
TACH4
THERM
V
D1+
D1–
D2+
D2–
+2.5V
CC
IN
PWM REGISTERS
AND
CONTROLLERS
VCCTO ADT7460
BAND GAP
TEMP SENSOR
ACOUSTIC
ENHANCEMENT
CONTROL
FAN SPEED
COUNTER
PERFORMANCE
MONITORING
THERMAL
PROTECTION
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
SMBUS
ADDRESS
SELECTION
GND
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
CONTROL
ADT7460
10-BIT
BAND GAP
REFERENCE
T
MIN
ADC
SERIAL BUS
INTERFACE
Figure 1.
1
Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
INTERRUPT
STATUS
REGISTERS
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
03228-001
www.analog.com
ADT7460
TABLE OF CONTENTS
Specifications..................................................................................... 3
Additional ADC Functions for Voltage Measurements........ 17
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Product Description ......................................................................... 9
Measurement Inputs .................................................................... 9
Sequential Measurement ............................................................. 9
Recommended Implementation................................................. 9
ADT7460 Address Selection..................................................... 10
Internal Registers of the ADT7460 .......................................... 10
Theory of Operation ...................................................................... 11
Serial Bus Interface..................................................................... 11
Voltage Measurement Input...................................................... 15
Temperature Measurement System.......................................... 17
Additional ADC Functions for Temperature Measurement 19
Limits, Status Registers, and Interrupts................................... 20
Status Registers ........................................................................... 21
Handling
THERM
SMBALERT
Interrupts............................................. 22
Timer ........................................................................... 24
Fan Drive Using PWM Control ............................................... 27
Operating from 3.3 V Standby ................................................. 33
XNOR Tree Test Mode .............................................................. 33
Power-On Default ...................................................................... 33
ADT7460 Register Summary........................................................ 34
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 51
REVISION HISTORY
3/05—Rev. B to Rev. C
Updated Format .................................................................. Universa
Changes to Absolute Maximum Ratings Table..............................5
Changes to ADT7460 Register Map Summary Section .............34
Updated Ordering Guide................................................................51
9/03—Rev. A to Rev. B
Changed XOR Tree Test Mode to XNOR ............................Universal
Changes to SPECIFICATIONS.............................................................2
Changes to TPC 7.................................................................................... 7
6/03—Rev. 0 to Rev. A
l
Updated ORDERING ............................................................................4
Updated the SERIAL BUS INTERFACE section................................9
Added the To Assign
Added the
Renamed the Therm Input section to
Renumbered the figures after Figure 25.............................................22
Updated Step 1 in the Configuring the Desired
section........................................................................................................2
Updated the Fan Speed Control section ............................................28
Added the POWER-ON DEFAULT section .....................................29
Updated Table IV ..................................................................................30
Updated Table XVIII ............................................................................38
Updated Table XX .................................................................................40
Updated Table XXXV ...........................................................................46
Updated OUTLINE DIMENSIONS ...................................................49
THERM
THERM
as an Input section.............................................21
Functionality to a Pin 9 section ....21
THERM
Timer ....................21
THERM
Behavior
Rev. C | Page 2 of 52
ADT7460
SPECIFICATIONS
TA = T
Table 1.
Parameter
POWER SUPPLY
20 µA Standby mode
TEMPERATURE-TO-DIGITAL CONVERTER
11 µA Low level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
FAN RPM-TO-DIGITAL CONVERTER
OPEN-DRAIN DIGITAL OUTPUTS, PWM1–PWM3, XTO
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V
High Level Output Current, I
SMBUS DIGITAL INPUTS (SCL, SDA)
MIN
to T
1, , 2 3
, VCC = V
MAX
MIN
to V
, unless otherwise noted.
MAX
Min Typ
4
Max Unit Test Conditions/Comments
Supply Voltage 3.0 5.0 5.5 V
Supply Current, I
CC
3 mA Interface inactive, ADC active
Local Sensor Accuracy ±1.5 °C 0°C ≤ TA ≤ 70°C
±3 °C −40°C ≤ TA ≤ +120°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±1.5 °C 0°C ≤ TA ≤ 70°C; 0°C ≤ TD ≤ 120°C
±2.5 °C 0°C ≤ TA ≤ 105°C; 0°C ≤ TD ≤ 120°C
±3 °C 0°C ≤ TA ≤ 120°C; 0°C ≤ TD ≤ 120°C
Resolution 0.25 °C
Remote Sensor Source Current 180 µA High level
Total Unadjusted Error, TUE ±1.5 %
Differential Nonlinearity, DNL ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11.38 13 ms Averaging enabled
Conversion Time (Local Temperature) 12.09 13.50 ms Averaging enabled
Conversion Time (Remote Temperature) 25.59 28 ms Averaging enabled
Total Monitoring Cycle Time 120.17 134.50 ms Averaging enabled (incl. delay5)
13.51 15 ms Averaging disabled
Input Resistance 80 140 200 kΩ
Accuracy ±7 % 0°C ≤ TA ≤ 70°C
±11 % 0°C ≤ TA ≤ 105°C
±13 % −40°C ≤ TA ≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10000 RPM Fan count = 0x021C
Internal Clock Frequency 82.8 90.0 97.2 kHz
Current Sink, I
Output Low Voltage, V
OL
OL
High Level Output Current, I
OL
OH
Input High Voltage, V
Input Low Voltage, V
IH
IL
OH
8.0 mA
0.4 V I
0.1 1 µA V
0.4 V I
0.1 1 µA V
= −8.0 mA, VCC = 3.3 V
OUT
= V
OUT
= −4.0 mA, VCC = 3.3 V
OUT
= V
OUT
2.0 V
0.4 V
CC
CC
Hysteresis 500 mV
Rev. C | Page 3 of 52
ADT7460
A
Parameter
1, 2, 3
Min Typ
4
Max Unit Test Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
2.0 V
5.5 V Maximum input voltage
Input Low Voltage, V
IL
+0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, V
Input Low Voltage, V
IH
IL
1.7 V
0.8 V
DIGITAL INPUT CURRENT
Input High Current, I
Input Low Current, I
Input Capacitance, C
SERIAL BUS TIMING
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Detect Clock Low Timeout, t
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Logic inputs accept input high voltages up to V
3
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a rising edge.
4
Typicals are at TA = 25°C and represent the most likely parametric norm.
5
The delay is the time between the round robin finishing one set of measurements and starting the next.
6
Guaranteed by design, not production tested.
BUF
LOW
HIGH
6
SCLK
SW
SU;STA
HD;STA
SU;DAT
IH
IL
IN
R
F
TIMEOUT
even when the device is operating down to V
MAX
−1 µA VIN = V
CC
+1 µA VIN = 0
5 pF
400 kHz See Figure 2
50 ns
1.3 µs See Figure 2
0.6 µs See Figure 2
0.6 µs See Figure 2
1.3 µs See Figure 2
0.6 µs See Figure 2
300 ns See Figure 2
300 µs See Figure 2
100 ns See Figure 2
15 35 ms Can be optionally disabled
.
MIN
t
F
t
HIGH
t
SU; DAT
SP
Figure 2. Serial Bus Timing Diagram
t
SU; STA
t
HD; STA
t
SU; STO
03228-002
SCL
SD
t
BUF
PS
t
HD; STA
t
LOW
t
R
t
HD; DAT
Rev. C | Page 4 of 52
ADT7460
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 6.5 V
Voltage on Any Other Input or Output Pin −0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 220°C
IR Reflow Peak Temperature for Pb Free 260°C
Lead Temperature (Soldering 10 s) 300°C
ESD Rating 1500 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-Lead QSOP Package:
θ
= 150°C/W
JA
= 39°C/W
θ
JC
Rev. C | Page 5 of 52
ADT7460
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL
GND
V
TACH3
2/SMBALERT
PWM
TACH1
TACH2
PWM3/ADDRESS ENABLE
CC
1
2
3
ADT7460
4
TOP VIEW
(Not to Scale)
5
6
7
8
SDA
16
PWM1/XTO
15
/SMBALERT
+2.5V
14
IN
13
D1+
12
D1–
11
D2+
10
D2–
9
TACH4/ADDRESS SELECT/THERM
03228-003
Figure 3. Pin Configuration
Table 3. P tion Descript
Pin No. Mnemonic
in Func ions
Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND 460. Ground Pin for the ADT7
3 V
CC
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also
monitored through this pin. The ADT7460 can also be powered from a 5 V supply. Setting Bit 7 of
Configuration Register 1 (Reg. 0x40) rescales the V
4 TACH3
input attenuators to correctly measure a 5 V supply.
CC
re speed of Fan 3. Can be reconfigured as an Digital Input (Open Drain). Fan tachometer input to measu
analog input (AIN3) to measure the speed of 2-wire fans.
5 PWM2
Digital O
utput (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control
Fan 2 speed.
SMBALERT
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
6 TACH1
re speed of Fan 1. Can be reconfigured as an Digital Input (Open Drain). Fan tachometer input to measu
analog input (AIN1) to measure the speed of 2-wire fans.
7 TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an
analog input (AIN2) to measure the speed of 2-wire fans.
8 PWM3
pull-up.
ADDRESS ENABLE If pulled low on power-up, this places the ADT7460 into address select mode, and the state of Pin 9
determines the ADT7460’s slave address.
9 TACH4
put to measure speed of Fan 4. Can be reconfigured as an Digital Input (Open Drain). Fan tachometer in
analog input (AIN4) to measure the speed of 2-wire fans.
ADDRESS SELECT If in address select mode, this pin determines the SMBus device address.
THERM Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monit
assertions on the
THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 +2.5V
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
IN
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
out-of-limit conditions.
15 PWM1/XTO
Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical
pull-up.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
ypical Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/4 speed. Requires 10 kΩ t
or
Rev. C | Page 6 of 52
ADT7460
TYPICAL PERFORMANCE CHARACTERISTICS
15
3
10
5
0
–5
–10
–15
REMOTE TEMPERATURE ERROR (°C)
–20
1 3.3 100.0
DXPTO GND
DXP TO VCC(3.3V)
LEAKAGE RESISTANCE (MΩ)
10.0 30.0
Figure 4. Remote Temperature Error vs. Leakage Resistance
3
REMOTE TEMPERATURE ERROR (°C)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
REMOTE TEMPERATURE ERROR (°C)
–33
–36
1
2.2 3.3 4.7 10.0 22.0 47.0
DXP–DXN CAPACITANCE (nF)
Figure 5. Remote Temperature Error vs. Capacitance between D+ and D−
03228-004
03228-005
2
1
0
–1
–2
LOCAL TEMPERATURE ERROR (°C)
–3
–40 10 110
HIGH LIMIT
+3 SIGMA
–3 SIGMA
LOW LIMIT
60
TEMPERATURE (°C)
Figure 7. Local Temperature Error vs. Actual Temperature
14
12
10
8
6
4
2
0
REMOTE TEMPERATURE ERROR (°C)
–2
100k 550k 50M
Figure 8. Remote Temperature Error vs. Power Supply Noise Frequency
250mV
100mV
5M
FREQUENCY (Hz)
03228-007
03228-008
3
2
1
0
–1
–2
REMOTE TEMPERATURE ERROR (°C)
–3
–40
Figure 6. Remote Temperature Error vs. Actual Temperature
HIGH LIMIT
+3 SIGMA
–3 SIGMA
LOW LIMIT
10 60 110
TEMPERATURE (°C)
03228-006
Rev. C | Page 7 of 52
12.5
10.0
7.5
RROR (°C)
E
5.0
2.5
0
LOCAL TEMPERATURE
–2.5
–5.0
100k 550k 50M
250mV
100mV
5M
FREQUENCY (Hz)
Figure 9. Local Temperature Error vs. Power Supply Noise Frequency
03228-009
ADT7460
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
SUPPLY CURRENT (mA)
1.50
1.45
1.40
2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
2.5
SUPPLYVOLTAGE(V)
Figure 10. Supply Current vs. Supply Voltage
16
14
12
10
8
6
4
2
REMOTE TEMPERATURE ERROR (°C)
0
–2
60k
110k 1M 10M 50M
Figure 11. Remote Temperature Error vs. Differential Mode Noise Frequency
20mV
10mV
FREQUENCY (Hz)
5.5
03228-010
03228-011
40
35
30
25
20
15
10
5
0
REMOTE TEMPERATURE ERROR (°C)
–5
–10
10k
40mV
100mV
20mV
100k 1M 10M
FREQUENCY (Hz)
03228-012
Figure 12. Remote Temperature Error vs. Common-Mode Noise Frequency
Rev. C | Page 8 of 52
ADT7460
PRODUCT DESCRIPTION
The ADT7460 is a thermal monitor and multiple fan controller
for any system requiring monitoring and cooling. The device
communicates with the system via a serial System Management
Bus (SMBus). The serial bus controller has an optional address
line for device selection (Pin 9), a serial data line for reading
and writing addresses and data (Pin 16), and an input line for
the serial clock (Pin 1). All control and programming functions
of the ADT7460 are performed over the serial bus. In addition,
two of the pins can be reconfigured as an
SMBALERT
output to
indicate out-of-limit conditions.
MEASUREMENT INPUTS
The device has three measurement inputs, one for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip
temperature sensor.
Pin 14 is an analog input with an on-chip attenuator and is
configured to monitor 2.5 V.
SEQUENTIAL MEASUREMENT
When the ADT7460 monitoring sequence is started, it cycles
sequentially through the measurement of 2.5 V input and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are
stored in the status registers, which can be read over the serial
bus to flag out-of-limit conditions.
RECOMMENDED IMPLEMENTATION
Configuring the ADT7460 as in Figure 13 allows the systems
designer the following features:
• Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
• Three TACH fan speed measurement inputs.
• V
measured internally through Pin 3.
CC
Power is supplied to the chip via Pin 3, and the system also
monitors V
through this pin. In PCs, this pin is normally
CC
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1± and D2±
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap
temperature sensor, which monitors system ambient
temperature.
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
TACH2
PWM3
TACH3
D1+
D1–
ADT7460
• CPU temperature measured using Remote 1 temperature
channel.
• Ambient temperature measured through Remote 2
temperature channel.
• Bidirectional
PROCHOT
overtemperature
•
SMBALERT
P
WM1
TACH1
D2+
D2–
THERM
PROCHOT
THERM
monitoring and can function as an
system interrupt output.
pin. Allows Intel Pentium 4
THERM
output.
SDA
SCL
SMBALERT
GND
Figure 13. Recommended Implementation
Rev. C | Page 9 of 52
ICH
3228-013
ADT7460
ADT7460 AD S SELECTION
Pin 8 is pulled low on p
Pin 9 (T SS SELECT/
ADT7460’s slave addres s high on power-up, the
ADT Bus Slave Address 0x2E. This function
is desc tail later.
Table 4. Summary Inte
Register Description
Configuration These registers provide control and configuration of the ADT7460, including alternate pinout functionality.
Address Pointer
Status Registers
Interrupt Mask
Value and Limit
Offset
T
T
Operating Point
Enhance Acoustics These registers allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics.
ACH4/ADDRE
7460 defaults to SM
ribed in more de
MIN
RANGE
DRES
-functio
n PWMPin 8 is the dual 3/
ADDRESS ENABLE
ower-up, the ADT7460 reads the state of
THERM
) to determine the
pin. If
INTERNAL REGISTERS OF THE ADT7460
Table 4 summarizes the ADT7460’s principal internal registers.
Table 41 to Table 81 describe the registers in more detail.
s. If Pin 8 i
rnal Registers
This register contains the address that selects one of the other internal registers. When writing to the ADT7460, the
first byte of data is always a register address, which is written to the address pointer register.
These registers provide the status of each limit comparison and are used to signal out-of-limit conditions on the
temperature, voltage, or fan speed channels. If Pin 14 or Pin 5 is configured as
whenever an unmasked status bit is set.
These registers allow each interrupt status event to be masked when Pin 14 or Pin 5 is configured as an
output.
The results of analog voltage input, temperature, and fan speed measurements are stored in these registers, along
with their limit values.
These registers allow each temperature channel reading to be offset by a twos complement value written to these
registers.
These registers program the starting temperature for each fan under automatic fan speed control.
These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each
PWM output.
These registers define the target operating temperatures for each thermal zone when running under dynamic T
control. This function allows the cooling solution to adjust dynamically in response to measured temperature and
system performance.
SMBALERT
, this pin asserts low
SMBALERT
MIN
Rev. C | Page 10 of 52
ADT7460
8
T
-
T
THEORY OF OPERATION
SERIAL BUS INTERFACE
Control of the ADT7460 is carried out using the serial System
Management Bus (SMBus). The ADT7460 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7460 has a 7-bit serial bus address. When the device is
powered up with Pin 8 (PWM3/
ADDRESS ENABLE
ADT7460 has a default SMBus address of 0101110 or 0x2E. If
more than one ADT7460 is to be used in a system, each ADT7460
should be placed in address select mode by strapping Pin 8 low
on power-up. The logic state of Pin 9 then determines the
device’s SMBus address. The logic state of these pins is sampled
on power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely, on the low-to-high
transition at the beginning of the eighth SCL pulse, when the
serial address byte matches the selected slave address. The
selected slave address is chosen using the
ADDRESS ENABLE
/ADDRESS SELECT pins. Any attempted changes in the
address has no effect after this.
Table 5. Address Select Mode
Pin 8 State Pin 9 State Address
0 Low (10 kΩ to GND) 0101100 (0x2C)
0 High (10 kΩ pull-up) 0101101 (0x2D)
1 Don’t Care 0101110 (0x2E) (default)
V
ADT7460
ADDR_SEL
PWM3/ADDR_EN
Figure 14. Default SMBus Address 0x2E
CC
9
8
ADDRESS = 0x2E
10k
Ω
ADT7460
Ω
10k
ADDR_SEL
PWM3/ADDR_EN
Figure 15. SMBus Address 0x2C (Pin 9 = 0)
9
8
ADDRESS = 0x2C
) high, the
03228-014
03228-015
V
CC
ADT7460
ADDR_SEL
PWM3/ADDR_EN
Figure 16. SMBus Address 0x2D (Pin 9 = 1)
ADT7460
ADDR_SEL
PWM3/ADDR_EN
CARE SHOULD BE TAKEN TO ENSURE THAT PIN
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8
FLOATING COULD CAUSE THE ADT7460 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS SELEC
MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNC
IONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS
MUXED IN AT THE CORRECT TIME.
Figure 17. Unpredictable SMBus Address if Pin 8 is Unconnected
facility to make hardwired changes to the SMBus slav
The e
ess allows the user to avoid conflicts with other devices
addr
shar
ing the same serial bus, for example, if more than one
ADT
7460 is used in a system.
The
serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
10k
Ω
9
8
ADDRESS = 0x2D
V
CC
10kΩ
9
8
NC
DO NOT LEAVE ADDR_EN
UNCONNECTED. C
CAUSE UNPREDIC
ADDRESSES
AN
TABLE
03228-016
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high
This indicates that an address/data stream will follow. All
slave peripherals connected to
the serial bus respond to the
star condition and shift in the next eight bits, consisting
a 7-bit address (MSB first) plus a R/
bit, which
W
determine the direction of the data transfer, that is,
whether data is written to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge bit. All other devices on the bus no
remain idle while the selected device
read from or written to it. If the R/
writes to the slave device. If the R/
waits for data to be
bit is a 0, the master
W
bit is a 1, the master
W
reads from the slave device.
03228-017
of
w
.
Rev. C | Page 11 of 52
ADT7460
2.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge bit
from the slave device. Transitions on the data line must occ
during the low period of the clock signal and remain stable
during the high period, as a low-to-high transition when the
clock is high may be interpreted as a st
op signal. The number
of data bytes that can be transmitted over the serial bus in a
single read or write operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written, stop conditio
are established. In write
mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit
by pulling the data line high during the low period
before the
ninth clock pulse. This is known as No Acknowledge. The
master then takes the data line low during the low period
before the 10th clock pulse, then high during the 10th clock
pulse to assert a stop condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
1
SCL
ur
ns
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7460, write operations contain either one
or two bytes, and read operations contain one byte.
To write data to one of the device data re
gisters or read data
from it, the address pointer register must be set so that the
correct data register is addressed. Then data can be written in
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register
selected by the addres
This is i
llustrated in Figure 18. The device address is sent over
the bus followed by R/
s pointer register.
being set to 0. This is followed by two
W
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
1
9
9
SDA
START BY
MASTER
0
0
1
SERIAL BUS ADDRESS
1
1
FRAME 1
BYTE
SDA (CONTINUED)
A0
A1
SCL (CONTINUED)
R/W
ACK. BY
ADT7460
1
D7
D6
D7
ADDRESS POINTER REGISTER BYTE
D5
D6
D5
D4
D4
D3
FRAME 3
DATA
BYTE
FRAME 2
D2
D3
D2
D1
D0
ACK. BY
ADT7460
9
D1
D0
ACK. BY
ADT7460
STOP BY
MASTER
03228-018
Figure 18. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
Rev. C | Page 12 of 52
ADT7460
When reading data from a register, there are two possibilities:
• If the ADT7460’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7460
as before, but only the data byte containing the register
address is sent because data is not to be written to the
register. This is shown in Figure 19.
A read operation is then performed, consisting of the serial
bus address, R/
bit set to 1, followed by the data byte
W
read from the data register. This is shown in Figure 20.
• If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, so Figure 19 can be omitted.
It is possible to read a data byte from a data register without first
writing to the address pointer register if the address pointer
register is already at the correct value. However, it is not possible
to write data to a register without writing to the address pointer
register because the first data byte of a write is always written to
the address pointer register.
In Figure 18 to Figure 20, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by the
address select mode function previously defined.
In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7460 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for more
information).
1
SCL
9
If it is required to perform several read or write operations in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
Write Operations
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7460 are discussed below. The following abbreviations are
used in the diagrams:
S—start
P—sto p
R—read
W—wr it e
A—ack nowledge
—no acknowledge
A
The ADT7460 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
1
9
SDA
START BY
MASTER
0
10
SERIAL BUS ADDRESS
1
FRAME 1
BYTE
D6
1
A0
A1
R/W
ACK. BY
ADT7460
D7
D4
D5
ADDRESS POINTER REGISTER BYTE
D3
FRAME 2
D2
D1
D0
ACK. BY
ADT7460
STOP BY
MASTER
03228-019
Figure 19. Writing to the Address Pointer Register Only
D0
NO ACK. BY
MASTER
9
STOP BY
MASTER
03228-020
1
SCL
0
SDA
START BY
MASTER
1011
FRAME 1
SERIAL BUS ADDRESS
BYTE
A0
A1
Figure 20. Read
9
1
D6
W
R/
ACK
. BY
ADT7460
D7
D4
D5
FRAME 2
DATA BYTE FROM ADT7460
ing Data from a Previously Selec ted Register
Rev. C | Page 13 of 52
D3
D2
D1
ADT7460
7460, the send byte protocol is used to write to the For the ADT
address pointer register for a subsequent single-byte read from
the same address. This is illustrated in Figure 21.
231564
SLAVE
ADDRESS ADDRESS
Figure 21. Settin
ely after
If it is required to read data from the register immediat
tin art
set g up the address, the master can assert a repeat st
d nd carry out a
con ition immediately after the final ACK a
g a Register Address for Subsequent Read
single-byte read without asserting an intermediate stop
d
con ition.
i
Wr te Byt e
h ends a command byte and
In t is operation, the master device s
one data byte to the slave device as follows:
1. evice asserts a start condition on SDA.
The master d
2. The master sends the 7-bit
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The maste
5. The slave assert
r sends the register address.
s ACK on SDA.
REGISTER
WASAP
03228-021
slave address followed by the
3. The addressed slave de
vice asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SD
A.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7460, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by
a send byte or by write byte operation.
213564
SLAVE
SWA AP
ADDRESS
Figure 23. Single-Byte Read from a Register
REGISTER
ADDRESS
03228-023
Alert Response Address
r t
Ale t response address (ARA) is a feature of SMBus devices tha
allow
s an interrupting device to identify itself to the host when
mul
tiple devices exist on the same bus.
The
SMBALERT
can be used as an
ected to a common conn
ter. If a device’s
mas
output can be used as an interrupt output or
SMBALERT
SMBALERT
. One or more outputs can be
SMBALERT
line connected to
line goes low, the following
the
occurs:
6. The master sends a data byte.
7. The slave
asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated i
n Figure 22.
24653178
SLAVE
ADDRESS ADDRESS
Figure
REGISTER
22. Single-Byte Write to a Register
DATAAAWSAP
03228-022
Read Operations
The ADT7460 uses the following SMB
e
Rec ive Byte
This is useful when repeatedly reading a single register. Th
regis have been set up previously. In this
ter address needs to
us read protocols.
e
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a start condition on SD
2. The master sends the 7-bit ave address followed by the
read bit (
high).
sl
A.
1.
SMBALERT
is pulled low.
Master2. initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address, which must not be used as a specific device
address.
3. The device whose
SMBALERT
output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it
can be interrogated in the usual way.
4. If more than one device’s
SMBALERT
output is low, the
one with the lowest device address has priority in
accordance with normal SMBus arbitration.
5. Once the ADT7460 has responded to the alert response
address, the master must read the status registers and the
SMBALERT
is cleared only if the error condition has gone
away.
Rev. C | Page 14 of 52
ADT7460
SMBus Timeout
The ADT7460 includes an SMBus timeout feature. If there is no
SMBus activity for 25 ms, the ADT7460 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Table 6. Configuration Register 1 (Reg. 0x40)
Bit Description
<6> TODIS 0: SMBus timeout enabled (default)
<6> TODIS 1: SMBus timeout disabled
VOLTAGE MEASUREMENT INPUT
The ADT7460 has one external voltage measurement channel.
It can also measure its own supply voltage, V
Pin 14 may be configured to measure a 2.5 V supply. The V
supply voltage measurement is carried out through the V
(Pin 3). Setting Bit 7 of Configuration Register 1 (Reg. 0x40)
allows a 5 V supply to power the ADT7460 and be measured
without overranging the V
measurement channel. The 2.5 V
CC
input can be used to monitor a chipset supply voltage in
computer systems.
Analog-to-Digital Converter
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolution
of 10 bits. The basic input range is 0 V to 2.25 V, but the input
has built-in attenuators to allow measurement of 2.5 V without
any external components. To allow the tolerance of the supply
voltage, the ADC produces an output of 3/4 full scale (768d or
0x300) for the nominal input voltage and so has adequate
headroom to deal with overvoltages.
.
CC
CC
pin
CC
Input Circuitry
The internal structure for the 2.5 V analog input is shown in
Figure 24. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives the input immunity to high frequency
noise.
Table 7. Voltage Measurement Registers
Register Description Default
0x20 2.5 V reading 0x00
0x22 VCC reading 0x00
Associated with the voltage measurement channels are a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate
SMBALERT
interrupts.
Table 8. 2.5 V Limit Registers
Register Description Default
0x44 2.5 V low limit 0x00
0x45 2.5 V high limit 0xFF
0x48 VCC low limit 0x00
0x49 VCC high limit 0xFF
2.5V
IN
Figure 24. Structure of Analog Inputs
45kΩ
94kΩ 30pF
03228-024
Table 9 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
Rev. C | Page 15 of 52
ADT7460
Table 9. 10-Bit A/D Output Code vs. V
5 V
IN
VCC (3.3 VIN)
<0.0065 <0.0042 <0.0032 0 00000000 00
0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 1 00000000 01
0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 2 00000000 10
0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 3 00000000 11
0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 4 00000001 00
0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 5 00000001 01
0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 6 00000001 10
0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 7 00000001 11
0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 8 00000010 00
• • • • •
• • • • •
• • • • •
1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 256 (1/4 scale) 01000000 00
• • • • •
• • • • •
• • • • •
3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 512 (1/2 scale) 10000000 00
• • • • •
• • • • •
• • • • •
5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 768 (3/4 scale) 11000000 00
• • • • •
• • • • •
• • • • •
6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 1013 11111101 01
6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 1014 11111101 10
6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 1015 11111101 11
6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 1016 11111110 00
6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 1017 11111110 01
6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 1018 11111110 10
6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 1019 11111110 11
6.6439–6.6504 4.3828–4.3871 3.3169v3.3202 1020 11111111 00
6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 1021 11111111 01
6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 1022 11111111 10
>6.6634 >4.3957 >3.3267 1023 11111111 11
1
The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), the VCC output codes are
the same as for the 5 V
column.
IN
IN
Input Voltage A/D Output
1
2.5 V
IN
Decimal Binary (10 Bits)
Rev. C | Page 16 of 52
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