ANALOG DEVICES ADT7411 Service Manual

SPI®-/I2C®-Compatible, 10-Bit Digital

www.BDTIC.com/ADI

Temperature Sensor and 8-Channel ADC

FEATURES

10-bit temperature-to-digital converter
10-bit 8-channel ADC

DC input bandwidth

Input range: 0 V to 2.25 V and 0 V to V
Temperature range: −40°C to +120°C
Temperature sensor accuracy of ±0.5°C
Supply range: 2.7 V to 5.5 V
Power-down current : <10 μA
Internal 2.25 V

option

REF

Double-buffered input logic

2

I

C, SPI, QSPI™, MICROWIRE™, and DSP compatible
4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP

APPLICATIONS

Portable battery-powered instruments
PCs
Smart battery chargers
Telecommunications systems electronic test equipment
Domestic appliances
Process controls

GENERAL DESCRIPTION

DD

ADT7411

PIN CONFIGURATION

1

AIN6

2

AIN5

3

NC

ADT7411

TOP VIEW

4

CS

(Not to Scale)

5

GND

6

V

DD

7

D+/AIN1

8

D–/AIN2 AIN3

NC = NO CONNECT

Figure 1.

16

AIN7

15

AIN8

14

AIN4

13

SCL/SCLK

12

SDA/DIN

11

DOUT/ADD

10

INT/INT

9

02882-005

The ADT74111 combines a 10-bit temperature-to-digital
converter and a 10-bit 8-channel ADC in a 16-lead QSOP. This
includes a band gap temperature sensor and a 10-bit ADC to
monitor and digitize the temperature reading to a resolution of

0.25°C. The ADT7411 operates from a single 2.7 V to 5.5 V
supply. The input voltage on the ADC channels has a range of
0 V to 2.25 V and the input bandwidth is dc. The reference for
the ADC channels is derived internally. The ADT7411 provides
two serial interface options: a 4-wire serial interface compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards,
and a 2-wire SMBus/I

2

C interface. It features a standby mode

that is controlled via the serial interface.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADT7411’s wide supply voltage range, low supply current,

2

nd SPI-/I

a

C-compatible interface make it ideal for a variety of
applications, including PCs, office equipment, and domestic
appliances.

1

Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; 5,764174. Other

patents pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADT7411

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TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 13

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Functional Block Diagram .............................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Functional Descriptions.......................... 8

Te r mi n ol o g y ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

REVISION HISTORY

12/06–Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 7

Changes to Theory of Operation Section.................................... 13

Changes to Figure 20...................................................................... 14

Changes to Table 7.......................................................................... 20

Changes to Table 16 Title............................................................... 22

Changes to Internal T

[Address = 25h] Section ................................................................ 25

Changes to Internal T

[Address = 26h] Section ................................................................ 26

Changes to External T

(Read/Write) [Address = 27h] Section ........................................ 26

Changes to External T

(Read/Write) [Address = 28h] Section ........................................ 26

Changes to Serial Interface Selection Section............................. 29

Changes to SPI Serial Interface Section....................................... 30

Changes to Read Operation Section ............................................32

Changes to Ordering Guide.......................................................... 35

Limit Register (Read/Write)

HIGH

Limit Register (Read/Write)

LOW

HIGH

/AIN1 V

LOW

/AIN1 V

Limit Register

HIGH

Limit Register

LOW

Power-Up Calibration ................................................................ 13

Conversion Speed....................................................................... 13

Functional Description .................................................................. 14

Analog Inputs ............................................................................. 14

Functional Description—Measurement.................................. 15

ADT7411 Registers .................................................................... 19

Serial Interface............................................................................ 29

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

3/04–Rev. 0 to Rev. A

ormat Updated.................................................................. Universal

F

Change to Equation........................................................................ 17

8/03–Revision 0: Initial Version

Rev. B | Page 2 of 36

ADT7411

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SPECIFICATIONS

VDD = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Temperature ranges are −40°C to +120°C.

Table 1.

Parameter

ADC DC ACCURACY Maximum VDD = 5 V.

Resolution 10 Bits
Total Unadjusted Error (TUE) 2 3 % of FSR VDD = 2.7 V to 5.5 V.
2 % of FSR VDD = 3.3 V (±10%).
Offset Error ±0.5 % of FSR

Gain Error ±2 % of FSR
ADC BANDWIDTH DC Hz
ANALOG INPUTS

Input Voltage Range 0 2.25 V AIN1 to AIN8. C4 = 0 in Control Configuration 3.

0 V

DC Leakage Current ±1 μA

Input Capacitance 5 20 pF

Input Resistance 10 MΩ
THERMAL CHARACTERISTICS Internal reference used. Averaging on.

Internal Temperature Sensor

External Temperature Sensor External transistor = 2N3906.

CONVERSION TIMES Single-channel mode.

Slow ADC

Fast ADC

1

Accuracy @ VDD = 3.3 V ± 10% ±1.5 °C TA = 85°C.
±0.5 ±3 °C TA = 0°C to 85°C.
±2 ±5 °C TA = −40°C to +120°C.
Accuracy @ VDD = 5 V ± 5% ±2 ±3 °C TA = 0°C to 85°C.
±3 ±5 °C TA = −40°C to +120°C.
Resolution 10 Bits Equivalent to 0.25°C.
Long-Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C.

Accuracy @ VDD = 3.3 V ± 10% ±1.5 °C TA = 85°C.
±3 °C TA = 0°C to 85°C.
±5 °C TA = −40°C to +120°C.
Accuracy @ VDD = 5 V ± 5% ±2 ±3 °C TA = 0°C to 85°C.
±3 ±5 °C TA = −40°C to +120°C.
Resolution 10 Bits Equivalent to 0.25°C.
Output Source Current 180 μA High level.
11 μA Low level.

VDD/AIN 11.4 ms Averaging (16 samples) on.
712 μs Averaging off.
Internal Temperature 11.4 ms Averaging (16 samples) on.
712 μs Averaging off.
External Temperature 24.22 ms Averaging (16 samples) on.

1.51 ms Averaging off.

VDD/AIN 712 μs Averaging (16 samples) on.

44.5 μs Averaging off.
Internal Temperature 2.14 ms Averaging (16 samples) on.
134 μs Averaging off.
External Temperature 14.25 ms Averaging (16 samples) on.
890 μs Averaging off.

Min Typ Max Unit Conditions/Comments

DD

V AIN1 to AIN8. C4 = 1 in Control Configuration 3.

Rev. B | Page 3 of 36

ADT7411

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Parameter

ROUND ROBIN UPDATE RATE

1

2

Min Typ Max Unit Conditions/Comments

Time to complete one measurement cycle

ough all channels.

thr

Slow ADC @ 25°C

Averaging On 125.4 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging Off 17.1 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging On 140.36 ms D+ and D– are selected on Pin 7 and Pin 8.
Averaging Off 12.11 ms D+ and D− are selected on Pin 7 and Pin 8.

Fast ADC @ 25°C

Averaging On 9.26 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging Off 578.96 μs AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging On 24.62 ms D+ and D− are selected on Pin 7 and Pin 8.
Averaging Off 3.25 ms D+ and D− are selected on Pin 7 and Pin 8.

ON-CHIP REFERENCE

3

Reference Voltage 2.2662 2.28 2.2938 V
Temperature Coefficient 80 ppm/°C

DIGITAL INPUTS

1, 3

Input Current ±1 μA VIN = 0 V to VDD.
VIL, Input Low Voltage 0.8 V
VIH, Input High Voltage 1.89 V
Pin Capacitance 3 10 pF All digital inputs.
SCL, SDA Glitch Rejection 50 ns

Input filtering suppresses n

oise spikes of less

than 50 ns.

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Output High Current, I
Output Capacitance, C

OH

OL

OH

OUT

INT/INT Output Saturation Voltage

I2C TIMING CHARACTERISTICS

Serial Clock Period, t
Data In Setup Time to SCL High, t
Data Out Stable after SCL Low, t

4, 5

1

2

3

SDA Low Setup Time to SCL Low

(Start Condition), t

4

SDA High Hold Time after SCL High

(Stop Condition), t
SDA and SCL Fall Time, t
SDA and SCL Rise Time, t

SPI TIMING CHARACTERISTICS

CS to SCLK Setup Time, t
SCLK High Pulse Width, t
SCLK Low Pulse Width, t

5

6

7

1, 3, 7

1

2

3

Data Access Time after SCLK Falling Edge, t

2.4 V I

SOURCE

= I

= 200 μA.

SINK

0.4 V IOL = 3 mA.
1 mA VOH = 5 V.
50 pF

0.8 V I

= 4 mA.

OUT

2.5 μs Fast-mode I2C. See Figure 2.
50 ns
0 ns See Figure 2.
50 ns See Figure 2.

50 ns See Figure 2.

300 ns See Figure 2.
300

6

ns See Figure 2.

0 ns See Figure 3.
50 ns See Figure 3.

50 ns See Figure 3.

7

35 ns See Figure 3.

4

Data Setup Time Prior to SCLK Rising Edge, t520 ns See Figure 3.
Data Hold Time after SCLK Rising Edge, t
CS to SCLK Hold Time, t
CS to DOUT High Impedance, t

7

8

0 ns See Figure 3.

6

0 ns See Figure 3.
40 ns See Figure 3.

Rev. B | Page 4 of 36

ADT7411

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Parameter

1

Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

V

DD

2.7 5.5 V
VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level.
IDD (Normal Mode)

8

3 mA VDD = 3.3 V, VIH = VDD and VIL = GND.

2.2 3 mA VDD = 5 V, VIH = VDD and VIL = GND.
IDD (Power-Down Mode) 10 μA VDD = 3.3 V, VIH = VDD and VIL = GND.
10 μA VDD = 5 V, VIH = VDD and VIL = GND.
Power Dissipation 10 mW VDD = 3.3 V. Using normal mode.
33 μW VDD = 3.3 V. Using shutdown mode.

1

See the Terminology section.

2

Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,

AIN6, AIN7, and AIN8.

3

Guaranteed by design and characterization, not production tested.

4

The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer

rate but has a negative effect on the EMC behavior of the part.

5

Guaranteed by design. Not tested in production.

6

The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.

7

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.

8

IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.

t

1

SCL

t

5

t

6

t

7

02882-002

SDA

DATA IN

SDA

DATA OUT

t

4

Figure 2. I

t

2

t

3

2

C Bus Timing Diagram

CS

SCLK

DIN

DOUT

t

1

D7

X X X X X X X X D7D6D5 D4D3D2D1 D0

t

2

t

3

D6D5D4D3D2D1D0X X XXXXX X

t

t

5

6

t

4

t

7

t

8

02882-003

Figure 3. SPI Bus Timing Diagram

200µA I

TO

OUTPUT

PIN

C

L

50pF

200µA I

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

OL

1.6V

OH

02882-004

Rev. B | Page 5 of 36

ADT7411

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FUNCTIONAL BLOCK DIAGRAM

D+/AIN1

D–/AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

7

8

9

14

2

1

16

15

ON-CHIP

TEMPERATURE

SENSOR

ANALOG

MUX

V

DD

SENSOR

6

V

DD

INTERNAL

TEMPERATURE

VALUE REGISTER

EXTERNAL

TEMPERATURE

VALUE REGISTER

A-TO-D

CONVERTER

V

DD

VALUE REGISTER

AIN1

VALUE REGISTER

AIN2

VALUE REGISTER

AIN3

VALUE REGISTER

AIN4

VALUE REGISTER

AIN5

VALUE REGISTER

AIN6

VALUE REGISTER

AIN7

VALUE REGISTER

AIN8

VALUE REGISTER

5

GND

COMPARATOR

DIGITAL MUX

REGISTERS

Figure 5.

LIMIT

STATUS

4

CS

ADT7411

ADDRESS POINTER

REGISTER

T

HIGH

REGISTERS

T

LOW

REGISTERS

VDD LIMIT

REGISTERS

AIN

DIGITAL MUX

SPI/SMBus INTERFACE

13

SCL/SCLK

REGISTERS

AIN

REGISTERS

CONTROL CONFIG . 1

REGISTER

CONTROL CONFIG . 2

REGISTER

CONTROL CONFIG . 3

REGISTER

INTERRUPT MASK

REGISTERS

12

SDA/DI N

HIGH

LOW

LIMIT

LIMIT

LIMIT

LIMIT

11

DOUT/ ADD

10

INT/INT

02882-001

Rev. B | Page 6 of 36

ADT7411

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +120°C
Storage Temperature Range −65°C to +150°C
Junction Temperature

16-Lead QSOP 150°C

Power Dissipation
Thermal Impedance

θJA Junction-to-Ambient 105.44°C/W
θJC Junction-to-Case 38.8°C/W

IR Reflow Soldering

Peak Temperature 220°C (0°C/5°C)
Time at Peak Temperature 10 sec to 20 sec
Ramp-Up Rate 2°C/sec to 3°C/sec
Ramp-Down Rate −6°C/sec

IR Reflow Soldering (Pb-Free Package)

Peak Temperature 260°C (+0°C)
Time at Peak Temperature 20 sec to 40 sec
Ramp-Up Rate 3°C/sec maximum
Ramp-Down Rate −6°C/sec maximum
Time 25°C to Peak Temperature 8 minutes maximum

1

Values relate to package being used on a 4-layer board.

2

Junction-to-case resistance is applicable to components featuring a

preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air-cooled PCB­mounted components.

1

2

(T

Jmax

− TA)/θ

JA

Table 3. I2C Address Selection

ADD Pin I2C Address

Low 1001 000
Float 1001 010
High 1001 011

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 36

ADT7411

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PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

1

AIN6

2

AIN5

3

NC

ADT7411

TOP VIEW

4

CS

(Not to Scale)

5

GND

6

V

DD

7

D+/AIN1

8

D–/AIN2 AIN3

NC = NO CONNECT

Figure 6. Pin Configuration

16

AIN7

15

AIN8

14

AIN4

13

SCL/SCLK

12

SDA/DIN

11

DOUT/ADD

10

INT/INT

9

02882-005

Table 4. Pin Function Descriptions

Pin
No.

Mnemonic Description

1 AIN6 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
2 AIN5 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
3 NC No Connection.
4

CS

SPI—Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it
enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent

serial clocks. It is recommended that this pin be tied high to V

when operating the serial interface in I2C mode.

DD

5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
6 V

DD

7 D+/AIN1

Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
Positive Connection to External Temperature Sensor/A

nalog Input. Single-ended analog input channel.

Input range is 0 V to 2.25 V or 0 V to 5 V.

8 D−/AIN2

Negative Connection to External Temperature Sensor/Anal

og Input. Single-ended analog input channel.

Input range is 0 V to 2.25 V or 0 V to 5 V.
9 AIN3 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
10

INT/INT

11 DOUT/ADD

Overlimit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when

temperature, V

DOUT—SPI Serial Data Output. Log

, or AIN limits are exceeded. Default is active low. Open-drain output needs a pull-up resistor.

DD

ic output. Data is clocked out of any register at this pin. Data is clocked out on the

falling edge of SCLK. Open-drain output needs a pull-up resistor.

2

ADD—I

floating gives the Address 1001 010 and setting it high gives the Address 1001 011. The I

C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the Address 1001 000, while leaving it

2

ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the

12 SDA/DIN

second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no

effect on the I

SDA—I

2

C serial bus address.

2

C Serial Data Input. I2C serial data to be loaded into the part’s registers is provided on this input. An open­drain configuration needs a pull-up resistor.
DIN—SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this input. Data is
clocked into a register on the rising edge of SCLK. An open-drain configuration needs a pull-up resistor.

13 SCL/SCLK

Serial Clock Input. This is the clock input f

or the serial port. The serial clock is used to clock data out of any register
of the ADT7411 and to clock data into any register that can be written to. An open-drain configuration needs a pull­up resistor.

14 AIN4 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
15 AIN8 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
16 AIN7 Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.

C address set up by the

Rev. B | Page 8 of 36

ADT7411

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TERMINOLOGY

Relative Accuracy

Relative accuracy or integral nonlinearity (INL) is a measure of

e maximum deviation, in LSBs, from a straight line passing

th
through the endpoints of the ADC transfer function. A typical
INL vs. code plot can be seen in

Tot a l U n ad ju s te d E rr o r ( TU E)

Total unadjusted error is a comprehensive specification that

cludes the sum of the relative accuracy error, gain error, and

in
offset error under a specified set of conditions.

Offset Error

This is a measure of the offset error of the ADC. It can be
ne

gative or positive. It is expressed in mV.

Gain Error

This is a measure of the span error of the ADC. It is the

viation in slope of the actual ADC transfer characteristic

de
from the ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
t

emperature. It is expressed in ppm of full-scale range/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in

emperature. It is expressed in ppm of full-scale range/°C.

t

Figure 10.

Long-Term Temperature Drift

This is a measure of the change in temperature error with the

assage of time. It is expressed in degrees Celsius. The concept

p
of long-term stability has been used for many years to describe
by what amount an IC’s parameter would shift during its
lifetime. This is a concept that has been typically applied to both
voltage references and monolithic temperature sensors.
Unfortunately, ICs cannot be evaluated at room temperature
(25°C) for 10 years or so to determine this shift. As a result,
manufacturers typically perform accelerated lifetime testing of
ICs by operating ICs at elevated temperatures (between 125°C
and 150°C) over a shorter period (typically between 500 hours
and 1,000 hours). Because of this operation, the lifetime of an
IC is significantly accelerated due to the increase in rates of
reaction within the semiconductor material.

DC Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio (PSRR) is defined as the ratio
o

f the power in the ADC output at full-scale frequency f to the
power of a 100 mV sine wave applied to the V
frequency fs.

PSRR (dB) = 10 log(Pf/Pfs)

where:

Pf is th

e power at frequency f in ADC output.

Pfs is th

e power at frequency fs coupled into the V

supply of

DD

DD

supply.

Round Robin

This term describes the ADT7411 cycling through the available
m

easurement channels in sequence, taking a measurement on

each channel.

Rev. B | Page 9 of 36

ADT7411

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TYPICAL PERFORMANCE CHARACTERISTICS

2.00

ADC OFF

1.95

1.90

(mA)

CC

I

1.85

1.80

1.75

2.73.13.53.94.34.75.12.9 3.3 3.7 4.1 4.5 4.9 5.3 5. 5
V

(V)

CC

Figure 7. Supply Current vs. Supply Voltage at 25°C

0

±100mV RIPPLE ON V
V

= 2.25V

REF

V

= 3.3V

DD

–10

TEMPERATURE = 25°C

CC

2882-006

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (L SB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 800 1000

Figure 10. ADC INL with Ref = V

ADC CODE

(3.3 V)

DD

1.5

EXTERNAL TEMPERATURE @ 5V

1.0

INTERNAL T EMPERATURE @ 3.3V

02882-009

–20

–30

AC PSRR (dB)

–40

–50

–60

1 10 100

FREQUENCY (kHz)

Figure 8. PSRR vs. Supply Ripple Frequency

7

6

5

4

(µA)

CC

I

3

2

1

0.5

0

TEMPERATURE ERROR (°C)

–0.5

–1.0

02882-007

INTERNAL T EMPERATURE @ 5V

–30 0 40 85 120

EXTERNAL TEMPERATURE @ 3.3V

TEMPERATURE (° C)

02882-010

Figure 11. Temperature Error at 3.3 V and 5 V

3

V

= 3.3V

DD

2

1

0

–1

ERROR (LSB)

–2

–3

OFFSET ERROR

GAIN ERROR

0

2.72.93.13.33.53.73.94.14.34.54.74.95.15.35.5
V

(V)

CC

02882-008

Figure 9. Power-Down Current vs. Supply Voltage at 25°C

Rev. B | Page 10 of 36

–4

–40 –20 0

20 40 60 80 100 120

TEMPERATURE ( °C)

Figure 12. ADC Offset Error and Gain Error vs. Temperature

02882-011

ADT7411

www.BDTIC.com/ADI

15

10

5

D+ TO GND

0

VDD = 3.3V
TEMPERAT URE = 25°C

0

VDD = 3.3V

–10

–20

–5

D+ TO V

CC

–10

–15

TEMPERATURE ERROR (°C)

–20

–25

01020

30 40 50 60 70 80 90 100

PCB LEAKAGE RESI STANCE (M Ω)

Figure 13. External Temperature Error vs. PCB Leakage Resistance

10

VDD = 3.3V
COMMON-MODE

8

VOLTAG E = 100mV

6

4

2

0

–2

TEMPERATURE ERROR (°C)

–4

–6

1 100 200 300 400 500 600

NOISE FREQ UENCY (Hz)

Figure 14. External Temperature Error vs.

Com

mon-Mode Noise Frequency

3

2

OFFSET ERROR

–30

–40

TEMPERATURE ERROR (°C)

–50

–60

0 5 10 15 20 25

2882-012

CAPACITANCE (nF )

30 35 40 45 50

2882-015

Figure 16. External Temperature Error vs. Capacitance Between D+ and D−

70

60

50

40

30

20

10

TEMPERATURE ERROR (°C)

0

–10

1 100 200

02882-013

NOISE FREQ UENCY (MHz)

VDD = 3.3V
DIFFERENTIAL-MODE
VOLTAG E = 100mV

300 400 500 600

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Figure 17. External Temperature Error vs. Differential Mode Noise Frequency

0.6
VDD = 3.3V

0.4

1

0

ERROR (LSB)

–1

–2

–3

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

VDD (V)

Figure 15. ADC Offset Error and Gain Error vs. V

GAIN ERROR

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DD

Rev. B | Page 11 of 36

0.2

0

–0.2

TEMPERATURE E RROR (°C)

–0.4

–0.6

1 100 200 300 400 500 600

±250mV

NOISE FREQ UENCY (Hz)

Figure 18. Internal Temperature Error vs. Power Supply Noise Frequency

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