±0.25°C from −20°C to +105°C at 3.0 V to 3.6 V
16-bit temperature resolution: 0.0078°C
Ultralow temperature drift: 0.0073°C
NIST traceable or equivalent
Fast first temperature conversion on power-up of 6 ms
Easy implementation
No temperature calibration/correction required by user
No linearity correction required
Low power
Power saving 1 sample per second (SPS) mode
700 µW typical at 3.3 V in normal mode
7 µW typical at 3.3 V in shutdown mode
Wide operating ranges
Temperature range: −40°C to +150°C
Voltage range: 2.7 V to 5.5 V
SPI-compatible interface
16-lead, RoHS-compliant, 4 mm × 4 mm LFCSP package
SPI Temperature Sensor
GENERAL DESCRIPTION
The ADT7320 is a high accuracy digital temperature sensor that
o
ffers breakthrough performance over a wide industrial temperature
range, housed in a 4 mm × 4 mm LFCSP package. It contains an
internal band gap reference, a temperature sensor, and a 16-bit
analog-to-digital converter (ADC) to monitor and digitize the
temperature to a resolution of 0.0078°C. The ADC resolution,
by default, is set to 13 bits (0.0625°C). The ADC resolution is a
user programmable mode that can be changed through the
serial interface.
The ADT7320 is guaranteed to operate over supply voltages from
.7 V to 5.5 V. Operating at 3.3 V, the average supply current is
2
typically 210 µA. The ADT7320 has a shutdown mode that powers
down the device and offers a shutdown current of typically 2.0 µA
at 3.3 V. The ADT7320 is rated for operation over the −40°C to
+150°C temperature range.
The CT pin is an open-drain output that becomes active when the
temperature exceeds a programmable critical temperature limit.
The INT pin is also an open-drain output that becomes active
when the temperature exceeds a programmable limit. The INT pin
and CT pin can operate in either comparator or interrupt mode.
APPLICATIONS
RTD and thermistor replacement
Thermocouple cold junction compensation
Medical equipment
Industrial control and test
Food transportation and storage
Environmental monitoring and HVAC
Laser diode temperature control
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. Ease of use, no calibration or correction required by the user.
2. Low power consumption.
3. Excellent long term stability and reliability.
4. High accuracy for industrial, instrumentation, and medical
applications.
5. Packaged in a 16-lead, RoHS-compliant, 4 mm × 4 mm
TA = −40°C to +125°C, VDD = 2.7 V to 5.5 V, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
±0.25
±0.30 °C TA = −40°C to +105°C, VDD = 3.0 V
±0.35 °C TA = −40°C to +105°C, VDD = 2.7 V to 3.3 V
±0.50 °C TA = −40°C to +125°C, VDD = 3.0 V to 3.6 V
±0.503 °C TA = −10°C to +105°C, VDD = 4.5 V to 5.5 V
±0.65 °C TA = −40°C to +125°C, VDD = 4.5 V to 5.5 V
−0.85 °C TA = +150°C, VDD = 4.5 V to 5.5 V
−1.0 °C TA = +150°C, VDD = 2.7 V to 3.6 V
ADC Resolution 13 Bits Twos complement temperature value of sign bit plus
16 Bits Twos complement temperature value of sign bit plus
Temperature Resolution
Temperature Conversion Time 240 ms Continuous conversion and one-shot conversion mode
Fast Temperature Conversion Time 6 ms First conversion on power-up only
1 SPS Conversion Time 60 ms Conversion time for 1 SPS mode
Temperature Hysteresis ±0.002 °C Temperature cycle = 25°C to 125°C and back to 25°C
Repeatability
Drift5 0.0073 °C 500 hour stress test at 150°C with VDD = 5.0 V
DC PSRR 0.1 °C/V TA = 25°C
DIGITAL OUTPUTS (CT, INT), OPEN DRAIN
High Output Leakage Current, IOH 0.1 5 µA CT and INT pins pulled up to 5.5 V
Output Low Voltage, VOL 0.4 V IOL = 3 mA at 5.5 V, IOL = 1 mA at 3.3 V
Output High Voltage, VOH 0.7 × VDD V
Output Capacitance, C
DIGITAL INPUTS (DIN, SCLK, CS)
Input Current ±1 µA VIN = 0 V to VDD
Input Low Voltage, VIL 0.4 V
Input High Voltage, VIH 0.7 × VDD V
Pin Capacitance 5 10 pF
DIGITAL OUTPUT (DOUT)
Output High Voltage, VOH VDD − 0.3 V I
Output Low Voltage, V
Output Capacitance, C
POWER REQUIREMENTS
Supply Voltage 2.7 5.5 V
Supply Current Peak current while converting, SPI interface inactive
1 SPS Current 1 SPS mode, TA = 25°C
1
0.0017 ±0.202 °C TA = −10°C to +85°C, VDD = 3.0 V to 3.3V
°C TA = −20°C to +105°C, VDD = 3.0 V to 3.6 V
±0.25
TA = −20°C to +85°C, VDD = 2.7 V
12 ADC bits (power-up default resolution)
15 ADC bits (Bit 7 = 1 in the configuration register)
13-Bit 0.0625 °C 13-bit resolution (sign + 12 bits)
16-Bit 0.0078 °C 16-bit resolution (sign + 15 bits)
4
OUT
OL
50 pF
OUT
±0.015 °C TA = 25°C
2 pF
= I
SOURCE
SINK
0.4 V IOL = 200 µA
= 200 µA
At 3.3 V 210 265 µA
At 5.5 V 250 300 µA
Rev. PrD | Page 4 of 26
Preliminary Technical Data ADT7320
Parameter Min Typ Max Unit Test Conditions/Comments
At 3.3 V 46 µA VDD = 3.3 V
At 5.5 V 65 µA VDD = 5.5 V
Shutdown Current Supply current in shutdown mode
At 3.3 V 2.0 15 µA
At 5.5 V 5.2 25 µA
Power Dissipation, Normal Mode 700 µW VDD = 3.3 V, normal mode at 25°C
Power Dissipation, 1 SPS Mode 150 µW Power dissipated for VDD = 3.3 V, TA = 25°C
1
Accuracy specification includes repeatability.
2
The equivalent 3 σ limits are ±0.15°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits.
3
For higher accuracy at 5 V operation, contact Analog Devices, Inc.
4
Based on a floating average of 10 readings.
5
Drift includes solder heat resistance and lifetime test performed as per JEDEC Standard JESD22-A108.
SPI TIMING SPECIFICATIONS
TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
t1 0 ns min
t2 100 ns min SCLK high pulse width
t3 100 ns min SCLK low pulse width
t4 30 ns min Data setup time prior to SCLK rising edge
t5 25 ns min Data hold time after SCLK rising edge
t6 5 ns min Data access time after SCLK falling edge
60 ns max VDD = 4.5 V to 5.5 V
80 ns max VDD = 2.7 V to 3.6 V
3
t
10 ns min Bus relinquish time after CS inactive edge
7
80 ns max Bus relinquish time after CS inactive edge
t8 0 ns min SCLK inactive edge to CS rising edge hold time
t9 0 ns min
60 ns max VDD = 4.5 V to 5.5 V
80 ns max VDD = 2.7 V to 3.6 V
t10 10 ns min SCLK inactive edge to DOUT low
1
Sample tested during initial release to ensure compliance.
2
See Error! Reference source not found..
3
This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus
loading capacitances.
1, 2
Limit at T
MIN
, T
Unit Descriptions
MAX
CS
CS
falling edge to SCLK active edge setup time
falling edge to DOUT active time
Rev. PrD | Page 5 of 26
ADT7320 Preliminary Technical Data
DOUT
CS
t
1
t
SCLK
DIN
2
1
t
4
t
MSBLSB
t
9
5
t
3
23
9102324
876
t
6
MSB
Figure 2. Detailed SPI Timing Diagram
t
8
t
10
LSB
t
7
09012-002
Rev. PrD | Page 6 of 26
Preliminary Technical Data ADT7320
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
DIN Input Voltage to GND −0.3 V to VDD + 0.3 V
DOUT Voltage to GND −0.3 V to VDD + 0.3 V
SCLK Input Voltage to GND −0.3 V to VDD + 0.3 V
Input Voltage to GND −0.3 V to VDD + 0.3 V
CS
CT and INT Output Voltage to GND −0.3 V to VDD + 0.3 V
ESD Rating (Human Body Model) 2.0 kV
Operating Temperature Range
1
−40°C to +150°C
Storage Temperature Range −65°C to +160°C
Maximum Junction Temperature, T
150°C
JMAX
Power Dissipation2
16-Lead LFCSP3 W
MAX
= (T
− TA)/θJA
JMAX
Thermal Impedance4
θJA, Junction-to-Ambient (Still Air) 37°C/W
θJC, Junction-to-Case 33°C/W
IR Reflow Soldering 220°C
Peak Temperature (RoHS-Compliant
260°C (0°C/−5°C)
Package)
Time at Peak Temperature 20 sec to 40 sec
Ramp-Up Rate 3°C/sec maximum
Ramp-Down Rate −6°C/sec maximum
Time from 25°C to Peak Temperature 8 minutes maximum
1
Sustained operation above 125°C results in a shorter product lifetime. For
more information, contact an Analog Devices, Inc., sales representative.
2
Values relate to package being used on a standard 2-layer PCB. This gives a
worst-case θJA and θJC.
3
TA = ambient temperature.
4
Junction-to-case resistance is applicable to components featuring a
preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air cooled, PCBmounted components.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. PrD | Page 7 of 26
ADT7320 Preliminary Technical Data
N
C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
C
C
N
6
5
1
1
1
SCLK
2
DOUT
3
DIN
4
CS
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
THE NC PIN IS NOT BONDED TO THE DIE INTERNALLY.
2. TO ENSURE CORRECT OPERATION, THE EXPOSED PAD
SHOULD EITHER BE LEFT FLOATING OR CONNECTED
TO GROUND.
ADT7320
TOP VIEW
(Not to Scale)
6
5
C
C
N
N
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK Serial Clock Input. The serial clock is used to clock data into and out of any register of the ADT7320.
2 DOUT Serial Data Output. Data is clocked out on the SCLK falling edge and is valid on the SCLK rising edge.
3 DIN Serial Data Input. Serial data to be loaded to the control registers of the part is provided on this input. Data is
clocked into the registers on the rising edge of SCLK.
4
CS
Chip Select Input. The device is enabled when this input is low. The device is disabled when this pin is high.
5 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
6 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
7 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
8 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
9 INT Overtemperature and Undertemperature Interrupt. Logic output. Power-up default setting is as an active low
comparator interrupt. Open-drain configuration. A pull-up resistor is required, typically 10 kΩ.
10 CT Critical Overtemperature Interrupt. Logic output. Power-up default polarity is active low. Open-drain
configuration. A pull-up resistor is required, typically 10 kΩ.
11 GND Analog and Digital Ground.
12 VDD Positive Supply Voltage (2.7 V to 5.5 V). Decouple the supply with a 0.1 µF ceramic capacitor to GND.
13 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
14 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
15 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
16 NC No Connect. Do not connect to this pin. The NC pin is not bonded to the die internally.
17 EPAD Exposed Pad. To ensure correct operation, the exposed pad should either be left floating or connected to ground.
C
N
N
3
4
1
1
17 EPAD
12
V
DD
11
GND
10
CT
9
INT
8
7
C
C
N
N
09012-003
Rev. PrD | Page 8 of 26
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