Analog Devices ADT7318ARQ, ADT7317ARQ, ADT7316ARQ Datasheet

PRELIMINARY TECHNICAL DA T A

T





SPI/I2C



Compatible, 10-Bit Digital Temperature

=

Sensor and Quad Voltage Output 12/10/8-Bit DAC

Preliminary Technical Data

FEATURES
ADT7316 - Four 12-Bit DACs
ADT7317 - Four 10-Bit DACs
ADT7318 - Four 8-Bit DACs
Buffered Voltage Output
Guaranteed Monotonic By Design Over All Codes
10-Bit Temperature to Digital Converter
Temperature range: -40
Temperature Sensor Accuracy of ±0.5
Supply Range : + 2.7 V to + 5.5 V

DAC Output Range: 0 - 2V
Power-Down Current 1
Internal 2.25 V

Option

Ref

Double-Buffered Input Logic
Buffered / Unbuffered Reference Input Option
Power-on Reset to Zero Volts
Simultaneous Update of Outputs (
On-Chip Rail-to-Rail Output Buffer Amplifier



2





I

C

, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4­wire Serial Interface
16-Lead QSOP Package

APPLICATIONS
Portable Battery Powered Instruments
Personal Computers
Telecommunications Systems
Electronic Test Equipment
Domestic Appliances
Process Control

INTERNAL T EMPERAT URE

VALUE REGISTER

A-TO-D

CONVERTER

EXTERNAL TEMPERATURE

VALUE REGISTER

D+

D-

TEMPERATURE

7
8

ON-CHIP
SENSOR

ANAL OG

MUX

V

DD

SENSOR

ADT7316/17/18

µµ

µA

µµ

o

REF

VALU E

REGISTER

C to +125oC

o

LDAC Function)

V

DD

C

X
U
M
L
A
T

I

COMPARATOR

G

I
D

LIMIT

STATUS

REGISTERS

ADDRESSPOINTER

X
U
M
L
A
T

I
G

I
D

CONTROL CONFIG. 1

CONTROL CONFIG. 2

CONTROL CONFIG. 3

DAC CONFIGURATION

LDAC C ONF IGURA TION

INTERRUPT MASK

ADT7316/7317/7318

GENERAL DESCRIPTION

The ADT7316/7317/7318 combines a 10-Bit Tempera­ture-to-Digital Converter and a quad 12/10/8-Bit DAC
respectively, in a 16-Lead QSOP package. This includes a
bandgap temperature sensor and a 10-bit ADC to monitor
and digitize the temperature reading to a resolution of

o

C. The ADT7316/17/18 operates from a single

0.25
+2.7V to +5.5V supply. The output voltage of the DAC
ranges from 0 V to 2V
time of typ 7 msec. The ADT7316/17/18 provides two
serial interface options, a four-wire serial interface which
is compatible with SPI
DSP interface standards; and a two-wire I
features a standby mode that is controlled via the serial
interface.

The reference for the four DACs is derived either inter­nally or from two reference pins (one per DAC pair) .The
outputs of all DACs may be updated simultaneously using
the software

LDAC

function or external LDAC pin. The
ADT7316/7317/7318 incorporates a power-on-reset cir­cuit, which ensures that the DAC output powers-up to
zero volts and it remains there until a valid write takes
place.

The ADT7316/7317/7318’s wide supply voltage range,
low supply current and SPI/I
make it ideal for a variety of applications, including per­sonal computers, office equipment and domestic appli­ances.

REGISTER

T

LIMIT

HIGH

REGISTERS

T

LIMIT

LOW

REGISTERS

VDDLim it

REGISTERS

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTERS

REGISTERS

REGISTERS

, with an output voltage settling

REF

TM

, QSPITM, MICROWIRETM and

2

C-compatible interface,

DAC A

DAC B

DAC C

REGISTERS

DAC D

REGISTERS

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

2

C interface. It

GAIN

SELECT

LOGIC

POWER

DOWN
LOGIC

2

1

16

15

10

V

-A

OUT

V

-B

OUT

V

-C

OUT

V

-D

OUT

INTERRUP

SMBus/SPI INTERFACE

6 5

VDDGND

4 13 12 11

CS

SCL/SCLK SDA/DIN

DOUT /ADD

FUNCTIONAL BLOCK DIAGRAM

REV. PrN 02/02

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

INTERNAL TEMP

9

LDAC

3

V

-AB

REF

SENSOR

14

V

-CD

REF

I2C is a registered trademark of Philips Corporation
* Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, INC.
MICROWIRE is a trademark of National Semiconductor Corporation.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL D A T A

ADT7316/ADT7317/ADT7318-SPECIFICATIONS

1

(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted)

Parameter

DAC DC PERFORMANCE

2

3,4

Min Typ Max Units Conditions/Comments

ADT7318

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic by design over all codes

ADT7317

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic by design over all codes

ADT7316

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Relative Accuracy tbd tbd LSB Excluding Offset and Gain errors

Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed Monotonic by design over all codes
Offset Error ±0.4 ±3 % of FSR
Offset Error Match ±0.5 LSB
Gain Error ±0.3 ±1.25 % of FSR
Gain Error Match ±0.5 LSB
Lower Deadband 20 60 mV Lower Deadband exists only if Offset Error is

Negative. See Figure 5.

Upper Deadband tbd tbd mV Upper Deadband exists if V

Offset Error Drift
Gain Error Drift

DC Power Supply Rejection Ratio

DC Crosstalk

6

6

6

6

THERMAL CHARACTERISTICS

-12

-5

ppm of FSR/°C
ppm of FSR/°C

-60 dB ∆V

200 µV R

plus Gain Error is positive. See Figure 6.

= ±10%

DD

= 2 KΩ to GND or V

L

Internal Reference used.

= VDD and Offset

REF

DD

INTERNAL TEMPERATURE
SENSOR

Accuracy @ VDD=3.3V ±2 °C TA = 0°C to +85°C

±3 °C T

Accuracy @ V

Resolution 10 Bits
Long Term Drift 0.5 °C/1000hrs

EXTERNAL TEMPERATURE
SENSOR External Transistor = 2N3906.

Accuracy @ V

Accuracy @ V

Resolution 10 Bits

Update Rate, t

Temperature Conversion Time

=5V ±2 °C TA = 0°C to +85°C

DD

=3.3V ±2 °C TA = 0°C to +85°C.

DD

=5V ±2 °C TA = 0°C to +85°C

DD

R

±3 °C T

±3 °C T

±3 °C T

TBD µ s Round Robin5 enabled
TBD µs Round Robin disabled
TBD

µs

= -40°C to +125°C

A

= -40°C to +125°C

A

= -40°C to +125°C

A

= -40°C to +125°C

A

Output Source Current 180 µA High Level

11 µA Low Level

VOLTAGE OUTPUT

8-Bit DAC Output

Resolution 1 °C
Scale Factor 8.79 mV/°C 0-V

17.58 mV/°C 0-2V

Output. TA = -40°C to +125°C

REF

Output. TA = -40°C to +125°C

REF

10-Bit DAC Output

Resolution 0.25 °C

–2–

REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

Parameter

DAC ERTERNAL
REFERENCE INPUT

2

Scale Factor 2.2 mV/°C 0-V

6

V

Input Range 1 V

REF

Input Range 0.25 V

V

REF

V

Input Impedance 37 45 k Ω Unbuffered Reference Mode. 0-2 V

REF

Min Typ Max Units Conditions/Comments

Output. TA = -40°C to +125°C

4.39 mV/°C 0-2V

DD
DD

74 90 kΩ Unbuffered Reference Mode. 0- V

V Buffered Reference Mode
V Unbuffered Reference Mode

REF

Output. TA = -40°C to +125°C

REF

>10 MΩ Buffered reference mode and Power-Down Mode

Output Range.

REF

Output Range.

REF

Reference Feedthrough -90 dB Frequency=10KHz
Channel-toChannel Isolation -75 dB Frequency=10KHz

ON-CHIP REFERENCE

Reference Voltage
Temperature Coefficient

OUTPUT CHARACTERISTICS

Output Voltage

6

6

7

6

0.001 VDD-0.001 V This is a measure of the minimum and maximum drive

2.25 V
80 ppm/

°C

capability of the output amplifier

DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA V

16 mA V

Power Up Time 2.5 µs Coming out of Power Down Mode. V

5 µs Coming out of Power Down Mode. VDD = +3 V

DIGITAL INPUTS

6

Input Current ±1 µ A VIN = 0V to V
VIL, Input Low Voltage 0.8 V V

0.6 V V

V

, Input High Voltage 1.89 V

IH

Pin Capacitance 3 10 pF All Digital Inputs

= +5V

DD

= +3V

DD

= +5V±10%

DD

= +3V±10%

DD

DD

= +5 V

DD

SCL, SDA Glitch Rejection 50 ns Input Filtering Suppresses Noise Spikes of Less than 50

ns

DIGITAL OUTPUT

Output High Voltage, V
Output Low Voltage, V
Output High Current, I

Output Capacitance, C

ALERT Output Saturation Voltage

I2C TIMING CHARACTERISTICS

Serial Clock Period, t

OH

OL

OH

OUT

8,9

1

Data In Setup Time to SCL High, t
Data Out Stable after SCL Low, t

2.4 V I

0.4 V IOL = 3 mA
1mAV

50 pF

0.8 V I

2.5 µs Fast-Mode I2C. See Figure 1

2

0 ns See Figure 1

3

SOURCE

= 5 V

OH

= 4 mA

OUT

= I

SINK

= 200 µA

SDA Low Setup Time to SCL Low

(Start Condition), t

4

50 ns See Figure 1

SDA High Hold Time after SCL High

(Stop Condition), t

SDA and SCL Fall Time, t

5

6

SPI TIMING CHARACTERISTICS

CS to SCLK Setup Time, t
SCLK High Pulsewidth, t
SCLK Low Pulse, t
Data Access Time after

SCLK Falling edge, t

1

2

3

12

4

50 ns See Figure 1

90 ns See Figure 1

10, 11

0 ns See Figure 2
50 ns See Figure 2
50 ns See Figure 2

35 ns See Figure 2

Data Setup Time Prior

to SCLK Rising Edge, t

5

20 ns See Figure 2

Data Hold Time after

SCLK Rising Edge, t

CS to SCLK Hold Time, t

6

7

CS to DOUT High Impedance, t

0 ns See Figure 2
0 ns See Figure 2

8

40 ns See Figure 2

POWER REQUIREMENTS

V

DD

Settling Time 50 ms VDD settles to within 10% of it’s final voltage

V

DD

2.7 5.5 V

level.

–3–REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

I

(Normal Mode)

DD

I

(Power Down Mode) 1 3 µA V

DD

Power Dissipation tbd tbd tbd µW V

Notes:

1

Temperature ranges are as follows: A Version: -40°C to +125°C.

2

See Terminology.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)

5

See Terminology.

6

Guaranteed by Design and Characterization, not production tested

7

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
"Offset plus Gain" Error must be positive.

8

The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I
rate but has a negative affect on the EMC behaviour of the part.

9

Guaranteed by design. Not tested in production.

10

Guaranteed by design and characterization, not production tested.

11

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

12

Measured with the load circuit of Figure 3.

13

IDD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

13

0.85 1.3 mA VIH = VDD and V
= +4.5V to +5.5V, VIH=VDD and VIL=GND

0.5 1 µA V

DD

= +2.7V to +3.6V, VIH=VDD and VIL=GND

DD

= +2.7 V. Using Normal Mode

DD

= GND

IL

tbd tbd tbd µW VDD = +2.7 V. Using Shutdown Mode

2

C specification. Switching off the input filters improves the transfer

REF=VDD

,

DAC AC CHARACTERISTICS

Parameter

2

1

Min Typ @ 25°C M ax Units Conditions/Comments

Output Voltage Settling Time V

(VDD = +2.7V to +5.5 V; R
4K7Ω to V

; All specifications T

DD

=4k7Ω to GND; C

L

to T

MIN

REF=VDD

MAX

=+5V

=200pF to GND;

L

unless otherwise noted.)

ADT7318 6 8 µs 1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
ADT7317 7 9 µs 1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
ADT7316 8 10 µs 1/4 Scale to 3/4 Scale change (400 Hex to

C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry.
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 1 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion -70 dB V

NOTES

1

Guaranteed by Design and Characterization, not production tested

2

See Terminology

=2V±0.1Vpp

REF

=2.5V±0.1Vpp. Frequency=10kHz.

REF

Specifications subject to change without notice.

SCL

SDA

DATA IN

SDA

DATA O U T

t

1

t

4

t

2

t

3

Figure 1. Diagram for I2C Bus Timing

–4– REV. PrN

t

5

t

6

+5

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

t

1

SCLK

DOUT DBX

DIN

DB7

MSB L SB

t

t

1

2

2

DBX DBX

DB6 DB0

3

4

t

3

DBX

t

t

5

6

DB5

8

t

4

DB7
MSB

DB8

MSB

7

t

8

Figure 2. Diagram for SPI Bus Timing

I

A

200

␮

OL

TO

OUTPUT

PIN

50pF

C

L

1.6V

A

200

I

␮

OL

Figure 3. Load Circuit for Access Time and Bus Relinquish Time

DD

V

To DAC

Outp ut

4Κ7Ω

4Κ7Ω 200

pF

Figure 4. Load Circuit for DAC Outputs

–5–REV. PrN

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

ABSOLUTE MAXIMUM RATINGS*

VDD to GND –0.3 V to +7 V
Digital Input Voltage to GND –0.3 V to V
Digital Output Voltage to GND –0.3 V to V
Reference Input voltage to GND –0.3 V to V
Operating Temperature Range –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature +150°C
16-Lead QSOP Package
Power Dissipation (T

θ

Thermal Impedance 150 °C/W (QSOP)

JA

j

Reflow Soldering
Peak Temperature +220 +/- 0°C

Time of Peak Temperature 10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DD
DD

DD

max - T

+ 0.3 V
+ 0.3 V

+ 0.3V

) / θ

A

JA

2

Table 1. I

C Address Selection

ADD Pin I2C Address

Low 1001 000

Float 1001 010

High 1001 011

PIN CONFIGURATION

QSOP

V

-B

out

V

-A

out

V

ref

2

-AB V

3

ADT7316/

4

CS

GND

D+

D-

7317/7318

5

TOP VIEW

6

(Not to Scale)

7

89

V

16

V

15

14

13

SCL/SCLK

12

SDA/D IN
DOUT/ADDVDD

11

10

INTERRUPT

LDAC

out
out
ref

-C1

-D

-CD

ORDERING GUIDE

Model Temperature Range DAC Resolution Package Description Package Options

ADT7318ARQ –40°C to +125°C 8-Bits 16-Lead QSOP RQ-16
ADT7317ARQ -40°C to +125°C 10-Bits 16-Lead QSOP RQ-16
ADT7316ARQ -40°C to +125°C 12-Bits 16-Lead QSOP RQ-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

ADT7316/7317/7318

the

feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–6– REV. PrN

WARNING!

ESD SENSITIVE DEVICE

PRELIMINARY TECHNICAL D A T A

ADT7316/7317/7318

ADT7316/7317/7318 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1V
2V
3V

4 CS SPI Active low control Input. This is the frame synchronization signal for the input data.

5 GN D Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.
6VDDPositive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground.
7 D+ Positive connection to external temperature sensor
8 D- Negative connection to external temperature sensor
9 LDAC Active low control input that transfers the contents of the input registers to their respective

10 INTERRUPT Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active

11 DOUT/ADD SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is

12 SDA/DIN SDA - I

13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock

14 V

15 V
16 V

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

AB Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input

REF

to each or both of the DACs A and B. It has an input range from 0.25 V to V

in unbuffered

DD

mode and from 1 V to VDD in buffered mode.

When CS goes low, it enables the input register and data is transferred in and out on the ris­ing edges of the following serial clocks. This pin must be kept high for I

2

C mode of operation.

CS is also used as a control pin when selecting the serial interface type after power-up.

DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data. This allows simultaneous update of all DAC outputs. Bit C3 of Con­trol Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the
loading of DAC registers.

high interrupt when temperature, VDD and AIN limits are exceeded. Default is active low.

clocked out at the falling edge of SCLK.
ADD, I
nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/

18. Any subsequent changes on this pin will have no affect on the I

2

C serial bus address selection pin. Logic input. During the first valid I2C bus commu-

2

C serial bus address. A low
on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and set­ting it high gives the address 1001 011.

2

C Serial Data Input. I2C serial data to be loaded into the parts registers is provided
on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.

data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.

CD Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input

REF

to each or both of the DACs C and D. It has an input range from 0.25 V to V

in unbuffered

DD

mode and from 1 V to VDD in buffered mode.

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

–7–REV. PrN

ADT7316/7317/7318

PRELIMINARY TECHNICAL D A T A

TERMINOLOGY RELATIVE ACCURACY

Relative accuracy or integral nonlinearity (INL) is a mea­sure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. Typical INL versus Code plots can be seen in
TPCs 1, 2, and 3.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference be­tween the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity.
This DAC and Temperature Sensor ADC is guaranteed
monotonic by design. Typical DAC DNL versus Code
plots can be seen in TPCs 4, 5, and 6.

OFFSET ERROR

This is a measure of the offset error of the DAC and the
output amplifier. (See Figures 5 and 6.) It can be negative
or positive. It is expressed in mV.

OFFSET ERROR MATCH

This is the difference in Offset Error between any two
channels.

GAIN ERROR

This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale
range.

GAIN ERROR MATCH

This is the difference in Gain Error between any two
channels.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with
changes in temperature. It is expressed in (ppm of full­scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full­scale range)/°C.

DC POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the
change in V
the DAC. It is measured in dBs. V
V

is varied ±10%.

DD

DC CROSSTALK

to a change in VDD for full-scale output of

OUT

is held at 2 V and

REF

This is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the
DAC output to the reference input when the DAC output
is not being updated (i.e., LDAC is high). It is expressed
in dBs.

CHANNEL-TO-CHANNEL ISOLATION

This is the ratio of the amplitude of the signal at the out­put of one DAC to a sine wave on the reference input of
another DAC. It is measured in dBs.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the
impulse injected into the analog output when the code in
the DAC register changes state. It is normally specified as
the area of the glitch in nV secs and is measured when the
digital code is changed by 1 LSB at the major carry transi­tion (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected
into the analog output of a DAC from the digital input
pins of the device but is measured when the DAC is not
being written to the. It is specified in nV secs and is mea­sured with a full-scale change on the digital input pins,
i.e., from all 0s to all 1s or vice versa.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of
another DAC. It is measured in stand-alone mode and is
expressed in nV secs.

ANALOG CROSSTALK

This is the glitch impulse transferred to the output of one
DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full­scale code change (all 0s to all 1s and vice versa) while
keeping LDAC high. Then pulse LDAC low and monitor
the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one
DAC due to a digital code change and subsequent out­put change of another DAC. This includes both digital
and analog crosstalk. It is measured by loading one of the
DACs with a full-scale code change (all 0s to all 1s and
vice versa) with LDAC low and monitoring the output of
another DAC. The energy of the glitch is expressed in nV
secs.

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth.
The multiplying bandwidth is a measure of this. A sine
wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying band­width is the frequency at which the output amplitude falls
to 3 dB below the input.

–8– REV. PrN

PRELIMINARY TECHNICAL D A T A

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure of
the harmonics present on the DAC output. It is measured
in dBs.

ROUND ROBIN

This term is used to describe the ADT7316/17/18 cycling
through the available measurement channels in sequence
taking a measurement on each channel.

GAIN ERROR

+

OFFSE T ERROR

ADT7316/7317/7318

OUTP UT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AM PL IFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

LOWER

DEADBAND

CODES

DAC CODE

ACTUAL
IDEAL

Figure 5. Transfer Function with Negative Offset

GAIN ERROR

+

OFFSET ERROR

UPPER

OUTP UT

VOLTAGE

DEADBA ND
CODES

ACTUAL
IDEAL

POSITIVE

OFFSET

ERROR

DAC CODE

FULL SCALE

Figure 6. Transfer Function with Positive Offset (V

–9–REV. PrN

REF

= VDD)

ADT7316/7317/7318

0

PRELIMINARY TECHNICAL D A T A

1.0

TA=25ⴗC

=5V

V

DD

0.5

L

­R

O

0

R
R
E
L
N

I

-0.5

-1.0
050 250100 150 200

CODE

TPC 1. ADT7318 Typical INL Plot

0. 3

TA=25ⴗC
V

=5V

DD

0. 2

s
B
S

0. 1

L

­R
O

0

R
R
E

L

-0.1

N
D

-0.2

3

TA=25ⴗC

=5V

V

DD

2

1

L

­R

0

O
R
R
E
L

-1

N

I

-2

-3
0 200 1000400 600 800

CODE

12

TA=25ⴗC

=5V

V

DD

8

s
B

4

S
L

­R

0

O
R
R
E
L

-4

N

I

-8

-12
040001000 2000 3000

CODE

TPC 2. ADT7317 Typical INL Plot TPC 3. ADT7316 Typical INL Plot

0.6

TA=25ⴗC

=5V

V

DD

0.4

s
B

0.2

S
L

­R

O

0

R
R
E
L

-0.2

N
D

-0.4

1

TA=25ⴗC

=5V

V

DD

0.5

s
B
S
L

­R

O

0

R
R
E
L
N
D

-0.5

-0.3
050 25100 150 200

CODE

TPC 4. ADT7318 Typical DNL Plot

0.5

VDD=5V
T

=25ⴗC

A

0.25

s
B
S
L

­R

0

O
R
R
E

-0.25

-0.5
01 5234

MAX INL

MIN DNL

MIN INL

V

REF

MAX DNL

-V

TPC 7. ADT7318 INL and DNL

Error vs V

REF

-0.6
2000

CODE

600400

800 100

-1
10000

2000

CODE

3000 4000

TPC 5. ADT7317 Typical DNL Plot TPC 6. ADT7316 Typical DNL Plot

0.5

VDD=5V

0.4

V

=3V

REF

0.3

0.2

s
B

0.1

S
L

-

0

R
O
R

-0.1

R
E

-0.2

-0.3

-0.4

-0.5

ⴚ

40 0 40

MAX INL

MAX DNL

MIN DNL

MIN INL

80 120

TEMPERATURE -ⴰC

TPC 8. ADT7318 INL Error and DNL

Error vs Temperature

1

VDD=5V
V

=2V

REF

0.5

R
S
F

%

-

0

R
O
R
R
E

-0.5

-1

ⴚ

GAIN E RROR

OFFS ET ER ROR

40 0 40

TEMPERATURE -ⴰC

80 120

TPC 9. ADT7318 Offset Error and Gain

Error vs Temperature

–10– REV. PrN