Analog Devices ADT7316 7 8 a Datasheet

V

±0.5°C Accurate Digital Temperature Sensor

and Quad Voltage Output 12-/10-/8-Bit DACs

FEATURES

ADT7316—four 12-Bit DACs
ADT7317—four 10-Bit DACs
ADT7318—four 8-Bit DACs
Buffered voltage output
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
Temperature range: −40°C to +120°C
Temperature sensor accuracy of ±0.5°C
Supply range: 2.7 V to 5.5 V
DAC output range: 0 V to 2 V
Power-down current 1 µA
Internal 2.28 V

option

REF

Double-buffered input logic
Buffered/unbuffered reference input option
Power-on reset to 0 V
Simultaneous update of outputs (

On-chip rail-to-rail output buffer amplifier

2

I

C®, SMBus, SPI®, QSPI™, MICROWIRE™, and DSP compatible

4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP package

REF

LDAC

function)

ADT7316/ADT7317/ADT7318

APPLICATIONS

Portable battery-powered instruments
Personal computers
Telecommunications systems
Electronic test equipment
Domestic appliances
Process control

PIN CONFIGURATION

V

-B

V

REF

OUT
OUT

-AB
CS

GND

V

D+
D–

-A

DD

1
2

ADT7316/

3

ADT7317/

ADT7318

4

TOP VIEW

5

(Not to Scale)

6
7
8

Figure 1.

V

16

OUT

15

V

OUT

V

14

REF

SCL/SCLK

13
12

SDA/DIN
DOUT/ADD

11

INT/INT

10

9

LDAC

-C

-D

-CD

02661-A-006

GENERAL DESCRIPTION

The ADT7316/ADT7317/ADT73181 combine a 10-bit temp­erature-to-digital converter and a quad 12-/10-/8-bit DAC,
respectively, in a 16-lead QSOP package. This includes a band
gap temperature sensor and a 10-bit ADC to monitor and
digitize the temperature reading to a resolution of 0.25°C. The
ADT7316/ADT7317/ADT7318 operate from a single 2.7 V to

5.5 V supply. The output voltage of the DAC ranges from 0 V to
, with an output voltage settling time of typ 7 ms. The

2 V

REF

ADT7316/ADT7317/ADT7318 provide two serial interface
options, a 4-wire serial interface that is compatible with SPI,
QSPI, MICROWIRE, and DSP interface standards, and a 2-wire
SMBus/I
controlled via the serial interface.

The reference for the four DACs is derived either internally or
from two reference pins (one per DAC pair). The outputs of all

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

2

C interface. They feature a standby mode that is

DACs may be updated simultaneously using the software LDAC

LDAC

function or external

pin. The ADT7316/ADT7317/
ADT7318 incorporate a power-on-reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place.

The ADT7316/ADT7317/ADT7318’s wide supply voltage range,

2

low supply current, and SPI/I

C compatible interface make
them ideal for a variety of applications, including personal
computers, office equipment, and domestic appliances.

1

Protected by the following U.S. patent numbers: 5,764,174; 5,867,012;

6,097,239; 6,169,442. Other patents pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADT7316/ADT7317/ADT7318

TABLE OF CONTENTS

Specifications..................................................................................... 3

Functional Block Diagram .............................................................. 7

DAC AC Characteristics .................................................................. 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 18

Power-Up Calibration ................................................................18

Conversion Speed....................................................................... 18

Functional Description—Voltage Output ................................... 19

Digital-to-Analog Converters................................................... 19

Digital-to-Analog Section ......................................................... 19

Resistor String............................................................................. 19

Functional Description—Measurement...................................... 22

Temperature Sensor ................................................................... 22

V

Monitoring .......................................................................... 22

DD

On-Chip Reference .................................................................... 23

Round Robin Measurement...................................................... 23

Single-Channel Measurement .................................................. 23

Temperature Measurement Method ........................................ 23

Temperature Value Format ....................................................... 24

Interrupts..................................................................................... 25

Registers........................................................................................... 26

Serial Interface ................................................................................ 34

Serial Interface Selection........................................................... 34

2

I

C Serial Interface ..................................................................... 34

SPI Serial Interface..................................................................... 35

Layout Considerations................................................................... 39

DAC External Reference Inputs ............................................... 19

Output Amplifier........................................................................ 20

Thermal Voltage Output............................................................ 20

REVISION HISTORY

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Updated Format...................................................................... Universal

Internal V

Change to Equation in Thermal Voltage Output Section ..............21

Changes to Outline Dimensions........................................................40

8/03—Initial Version: Rev.0

Value Change................................................... Universal

REF

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

Rev. A | Page 2 of 40

ADT7316/ADT7317/ADT7318

SPECIFICATIONS

Table 1. Temperature ranges are as follows: A Version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless
otherwise noted.

Parameter

DAC DC PERFORMANCE

ADT7318

ADT7317

ADT7316

Offset Error ±0.4 ±2 % of FSR
Gain Error ±0.4 ±2 % of FSR
Lower Dead Band 20 65 mV Lower dead band exists only if offset error is negative. See

Upper Dead Band 60 100 mV Upper dead band exists if V

Offset Error Drift

Gain Error Drift

DC Power Supply Rejection Ratio
DC Crosstalk 200 µV

THERMAL CHARACTERISTICS
INTERNAL TEMPERATURE SENSOR

Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = 85°C.

Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C.

Resolution 10 Bits Equivalent to 0.25°C.
Long Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C.

EXTERNAL TEMPERATURE SENSOR External Transistor = 2N3906.

Thermal Voltage Output

8-Bit DAC Output

17.58 mV/°C

1

See . Terminology

2

DC specifications tested with the outputs unloaded.

3

Linearity is tested using a reduced code range: ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255).

1

2,3

Min Typ Max Unit Conditions/Comments

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic over all codes.

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic over all codes.

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed monotonic over all codes.

Figure 2.

= VDD and offset plus gain

REF

Figure 3.

−12

error is positive. See

ppm of

FSR/°C

−5

ppm of

FSR/°C

−60

dB

∆V
See

DD

= ±10%.

Figure 6.

Internal reference used. Averaging on.

±0.5 ±3 °C TA = 0°C to +85°C.
±2 ±5 °C

±3 ±5 °C

T

= −40°C to +120°C.

A

T

= −40°C to +120°C.

A

Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = 85°C.
±3 °C TA = 0°C to +85°C.
±5 °C

T

= −40°C to +120°C.

A

Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C.
±3 ±5 °C

T

= −40°C to +120°C.

A

Resolution 10 Bits Equivalent to 0.25°C.
Output Source Current 180 µA High level.
11 µA Low level.

Resolution 1 °C
Scale Factor 8.79 mV/°C

0 V to V
0 V to 2 V

Output. TA = −40°C to +120°C.

REF

Output. TA = −40°C to +120°C.

REF

Rev. A | Page 3 of 40

ADT7316/ADT7317/ADT7318

Parameter

1

Min Typ Max Unit Conditions/Comments

10-Bit DAC Output

Resolution 0.25 °C
Scale Factor 2.2 mV/°C

4.39 mV/°C

0 V to V
0 V to 2 V

Output. TA = −40°C to +120°C.

REF

Output. TA= −40°C to +120°C.

REF

CONVERSION TIMES Single Channel Mode.

Slow ADC

V

DD

11.4 ms Averaging (16 samples) on.
712 µs Averaging off.
Internal Temperature 11.4 ms Averaging (16 samples) on.
712 µs Averaging off.
External Temperature 24.22 ms Averaging (16 samples) on

1.51 ms Averaging off.
Fast ADC

V

DD

712 µs Averaging (16 samples) on.

44.5 µs Averaging off.
Internal Temperature 2.14 ms Averaging (16 samples) on.
134 µs Averaging off.

External Temperature 14.25 ms Averaging (16 samples) on.
890 µs Averaging off.
ROUND ROBIN UPDATE RATE4 Time to complete one measurement cycle through all

channels.

Slow ADC at 25°C

Averaging On 59.95 ms

Averaging Off 6.52 ms

Fast ADC at 25°C

Averaging On 19.59 ms

Averaging Off 2.89 ms
DAC EXTERNAL REFERENCE INPUT

V

Input Range 1 V

REF

V

Input Range 0.25 V

REF

V

Input Impedance 37 45

REF

0 V to 2 V
74 90
0 V to V
>10
Reference Feedthrough
Channel-to-Channel Isolation

5

V Buffered reference mode.
V Unbuffered reference mode.
kΩ

kΩ

MΩ

Unbuffered reference mode.

Unbuffered reference mode.

Buffered reference mode and power-down mode.

−90

−75

DD

DD

dB Frequency = 10 kHz.
dB Frequency = 10 kHz.

output range.

REF

output range.

REF

ON-CHIP REFERENCE

Reference Voltage5
Temperature Coefficient5

OUTPUT CHARACTERISTICS5

Output Voltage

6

DC Output Impedance 0.5

2.28 V
80 ppm/C

0.001 V

to

DD

0.001

V This is a measure of the minimum and maximum drive

capability of the output amplifier.

Ω
Short Circuit Current 25 mA VDD = 5 V.
16 mA VDD = 3 V.
Power-Up Time 2.5 µs Coming out of power-down mode. VDD = 5 V.
5 µs Coming out of power-down mode. VDD = 3.3 V.

4

Round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.

5

Guaranteed by design and characterization, but not production tested.

6

In order for the amplifier output to reach its minimum voltage, the offset error must be negative. In order for the amplifier output to reach its maximum voltage, V

, offset plus gain error must be positive.

V

DD

REF

=

Rev. A | Page 4 of 40

ADT7316/ADT7317/ADT7318

Parameter

DIGITAL INPUTS5

1

Min Typ Max Unit Conditions/Comments

Input Current ±1 µA VIN = 0 V to VDD.
Input Low Voltage, V
Input High Voltage, V

IL

IH

0.8 V

1.89 V
Pin Capacitance 3 10 pF All digital inputs.
SCL, SDA Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns.
LDAC

Pulse Width

20 ns Edge triggered input.

DIGITAL OUTPUT

Output High Voltage, V
Output Low Voltage, V
Output High Current, I
Output Capacitance, C

INT

INT/

Output Saturation Voltage

I2C TIMING CHARACTERISTICS

OH

OL

OH

OUT

7,8

Serial Clock Period, t1 2.5 µs

2.4 V I

SOURCE

= I

SINK

0.4 V IOL = 3 mA.

1 mA VOH = 5 V.
50 pF

0.8 V I

= 4 mA.

OUT

Fast-mode I

= 200 µA.

2

C. See Figure 4.

Data In Setup Time to SCL High, t2 50 ns
Data Out Stable after SCL Low, t
SDA Low Setup Time to SCL Low (Start

Condition), t

4

SDA High Hold Time after SCL High
(Stop Condition), t

SDA and SCL Fall Time, t

SPI TIMING CHARACTERISTICS

CS

to SCLK Setup Time, t
SCLK High Pulse Width, t
SCLK Low Pulse, t
Data Access Time after SCLK Falling

11

Edge, t

4

5

6

9,10

1

2

3

Data Setup Time Prior to SCLK Rising
Edge, t

5

Data Hold Time after SCLK Rising
Edge, t

6

CS

to SCLK Hold Time, t7
CS

to DOUT High Impedance, t

8

3

0 ns
50 ns

50 ns

90 ns

See
See

See

See

Figure 4.
Figure 4.

Figure 4.

Figure 4.

0 ns

50 ns
50 ns
35 ns

20 ns

0 ns

0 ns

40 ns

See

See
See
See

See

See

See

See

Figure 7.
Figure 7.
Figure 7.
Figure 7.

Figure 7.

Figure 7.

Figure 7.
Figure 7.

POWER REQUIREMENTS

VDD 2.7 5.5 V
VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level.
IDD (Normal Mode)

2.2 3 mA VDD = 5 V, VIH = V

12

3 mA VDD = 3.3 V, VIH = VDD and VIL = GND.

and VIL = GND.

DD

IDD(Power Down Mode) 10 µA VDD = 3.3 V, VIH = VDD and VIL = GND.
10 µA VDD = 5 V, VIH = V

and VIL = GND.

DD

Power Dissipation 10 mW VDD = 3.3 V. Using Normal Mode.

33 µW VDD = 3.3 V. Using Shutdown Mode.

7

The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer

rate but has a negative effect on the EMC behavior of the part.

8

Guaranteed by design. Not tested in production.

9

Guaranteed by design and characterization, but not production tested.

10

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

11

Measured with the load circuit of . Figure 5

12

IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Rev. A | Page 5 of 40

ADT7316/ADT7317/ADT7318

T

GAIN ERROR

+

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

DAC CODE

ACTUAL
IDEAL

SCL

SDA

DATA IN

SDA

DATA OU

t

4

t

1

Figure 4. I

t

2

t

3

2

C Bus Timing Diagram

t

5

t

6

02661-A-002

LOWER

DEADBAND

CODES

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

Figure 2. DAC Transfer Function with Negative Offset

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

Figure 3. DAC Transfer Function with Positive Offset (V

CS

SCLK

DIN

DAC CODE FULL SCALE

t

1

D7

D6D5D4D3D2D1D0XX XXXXX X

t

2

GAIN ERROR

OFFSET ERROR

UPPER
DEADBAND
CODES

ACTUAL
IDEAL

t

3

200µAI

TO OUTPUT

PIN

C

L

50pF

200µAI

02661-A-007

Figure 5. Load Circuit for Access Time and Bus Relinquish Time

OL

1.6V

OH

02661-A-004

+

TO DAC

OUTPUT

V

DD

4.7kΩ

4.7kΩ

200pF

02661-A-005

Figure 6. Load Circuit for DAC Outputs

02661-A-008

= VDD)

REF

t

7

t

t

6

5

t

8

t

4

DOUT

X X X X X X X XD7D6D5D4D3D2D1 D0

02661-A-003

Figure 7. SPI Bus Timing Diagram

Rev. A | Page 6 of 40

ADT7316/ADT7317/ADT7318

FUNCTIONAL BLOCK DIAGRAM

ADDRESS POINTER

REGISTER

T

LIMIT

HIGH

REGISTERS

LIMIT

T

LOW

REGISTERS

LIMIT

V

DD

REGISTERS

CONTROL CONFIG. 1

REGISTER

CONTROL CONFIG. 2

REGISTER

CONTROL CONFIG. 3

REGISTER

DAC CONFIGURATION

REGISTER

LDAC CONFIGURATION

REGISTER

INTERRUPT MASK

REGISTERS

DAC A

REGISTERS

DAC B

REGISTERS

DAC C

REGISTERS

DAC D

REGISTERS

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN

SELECT

LOGIC

POWER-

DOWN
LOGIC

V

–A

2

OUT

V

–B

1

OUT

V

–C

16

OUT

V

–D

15

OUT

10

INT/INT

D+

D–

TEMPERATURE

7

8

ON-CHIP
SENSOR

ANALOG

MUX

V

DD

SENSOR

INTERNAL TEMPERATURE

VALUE REGISTER

A-TO-D

CONVERTER

EXTERNAL TEMPERATURE

VALUE REGISTER

ADT7316/
ADT7317/

ADT7318

V

DD

VALUE

REGISTER

X
U
M
L
A

COMPARATOR

T

I
G

I
D

LIMIT

STATUS

REGISTERS

X
U
M
L
A
T

I
G

I
D

6 5

VDDGND

SMBus/SPI INTERFACE

4 13 12 11

CS SCL/SCLK SDA/DIN DOUT/ADD

Figure 8.

INTERNAL

9 3 14

REFERENCE

V

–AB V

REF

REF

02661-A-001

–CDLDAC

Rev. A | Page 7 of 40

ADT7316/ADT7317/ADT7318

DAC AC CHARACTERISTICS

Table 2. Guaranteed by design and characterization, but not production tested. VDD = 2.7 V to 5.5 V; RL = 4.7 kΩ to GND;

= 200 pF to GND; 4.7 kΩ to VDD. All specifications T

C

L

Parameter1 Min Typ (@ 25°C) Max Unit Conditions and Comments

Output Voltage Settling Time

ADT7318 6 8 µs 1/4 scale to 3/4 scale change (0x40 to 0xC0).
ADT7317 7 9 µs 1/4 scale to 3/4 scale change (0x100 to 0x300).
ADT7316 8 10 µs 1/4 scale to 3/4 scale change (0x400 to 0xC00).

Slew Rate 0.7 V/µs
Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry.
Digital Feedthrough 0.5
Digital Crosstalk 1 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion −70 dB V

MIN

to T

, unless otherwise noted.

MAX

V

= V

= +5 V

REF

DD

= 2 V ± 0.1 V p-p.

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz.

REF

1

See section. Terminology

Rev. A | Page 8 of 40

ADT7316/ADT7317/ADT7318

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

V

to GND −0.3 V to +7 V

DD

Digital Input Voltage to GND −0.3 V to V
Digital Output Voltage to GND −0.3 V to V
Reference Input Voltage to GND −0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range −40°C to +120°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead QSOP Package
Power Dissipation

Thermal Impedance

θ

Junction-to-Ambient 105.44°C/W

JA

θ

Junction-to-Case 38.8°C/W

JC

1

2

IR Reflow Soldering

(TJ max − TA)/θ

JA

Peak Temperature 220°C (0/5°C)
Time at Peak Temperature 10 sec to 20 sec
Ramp-Up Rate 2°C/sec to 3°C/sec
Ramp-Down Rate −6°C/sec

1

Values relate to package being used on a 4-layer board.

2

Junction-to-case resistance is applicable to components featuring a

preferential flow direction, e.g., components mounted on a heat sink.
Junction-to-ambient resistance is more useful for air-cooled PCB-mounted
components.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

2

Table 4. I

ADD Pin I

C Address Selection

2

C Address

Low 1001 000
Float 1001 010
High 1001 011

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 9 of 40

ADT7316/ADT7317/ADT7318

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

-B

1

V

OUT

2

V

-A

OUT

REF

-AB
CS

GND

V

DD

D+
D–

ADT7316/

3

ADT7317/

ADT7318

4

TOP VIEW

5

(Not to Scale)

6
7
8

Figure 9. Pin Configuration QSOP

Table 5. ADT7316/ADT7317/ADT7318 Pin Function Descriptions

Pin

Mnemonic Description

No.

1 V
2 V
3 V

-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

REF

-AB

Reference Input Pin for DACs A and B. It may be configured as a buffered or unbuffered input to both DACs A and B. It
has an input range from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode. DACs A and B default

DD

on power-up to this pin.

4

CS

SPI Active Low Control Input. This is the frame synchronization signal for the input data. When
the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial

clocks. It is recommended that this pin be tied high to V
5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
6 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
7 D+ Positive connection to external temperature sensor.
8 D− Negative connection to external temperature sensor.
9

LDAC

Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling

edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse

LDAC

width of 20 ns must be applied to the

pin to ensure proper loading of a DAC register. This allows simultaneous
update of all DAC outputs. Bit C3 of Control Configuration 3 register enables
controlling the loading of DAC registers.

10

INT/

INT

11 DOUT/ADD

Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature or V

limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor.

DD

SPI, Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling
edge of SCLK. Open-drain output—needs a pull-up resistor.

2

ADD, I

C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it floating
gives the address 1001 010 and setting it high gives the address 1001 011. The I
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent changes on this pin will have no affect on the I
serial bus address.

12 SDA/DIN

2

C Serial Data Input. I2C serial data that is loaded into the device’s registers is provided on this input. Open-drain

SDA, I
configuration—needs a pull-up resistor.

DIN, SPI Serial Data Input. Serial data to be loaded into the device’s registers is provided on this input. Data is clocked
into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.

13 SCL/SCLK

Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain
configuration—needs a pull-up resistor.

14 V

REF

-CD

Reference Input Pin for DACs C and D. It may be configured as a buffered or unbuffered input to both DACs C and D. It
has an input range from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode. DACs C and D

DD

default on power-up, to this pin.

15 V
16 V

-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

V

-C

16

OUT

15

V

-D

OUT

V

-CD

14

REF

SCL/SCLK

13
12

SDA/DIN
DOUT/ADD

11

INT/INT

10

9

LDAC

DD

02661-A-006

when operating the serial interface in I2C mode.

LDAC

2

C address set up by the ADD pin is

CS

goes low, it enables

pin. Default is with

LDAC

pin

2

C

Rev. A | Page 10 of 40

ADT7316/ADT7317/ADT7318

TERMINOLOGY

Relative Accuracy

Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. Typical
INL versus code plots can be seen in Figure 10, Figure 11, and
Figure 12.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±0.9 LSB
maximum ensures monotonicity. Typical DAC DNL versus
code plots can be seen in Figure 13, Figure 14, and Figure 15.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. (See Figure 2 and Figure 3.) It can be negative or
positive. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devi­ation in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in ppm of full-scale range/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm of full-scale range/°C.

Lo ng Ter m Tempera ture Drif t

This is a measure of the change in temperature error with the
passage of time. It is expressed in degrees Celsius. The concept
of long term stability has been used for many years to describe
by what amount an IC’s parameter would shift during its life­time. This is a concept that has been typically applied to both
voltage references and monolithic temperature sensors. Unfor­tunately, integrated circuits cannot be evaluated at room tem­perature (25°C) for 10 years or so to determine this shift. As a
result, manufacturers very typically perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated
temperatures (between 125°C and 150°C) over a shorter period
of time (typically between 500 and 1000 hours). As a result of
this operation, the lifetime of an integrated circuit is signifi­cantly accelerated due to the increase in rates of reaction within
the semiconductor material.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in decibels. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC Crosstalk

This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated (i.e.,

LDAC

is high). It is expressed in decibels.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in decibels.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011…11 to 100…00 or

100...00 to 011…11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, i.e., from all 0s to all 1s or vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change

LDAC

(all 0s to all 1s and vice versa) while keeping
LDAC

low and monitor the output of the DAC whose digital

high. Pulse

code was not changed. The area of the glitch is expressed
in nV-s.

Rev. A | Page 11 of 40

ADT7316/ADT7317/ADT7318

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code

LDAC

change (all 0s to all 1s and vice versa) with
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

low and

Total Harmonic Distortion

This is the difference between an ideal sine wave and its atten­uated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in
decibels.

Round Robin

This term is used to describe the ADT7316/ADT7317/
ADT7318 cycling through the available measurement channels
in sequence, taking a measurement on each channel.

DAC Output Settling Time

This is the time required, following a prescribed data change,
for the output of a DAC to reach and remain within ±0.5 LSB of
the final value. A typical prescribed change is from 1/4 scale to
3/4 scale.

Rev. A | Page 12 of 40