ANALOG DEVICES ADT7316 Service Manual

±0.5°C Accurate Digital Temperature Sensor

FEATURES

ADT7316—four 12-bit DACs
ADT7317—four 10-bit DACs
ADT7318—four 8-bit DACs
Buffered voltage output
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
Temperature range: −40°C to +120°C
Temperature sensor accuracy of ±0.5°C
Supply range: 2.7 V to 5.5 V
DAC output range: 0 V to 2 V
Power-down current : <10 μA
Internal 2.28 V

option

REF

Double-buffered input logic
Buffered/unbuffered reference input option
Power-on reset to 0 V
Simultaneous update of outputs (
On-chip rail-to-rail output buffer amplifier

2

I

C®-, SMBus-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-

compatible 4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP

REF

LDAC

function)

and Quad Voltage Output 12-/10-/8-Bit DACs

ADT7316/ADT7317/ADT7318

PIN CONFIGURATION

1

V

-B

OUT

2

V

-A

OUT

V

3

-AB

REF

GND

ADT7316/
ADT7317/

4

CS

ADT7318

5

TOP VIEW

(Not to Scale)

6

V

DD

7

D+

8

D– LDAC

Figure 1.

16

V

-C

OUT

15

-D

V

OUT

14

V

-CD

REF

13

SCL/SCLK

12

SDA/DIN

11

DOUT/ADD

10

INT/INT

9

02661-006

APPLICATIONS

Portable battery-powered instruments
Personal computers
Telecommunications systems
Electronic test equipment
Domestic appliances
Process control

GENERAL DESCRIPTION

The ADT7316/ADT7317/ADT73181combine a 10-bit
temperature-to-digital converter and a quad 12-/10-/8-bit
DAC, respectively, in a 16-lead QSOP. This includes a band
gap temperature sensor and a 10-bit ADC to monitor and
digitize the temperature reading to a resolution of 0.25°C. The
ADT7316/ ADT7317/ADT7318 operate from a single 2.7 V to

5.5 V supply. The output voltage of the DAC ranges from 0 V
to 2 V
The ADT7316/ ADT7317/ADT7318 provide two serial inter­face options, a 4-wire serial interface that is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards, and a
2-wire SMBus/I
is controlled via the serial interface.

, with an output voltage settling time of 7 μs typically.

REF

2

C interface. They feature a standby mode that

The reference for the four DACs is derived either internally
or from two reference pins (one per DAC pair). The outputs
of all DACs may be updated simultaneously using the software
LDAC function or external

LDAC

pin. The ADT7316/ADT7317/
ADT7318 incorporate a power-on-reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place.

The ADT7316/ADT7317/ADT7318 wide supply voltage range,
low supply current, and SPI-/I

2

C-compatible interface make
them ideal for a variety of applications, including personal
computers, office equipment, and domestic appliances.

1

Protected by the following U.S. patent numbers: 5,764,174; 5,867,012;

6,097,239; 6,169,442.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2007 Analog Devices, Inc. All rights reserved.

ADT7316/ADT7317/ADT7318

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Functional Block Diagram .............................................................. 8

DAC AC Characteristics.................................................................. 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Terminology .................................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 19

Power-Up Calibration................................................................ 19

Conversion Speed....................................................................... 19

Functional Description—Voltage Output................................... 20

Digital-to-Analog Converters................................................... 20

Digital-to-Analog Section .........................................................20

Resistor String............................................................................. 20

DAC External Reference Inputs ............................................... 20

REVISION HISTORY

1/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 3.......................................................................... 10

Changes to Internal T

[Address 0x25] Section .................................................................. 33

Changes to Internal T

[Address 0x26] Section .................................................................. 33

Changes to External T

[Address 0x27] Section .................................................................. 33

External T

Limit Register (Read/Write) [Address 0x28]

LOW

Section.............................................................................................. 37

Changes to SPI Interface Section.................................................. 38

Updated Outline Dimensions....................................................... 42

Changes to Ordering Guide.......................................................... 42

Limit Register (Read/Write)

HIGH

Limit Register (Read/Write)

LOW

Limit Register (Read/Write)

HIGH

Output Amplifier........................................................................ 21

Thermal Voltage Output ........................................................... 21

Functional Description—Measurement...................................... 23

Temperature Sensor ................................................................... 23

VDD Monitoring .......................................................................... 23

On-Chip Reference .................................................................... 24

Round Robin Measurement...................................................... 24

Single-Channel Measurement.................................................. 24

Temperature Measurement Method........................................ 24

Temperature Value Format ....................................................... 25

Interrupts..................................................................................... 26

Registers........................................................................................... 27

Register Descriptions................................................................. 28

Serial Interface ................................................................................ 36

Serial Interface Selection ........................................................... 36

I2C Serial Interface ..................................................................... 36

SPI Serial Interface..................................................................... 37

Layout Considerations................................................................... 41

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

6/04—Rev. 0 to Rev. A
U

pdated Format...................................................................... Universal

Internal V

Value Change................................................... Universal

REF

Change to Equation in Thermal Voltage Output Section..............21

Changes to Outline Dimensions .......................................................40

8/03—Revision 0: Initial Version

Rev. B | Page 2 of 44

ADT7316/ADT7317/ADT7318

SPECIFICATIONS

Temperature ranges for A version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.

Table 1.

Parameter

DAC DC PERFORMANCE

ADT7318

ADT7317

ADT7316

Offset Error ±0.4 ±2 % of FSR
Gain Error ±0.4 ±2 % of FSR
Lower Dead Band 20 65 mV Lower dead band exists only if offset error is

Upper Dead Band 60 100 mV Upper dead band exists if V

Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk 200 μV

THERMAL CHARACTERISTICS

INTERNAL TEMPERATURE SENSOR

Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = 85°C.

Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C.

Resolution 10 Bits Equivalent to 0.25°C.
Long-Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C.

EXTERNAL TEMPERATURE SENSOR External transistor = 2N3906.

Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = +85°C.
±3 °C TA = 0°C to +85°C.
±5 °C
Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C.
±3 ±5 °C
Resolution 10 Bits Equivalent to +0.25°C.
Output Source Current 180 μA High level.

Thermal Voltage Output

17.58 mV/°C

4.39 mV/°C

1

2, 3

Min Typ Max Unit Conditions/Comments

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic over all codes.

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic over all codes.

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed monotonic over all codes.

−12

−5

−60

ppm of FSR/°C
ppm of FSR/°C
dB

negative. See

plus gain error is positive. See

∆V

= ±10%.

DD

See

Figure 6.

Figure 2.

= VDD and offset

REF

Figure 3.

Internal reference used. Averaging on.

±0.5 ±3 °C TA = 0°C to +85°C.
±2 ±5 °C

±3 ±5 °C

T

= −40°C to +120°C.

A

T

= −40°C to +120°C.

A

T

= −40°C to +120°C.

A

T

= −40°C to +120°C.

A

11 μA Low level.

8-Bit DAC Output

Resolution 1 °C
Scale Factor 8.79 mV/°C

0 V to V
0 V to 2 V

output. TA = −40°C to +120°C.

REF

output. TA = −40°C to +120°C.

REF

10-Bit DAC Output

Resolution 0.25 °C
Scale Factor 2.2 mV/°C

0 V to V
0 V to 2 V

output. TA = −40°C to +120°C.

REF

output. TA= −40°C to +120°C.

REF

Rev. B | Page 3 of 44

ADT7316/ADT7317/ADT7318

Parameter

1

Min Typ Max Unit Conditions/Comments

CONVERSION TIMES Single channel mode.

Slow ADC

VDD 11.4 ms Averaging (16 samples) on.
712 μs Averaging off.
Internal Temperature 11.4 ms Averaging (16 samples) on.
712 μs Averaging off.
External Temperature 24.22 ms Averaging (16 samples) on

1.51 ms Averaging off.
Fast ADC

VDD 712 μs Averaging (16 samples) on.

44.5 μs Averaging off.
Internal Temperature 2.14 ms Averaging (16 samples) on.
134 μs Averaging off.

External Temperature 14.25 ms Averaging (16 samples) on.
890 μs Averaging off.
ROUND ROBIN UPDATE RATE4 Time to complete one measurement cycle

through all channels.

Slow ADC at 25°C

59.95 ms Averaging on.

6.52 ms Averaging off.

Fast ADC at 25°C

19.59 ms Averaging on.

2.89 ms Averaging off.

DAC EXTERNAL REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference mode.

REF

V

Input Range 0.25 VDD V Unbuffered reference mode.

REF

V

Input Impedance 37 45 kΩ Unbuffered reference mode.

REF

0 V to 2 V

5

output range.

REF

74 90 kΩ Unbuffered reference mode.
0 V to V

output range.

REF

>10 MΩ Buffered reference mode and power-down

mode.
Reference Feedthrough
Channel-to-Channel Isolation

−90

−75

dB Frequency = 10 kHz.
dB Frequency = 10 kHz.

ON-CHIP REFERENCE

Reference Voltage5
Temperature Coefficient5

OUTPUT CHARACTERISTICS5

Output Voltage

6

2.2662 2.28 2.2938 V
80 ppm/°C

0.001 V

to 0.001 V This is a measure of the minimum and maximum

DD

drive capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short-Circuit Current 25 mA VDD = 5 V.
16 mA VDD = 3 V.
Power-Up Time 2.5 μs Coming out of power-down mode. VDD = 5 V.
5 μs Coming out of power-down mode. VDD = 3.3 V.

DIGITAL INPUTS5

Input Current ±1 μA VIN = 0 V to VDD.
Input Low Voltage, VIL 0.8 V
Input High Voltage, VIH 1.89 V
Pin Capacitance 3 10 pF All digital inputs.
SCL, SDA Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than

50 ns.
LDAC

Pulse Width

20 ns Edge triggered input.

Rev. B | Page 4 of 44

ADT7316/ADT7317/ADT7318

Parameter1 Min Typ Max Unit Conditions/Comments

DIGITAL OUTPUT

Output High Voltage, VOH 2.4 V I
Output Low Voltage, VOL 0.4 V IOL = 3 mA.
Output High Current, IOH 1 mA VOH = 5 V.
Output Capacitance, C

INT

INT/

Output Saturation Voltage

I2C TIMING CHARACTERISTICS

50 pF

OUT

0.8 V I

7, 8

Serial Clock Period, t1 2.5 μs
Data In Setup Time to SCL High, t2 50 ns
Data Out Stable After SCL Low, t3 0 ns
SDA Low Setup Time to SCL Low

(Start Condition), t

4

SDA High Hold Time After SCL High

(Stop Condition), t

5

50 ns

50 ns

SDA and SCL Fall Time, t6 300 ns
SDA and SCL Rise Time, t6 3009 ns

SPI TIMING CHARACTERISTICS

CS

to SCLK Setup Time, t1

10, 11

0 ns
SCLK High Pulse Width, t2 50 ns
SCLK Low Pulse Width, t3 50 ns
Data Access Time After SCLK Falling

Edge, t

12

4

Data Setup Time Prior to SCLK

Rising Edge, t

5

Data Hold Time after SCLK Rising

Edge, t

6

CS

to SCLK Hold Time, t7

CS

to DOUT High Impedance, t8

35 ns

20 ns

0 ns

0 ns

40 ns

POWER REQUIREMENTS

VDD 2.7 5.5 V
VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level.
IDD (Normal Mode)13 3 mA VDD = 3.3 V, VIH = VDD, and VIL = GND.

2.2 3 mA VDD = 5 V, VIH = V
IDD (Power-Down Mode) 10 μA VDD = 3.3 V, VIH = VDD, and VIL = GND.
10 μA VDD = 5 V, VIH = VDD, and VIL = GND.
Power Dissipation 10 mW VDD = 3.3 V, using normal mode.

33 μW VDD = 3.3 V, using shutdown mode.

1

See the Terminology section.

2

DC specifications tested with the outputs unloaded.

3

Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).

4

A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.

5

Guaranteed by design and characterization, but not production tested.

6

For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

7

The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate,

but has a negative effect on the EMC behavior of the part.

8

Guaranteed by design. Not tested in production.

9

The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.

10

Guaranteed by design and characterization, but not production tested.

11

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

12

Measured with the load circuit of Figure 5.

13

IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

= I

SOURCE

SINK

= 4 mA.

OUT

Fast-mode I

See

Figure 4.

See

Figure 4.

See

Figure 4.

See

Figure 4.

See

Figure 4.

See

Figure 7.

See

Figure 7.

See

Figure 7.

See

Figure 7.

See

Figure 7.

See

Figure 7.

See

Figure 7.

See

Figure 7.

= 200 μA.

2

C. See Figure 4.

, and VIL = GND.

DD

= VDD, offset plus

REF

Rev. B | Page 5 of 44

ADT7316/ADT7317/ADT7318

GAIN ERROR

+

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

NEGATI VE

OFFSET

ERROR

Figure 2. DAC Transfer Functio

LOWER

DEAD BAND

CODES

DAC CODE

n with Negative Offset

ACTUAL
IDEAL

02661-007

GAIN ERROR

+

OFFSET ERROR

UPPER

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

DAC CODE FUL L SCALE

Figure 3. DAC Transfer Function with Positive Offset (V

DEAD BAND
CODES

ACTUAL
IDEAL

= VDD)

REF

02661-008

t

1

SCL

t

5

t

6

02661-002

SDA

DATA IN

SDA

DATA OUT

t

4

Figure 4. I

t

2

t

3

2

C Bus Timing Diagram

Rev. B | Page 6 of 44

ADT7316/ADT7317/ADT7318

V

200µA I

OL

TO OUTPUT

PIN

50pF

C

L

200µA I

1.6V

OH

02661-004

Figure 5. Load Circuit for Access Time and Bus Relinquish Time

DD

TO DAC

OUTPUT

4.7kΩ

4.7kΩ

200pF

02661-005

Figure 6. Load Circuit for DAC Outputs

CS

SCLK

DIN

DOUT

t

1

D7

XXXXXXXXD7D6D5D4D3D2D1 D0

t

2

t

t

3

D6 D5 D4 D3 D2 D1 D0 X X X X X X X X

t

6

5

t

4

Figure 7. SPI Bus Timing Diagram

t

7

t

8

02661-003

Rev. B | Page 7 of 44

ADT7316/ADT7317/ADT7318

FUNCTIONAL BLOCK DIAGRAM

ADDRESS POINTER

REGISTER

T

LIMIT

HIGH

REGISTERS

T

LIMIT

LOW

REGISTERS

V

LIMIT

DD

REGISTERS

CONTROL CONFIG . 1

REGISTER

CONTROL CONFIG . 2

REGISTER

CONTROL CONFIG . 3

REGISTER

DAC CONFIG URATION

REGISTER

LDAC CONFI GURATI ON

REGISTER

INTERRUPT MASK

REGISTERS

DAC A

REGISTERS

DAC B

REGISTERS

DAC C

REGISTERS

DAC D

REGISTERS

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN

SELECT

LOGIC

POWER-

DOWN
LOGIC

16

15

10

2

1

V

OUT

V

OUT

V

OUT

V

OUT

INT/INT

-A

-B

-C

-D

D+

D–

TEMPERATURE

7

8

ON-CHIP

SENSOR

ANALOG

MUX

V

DD

SENSOR

INTERNAL TEM PERATURE

VALUE REGISTER

A-TO- D

CONVERTER

EXTERNAL TEM PERATURE

VALUE REGISTER

ADT7316/
ADT7317/

ADT7318

V

DD

VALUE

REGISTER

X
U

M
L
A

COMPARATO R

IT
IG

D

LIMIT

STATUS

REGISTERS

X
U

M
L
A

IT
IG

D

6 5

VDDGND

SMBus/SPI INTERFACE

4 13 12 11

CS SCL/ SCLK SDA/DIN DOUT/ADD

9 3 14

INTERNAL

REFERENCE

V

-AB V

REF

REF

-CDLDAC

02661-001

Figure 8.

Rev. B | Page 8 of 44

ADT7316/ADT7317/ADT7318

DAC AC CHARACTERISTICS

Guaranteed by design and characterization, but not production tested. VDD = 2.7 V to 5.5 V; RL = 4.7 kΩ to GND;
C

= 200 pF to GND; 4.7 kΩ to VDD. All specifications T

L

Table 2.

Parameter1 Min Typ (@ 25°C) Max Unit Conditions and Comments

Output Voltage Settling Time

ADT7318 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0).
ADT7317 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300).
ADT7316 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00).

Slew Rate 0.7 V/μs
Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry.
Digital Feedthrough 0.5
Digital Crosstalk 1 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion −70 dB V

1

See Terminology section.

MIN

to T

, unless otherwise noted.

MAX

V

= VDD = +5 V.

REF

= 2 V ± 0.1 V p-p.

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz.

REF

Rev. B | Page 9 of 44

ADT7316/ADT7317/ADT7318

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +120°C
Storage Temperature Range −65°C to +150°C
Junction Temperature

16-Lead QSOP 150°C

Power Dissipation

Thermal Impedance

1

2

(TJ max − TA)/θJA

θJA Junction-to-Ambient 105.44°C/W
θJC Junction-to-Case 38.8°C/W

IR Reflow Soldering

Peak Temperature 220°C (0/5°C)
Time at Peak Temperature 10 sec to 20 sec
Ramp-Up Rate 2°C/sec to 3°C/sec
Ramp-Down Rate −6°C/sec

IR Reflow Soldering (Pb-Free Package)

Peak Temperature 260°C (+ 0°C)
Time at Peak Temperature 20 sec to 40 sec
Ramp-Up Rate 3°C/sec maximum
Ramp-Down Rate –6°C/sec maximum
Time 25°C to Peak Temperature 8 minutes maximum

1

Values relate to package being used on a 4-layer board.

2

Junction-to-case resistance is applicable to components featuring a

preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air-cooled, PCB­mounted components.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 4. I2C Address Selection

ADD Pin I

2

C Address

Low 1001 000
Float 1001 010
High 1001 011

ESD CAUTION

Rev. B | Page 10 of 44

ADT7316/ADT7317/ADT7318

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

-B

OUT

2

V

-A

OUT

3

-AB

REF

GND

ADT7316/
ADT7317/

4

CS

ADT7318

5

TOP VIEW

(Not to Scal e)

6

V

DD

7

D+

8

D– LDAC

16

V

15

V

14

V

13

SCL/SCLK

12

SDA/DIN

11

DOUT/ADD

10

INT/INT

9

OUT

OUT

REF

-C

-D

-CD

02661-006

Figure 9. Pin Configuration QSOP

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V
3 V

-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

REF

-AB

Reference Input Pin for DAC A and DAC B. It may be configured as a buffered or unbuffered input to both DAC A

AC B. It has an input range from 0.25 V to V

and D

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

DAC A and DAC B default on power-up to this pin.

4

SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it

CS

enables the input register, and data is transferred in on the rising edges and out on the falling edges of the
subsequent serial clocks. It is recommended that this pin be tied high to V

2

C mode.

in I

when operating the serial interface

DD

5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
6 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
7 D+ Positive connection to external temperature sensor.
8 D− Negative connection to external temperature sensor.
9

Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling

LDAC

edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows

simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC

10

Over-Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when

INT/INT

11 DOUT/ADD

Default is with the LDAC

temperature or V

DOUT: SPI Serial Data Output. L

pin controlling the loading of DAC registers.

limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor.

DD

ogic output. Data is clocked out of any register at this pin. Data is clocked out on

the falling edge of SCLK. Open-drain output—needs a pull-up resistor.

2

C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it

ADD: I

floating gives the address 1001 010, and setting it high gives the address 1001 011. The I
ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the

12 SDA/DIN

second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no
affect on the I

2

C Serial Data Input. I2C serial data that is loaded into the device registers is provided on this input. Open-

SDA: I

2

C serial bus address.

drain configuration—needs a pull-up resistor.

DIN: SPI Serial Data Input. Serial da

ta to be loaded into the device registers is provided on this input. Data is

clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.

13 SCL/SCLK

Serial Clock Input. This is the clock input f

or the serial port. The serial clock is used to clock data out of any register
of the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain
configuration; needs a pull-up resistor.

14 V

REF

-CD

Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to both DAC C

AC D. It has an input range from 0.25 V to V

and D

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

DAC C and DAC D default, on power-up, to this pin.

15 V
16 V

-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

pin.

2

C address set up by the

Rev. B | Page 11 of 44

ADT7316/ADT7317/ADT7318

TERMINOLOGY

Relative Accuracy

Relative accuracy or integral nonlinearity (INL) is a measure of

he maximum deviation, in LSBs, from a straight line passing

t
through the endpoints of the DAC transfer function. Typical
INL vs. code plots can be seen in

Figure 10, Figure 11, and

Figure 12.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
cha

nge and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±0.9 LSB maximum
ensures monotonicity. Typical DAC DNL vs. code plots can be
seen in

Figure 13, Figure 14, and Figure 15.

Offset Error

This is a measure of the offset error of the DAC and the output

mplifier (see Figure 2 and Figure 3). It can be negative or

a
p

ositive. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia-

ion in slope of the actual DAC transfer characteristic from

t
the ideal. It is expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes
in t

emperature. It is expressed in ppm of full-scale range/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
t

emperature. It is expressed in ppm of full-scale range/°C.

Long Term Temperature Drift

This is a measure of the change in temperature error with the

assage of time. It is expressed in degrees Celsius. The concept

p
of long term stability has been used for many years to describe
by what amount an IC’s parameter would shift during its lifetime.
This is a concept that has been typically applied to both voltage
references and monolithic temperature sensors. Unfortunately,
integrated circuits cannot be evaluated at room temperature
(25°C) for 10 years or so to determine this shift. As a result,
manufacturers very typically perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated tem­peratures (between 125°C and 150°C) over a shorter period of
time (typically between 500 and 1000 hours). As a result of this
operation, the lifetime of an integrated circuit is significantly
accelerated due to the increase in rates of reaction within the
semiconductor material.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
i

n the supply voltage. PSRR is the ratio of the change in V
a change in V
in decibels. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC Crosstalk

This is the dc change in the output level of one DAC in response
t

o a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in microvolts.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output to

he reference input when the DAC output is not being updated

t
(that is,

LDAC

is high). It is expressed in decibels.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one

DAC to a sine wave on the reference input of another DAC.

It is measured in decibels.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
i

njected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011…11 to 100…00 or 100...00 to
011…11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
t

he analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s or vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
a

t midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC

ue to a change in the output of another DAC. It is measured by

d
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping
LDAC

low and monitor the output of the DAC whose digital

LDAC

high. Pulse

code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC C rosst a l k

This is the glitch impulse transferred to the output of one DAC
d

ue to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale
code change (all 0s to all 1s and vice versa) with

LDAC

low
and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.

Rev. B | Page 12 of 44

ADT7316/ADT7317/ADT7318

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
m

ultiplying bandwidth is a measure of this. A sine wave on
the reference (with full-scale code loaded to the DAC) appears
on the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its
a

ttenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure
of the harmonics present on the DAC output. It is measured
in decibels.

Round Robin

This term is used to describe the ADT7316/ADT7317/
ADT7318
channels in sequence, taking a measurement on each
channel.

DAC Output S ettling Tim e

This is the time required, following a prescribed data change,

r the output of a DAC to reach and remain within ±0.5 LSB

fo
of the final value. A typical prescribed change is from 1/4 scale
to 3/4 scale.

cycling through the available measurement

Rev. B | Page 13 of 44

ADT7316/ADT7317/ADT7318

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

0

–0.05

INL ERROR (L SB)

–0.10

–0.15

–0.20

050100150

DAC CODE

Figure 10. ADT7318 Typical INL Plot

200 250

2661-009

0.10

0.08

0.06

0.04

0.02

0

–0.02

DNL ERROR (LSB)

–0.04

–0.06

–0.08

–0.10

0 50 100 150 200 250

DAC CODE

Figure 13. ADT7318 Typical DNL Plot

2661-012

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

0 200 400 600

DAC CODE

Figure 11. ADT7317 Typical INL Plot

2.5

2.0

1.5

1.0

0.5

0

–0.5

INL ERROR (L SB)

–1.0

–1.5

–2.0

–2.5

0 500 1000 1500 2000 2500 3000 3500 4000

DAC CODE

Figure 12. ADT7316 Typical INL Plot

800 1000

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

0 200 400 600 800 1000

2661-010

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

2661-011

Figure 14. ADT7317 Typical DNL Plot

0

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 15. ADT7316 Typical DNL Plot

DAC CODE

DAC CODE

2661-013

2661-014

Rev. B | Page 14 of 44