Analog Devices ADSST-SALEM-3T, ADSST-EM-3040 User Manual
FEATURES
High accuracy
Supports IEC 60687/61036 and ANSI C12.1/12.20
Suitable for class0.5 and class0.2 meter
Full four quadrant measurement of parameters
SPI® compatible serial interface
Pulse output with programmable pulse constant as
pulses/kWh or Wh/pulse
Programmable duty cycle for pulse output
Embedded calibration routines for gain and dc offset
Software based phase and nonlinearity compensation for
current transformers
15 kHz sampling frequency
UART mode enables a PC to directly access all computed
parameters
Flags to indicate tamper conditions
Single 3.0 V supply
Developer’s kit to accelerate design process (See
Ordering Guide for separate ordering number.)
GENERAL DESCRIPTION
The ADSST-SALEM-3T energy meter chipset consists of an
efficient ADSST-218x digital signal processor (DSP), a fast and
accurate 6-channel, 16-bit ADSST-73360LAR sigma-delta analog-to-digital converter (ADC), and metering software. Two
chipset versions are available to support differing ranges of
operating temperature: The ADSST-EM-3040 chipset is rated at
0°C to 70°C for commercial applications, while the ADSST-EM3041 chipset operates at –25°C to +85°C for industrial use.
SMPS LCD DISPLAY
RESISTOR
BLOCK
CT
CT
CT
Figure 1. Block Diagram of a Functional Meter
DSP
ADC
ADSST-EM-3040
The ADC and DSP are interfaced to simultaneously acquire
voltage and current samples on all three phases and to perform
mathematically intensive computations to calculate various
instantaneous parameters and perform harmonic analysis. The
SPI BUS
BOOT
FLASH
FLASH
RTC
µC
OPTO
RS-232
03738-0-001
BUTTONS
Powerful Energy Meter Chipset
ADSST-SALEM-3T
chipset can be interfaced to any general-purpose microprocessor to develop state of the art tri-vector or polyphase energy
metering solutions with a wide range of basic currents from 1 A
to 30 A. By incorporating a comprehensive data set of parameters, including instantaneous measurements, accumulated
parameters, and harmonic analysis data, the ADSST-SALEM-3T
chipset meets high end energy metering requirements. The ability to easily configure the chipset for various parameters makes
it a very flexible solution.
The phase and nonlinearity compensation for current
transformers is done in software (patent pending) without
having to use any passive components in the circuit for
compensation, thus minimizing variations in accuracy with
temperature and time.
The ADSST-SALEM-3T measures and computes a large number of parameters essential for high end metering.
Table 1.
Parameter Each Phase Total
RMS Voltage
RMS Current
Active Power
Apparent Power
Inductive Reactive Power
Capacitive Reactive Power
Power Factor
Frequency
Positive Active Energy
Negative Active Energy
Apparent Energy
Positive Inductive Reactive Energy
Negative Inductive Reactive Energy
Positive Capacitive Reactive Energy
Negative Capacitive Reactive Energy
Voltage Magnitude and Phase for All
Odd Harmonics up to 21
Current Magnitude and Phase for All
Odd Harmonics up to 21
st
Order
st
Order
The ADSST-SALEM-3T offers some excellent features that
make the final meter cost-effective and easy to manufacture.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSST-SALEM-3T
TABLE OF CONTENTS
Easy Calibration............................................................................ 3
Effective Phase Compensation ................................................... 3
Ease of Design............................................................................... 3
Quadrant and Other Conventions ............................................. 3
General Description of the ADSST-218x DSP ......................... 4
General Description of the ADSST-73360LAR ADC................ 11
Specifications—ADSST-73360LAR ............................................. 12
Absolute Maximum Ratings—ADSST-73360LAR .................... 14
ESD Caution................................................................................ 14
Pin Configuration and Pin Function Descriptions—
ADSST-73360LAR
.......................................................................... 15
Architecture Overview ................................................................ 4
ADSST-218x Common-Mode Pins ........................................... 6
Clock Signals................................................................................. 7
............................................................................................ 7
RESET
Recommended Operating Conditions ...................................... 7
ADSST-218x Electrical Characteristics ......................................... 8
Absolute Maximum Ratings—ADSST-218x................................. 9
ESD Caution.................................................................................. 9
Pin Configuration—ADSST-218x................................................ 10
REVISION HISTORY
7/04—Revision 0: Initial Version
Pin Function Descriptions ........................................................ 15
Grounding and Layout .............................................................. 16
Power-Up Initialization and Data from the
ADSST-SALEM-3T
Voltage and Current Sensing .................................................... 17
Accuracy of Reference Design Using the
ADSST-SALEM-3T Chipset
Outline Dimensions....................................................................... 20
Ordering Guide............................................................................... 21
.................................................................... 17
..................................................... 18
Rev. 0 | Page 2 of 24
ADSST-SALEM-3T
EASY CALIBRATION
The ADSST-SALEM-3T chipset has highly advanced calibration
routines embedded into the software. Ease of calibration is the
key feature in this chipset. By sending specific commands to the
ADSST-SALEM-3T chipset, the dc offsets and gains for all voltage and current channels can be calibrated automatically. Active
and reactive power calibration is also available for fine-tuning
the errors.
The meter and calibration constants are stored in an external
flash memory, and the lock/unlock calibration feature enables
protection of the calibration constants. The ability to upgrade
the firmware residing in the flash memory makes the meter
adaptable to future needs.
EFFECTIVE PHASE COMPENSATION
The ADSST-SALEM-3T chipset employs an algorithm (patent
pending) for phase compensation. The ADSST-SALEM3T chipset based meter, which is very effective and user friendly,
can be calibrated for phase compensation at three current
points to cover the complete current range. This also reduces
the cost of the end product by reducing the cost of the sensing
elements, i.e., current transformers.
ACTIVE EXPORT
REACTIVE
SIN Φ =–1
EASE OF DESIGN
Designing a complete meter using the ADSST-SALEM-3T is
very easy with the ADSST-SALEM-3T-DK developer’s kit. The
kit in the UART mode enables a user to evaluate and test the
computational element by connecting to a PC, without building
the complete hardware.
QUADRANT AND OTHER CONVENTIONS
The metering data computed by the ADSST-SALEM-3T chipset
uses the following conventions for various parameters:
• Figure 2 gives the quadrant conventions used by the
chipset.
• Import means power delivered from the utility to the user.
• Export means power delivered by the user to the utility.
• Total means total of all three phases.
Import and export are with reference to consumption.
U, I: Magnitude of voltage and current
P: Active Power (U × I × cos Φ)
Q: Reactive Power (U × I × sin Φ)
Φ: Phase angle from the standpoint of I with respect to U,
always positive in counterclockwise direction.
Phase U: L1 = 0° Abs
L2 = 240° Abs
L3 = 120° Abs
ACTIVE IMPORT
(–90° Φ)
(90° ABS)
REACTIVE EXPORT
ACTIVE
COS Φ =–1
(±180° Φ)
(180° ABS)
REACTIVE IMPORT
P–Q– P+Q–
QUADRANT II QUADRANT I
Φ
I
I
Q
QUADRANT III QUADRANT IV
P+Q+
P–Q+
REACTIVE
SIN Φ =+1
Figure 2. Quadrant Conventions
Rev. 0 | Page 3 of 24
(+90° Φ)
(270° ABS)
L1, L2, L3
ACTIVE
CAPACITIVE (LEAD)
ACTIVE
COS Φ = +1
(0° Φ)
(0° ABS)
ACTIVE
INDUCTIVE (LAG)
03738-0-002
ADSST-SALEM-3T
GENERAL DESCRIPTION OF THE ADSST-218X DSP
The ADSST-218x is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The DSP combines the ADSP-2100 family base architecture
(three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, flag I/O, extensive interrupt capabilities, and on-chip program and data
memory.
The ADSST-218x is fabricated in a high speed, low power
CMOS process. Every instruction can execute in a single processor cycle.
The ADSST-218x’s flexible architecture and comprehensive
instruction set enable the processor to perform multiple operations in parallel. In one processor cycle, the ADSST-218x can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
ARCHITECTURE OVERVIEW
The ADSST-218x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSST-218x assembly language uses an
algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program
development.
Figure 3 is the functional block diagram of the ADSST-218x.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations.
• Perform a computational operation
DATA ADDRESS
GENERATORS
DAG1 DAG2
ARITHMETIC UNITS SERIAL PORTS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
16K × 24-BIT
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
SPORT0
MEMORY
16K × 16-BIT
SPORT1
Figure 3. Functional Block Diagram
DATA
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
03738-0-008
Rev. 0 | Page 4 of 24
ADSST-SALEM-3T
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus Program Memory
Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain
BR
control of external buses with bus request/grant signals (
BGH
ADSST-218x to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses
are granted.
, and
BG0
). One execution mode (go mode) enables the
,
The ADSST-218x can respond to 11 interrupts. There are up to
six external interrupts (one edge sensitive, two level sensitive,
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the byte DMA port, and
RESET
the power-down circuitry. There is also a master
The two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation.
signal.
Serial Ports
The ADSST-218x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Package Description
The ADSST-218x is available in a 100-lead low profile quad flat
package (LQFP, refer to Figure 5).
Rev. 0 | Page 5 of 24
ADSST-SALEM-3T
ADSST-218X COMMON-MODE PINS
Table 2.
Pin Name No. of Pins I/O Function
BG
BGH
BMS
BR
CMS
DMS
IOMS
PMS
RD
RESET
WR
IRQ2/
PF7 I/O Programmable I/O Pin
IRQL1/
PF6 I/O Programmable I/O Pin
IRQL0/
PF5 I/O Programmable I/O Pin
IRQE/
PF4 I/O Programmable I/O Pin
MODE A 1 I
PF0 I/O Programmable I/O Pin during Normal Operation
MODE B 1 I
PF1 I/O Programmable I/O Pin during Normal Operation
MODE C 1 I
PF2 I/O Programmable I/O Pin during Normal Operation
MODE D 1 I
PF3 I/O Programmable I/O Pin during Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
EZ-Port 9 I/O For Emulation Use
FI, FO Flag In, Flag Out
FL0, FL1, FL2 3 O Output Flags
GND 10 I Power and Ground
IRQ1:0
PWD
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
PWDACK 1 O Power-Down Control Output
V
DDEXT
V
DDEXT
V
2 I Internal VDD (2.5 V) Power (LQFP)
DDINT
V
4 I Internal VDD (2.5 V) Power (Mini-BGA)
DDINT
1
Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control register. Software configurable.
1 O Bus Grant Output
1 O Bus Grant Hung Output
1 O Byte Memory Select Output
1 I Bus Request Input
1 O Combined Memory Select Output
1 O Data Memory Select Output
1 O Memory Select Output
1 O Program Memory Select Output
1 O Memory Read Enable Output
1 I Processor Reset Input
1 O Memory Write Enable Output
1 I Edge- or Level-Sensitive Interrupt Request
1 I Level-Sensitive Interrupt Requests
1 I Level-Sensitive Interrupt Requests
1 I Edge-Sensitive Interrupt Requests
1
1
1
Mode Select Input−Checked only during RESET
Mode Select Input−Checked only during RESET
Mode Select Input−Checked only during RESET
Mode Select Input−Checked only during RESET
2
Edge- or Level-Sensitive Interrupts
1 I Power-Down Control Input
4
7
I External VDD (2.5 V or 3.3 V) Power (LQFP)
I External V
(2.5 V or 3.3 V) Power (Mini-BGA)
DD
1
Rev. 0 | Page 6 of 24
ADSST-SALEM-3T
CLOCK SIGNALS
Either a crystal or a TTL compatible clock signal can clock the
ADSST-218x.
If an external clock is used, it should be a TTL compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL input must be left unconnected.
RESET
The
The
sequence to assure proper initialization.
power-up must be held long enough to enable the internal clock
to stabilize. If
clock continues to run and does not require stabilization time.
signal initiates a master reset of the ADSST-2185x.
RESET
signal must be asserted during the power-up
RESET
RESET
is activated any time after power-up, the
RESET
during initial
Because the ADSST-218x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 4. The capacitor values
are dependent on the crystal type and should be specified by the
crystal manufacturer. A parallel resonant, fundamental
frequency, microprocessor grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 autobuffer control register.
CLKIN XTAL
DSP
Figure 4. External Crystal Connections
CLKOUT
03738-0-003
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence, the
any subsequent resets, the
minimum pulse-width specification, t
The
input contains some hysteresis; however, if an RC
RESET
circuit is used to generate the
signal should be held low. On
RESET
signal must meet the
RESET
.
RSP
signal, the use of an exter-
RESET
nal Schmitt trigger is recommended.
RECOMMENDED OPERATING CONDITIONS
Table 3.
Parameter Min Max Unit
V
DDINT
V
DDEXT
1
V
INPUT
T
AMB
1
The ADSST-2185x is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but
voltage compliance (on output, V
(MAX) = V
V
OH
RFS1, SCLK0, SCLK1, TFS0, A1–A13, PF0–PF7) and input only pins (CLKIN,
RESET
, BR, DR0, DR1,
2.37 2.63 V
2.37 3.60 V
VIL = –0.3 VIH = 3.6 V
0 70 °C
) depends on the input V
(MAX). This applies to bidirectional pins (D0–D23, RFS0,
DDEXT
PWD
OH
).
DDEXT
; because
Rev. 0 | Page 7 of 24
ADSST-SALEM-3T
ADSST-218X ELECTRICAL CHARACTERISTICS
Table 4.
Parameter Test Conditions Min Typ Max Unit
VIH High Level Input Voltage
VIH High Level CLKIN Voltage @ V
VIL Low Level Input Voltage
VOH High Level Output Voltage
@ V
@ V
VOL Low Level Output Voltage
IIH High Level Input Current
IIL Low Level Input Current
I
Three-State Leakage Current
OZH
I
Three-State Leakage Current
OZL
IDD Supply Current (Idle)
@ V
IDD Supply Current (Dynamic)
@ V
IDD Supply Current (Power-Down)
CI Input Pin Capacitance
CO Output Pin Capacitance
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins:
3
Input only pins: CLKIN,
4
Output pins: BG,
5
Although specified for TTL outputs, all ADSP-2186 outputs are CMOS compatible and will drive to V
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23,
8
0 V on BR.
9
Idle refers to ADSST-218x state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and
Type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to the Power Dissipation section.
12
Applies to LQFP package type.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
RESET, BR
RESET, BR
PMS, DMS, BMS, IOMS, CMS, RD, WR
1, 2
1, 3
3
3
9
10
3, 6
6, 7, 12, 13
, DR0, DR1,
, DR0, DR1,
@ V
= Max 1.5 V
DDINT
= Max 2.0 V
DDINT
@ V
= Min 0.7 V
1, 4, 5
1, 4, 5
7
7
12
DDINT
@ V
= Min, IOH = –0.5 mA 2.0 V
DDEXT
= 3.0 V, IOH = –0.5 mA 2.4 V
DDEXT
= Min, IOH = –100 µA
DDEXT
@ V
= Min, IOL = 2 mA 0.4 V
DDEXT
@ V
= Max, VIN = 3.6 V 10 µA
DDINT
@ V
= Max, VIN = 0 V 10 µA
DDINT
@ V
= Max, VIN = 3.6 V
DDEXT
@ V
= Max, VIN = 0 V
DDEXT
@ V
= 2.5 V, tCK = 15 ns 9 mA
DDINT
= 2.5 V, tCK = 13.3 ns 10 mA
DDINT
@ V
= 2.5 V, tCK = 13.3 ns11, T
DDINT
= 2.5 V, tCK = 15 ns11, T
DDINT
@ V
= 2.5 V, T
DDINT
@ VIN = 2.5 V, fIN = 1.0 MHz, T
@ VIN = 2.5 V, fIN = 1.0 MHz, T
PWD
.
PWD
.
, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0,
PMS, DMS, BMS, IOMS, CMS, RD, WR
6
8
8
= +25°C 35 mA
AMB
= +25°C 38 mA
AMB
= +25°C in Lowest Power Mode 100 mA
AMB
= +25°C 8 pF
AMB
= +25°C 8 pF
AMB
BGH
.
and GND, assuming no dc loads.
DDEXT
V
– 0.3 V
DDEXT
10 µA
10 µA
, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
Rev. 0 | Page 8 of 24
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