Up to 600 MHz, 1.67 ns instruction cycle rate
24M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid
array package
Dual-computation blocks—each containing an ALU, a
multiplier, a shifter, a register file, and a communications
logic unit (CLU)
Dual-integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, four link ports, SDRAM controller, programmable
flag pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
DATA ADDRESS GENERATION
32
32
INTEGER
KALU
32-BIT × 32-BIT
128
128
DAB
DAB
PROGRAM
SEQUENCER
ADDR
FETCH
BTB
PC
IAB
CLU
INTEGER
JALU
32-BIT × 32-BIT
J-BUS ADDR
J-BUS DATA
K-BUS ADDR
K-BUS DATA
I-BUS ADDR
I-BUS DATA
T
X
REGISTER
MULALUSHIFT
FILE
32-BIT × 32-BIT
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for telecommunications
infrastructure and other large, demanding multiprocessor
DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in Table 1)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other
(multiprocessor) DSPs
Eases DSP programming through extremely flexible instruc-
tion set and high-level-language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Provides on-chip arbitration for glueless multiprocessing
24M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4 × CROSSBAR CONNECT
ADADA
A
D
32
128
32
128
32
128
S-BUS ADDR
S-BUS DATA
128
128
Y
REGISTER
FILE
32-BIT × 32-BIT
D
SOC
I/F
21
128
MUL ALU SHIFT
SOC BUS
CLU
JTAG
HOST
MULTI-
PROC
SDRAM
CTRL
C-BUS
ARB
DMA
L0
OUT
L1
OUT
L2
OUT
L3
OUT
JTAG PORT
6
EXTERNAL
PORT
32
64
8
10
EXT DMA
REQ
LINK PORTS
4
8
IN
4
8
4
8
IN
4
8
4
8
IN
4
8
4
8
IN
4
8
ADDR
DATA
CTRL
CTRL
4
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The ADSP-TS201S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting floating-point (IEEE 32-bit and extended
precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal
processors. The TigerSHARC static superscalar architecture lets
the DSP execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word
data, instruction, and I/O access and provide 33.6G bytes per
second of internal memory bandwidth. Operating at 600 MHz,
the ADSP-TS201S processor’s core has a 1.67 ns instruction
cycle time. Using its single-instruction, multiple-data (SIMD)
features, the ADSP-TS201S processor can perform 4.8 billion,
40-bit MACS or 1.2 billion, 80-bit MACS per second. Table 1
shows the DSP’s performance benchmarks.
Table 1. General-Purpose Algorithm Benchmarks
at 600 MHz
Clock
BenchmarkSpeed
Cycles
32-bit algorithm, 1.2 billion MACS/s peak performance
1K point complex FFT
64K point complex FFT
1
(Radix2)15.7 μs9419
1
(Radix2)2.33 ms1397544
FIR filter (per real tap)0.83 ns0.5
[8 × 8][8 × 8] matrix multiply (complex,
I/O DMA transfer rate
External port1G bytes/sn/a
Link ports (each)1G bytes/sn/a
1
Cache preloaded
The ADSP-TS201S processor is code compatible with the other
TigerSHARC processors.
The Functional Block Diagram on Page 1 shows the
ADSP-TS201S processor’s architectural blocks. These blocks
include:
• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, 128-bit CLU, and 32-word register file
and associated data alignment buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status register
• A program sequencer with instruction alignment buffer
(IAB) and branch target buffer (BTB)
• An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
• Four 128-bit internal data buses, each connecting to the six
4M bit memory banks
• On-chip DRAM (24M bit)
• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM
• A 14-channel DMA controller
• Four full-duplex LVDS link ports
• Two 64-bit interval timers and timer expired pin
• An 1149.1 IEEE-compliant JTAG test access port for onchip emulation
Figure 2 on Page 3 shows a typical single-processor system with
external SRAM and SDRAM. Figure 4 on Page 8 shows a typical
multiprocessor system.
ADSP-TS201S
RST_IN
RST_OUT
CLOCK
REFERENCE
REFERENCE
SDRAM
MEMORY
(OPTIONAL)
CS
CLK
ADDR
RAS
CAS
DATA
DQM
WE
CKE
A10
LINK
DEVICES
(4 MAX)
(OPTIONAL)
POR_IN
SCLK
SCLKRA T2–0
SCLK_V
REF
V
REF
IRQ3–0
FLAG3–0
ID2–0
MSSD3–0
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IORD
IOWR
IOEN
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
LxBCMPO
LxDATI3–0P/N
LxCLKINP/N
LxACKO
LxBCMPI
CONTROLIMP1–0
TMR0E
DS2–0
BMS
BRST
ADDR31–0
DATA63–0
WRH/WRL
ACK
MS1–0
MSH
HBR
HBG
BOFF
BR7–0
CPA
DPA
DMAR3–0
BM
BUSLOCK
JTAG
RD
L
S
S
O
E
R
R
T
D
N
D
O
A
C
Figure 2. ADSP-TS201S Single-Processor System with External SDRAM
A
T
A
D
BOOT
EPROM
(OPTIONAL)
CS
ADDR
DATA
MEMORY
(OPTIONAL)
ADDR
DATA
OE
WE
ACK
CS
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
DMA DEVICE
(OPTIONAL)
DATA
Rev. C | Page 3 of 48 | December 2006
ADSP-TS201S
TM
The TigerSHARC DSP uses a Static Superscalar
This architecture is superscalar in that the ADSP-TS201S processor’s core can execute simultaneously from one to four 32-bit
instructions encoded in a very large instruction word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
the DSP does not perform instruction re-ordering at runtime—
the programmer selects which operations will execute in parallel
prior to runtime—the order of instructions is static.
With few exceptions, an instruction line, whether it contains
one, two, three, or four 32-bit instructions, executes with a
throughput of one cycle in a 10-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source
and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs,
the compute blocks, and the program sequencer.
The ADSP-TS201S processor, in most cases, has a two-cycle
execution pipeline that is fully interlocked, so—whenever a
computation result is unavailable for another operation dependent on it—the DSP automatically inserts one or more stall
cycles as needed. Efficient programming with dependency-free
instructions can eliminate most computational and memory
transfer data dependencies.
In addition, the ADSP-TS201S processor supports SIMD operations two ways—SIMD compute blocks and SIMD
computations. The programmer can load both compute blocks
with the same data (broadcast distribution) or different data
(merged distribution).
DUAL COMPUTE BLOCKS
The ADSP-TS201S processor has compute blocks that can execute computations either independently or together as a singleinstruction, multiple-data (SIMD) engine. The DSP can issue up
to two compute instructions per compute block each cycle,
instructing the ALU, multiplier, shifter, or CLU to perform
independent, simultaneous operations. Each compute block can
execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD
computations in parallel with the operation in the other block.
These computation units support IEEE 32-bit single-precision
floating-point, extended-precision 40-bit floating point, and 8-,
16-, 32-, and 64-bit fixed-point processing.
The compute blocks are referred to as X and Y in assembly syntax, and each block contains four computational units—an
ALU, a multiplier, a 64-bit shifter, a 128-bit CLU—and a 32word register file.
• Register File—each compute block has a multiported 32word, fully orthogonal register file used for transferring
data between the computation units and data buses and for
†
Static Superscalar is a trademark of Analog Devices, Inc.
†
architecture.
storing intermediate results. Instructions can access the
registers in the register file individually (word-aligned), in
sets of two (dual-aligned), or in sets of four (quad-aligned).
• ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also
performs logic operations.
• Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and
accumulate.
• Shifter—the 64-bit shifter performs logical and arithmetic
shifts, bit and bit stream manipulation, and field deposit
and extraction operations.
• Communications Logic Unit (CLU)—this 128-bit unit provides trellis decoding (for example, Viterbi and Turbo
decoders) and executes complex correlations for CDMA
communication applications (for example, chip-rate and
symbol-rate functions).
Using these features, the compute blocks can:
• Provide 8 MACS per cycle peak and 7.1 MACS per cycle
sustained 16-bit performance and provide 2 MACS per
cycle peak and 1.8 MACS per cycle sustained 32-bit performance (based on FIR)
• Execute six single-precision floating-point or execute 24
fixed-point (16-bit) operations per cycle, providing
3.6G FLOPS or 14.4G/s regular operations performance at
600 MHz
• Perform two complex 16-bit MACS per cycle
• Execute eight trellis butterflies in one cycle
DATA ALIGNMENT BUFFER (DAB)
The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are
loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as
FIR filters.
DUAL INTEGER ALU (IALU)
The ADSP-TS201S processor has two IALUs that provide powerful address generation capabilities and perform many generalpurpose integer operations. The IALUs are referred to as J and
K in assembly syntax and have the following features:
• Provide memory addresses for data and update pointers
• Support circular buffering and bit-reverse addressing
As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus
and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each
IALU can specify either a single-, dual-, or quad-word access
from memory.
Rev. C | Page 4 of 48 | December 2006
ADSP-TS201S
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly
used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set
up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular
buffers can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
PROGRAM SEQUENCER
The ADSP-TS201S processor’s program sequencer supports the
following:
• A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles
• A 10-cycle instruction pipeline—four-cycle fetch pipe and
six-cycle execution pipe—computation results available
two cycles after operands are available
• Supply of instruction fetch memory addresses; the
sequencer’s instruction alignment buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution
• Management of program structures and program flow
determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software
exceptions
• Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches occur
with zero overhead cycles, overcoming the five-to-nine
stage branch penalty
• Compact code without the requirement to align code in
memory; the IAB handles alignment
Interrupt Controller
The DSP supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each
has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the IRQ3–0
are programmable.
hardware interrupts, which
The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include:
• CLU instructions for communications infrastructure to
govern trellis decoding (for example, Viterbi and Turbo
decoders) and despreading via complex correlations
• Algebraic assembly language syntax
• Direct support for all DSP, imaging, and video arithmetic
types
• Eliminates toggling DSP hardware modes because modes
are supported as options (for example, rounding, saturation, and others) within instructions
• Branch prediction encoded in instruction; enables zerooverhead loops
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
• User-defined partitioning between program and data
memory
DSP MEMORY
The DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in Figure 3.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is subdivided into smaller memory spaces.
The ADSP-TS201S processor internal memory has 24M bits of
on-chip DRAM memory, divided into six blocks of 4M bits
(128K words × 32 bits). Each block—M0, M2, M4, M6, M8, and
M10—can store program instructions, data, or both, so applications can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch. Each memory segment contains a 128K bit
cache to enable single cycle access to internal DRAM.
The six internal memory blocks connect to the four 128-bit wide
internal buses through a crossbar connection, enabling the DSP
to perform four memory transfers in the same cycle. The DSP’s
internal bus architecture provides a total memory bandwidth of
Rev. C | Page 5 of 48 | December 2006
ADSP-TS201S
INTERNAL S PACE
RESERVED
SO C RE GISTE RS (URE GS)
RESERVED
INTERNAL REGISTERS (UREG S)
RESERVED
INTERNAL MEMORY BLOCK 1 0
RESERVED
INTERNAL M EMORY BLOCK 8
RESERVED
INTERNAL MEMORY BLOCK 6
RESERVED
INTERNAL MEMORY BLOCK 4
RESERVED
INTERNAL M EMORY BLOCK 2
RESERVED
INTERNAL M EMORY BLOCK 0
0x03FFFFFF
0x 00 1F0 3F F
0x001F0000
0x 001 E0 3F F
0x001E0000
0x0015FFFF
0x0 01 40 00 0
0x0011FFFF
0x0 01 00 00 0
0x000DFFFF
0x 00 0C0 000
0x0009FFFF
0x0 00 80 00 0
0x0005FFFF
0x0 00 40 00 0
0x0001FFFF
0x0 00 00 00 0
GLOBAL SPACE
HOST (MSH)
RESE RV ED
MSSD BANK 3 (MSSD3)
E
C
A
P
S
Y
R
O
M
E
M
L
A
N
R
E
T
X
E
E
C
A
P
S
Y
R
O
M
E
M
R
O
S
S
E
C
O
R
IP
T
L
U
M
RESE RV ED
MSSD BANK 2 (MSSD2)
RESE RV ED
MSSD BANK 1 (MSSD1)
RESE RV ED
MSSD BANK 0 (MSSD0)
BANK 1 (MS 1)
BANK 0 (MS 0)
PROC ES SOR I D 7
PROC ES SOR I D 6
PROC ES SOR I D 5
PROC ES SOR I D 4
PROC ES SOR I D 3
PROC ES SOR I D 2
PROC ES SOR I D 1
PROC ES SOR I D 0
BROADCAST
RE S ER V ED
INTER NAL MEMORY
0xFFFFFFFF
0x 80 00 00 00
0x 74 00 00 00
0x 70 00 00 00
0x 64 00 00 00
0x 60 00 00 00
0x 54 00 00 00
0x 50 00 00 00
0x4 40 00 00 0
0x4 00 00 00 0
0x 38 00 00 00
0x 300 00 00 0
0x 2C00 00 00
0x 280 00 00 0
0x 240 00 00 0
0x 200 00 00 0
0x 1C00 00 00
0x 180 00 00 0
0x 140 00 00 0
0x 100 00 00 0
0x 0C00 00 00
0x 03 FFFF F F
0x 000 00 00 0
EACH IS A COPY
OF INTERNAL SPACE
Figure 3. ADSP-TS201S Memory Map
33.6G bytes per second, enabling the core and I/O to access
eight 32-bit data-words and four 32-bit instructions each cycle.
The DSP’s flexible memory structure enables:
• DSP core and I/O accesses to different memory blocks in
the same cycle
• DSP core access to three memory blocks in parallel—one
instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS201S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
Rev. C | Page 6 of 48 | December 2006
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus provides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G byte per
second over the external bus.
The external bus can be configured for 32-bit or 64-bit, littleendian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
ADSP-TS201S
The ADSP-TS201S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses; and
external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memorymapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS201S processor provides an easy and configurable
interface between its external bus and host processors through
the external port (see Figure 4). To accommodate a variety of
host processors, the host interface supports pipelined or slow
protocols for ADSP-TS201S processor access of the host as slave
or pipelined for host access of the ADSP-TS201S processor as
slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST
internally while the host continues to assert BRST
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF
nism. When the host asserts BOFF
current transaction and asserts HBG
external bus.
The host can directly read or write the internal memory of the
ADSP-TS201S processor, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector
interrupts support efficient execution of host commands.
signal, the DSP increments the address
.
signal provides the deadlock recovery mecha-
, the DSP backs off the
and relinquishes the
Multiprocessor Interface
The ADSP-TS201S processor offers powerful features tailored
to multiprocessing DSP systems through the external port and
link ports (see Figure 4). This multiprocessing capability provides the highest bandwidth for interprocessor communication,
including:
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Link ports for point-to-point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see Figure 3)
that enables direct interprocessor accesses of each
ADSP-TS201S processor’s internal memory and registers. The
DSP’s on-chip distributed bus arbitration logic provides simple,
glueless connection for systems containing up to eight
ADSP-TS201S processors and a host processor. Bus arbitration
has a rotating priority. Bus lock supports indivisible readmodify-write sequences for semaphores. A bus fairness feature
prevents one DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interprocessor communications with throughput of 4G bytes per second.
The cluster bus provides 1G byte per second throughput—with
a total of 4.8G bytes per second interprocessor bandwidth (limited by SOC bandwidth).
SDRAM Controller
The SDRAM controller controls the ADSP-TS201S processor’s
transfers of data to and from external synchronous DRAM
(SDRAM) at a throughput of 32 bits or 64 bits per SCLK cycle
using the external port and SDRAM control pins.
The SDRAM interface provides a glueless interface with standard SDRAMs—16M bit, 64M bit, 128M bit, 256M bit, and
512M bit. The DSP supports directly a maximum of four banks
of 64M words × 32 bits of SDRAM. The SDRAM interface is
mapped in external memory in each DSP’s unified
memory map.
EPROM Interface
The ADSP-TS201S processor can be configured to boot from an
external 8-bit EPROM at reset through the external port. An
automatic process (which follows reset) loads a program from
the EPROM into internal memory. This process uses 16 wait
cycles for each read access. During booting, the BMS
tions as the EPROM chip select signal. The EPROM boot
procedure uses DMA Channel 0, which packs the bytes into
32-bit instructions. Applications can also access the EPROM
(write flash memories) during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
flash memory interface can be used after boot via a DMA.
pin func-
DMA CONTROLLER
The ADSP-TS201S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions.
The DMA controller performs DMA transfers between internal
memory, external memory, and memory-mapped peripherals;
the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA controller performs the following DMA operations:
• External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memorymapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
• Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad-word data only
between link ports and between a link port and internal or
Figure 4. ADSP-TS201S Shared Memory Multiprocessing System
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
• AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
The DMA controller provides these additional features:
• Flyby transfers. Flyby operations only occur through the
external port (DMA Channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to transfer data from an I/O device to external SDRAM memory.
Rev. C | Page 8 of 48 | December 2006
During a transaction, the DSP relinquishes the external
data bus; outputs addresses and memory selects
(MSSD3–0
RD
); outputs the IORD, IOWR, IOEN, and
/WR strobes; and responds to ACK.
• DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.
• Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
ADSP-TS201S
LINK PORTS (LVDS)
The DSP’s four full-duplex link ports each provide additional
four-bit receive and four-bit transmit I/O capability, using low
voltage, differential-signal (LVDS) technology. With the ability
to operate at a double data rate—latching data on both the rising
and falling edges of the clock—running at up to 500 MHz, each
link port can support up to 500M bytes per second per direction, for a combined maximum throughput of 4G bytes
per second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also
use the link ports for booting.
Each link port has its own triple-buffered quad-word input and
double-buffered quad-word output registers. The DSP’s core
can write directly to a link port’s transmit register and read from
a receive register, or the DMA controller can perform DMA
transfers through eight (four transmit and four receive) dedicated link port DMA channels.
Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit
clock, LxACKI is the handshake input to control the data flow,
and the LxBCMPO
output indicates that the block transfer is
complete. For the receiver, LxCLKIN is the input receive clock,
LxACKO is the handshake output to control the data flow, and
the LxBCMPI
input indicates that the block transfer is complete. The LxDATO3–0 pins are the data output bus for the
transmitter and the LxDATI3–0 pins are the input data bus for
the receiver.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
TIMER AND GENERAL-PURPOSE I/O
The ADSP-TS201S processor has a timer pin (TMR0E) that
generates output when a programmed timer counter has
expired, and four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
After reset, the ADSP-TS201S processor has four boot options
for beginning operation:
• Boot from EPROM.
• Boot by an external master (host or another ADSP-TS201S
processor).
•Boot by link port.
• No boot—start running from memory address selected
with one of the IRQ3–0
interrupt signals. See Table 2.
Using the “no boot” option, the ADSP-TS201S processor must
start running from memory when one of the interrupts is
asserted.
The ADSP-TS201S processor core always exits from reset in the
idle state and waits for an interrupt. Some of the interrupts in
the interrupt vector table are initialized and enabled after reset.
For more information on boot options, see the EE-200:
ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation on the Analog Devices website (www.analog.com).
CLOCK DOMAINS
The DSP uses calculated ratios of the SCLK clock to operate, as
shown in Figure 5. The instruction execution rate is equal to
CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of
SCLK to CCLK (see Table 4 on Page 12). The link port clock is
generated from CCLK via a software programmable divisor, and
the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also
provides clock input for the external bus interface and defines
the ac specification reference for the external bus signals. The
external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal DSP clock
(CCLK) frequency.
RESET AND BOOTING
The ADSP-TS201S processor has three levels of reset:
• Power-up reset – after power-up of the system (SCLK, all
static inputs, and strap pins are stable), the RST_IN
must be asserted (low).
• Normal reset – for any chip reset following the power-up
reset, the RST_IN
pin must be asserted (low).
• DSP-core reset – when setting the SWRST bit in EMUCTL,
the DSP core is reset, but not the external port or I/O.
For normal operations, tie the RST_OUT
POR_IN
pin.
pin to the
pin
Rev. C | Page 9 of 48 | December 2006
SCLK
SCLKRATx
LCTLx REGISTER
PLL
SPD BITS,
Figure 5. Clock Domains
/CR
EXTERNAL INTERFACE
CCLK
(INSTRUCTION RA TE)
SOCCLK
/2
(PERIPHERAL BUS RATE)
LxCLKOUT
(LINK OUTPUT RATE)
ADSP-TS201S
POWER DOMAINS
The ADSP-TS201S processor has separate power supply connections for internal logic (V
buffer (V
), and internal DRAM (V
DD_IO
Note that the analog (V
), analog circuits (V
DD
DD_DRAM
) supply powers the clock generator
DD_A
DD_A
) power supply.
), I/O
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input V
attention to bypassing the V
. Designs must pay critical
DD_A
supply.
DD_A
FILTERING REFERENCE VOLTAGE AND CLOCKS
Figure 6 and Figure 7 show possible circuits for filtering V
and SCLK_V
. These circuits provide the reference voltages
REF
for the switching voltage reference and system clock reference.
V
DD_IO
R1
R2C1C2
V
SS
R1: 2k⍀ SERIES RESISTOR (±1%)
R2: 2.55k⍀ SERIES RESISTOR (±1%)
C1: 1F CAPACITO R (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
Figure 6. V
CLOCK DRIVER
*
VOLTAGE OR
V
DD_IO
R1
R2C1C2
R1: 2k⍀ SERIES RESISTOR (±1%)
R2: 2.55k⍀ SERIES RESISTOR (±1%)
C1: 1F CAPACITOR ( SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
*
IF CLOCK DRIVER VOLTAGE > V
Figure 7. SCLK_V
Filtering Scheme
REF
V
SS
DD_IO
Filtering Scheme
REF
V
REF
SCLK_V
REF
REF
,
DEVELOPMENT TOOLS
The ADSP-TS201S processor is supported with a complete set
of CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS201S processor.
†
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡
VisualDSP++ is a registered trademark of Analog Devices, Inc.
®
†
software and hardware development tools,
®
‡
devel-
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for theses tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important
features. Data visualization is enhanced by a plotting package
that offers a significant level of flexibility. This graphical
representation of user data enables the programmer to quickly
determine the performance of an algorithm. As algorithms grow
in complexity, this capability can have increasing significance
on the designer’s development schedule, increasing
productivity. Statistical profiling enables the programmer to
nonintrusively poll the processor as it is running the program.
This feature, unique to VisualDSP++, enables the software
developer to passively gather important code execution metrics
without interrupting the real-time characteristics of the
program. Essentially, the developer can identify bottlenecks in
software quickly and efficiently. By using the profiler, the
programmer can focus on those areas in the program that
impact performance and take corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits
programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
Rev. C | Page 10 of 48 | December 2006
ADSP-TS201S
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices’ technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
applications. It also is used for downloading components from
the Web, dropping them into the application, and publishing
component archives from within VisualDSP++. VCSE supports
component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system, view memory use in a
color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the
mouse, and examine runtime stack and heap usage. The expert
linker is fully compatible with existing linker definition file
(LDF), allowing the developer to move between the graphical
and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-TS201S processor to monitor and control the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third party software tools include DSP libraries, realtime operating systems, and block diagram design tools.
EVALUATION KIT
®
Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
†
evaluation plat-
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board
processor in-circuit. This permits the customer to download,
execute, and debug programs for the EZ-KIT Lite system. It also
allows in-circuit programming of the on-board flash device to
store user-specific boot code, enabling the board to run as a
standalone unit, without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any
custom-defined system. Connecting one of Analog Devices
JTAG emulators to the EZ-KIT Lite board enables high speed,
nonintrusive emulation.
DESIGNING AN EMULATOR-COMPATIBLE
DSP BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG test access port (TAP) on each JTAG DSP. The emulator
uses the TAP to access the internal features of the DSP, allowing
the developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—
use the string “EE-68” in site search. This document is updated
regularly to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-TS201S processor’s architecture and functionality. For
detailed information on the ADSP-TS201S processor’s core
architecture and instruction set, see the ADSP-TS201 Tiger-
SHARC Processor Hardware Reference and the ADSP-TS201
TigerSHARC Processor Programming Reference. For detailed
information on the development tools for this processor, see the
VisualDSP++ User’s Guide for TigerSHARC Processors.
†
EZ-Kit Lite is a registered trademark of Analog Devices, Inc.
Rev. C | Page 11 of 48 | December 2006
ADSP-TS201S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS201S processor’s input pins are normally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the ac
specification for asynchronous signals when the system design
requires predictable, cycle-by-cycle behavior for these signals.
The output pins can be three-stated during normal operation.
The DSP three-states all output pins during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
pins have an internal pull-up or pull-down resistor (±30% tolerance) that maintains a known value during transitions between
different drivers.
Table 3. Pin Definitions—Clocks and Reset
SignalTypeTermDescription
SCLKRAT2–0I (pd)naCore Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-
programmable using the SCLKRATx pins to the values shown in Table 4 . These pins
may change only during reset; connect these pins to V
or VSS. All reset specifica-
DD_IO
tions in Tab le 25 , Tab le 26 , and Tab le 27 must be satisfied. The core clock rate (CCLK)
is the instruction cycle rate.
SCLKInaSystem Clock Input. The DSP’s system input clock for cluster bus. The core clock rate
is user-programmable using the SCLKRATx pins. For more information, see Clock
Domains on Page 9.
RST_IN
I/AnaReset. Sets the DSP to a known state and causes program to be in idle state. RST_IN
must be asserted a specified time according to the type of reset operation. For details,
see Reset and Booting on Page 9, Table 25 on Page 26, and Figure 13 on Page 26.
RST_OUT
POR_IN
OnaReset Output. Indicates that the DSP reset is complete. Connect to POR_IN.
I/AnaPower-On Reset for internal DRAM. Connect to RST_OUT.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 kΩ to V
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
, nc = not connected; na = not applicable (always used); V
Table 5. Pin Definitions—External Port Bus Controls
SignalTypeTermDescription
ADDR31–0I/O/T
(pu_ad)
DATA63–0I/O/T
(pu_ad)
RD
I/O/T
(pu_0)
WRL
I/O/T
(pu_0)
WRH
I/O/T
(pu_0)
ACKI/O/T/OD
(pu_od_0)
BMS
O/T
(pu_0)
MS1–0
O/T
(pu_0)
MSH
O/T
(pu_0)
BRST
I/O/T
(pu_0)
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
= internal pull-up 40 k
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
1
This external pull-up may be omitted for the ID = 000 TigerSHARC processor.
Ω to V
, nc = not connected; na = not applicable (always used); V
DD_IO
ncAddress Bus. The DSP issues addresses for accessing memory and peripherals on
these pins. In a multiprocessor system, the bus master drives addresses for accessing
internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP
inputs addresses when a host or another DSP accesses its internal memory or I/O
processor registers.
ncExternal Data Bus. The DSP drives and receives data and instructions on these pins.
Pull-up or pull-down resistors on unused DATA pins are unnecessary.
1
epu
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD
is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. RD changes concurrently with ADDR pins.
1
epu
Write Low. WRL is asserted in two cases: when the ADSP-TS201S processor writes to
an even address word of external memory or to another external bus agent; and when
the ADSP-TS201S processor writes to a 32-bit zone (host, memory, or DSP
programmed to 32-bit bus). An external master (host or DSP) asserts WRL
for writing
to a DSP’s low word of internal memory. In a multiprocessor system, the bus master
drives WRL
. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL
is an input and indicates write transactions that access its internal memory or
universal registers.
1
epu
Write High. WRH is asserted when the ADSP-TS201S processor writes a long word
(64 bits) or writes to an odd address word of external memory or to another external
bus agent on a 64-bit data bus. An external master (host or another DSP) must assert
for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system,
WRH
the bus master drives WRH
. WRH changes concurrently with ADDR pins. When the
DSP is a slave, WRH is an input and indicates write transactions that access its internal
memory or universal registers.
1
epu
Acknowledge. External slave devices can deassert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The DSP can deassert ACK to add wait states to read and write
accesses of its internal memory. The pull-up is 50 Ω on low-to-high transactions and
is 500 Ω on all other transactions.
naBoot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS
cessor system, the DSP bus master drives BMS
as a strap pin (EBOOT) for EPROM boot mode. In a multipro-
. For details, see Reset and Booting on
Page 9 and the EBOOT signal description in Table 16 on Page 20.
ncMemory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0
or 1, respectively. MS1–0
with ADDR pins. When ADDR31:27 = 0b00110, MS0
are decoded memory address pins that change concurrently
is asserted. When ADDR31:27 =
0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0.
ncMemory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31 = 0b1). MSH
is a decoded memory address pin that changes concur-
rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH
1
epu
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST
is asserted.
DD_IO
Ω to V
= connect directly to V
; epu = external pull-up approx-
SS
; VSS = connect directly to V
DD_IO
.
SS
Rev. C | Page 13 of 48 | December 2006
ADSP-TS201S
Table 6. Pin Definitions—External Port Arbitration
SignalTypeTermDescription
BR7–0
I/OV
DD_IO
1
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused BRx
pins high (V
DD_IO
).
ID2–0I (pd)naMultiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in
a multiprocessor system. These pins also indicate to the DSP which bus request
(BR0
–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 = BR3
, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a
constant value during system operation and can change during reset only.
BM
OnaBus Master. The current bus master DSP asserts BM. For debugging only. At reset this
is a strap pin. For more information, see Table 16 on Page 20.
BOFF
IepuBack Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
BUSLOCKO/T
(pu_0)
HBR
IepuHost Bus Request. A host must assert HBR to request con trol of the DSP’s externa l bus.
naBus Lock Indication. Provides an indication that the current bus master has locked the
bus. At reset, this is a strap pin. For more information, see Table 16 on Page 20.
When HBR
is asserted in a multiprocessing system, the bus master relinquishes the
bus and asserts HBG once the outstanding transaction is finished.
HBG
I/O/T
(pu_0)
epu
2
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0, MSH
, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD,
IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and HDQM pins, and the DSP
puts the SDRAM in self-refresh mode. The DSP asserts HBG
until the host deasserts
HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave
DSPs monitor it.
CPA
I/O/OD
(pu_od_0)
epu
2
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions. CPA
is an open drain
output, connected to all DSPs in the system. If not required in the system, leave CPA
unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7).
DPA
I/O/OD
(pu_od_0)
epu
2
DMA Priority Access. Asserted while a high priority DSP DMA channel accesses
external memory. This pin enables a high priority DMA channel on a slave DSP to
interrupt transfers of a normal priority DMA channel on a master DSP and gain control
of the external bus for DMA-initiated transactions. DPA
connected to all DSPs in the system. If not required in the system, leave DPA
is an open drain output,
uncon-
nected (external pull-ups will be required for DSP ID = 1 through ID = 7).
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
1
The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V
2
This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Ω to V
; epu = external pull-up approx-
Ω to V
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
SS
; VSS = connect directly to V
DD_IO
DD_IO
SS
.
Rev. C | Page 14 of 48 | December 2006
ADSP-TS201S
Table 7. Pin Definitions—External Port DMA/Flyby
SignalTypeTermDescription
DMAR3–0
IOWR
IORD
IOEN
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull- down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Ω to V
DD_IO
I/AepuDMA Request Pins. Enable external I/O devices to request DMA services from the DSP.
In response to DMARx, the DSP performs DMA transfers according to the DMA
channel’s initialization. The DSP ignores DMA requests from uninitialized channels.
O/T
(pu_0)
ncI/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP
asserts the IOWR
signal during the data cycles. This assertion makes the I/O device
sample the data instead of the TigerSHARC.
O/T
(pu_0)
ncI/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP
asserts the IORD signal during the data cycle. This assertion with the IOEN makes the
I/O device drive the data instead of the TigerSHARC.
O/T
(pu_0)
ncI/O Device Output Enable. Enables the output buffers of an external I/O device for fly-
by transactions between the device and external memory. Active on flyby
transactions.
Ω to V
; epu = external pull-up approx-
, nc = not connected; na = not applicable (always used); V
= connect directly to V
DD_IO
SS
; VSS = connect directly to V
DD_IO
SS
Rev. C | Page 15 of 48 | December 2006
ADSP-TS201S
Table 8. Pin Definitions—External Port SDRAM Controller
SignalTypeTermDescription
MSSD3–0
RAS
CASI/O/T
LDQMO/T
HDQMO/T
SDA10O/T
SDCKEI/O/T
SDWEI/O/T
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
5k
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Ω to V
I/O/T
(pu_0)
ncMemory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins
that are asserted whenever the DSP issues an SDRAM command cycle (access to
ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multiprocessor system, the master DSP drives MSSD3–0
I/O/T
(pu_0)
ncRow Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
ncColumn Address Select. When sampled low, CAS indicates that a column address is
(pu_0)
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
ncLow Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
(pu_0)
buffers. LDQM is valid on SDRAM transactions when CAS
read transactions. On write transactions, LDQM is active when accessing an odd
address word on a 64-bit memory bus to disable the write of the low word.
ncHigh Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
(pu_0)
buffers. HDQM is valid on SDRAM transactions when CAS is asserted, and inactive on
read transactions. On write transactions, HDQM is active when accessing an even
address in word accesses or when memory is configured for a 32-bit bus to disable
the write of the high word.
ncSDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while
(pu_0)
the DSP executes non-SDRAM transactions.
ncSDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
(pu_m/
pd_m)
modes. A slave DSP in a multiprocessor system does not have the pull-up or pulldown. A master DSP (or ID = 0 in a single processor system) has a pull-up before
granting the bus to the host, except when the SDRAM is put in self refresh mode. In
self refresh mode, the master has a pull-down before granting the bus to the host.
ncSDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
(pu_0)
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to
execute according to SDRAM specification.
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
.
is asserted, and inactive on
Ω to V
; epu = external pull-up approx-
SS
; VSS = connect directly to V
DD_IO
SS
Rev. C | Page 16 of 48 | December 2006
Table 9. Pin Definitions—JTAG Port
ADSP-TS201S
SignalTypeTermDescription
EMU
O/ODnc
TCKIepd or epu
TDII (pu_ad)nc
TDOO/Tnc
TMSI (pu_ad)nc
TRST
I/A (pu_ad)naTest Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low
1
1
1
1
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
1
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
Test Data Input (JTAG). A serial data input of the scan path.
Test Data Output (JTAG). A serial data output of the scan path.
Test Mode Select (JTAG). Used to control the test state machine.
after power up for proper device operation. For more information, see Reset and
Booting on Page 9.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull- down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
1
See the reference on Page 11 to the JTAG emulation technical reference EE-68.
Ω to V
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
Ω to V
; epu = external pull-up approx-
SS
; VSS = connect directly to V
DD_IO
Table 10. Pin Definitions—Flags, Interrupts, and Timer
SignalTypeTermDescription
FLAG3–0I/O/A
(pu)
ncFLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
can be configured individually for input or for output. FLAG3–0 are inputs after power-up
and reset.
IRQ3–0
I/A
(pu)
ncInterrupt Request. When asser ted, the DSP generates an interrupt. Each of the IRQ3–0 pins
can be independently set for edge-triggered or level-sensitive operation. After reset, these
pins are disabled unless the IRQ3–0 strap option and interrupt vectors are initialized for
booting.
TMR0EOnaTimer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
For more information, see Table 16 on Page 20.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 kΩ to V
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
Ω to V
; epu = external pull-up approx-
SS
; VSS = connect directly to V
DD_IO
SS
SS
Rev. C | Page 17 of 48 | December 2006
ADSP-TS201S
Table 11. Pin Definitions—Link Ports
SignalTypeTermDescription
LxDATO3–0POncLink Ports 3–0 Data 3–0 Transmit LVDS P
LxDATO3–0NOncLink Ports 3–0 Data 3–0 Transmit LVDS N
LxCLKOUTPOncLink Ports 3–0 Transmit Clock LVDS P
LxCLKOUTNOncLink Ports 3–0 Transmit Clock LVDS N
LxACKII (pd)ncLink Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPO
LxDATI3–0PIV
LxDATI3–0NIV
LxCLKINPI/AV
LxCLKINNI/AV
LxACKOOncLink Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
LxBCMPI
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 kΩ; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on
Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Ω to V
O (pu)ncLink Ports 3–0 Block Completion. When the transmission is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed. The pull-up
resistor is present on L0BCMPO
pins are strap pins. For more information, see Table 16 on Page 20.
DD_IO
DD_IO
DD_IO
DD_IO
Link Ports 3–0 Data 3–0 Receive LVDS P
Link Ports 3–0 Data 3–0 Receive LVDS N
Link Ports 3–0 Receive Clock LVDS P
Link Ports 3–0 Receive Clock LVDS N
transmitter that it may continue the transmission.
I (pd_l)V
SS
Link Ports 3–0 Block Completion. When the reception is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed.
, nc = not connected; na = not applicable (always used); V
Impedance Control. As shown in Tab le 13 , the CONTROLIMP1–0 pins select between
normal driver mode and A/D driver mode. When using normal mode (recommended),
the output drive strength is set relative to maximum drive strength according to
Tab le 14 . When using A/D mode, the resistance control operates in the analog mode,
where drive strength is continuously controlled to match a specific line impedance as
shown in Tab le 14 .
DS2, 0
DS1
I (pu)
I (pd)
naDigital Drive Strength Selection. Selected as shown in Tab le 14 . For drive strength calcu-
lation, see Output Drive Currents on Page 36. The drive strength for some pins is preset,
not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%)
include: CPA, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always
x2 drive strength 7 (100%).
ENEDREGI (pu)V
SS
Connect the ENEDREG pin to VSS. Connect the V
pins to a properly decoupled
DD_DRAM
DRAM power supply.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
5k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Ω to V
; epu = external pull-up approx-
Ω to V
, nc = not connected; na = not applicable (always used); V
LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST
can be
REF
connected to a power supply or set by a voltage divider circuit as shown in Figure 6.
For more information, see Filtering Reference Voltage and Clocks on Page 10.
SCLK_V
REF
InaSystem Clock Reference. Connect this pin to a reference voltage as shown in Figure 7.
For more information, see Filtering Reference Voltage and Clocks on Page 10.
V
SS
GnaGround pins.
NC—ncNo Connect. Do not connect these pins to anything (not to any supply, signal, or each
other). These pins are reserved and must be left unconnected.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
5k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Ω to V
; epu = external pull-up approx-
Ω to V
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
SS
; VSS = connect directly to V
DD_IO
SS
Rev. C | Page 19 of 48 | December 2006
ADSP-TS201S
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an internal pull-up or pull-down
for the default value. If a strap pin is not connected to an overdriving external pull-up, pull-down, or logic load, the DSP
samples the default value during reset. If strap pins are
connected to logic inputs, a stronger external pull-up or pulldown may be required to ensure default value depending on
leakage and/or low level input current of the logic load. To set a
mode other than the default mode, connect the strap pin to a
sufficiently stronger external pull-up or pull-down. Table 16
lists and describes each of the DSP’s strap pins.
Table 16. Pin Definitions—I/O Strap Pins
Type (at
Signal
EBOOTI
IRQENI
LINK_DWIDTHI
SYS_REG_WEI
TM1I
TM2I
TM3I
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
= internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
Reset)On Pin …Description
BMS
(pd_0)
BMInterrupt Enable.
(pd)
TMR0ELink Port Input Default Data Width.
(pd)
BUSLOCK
(pd_0)
L1BCMPO
(pu)
L2BCMPOTest Mode 2. Do not overdrive default value during reset.
(pu)
L3BCMPO
(pu)
EPROM Boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP
through the external port or a link port
0 = disable and set IRQ3–0 interrupts to edge-sensitive after
Test Mode 1. Do not overdrive default value during reset.
Test Mode 3. Do not overdrive default value during reset.
interrupts to level-sensitive
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a
500 Ω resistor connected to V
external pull-downs, do not strap these pins directly to V
is required. If providing
DD_IO
SS
; the
strap pins require 500 Ω resistor straps.
All strap pins are sampled on the rising edge of RST_IN
(deassertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN
sertion of RST_IN
, these pins are reconfigured to their normal
). Shortly after deas-
functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN
is active (low) or if RST_IN is deasserted (high).
Table 17 shows the resistors that are enabled during active reset
pd = internal pull-down 5 k
pd_0 = internal pull-down 5 k
pu_0 = internal pull-up 5 k
= 0) vs. Normal Operation (RST_IN = 1)
(pd_0)(pu_0)
(pd)Driven
(pd_0)(pu_0)
(pu)Driven
(pu)Driven
(pu)Driven
Ω; pu = internal pull-up 5 kΩ;
Ω on DSP ID = 0;
Ω on DSP ID = 0
ADSP-TS201S—SPECIFICATIONS
Note that component specifications are subject to change without notice. For information on link port electrical
characteristics, see Link Port Low Voltage, Differential-Signal
(LVDS) Electrical Characteristics, and Timing on Page 30.
Analog Supply Voltage@ CCLK = 600 MHz0601.141.201.26V
@ CCLK = 500 MHz0501.001.051.10V
V
DD_IO
V
DD_DRAM
I/O Supply Voltage(all)2.382.502.63V
Internal DRAM Supply Voltage@ CCLK = 600 MHz0601.521.601.68V
@ CCLK = 500 MHz0501.425 1.500 1.575 V
T
CASE
T
CASE
V
IH1
V
IH2
V
IL
I
DD
I
DD_A
I
DD_IO
I
DD_DRAM
V
REF
SCLK_V
1
Specifications vary for different grades (for example, SABP-060, SABP-050, SWBP-050). For more information on part grades, see Ordering Guide on Page 46.
Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is equivalent
to 100% duty cycle.
4
V
specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.
IH2
5
Applies to input and bidirectional pins.
6
For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
2
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence. The
practical worst case for period of occurrence for either overshoot or undershoot
is 2 × t
SCLK
.
ELECTRICAL CHARACTERISTICS
Parameter DescriptionTest ConditionsMinMaxUnit
V
OH
V
OL
High Level Input Current@V
I
IH
I
IH_PU
I
IH_PD
I
IH_PD_L
I
Low Level Input Current@V
IL
I
IL_PU
I
IL_PU_AD
I
OZH
I
OZH_PD
Three-State Leakage Current Low @V
I
OZL
I
OZL_PU
I
OZL_PU_AD
I
OZL_OD
C
IN
High Level Output Voltage
Low Level Output Voltage
High Level Input Current@V
High Level Input Current@V
High Level Input Current@V
Low Level Input Current@V
Low Level Input Current@V
Three-State Leakage Current High@V
Three-State Leakage Current High@V
Three-State Leakage Current Low@V
Three-State Leakage Current Low@V
Three-State Leakage Current Low@V
Input Capacitance
2, 3
Parameter name suffix conventions: no suffix = applies to pins without pull-up or pull-down resistors, _PD = applies to pin types (pd) or
(pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD, _PD_L = applies
to pin types (pd_l)
1
Applies to output and bidirectional pins.
2
Applies to all signals.
3
Guaranteed but not tested.
1
1
@V
=Min, IOH = –2 mA2.18V
DD_IO
@V
=Min, IOL=4 mA0.4V
DD_IO
=Max, VIN=VIH Max20μA
DD_IO
=Max, VIN=VIH Max20μA
DD_IO
=Max, VIN=V
DD_IO
=Max, VIN=VIH Max3076μA
DD_IO
=Max, VIN=0 V20μA
DD_IO
=Max, VIN=0 V0.30.76mA
DD_IO
=Max, VIN= 0 V30100μA
DD_IO
=Max, VIN=VIH Max50μA
DD_IO
=Max, VIN=V
DD_IO
=Max, VIN=0 V20μA
DD_IO
=Max, VIN=0 V0.30.76mA
DD_IO
=Max, VIN= 0 V30100μA
DD_IO
=Max, VIN =0 V47.6mA
DD_IO
@fIN=1 MHz, T
CASE
Max0.30.76mA
DD_IO
Max0.30.76mA
DD_IO
=25°C, VIN=2.5 V3pF
Rev. C | Page 22 of 48 | December 2006
ADSP-TS201S
PACKAGE INFORMATION
The information presented in Figure 8 provide details about the
package branding for the ADSP-TS201S processors. For a complete listing of product availability, see Ordering Guide on
Page 46.
a
ADSP-TS20xS
tppZ-ccc
LLLLLLLLL-L 2.0
yyww country_of_origin
T
Figure 8. Typical Package Brand
Table 19. Package Brand Information
Brand KeyField Description
t Temperature Range
pp Package Type
Z Lead Free Option (optional)
cccSee Ordering Guide
LLLLLLLLL-LSilicon Lot Number
R.RSilicon Revision
yywwDate Code
vvvvvvAssembly Lot Code
vvvvv
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 20. Absolute Maximum Ratings
ParameterRating
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (V
External (I/O) Supply Voltage (V
External (DRAM) Supply Voltage (V
Input Voltage
1
Output Voltage Swing–0.5 V to V
Storage Temperature Range–65°C to +150°C
1
Applies to 10% transient duty cycle. For other duty cycles see Table 18.
)–0.3 V to +1.4 V
DD
)–0.3 V to +1.4 V
DD_A
)–0.3 V to +3.5 V
DD_IO
)–0.3 V to +2.1 V
DD_DRAM
–0.63 V to +3.93 V
+0.5 V
DD_IO
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be take to avoid
performance degradation or loss of functionality.
Rev. C | Page 23 of 48 | December 2006
ADSP-TS201S
TIMING SPECIFICATIONS
With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSPTS201S processor has few calculated (formula-based) values.
For information on ac timing, see General AC Timing. For
information on link port transfer timing, see Link Port Low
Voltage, Differential-Signal (LVDS) Electrical Characteristics,
and Timing on Page 30.
General AC Timing
Timing is measured on signals when they cross the 1.25 V level
as described in Figure 15 on Page 29. All delays (in nanoseconds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
Table 21. AC Asynchronous Signal Specifications
NameDescriptionPulse Width Low (Min)Pulse Width High (Min)
1
IRQ3–0
DMAR3–0
FLAG3–0
TMR0E
1
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
2
For output specifications on FLAG3–0 pins, see Table 29.
3
This pin is a strap option. During reset, an internal resistor pulls the pin low.
1
2
3
Interrupt Request2× t
DMA Request2 × t
FLAG3–0 Input2 × t
Timer 0 Expired4×t
The general ac timing data appears in Table 22 and Table 29. All
ac specifications are measured with the load specified in
Figure 36 on Page 38, and with the output drive strength set to
strength 4. In order to calculate the output valid and hold times
for different load conditions and/or output drive strengths, refer
to Figure 37 on Page 38 through Figure 44 on Page 39 (Rise and
Fall Time vs. Load Capacitance) and Figure 45 on Page 39 (Output Valid vs. Load Capacitance and Drive Strength).
The ac asynchronous timing data for the IRQ3–0
, DMAR3–0,
FLAG3–0, and TMR0E pins appears in Table 21.
ns2 × t
SCLK
ns2 × t
SCLK
ns2× t
SCLK
ns—
SCLK
SCLK
SCLK
SCLK
ns
ns
ns
Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time
Grade = 060 (600 MHz)Grade = 050 (500 MHz)
ParameterDescription
1
t
CCLK
1
CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 46.
Core Clock Cycle Time1.6712.52.012.5ns
) divided by the system clock ratio
SCLK
t
CCLK
CCLK
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
UnitMinMaxMinMax
Rev. C | Page 24 of 48 | December 2006
Table 23. Reference Clocks—System Clock (SCLK) Cycle Time
SCLKRAT = 4×, 6×, 8×, 10×, 12× SCLKRAT = 5×, 7×
ParameterDescription
1, 2, 3
t
SCLK
t
SCLKH
t
SCLKL
t
SCLKF
t
SCLKR
5, 6
t
SCLKJ
1
For more information, see Table 3 on Page 12.
2
For more information, see Clock Domains on Page 9.
3
The value of (t
4
System clock transition times apply to minimum SCLK cycle time (t
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
System Clock Cycle Time850850ns
System Clock Cycle High Time0.40 × t
System Clock Cycle Low Time0.40 × t
System Clock Transition Time—Falling Edge
4
—1.5—1.5ns
System Clock Transition Time—Rising Edge—1.5—1.5ns
System Clock Jitter Tolerance—500—500ps
/ SCLKRAT2-0) must not violate the specification for t
SCLK
t
SCLKH
SCLK
t
SCLK
SCLK
CCLK
) only.
t
SCLKL
.
SCLK
SCLK
0.60 × t
0.60 × t
t
SCLKJ
SCLK
SCLK
0.45 × t
0.45 × t
t
SCLKF
ADSP-TS201S
0.55 × t
SCLK
0.55 × t
SCLK
t
SCLKR
SCLK
SCLK
UnitMinMaxMinMax
ns
ns
Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time
Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
ParameterDescriptionMinMaxUnit
t
TCK
t
TCKH
t
TCKL
Test Clock (JTAG) Cycle TimeGreater of 30 or t
× 4 —ns
CCLK
Test Clock (JTAG) Cycle High Time12—ns
Test Clock (JTAG) Cycle Low Time12—ns
t
TCK
TCK
t
TCKH
Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
t
TCKL
Rev. C | Page 25 of 48 | December 2006
ADSP-TS201S
Table 25. Power-Up Timing
1
ParameterMinMaxUnit
Timing Requirement
t
VDD_DRAM
1
For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.
V
DD_A
V
DD_IO
V
DD_DRAM
V
DD_DRAM
V
DD
Stable After VDD, V
t
DD_A
VDD_DRAM
, V
Stable >0ms
DD_IO
Figure 12. Power-Up Timing
Table 26. Power-Up Reset Timing
ParameterMinMaxUnit
Timing Requirements
t
RST_IN_PWR
RST_IN Deasserted After VDD, V
DD_A
, V
DD_IO
, V
DD_DRAM
, SCLK, and Static/
Strap Pins Stable2ms
t
TRST_IN_PWR
1
TRST Asserted During Power-Up Reset100 × t
SCLK
ns
Switching Characteristic
t
RST_OUT_PWR
1
Applies after VDD, V
RST_OUT Deasserted After RST_IN Deasserted1.5ms
, V
DD_A
DD_IO
, V
, and SCLK are stable and before RST_IN deasserted.
DD_DRAM
RST_IN
RST_OUT
TRST
SCLK, V
DD,VDD_A,
V
DD_IO,VDD_DRAM
STATIC/STRAP PINS
t
RST_IN_PWR
t
TRST_IN_PWR
t
RST_OUT_PWR
Figure 13. Power-Up Reset Timing
Rev. C | Page 26 of 48 | December 2006
ADSP-TS201S
Table 27. Normal Reset Timing
ParameterMinMaxUnit
Timing Requirements
t
RST_IN
t
STRAP
Switching Characteristic
t
RST_OUT
RST_IN Asserted2ms
RST_IN Deasserted After Strap Pins Stable1.5ms
RST_OUT Deasserted After RST_IN Deasserted1.5ms
t
RST_IN
RST_IN
t
RST_OUT
RST_OUT
t
STRAP
STRAP PINS
Figure 14. Normal Reset Timing
Table 28. On-Chip DRAM Refresh
1
ParameterMinMaxUnit
Timing Requirement
t
REF
1
For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference.
ACKAcknowledge for Data High to Low1.50.53.61.01.152.0SCLK
Acknowledge for Data Low to High1.50.54.20.91.152.0SCLK
SDCKESDRAM Clock Enable1.50.54.01.01.152.0SCLK
RAS
CAS
SDWE
Row Address Select1.50.54.01.01.152.0SCLK
Column Address Select1.50.54.01.01.152.0SCLK
SDRAM Write Enable1.50.54.01.01.152.0SCLK
LDQMLow Word SDRAM Data Mask——4.01.01.152.0SCLK
HDQMHigh Word SDRAM Data Mask——4.01.01.152.0SCLK
SDA10SDRAM ADDR10——4.01.01.152.0SCLK
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
BM
IORD
IOWR
IOEN
CPA
Host Bus Request1.50.5————SCLK
Host Bus Grant1.50.54.01.01.152.0SCLK
Back Off Request1.50.5————SCLK
Bus Lock——4.01.01.152.0SCLK
Burst Pin1.50.54.01.01.152.0SCLK
Multiprocessing Bus Request Pins1.50.54.01.0——SCLK
Bus Master Debug Aid Only——4.01.0——SCLK
I/O Read Pin——4.01.01.02.0SCLK
I/O Write Pin——4.01.01.152.0SCLK
I/O Enable Pin——4.01.01.152.0SCLK
Core Priority Access High to Low1.50.54.01.00.752.0SCLK
Core Priority Access Low to High1.50.529.52.00.752.0SCLK
DPA
DMA Priority Access High to Low1.50.54.01.00.752.0SCLK
DMA Priority Access Low to High1.50.529.52.00.752.0SCLK
BMS
FLAG3–0
RST_IN
2
3, 4
Boot Memory Select——4.01.01.152.0SCLK
FLAG Pins——4.01.01.152.0SCLK
Global Reset Pin1.52.5————SCLK
5
TMSTest Mode Select (JTAG)1.50.5————TCK
TDITest Data Input (JTAG)1.50.5————TCK
TDO Test Data Output (JTAG)——4.01.00.752.0TCK
4
TRST3,
7
EMU
8
ID2–0
CONTROLIMP1–0
8
Test Reset (JTAG)1.50.5————TCK
Emulation High to Low——5.52.01.154.0TCK or SCLK
Static Pins—Must Be Constant———————
Static Pins—Must Be Constant———————
6
Rev. C | Page 28 of 48 | December 2006
Table 29. AC Signal Specifications (Continued)
(All values in this table are in nanoseconds.)
ADSP-TS201S
1
NameDescription
8
DS2–0
SCLKRAT2–0
8
Static Pins—Must Be Constant———————
Static Pins—Must Be Constant———————
ENEDREGStatic Pins—Must Be Connected to V
STRAP SYS
JTAG SYS
1
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2
For input specifications on FLAG3–0 pins, see Table 21.
3
These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4
For additional requirement details, see Reset and Booting on Page 9.
5
RST_IN clock reference is the falling edge of SCLK.
6
TDO output clock reference is the falling edge of TCK.
7
Reference clock depends on function.
8
These pins may change only during reset; recommend connecting it to V
JTAG system output timing clock reference is the falling edge of TCK.
REFERENCE
CLOCK
t
OR t
SCLK
1.25V
TCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
INPUT
SETUP
OUTPUT
VALID
OUTPUT
DISABLE
1.25V
1.25V
Figure 15. General AC Parameters Timing
Rev. C | Page 29 of 48 | December 2006
INPUT
HOLD
OUTPUT
HOLD
OUTPUT
ENABLE
ADSP-TS201S
Link Port Low Voltage, Differential-Signal (LVDS)
Electrical Characteristics, and Timing
Table 30 and Table 31 with Figure 16 provide the electrical
characteristics for the LVDS link ports. The LVDS link port signal definitions represent all differential signals with a V
level and use signal naming without N (negative) and P (positive) suffixes (see Figure 17).
Table 30. Link Port LVDS Transmit Electrical Characteristics
ParameterDescriptionTest ConditionsMinMaxUnit
V
OH
V
OL
|V
|Output Differential VoltageRL = 100 Ω300650mV
OD
I
OS
V
OCM
Output Voltage High, V
Output Voltage Low, V
O_P
O_P
or V
or V
O_N
O_N
Short-Circuit Output CurrentV
Common-Mode Output Voltage1.201.50V
Table 31. Link Port LVDS Receive Electrical Characteristics
ParameterDescriptionTest ConditionsMinMaxUnit
|Differential Input Voltaget
|V
ID
V
ICM
Common-Mode Input Voltage0.61.57V
OD
=0V
RL = 100 Ω1.85V
RL = 100 Ω0.92V
or V
O_P
V
OD
LDIS/tLDIH
t
LDIS/tLDIH
t
LDIS/tLDIH
t
LDIS/tLDIH
= 0 V+5/– 55mA
O_N
= 0 V±10mA
≥ 0.20 ns
≥ 0.25 ns
≥ 0.30 ns
≥ 0.35 ns
250
217
206
195
850
850
850
850
mV
mV
mV
mV
V
O_P
R
L
V
O_N
VOD=(V
V
OCM
Figure 16. Link Ports—Transmit Electrical Characteristics
DIFFERENTI AL P AIR WAVEFORMS
Lx <P IN >P
Lx<PIN>N
DIFFE RENTIAL VOLTAG E WAVEFORM
Lx<PIN>
V
=0V
OD
VOD=V
V
O_N
V
O_P
O_P–VO_N
Figure 17. Link Ports—Signals Definition
O_P–VO_N
(V
O_P+VO_N
=
)
)
2
Rev. C | Page 30 of 48 | December 2006
ADSP-TS201S
Link Port—Data Out Timing
Table 32 with Figure 18, Figure 19, Figure 20, Figure 21,
Figure 22, and Figure 23 provide the data out timing for the
LVDS link ports.
Table 32. Link Port—Data Out Timing
Parameter DescriptionMinMaxUnit
Outputs
t
REO
t
FEO
t
LCLK OP
t
LCLK OH
t
LCLK OL
t
COJT
t
LDOS
t
LDOH
t
LACKID
t
BCMPOV
t
BCMPOH
Inputs
t
LACKIS
t
LACKIH
1
Timing is relative to the 0 differential voltage (VOD = 0).
2
LCR (link port clock ratio) = 1, 1.5, 2, or 4. t
3
For the cases of t
4
LCR= 1.
5
LCR= 1.5.
6
LCR= 2.
7
LCR= 4.
8
The t
LDOS
9
TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × t
Rising Edge (Figure 19)350ps
Falling Edge (Figure 19)350ps
LxCLKOUT Period (Figure 18)Greater of 2.0 or
0.9 × LCR × t
LxCLKOUT High (Figure 18)0.4× t
LxCLKOUT Low (Figure 18)0.4× t
LCLK OP
LCLK OP
1, 2, 3
CCLK
1
1
LxCLKOUT Jitter (Figure 18)±1504, 5,
LxDATO Output Setup (Figure 20)0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
LxDATO Output Hold (Figure 20)0.25 × LCR × t
0.25 × LCR × t
0.25 × LCR × t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
–0.10 × t
–0.15 × t
–0.30 × t
–0.10 × t
–0.15 × t
–0.30 × t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
1, 4, 8
1,
5, 6,
1,
7,
1, 4, 8
1, 5, 6, 8
1, 7, 8
Delay from LxACKI rising edge to first transmission
Smaller of 12.5 or
1.1 × LCR × t
0.6 × t
0.6 × t
±250
8
8
16 × LCR × t
LCLK OP
LCLK OP
7
1, 2, 3
CCLK
1
1
6
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
1, 2
CCLK
ns
clock edge (Figure 21)
LxBCMPO Valid (Figure 21)2× LCR × t
LxBCMPO Hold (Figure 22)3× TSW – 0.5
1, 9
CCLK
1, 2
ns
ns
LxACKI low setup to guarantee that the transmitter
stops transmitting (Figure 22)
LxACKI high setup to guarantee that the transmitter
continues its transmission without any interruption
(Figure 23)16× LCR × t
CCLK
1, 2
ns
LxACKI High Hold Time (Figure 23)0.51ns
is the core period.
= 2.0 ns and t
LCLKOP
and t
values include LCLKOUT jitter.
LDOH
CCLK
= 12.5 ns, the effect of t
LCLKOP
specification on output period must be considered.
COJT
. For a 1-bit link, it is 8 × LCR × t
CCLK
CCLK
ns.
Rev. C | Page 31 of 48 | December 2006
ADSP-TS201S
t
LCLKOP
VOD=0V
LxCLKOUT
t
COJT
t
LCLKOH
t
LCLKOL
Figure 18. Link Ports—Output Clock
V
+|V
-
O_P
C
t
REO
L_P
C
L_N
t
FEO
R
MIN
OD|
=0V
V
OD
V
MIN
|
OD|
C
L
V
L
O_N
RL=100⍀
=0.1pF
C
L
C
=5pF
L_P
=5pF
C
L_N
Figure 19. Link Ports—Differential Output Signals Transition Time
LxCLKOUT
=0V
V
OD
t
LDOStLDOHtLDOStLDOH
LxDATO
VOD=0V
Figure 20. Link Ports—Data Output Setup and Hold
1
These parameters are valid for both clock edges.
1
LxCLKOUT
V
=0V
OD
LxDATO
VOD=0V
LxACKI
LxBCMPO
t
LACK ID
t
BCMPOV
Figure 21. Link Ports—Transmission Start
Rev. C | Page 32 of 48 | December 2006
LxCLKOUT
V
=0V
OD
LxDATO
VOD=0V
ADSP-TS201S
FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD
LASTEDGEINAQUADWORD
LxACKI
LxBCMPO
LxCLKOUT
V
=0V
OD
t
LACKIS
t
BCMPOH
Figure 22. Link Ports—Transmission End and Stops
LAST EDGE IN A QUAD WORD
t
LACKIH
LxDATO
VOD=0V
LxACKI
t
LACKIS
Figure 23. Link Ports—Back to Back Transmission
Rev. C | Page 33 of 48 | December 2006
t
LACKIH
ADSP-TS201S
Link Port—Data In Timing
Table 33 with Figure 24 and Figure 25 provide the data in
timing for the LVDS link ports.
Table 33. Link Port—Data In Timing
ParameterDescriptionMinMaxUnit
Inputs
t
LCLKI P
t
LDIS
t
LDIH
t
BCMPIS
t
BCMPIH
1
Timing is relative to the 0 differential voltage (VOD = 0).
2
|VID| = 250 mV
3
|VID| = 217 mV
4
|VID| = 206 mV
5
|VID| = 195 mV
LxCLKIN Period (Figure 25)Greater of 1.8
or 0.9 × t
LxDATI Input Setup (Figure 25)0.20
1, 2
0.251,
0.301,
0.351,
0.25
0.30
0.35
1, 2
1, 3
1, 4
1, 5
LxDATI Input Hold (Figure 25)0.20
LxBCMPI Setup (Figure 24)2×t
LxBCMPI Hold (Figure 24)2×t
3
4
5
LCLK IP
LCLK IP
CCLK
1
1
1
12.5ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LxCLKIN
V
=0V
OD
LxDATI
VOD=0V
LxBCMPI
FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD
t
BCMPIS
Figure 24. Link Ports—Last Received Quad Word
t
BCMPIH
Rev. C | Page 34 of 48 | December 2006
LxCLKIN
=0V
V
OD
LxDATI
VOD=0V
t
LCLKIP
t
LDIStLDIHtLDIStLDIH
ADSP-TS201S
Figure 25. Link Ports—Data Input Setup and Hold
1
These parameters are valid for both clock edges.
1
Rev. C | Page 35 of 48 | December 2006
ADSP-TS201S
OUTPUT DRIVE CURRENTS
Figure 26 through Figure 33 show typical I–V characteristics for
the output drivers of the ADSP-TS201S processor. The curves in
these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of
drive strengths. Typical drive currents for intermediate temperatures (such as 85°C) should be obtained from the curves using
linear interpolation. For complete output driver characteristics,
refer to the DSP’s IBIS models, available on the Analog Devices
website (www.analog.com).
15.0
)
A
m
(
T
N
E
R
R
U
C
N
I
P
T
U
P
T
–10.0
U
O
–12.5
–15.0
12.5
10.0
7.5
5.0
2.5
–2.5
–5.0
–7.5
I
OL
V
= 2.38V, +105°C
DD_IO
0
V
=2.38V,+105°C
DD_IO
02.80.40.81.21.62.02.4
Figure 26. Typical Drive Currents at Strength 0
30
5
V
0
DD_IO
V
DD_IO
02.80.4
I
OL
= 2.38V, +105°C
= 2.38V, +105°C
25
20
)
15
A
m
(
10
T
N
E
R
R
U
C
–5
N
I
P
–10
T
U
P
–15
T
U
O
–20
–25
–30
Figure 27. Typical Drive Currents at Strength 1
STRENGTH 0
V
=2.5V,+25°C
DD_IO
V
=2.5V,+25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
STRENGTH 1
V
=2.5V,+25°C
DD_IO
V
=2.5V,+25°C
DD_IO
1.21.62.02.4
0.8
OUTPUT PIN VOLTAGE (V)
V
V
DD_IO
DD_IO
V
DD_IO
V
DD_IO
= 2.63V, –40°C
=2.63V,–40°C
I
OH
= 2.63V, –40°C
= 2.63V, –40°C
I
OH
STRENGTH 2
V
= 2.5V, +25°C
DD_IO
= 2.38V, +105°C
V
= 2.5V, +25°C
DD_IO
1.21.62.02.4
0.8
OUTPUT PIN VOLTAGE (V)
V
DD_IO
)
A
m
(
T
N
E
R
R
U
C
N
I
P
T
U
P
T
U
O
45
36
27
18
9
0
–9
–18
–27
–36
–45
02.80.4
V
DD_IO
I
OL
V
DD_IO
= 2.38V, +105°C
Figure 28. Typical Drive Currents at Strength 2
55
44
33
)
A
m
22
(
T
N
E
11
R
R
U
C
IN
P
–11
T
U
P
T
–22
U
O
–33
–44
–55
I
OL
V
V
DD_IO
DD_IO
= 2.38V, +105°C
= 2.38V, +105°C
0
02.80.40.81.21.62.02.4
STRENGTH 3
V
=2.5V,+25°C
DD_IO
V
=2.5V, +25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
Figure 29. Typical Drive Currents at Strength 3
70
60
50
40
)
A
30
m
(
20
T
N
E
10
R
R
U
C
–10
N
I
P
–20
T
U
–30
P
T
U
–40
O
–50
–60
–70
I
OL
V
V
DD_IO
DD_IO
= 2.38V, +105°C
=2.38V,+105°C
0
02.80.40.81.21.62.02.4
STRENGTH 4
V
=2.5V,+25°C
DD_IO
V
=2.5V,+25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
V
DD_IO
= 2.63V, –40°C
V
DD_IO
V
DD_IO
V
DD_IO
V
DD_IO
= 2.63V, –40°C
I
OH
= 2.63V, –40°C
= 2.63V, –40°C
I
OH
= 2.63V, –40°C
=2.63V,–40°C
I
OH
Rev. C | Page 36 of 48 | December 2006
Figure 30. Typical Drive Currents at Strength 4
ADSP-TS201S
88
77
66
55
)
44
A
m
33
(
T
22
N
E
11
R
R
U
C
–11
IN
P
–22
T
U
–33
P
T
–44
U
O
–55
–66
–77
–88
I
OL
V
V
DD_IO
DD_IO
= 2.38V, +105°C
= 2.38V, +105°C
0
02.80.40.81.21.62.02.4
STRENGTH 5
V
=2.5V,+25°C
DD_IO
V
=2.5V,+25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
Figure 31. Typical Drive Currents at Strength 5
100
)
A
m
(
T
N
E
R
R
U
C
N
I
P
T
U
P
T
U
O
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
90
80
70
60
50
40
30
20
10
I
OL
V
V
DD_IO
DD_IO
=2.38V,+105°C
0
02.80.40.81.21.62.02.4
STRENGTH 6
V
=2.5V,+25°C
DD_IO
= 2.38V, +105°C
V
=2.5V,+25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
Figure 32. Typical Drive Currents at Strength 6
110
)
A
m
(
T
N
E
R
R
U
C
IN
P
T
U
P
T
U
O
100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
90
80
70
60
50
40
30
20
10
I
OL
V
V
DD_IO
DD_IO
= 2.38V, +105°C
= 2.38V, +105°C
0
02.80.40.81.21.62.02.4
STRENGTH 7
V
=2.5V,+25°C
DD_IO
V
=2.5V, +25°C
DD_IO
OUTPUT PIN VOLTAGE (V)
V
V
V
DD_IO
V
DD_IO
DD_IO
V
DD_IO
V
DD_IO
DD_IO
=2.63V,–40°C
= 2.63V, –40°C
I
OH
=2.63V,–40°C
= 2.63V, –40°C
I
OH
= 2.63V, –40°C
=2.63V,–40°C
I
OH
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 29 on Page 28. These include output disable time, output
enable time, and capacitive loading. The timing specifications
for the DSP apply for the voltage reference levels in Figure 34.
INPUT
OR
OUTPUT
Figure 34. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, C
load current, I
lowing equation:
The output disable time t
t
MEASURED_DIS
t
MEASURED_DIS
switches to when the output voltage decays ΔV from the measured output high or output low voltage. t
with test loads C
REFERENCE
V
OH (MEASURED)
V
OL (MEASURED)
1.25V1.25V
. This decay time can be approximated by the fol-
L
and t
t
DECAY
as shown in Figure 35. The time
DECAY
CLVΔ()I
⁄=
L
is the difference between
DIS
is the interval from when the reference signal
is calculated
DECAY
t
MEASURED_ENA
t
ENA
– ⌬V
+ ⌬V
t
RAMP
OUTPUT STARTS
1.65V
0.85V
SIGNAL
and IL, and with ΔV equal to 0.4 V.
L
t
MEASURED_DIS
t
DIS
V
OH (MEASURED)
V
OL (MEASURED)
t
DECAY
OUTPUT STOPS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE A PPROXIMATELY 1.25V.
Figure 35. Output Enable/Disable
and the
L
DRIVING
Figure 33. Typical Drive Currents at Strength 7
Rev. C | Page 37 of 48 | December 2006
ADSP-TS201S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, C
, and the drive current, ID.
L
This ramp time can be approximated by the following equation:
t
RAMP
The output enable time t
t
MEASURED_ENA
t
MEASURED_ENA
and t
RAMP
is the interval from when the reference signal
as shown in Figure 35. The time
CLVΔ()I
⁄=
D
is the difference between
ENA
switches to when the output voltage ramps ΔV from the measured three-stated output level. t
, drive current ID, and with ΔV equal to 0.4 V.
C
L
is calculated with test load
RAMP
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see Figure 36). The delay and hold specifications given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF. Figure 37
through Figure 44 show how output rise time varies with capacitance. Figure 45 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 37.) The graphs of Figure 37 through Figure 45 may not be
linear outside the ranges shown.
30pF
STRENGTH 0
(V
=2.5V)
DD_IO
RISE TIME
50⍀
1.25V
DD_IO
=2.5V)
TO
OUTPUT
PIN
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
25
)
s
n
(
20
S
E
M
I
T
L
L
A
F
D
N
A
E
S
I
R
FALL TIM E
15
Y = 0.251x + 4.2245
10
5
0
0
10 2030 40 50 60 7080 90 100
Y = 0.259x + 3.0842
LOAD CAPACITANCE (pF)
Figure 37. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 0
STRENGTH 1
=2.5V)
(V
25
)
s
n
(
S
E
20
M
I
T
L
L
A
15
F
D
N
A
E
10
S
I
R
5
0
0 102030405060708090100
Y = 0.1527x + 0.7485
DD_IO
FALL TIME
RISE TI ME
Y = 0.1501
LOAD CAPACITANCE (pF)
x
+0.05
Figure 38. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 1
STREN GTH 2
=2.5V)
(V
25
)
s
n
(
S
20
E
M
I
T
L
L
A
15
F
D
N
A
E
10
S
I
R
5
0
0102030405060708090100
DD_IO
FALL TIM E
Y = 0.0949x + 0.8112
RISE TIME
Y = 0.0861
LOAD CAPACITAN CE (pF)
x
+ 0.4712
Figure 39. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 2
STRENGTH 3
=2.5V)
(V
25
)
s
n
(
S
20
E
M
I
T
L
L
A
15
F
D
N
A
E
10
S
I
R
5
0
0 102030405060708090100
DD_IO
FALL TIME
Y = 0.0691x + 1.1158
Y=0.06
LOAD CAPACITANCE (pF)
RISE TIME
x
+1.1362
Figure 40. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 3
DD_IO
DD_IO
DD_IO
=2.5V)
=2.5V)
=2.5V)
Rev. C | Page 38 of 48 | December 2006
ADSP-TS201S
STRENG TH 4
=2.5V
(V
25
)
s
n
(
S
20
E
M
I
T
L
L
15
A
F
D
N
A
E
10
IS
R
5
0
0
1020 30 40 5060 70 80 90 100
DD_IO
FALL TIME
Y = 0.0592x + 1.0629
LOAD CAPACITANCE (pF)
)
RISE TIME
Y = 0.0573x + 0.9789
Figure 41. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 4
STRENGTH 5
=2.5V)
(V
25
)
s
n
(
20
S
E
M
I
T
L
L
15
A
F
D
N
A
10
E
S
I
R
5
0
0
10 2030 40 50 60 7080 90 100
DD_IO
FALL TIME
Y = 0.0493x + 0.8389
LOAD CAPACITANCE (pF)
RISE TIME
Y = 0.0481
x
DD_IO
+0.7889
=2.5V)
STRENGTH 7
(V
=2.5V)
25
)
s
n
(
S
20
E
M
I
T
L
L
15
A
F
D
N
A
10
E
S
I
R
5
0
0
FALL TIME
Y = 0.0313x + 0.818
1020 30 40 50 60 7080 90 100
DD_IO
LOAD CAPACITANCE (pF)
RISE TIME
Y = 0.0321
x
Figure 44. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 7
15
)
s
n
(
10
D
I
L
A
V
T
U
P
T
U
O
5
0
0 102030405060708090100
STRENGTH 0–7
=2.5V)
(V
DD_IO
LOAD CAPACITANCE (pF)
+0.6512
DD_IO
=2.5V)
0
1
2
3
4
5
6
7
Figure 42. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 5
STREN GTH 6
(V
=2.5V)
25
)
s
n
(
S
20
E
M
I
T
L
L
15
A
F
D
N
A
E
10
S
I
R
5
0
0
FALL TIME
Y = 0.0374x + 0.851
10 2030 40 50 60 7080 90 100
DD_IO
LOAD CAPACITANCE (pF)
RISE TIME
Y = 0.0377
x
Figure 43. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 6
Rev. C | Page 39 of 48 | December 2006
DD_IO
+0.7449
DD_IO
=2.5V)
=2.5V)
Figure 45. Typical Output Valid (V
Case Temperature and Strength 0 to 7
1
The line equations for the output valid vs. load capacitance are:
= 2.5 V) vs. Load Capacitance at Max
DD_IO
1
Strength 0: y = 0.1255x + 2.7873
Strength 1: y = 0.0764x + 1.0492
Strength 2: y = 0.0474x + 1.0806
Strength 3: y = 0.0345x + 1.2329
Strength 4: y = 0.0296x + 1.2064
Strength 5: y = 0.0246x + 1.0944
Strength 6: y = 0.0187x + 1.1005
Strength 7: y = 0.0156x + 1.084
ADSP-TS201S
ENVIRONMENTAL CONDITIONS
The ADSP-TS201S processor is rated for performance under
T
environmental conditions specified in the Operating Con-
CASE
ditions on Page 21.
Thermal Characteristics
The ADSP-TS201S processor is packaged in a 25 mm × 25 mm,
thermally enhanced ball grid array (BGA_ED). The
ADSP-TS201S processor is specified for a case temperature
(T
). To ensure that the T
CASE
exceeded, a heat sink and/or an air flow source may be required.
Table 34 shows the thermal characteristics of the 25 mm ×
25 mm BGA_ED package. All parameters are based on a
JESD51-9 four-layer 2s2p board. All data are based on 3 W
power dissipation.
Table 34. Thermal Characteristics for 25 mm × 25 mm
Package
U21L1CLKINNV21L1DATI3_NW21L1CLKONY21L1DATO1_N
U22L1CLKINPV22L1DATI3_PW22L1CLKOPY22L1DATO1_P
U2 3L 1D ATI 1_ NV2 3L1 DAT I2 _ NW 23L1 DAT O3 _NY 23L 1D ATO 2_ N
U2 4L 1D ATI 1_ PV2 4L1 DAT I2 _PW 24L 1D ATO 3_ PY2 4L 1D ATO2 _ P
AA1FLAG2AB1V
AA2FLAG1AB2V
AA3IRQ3AB3V
AA4V
The ADSP-TS201S processor is available in a 25 mm × 25 mm,
576-ball metric thermally enhanced ball grid array (BGA_ED)
package with 24 rows of balls (BP-576).
25.20
25.00
24.80
1.25
1.00
0.75
3.10
2.94
2.78
NOTES:
1. ALL DIMENSIO NS ARE IN MILL IM ETERS.
2. THE ACTUAL PO SITION OF THE BALL GRID IS W ITHIN 0.25 mm OF ITS
IDEAL P OSITIO N RELATIVE TO THE PACKAGE EDGES.
3. CENTER DIMENSIONS ARE NOMINAL.
4. THIS PACKAGE CONFORMS TO JEDEC MS-034 S PECIFICATION.
1.25
1.00
0.75
A1 BALL
INDICATOR
TOP VIEW
25.20
25.00
24.80
DETAIL A
1.00
BSC
23.00
BSC
SQ
1.00
BSC
(BALL
PITCH)
1.00
BSC
0.97 BSC
SEATING PLANE
10121416182024 22
1721 1923
1113
15
BOTTOM VIEW
0.75
0.65
0.55
(BALL
DIAMETER)
ADSP-TS201S
68
42
79531
1.60 MAX
0.20 M AX
0.60
0.50
0.40
B
D
F
H
K
M
P
T
V
Y
AB
AD
A
C
E
G
J
L
N
R
U
W
AA
AC
DETAIL A
Figure 47. 576-Ball BGA_ED (BP-576)
SURFACE MOUNT DESIGN
Table 36 is provided as an aid to PCB design. For industry-
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 36. BGA Data for Use with Surface Mount Design
PackageBall Attach TypeSolder Mask OpeningBall Pad Size
576-Ball BGA_ED
(BP-576)
Nonsolder Mask Defined (NSMD)0.69 mm diameter0.56 mm diameter
Rev. C | Page 45 of 48 | December 2006
ADSP-TS201S
ORDERING GUIDE
Model
Temperature
1
Range
Instruction
2
Rate
On-Chip
DRAMOperating Voltage
ADSP-TS201SABP-060–40°C to +85°C600 MHz24M bit1.20 V
ADSP-TS201SABP-050–40°C to +85°C500 MHz24M bit1.05 V
ADSP-TS201SYBP-050–40°C to +105°C 500 MHz24M bit1.05 V
ADSP-TS201SABPZ060
ADSP-TS201SABPZ050
ADSP-TS201SYBPZ050
1
Represents case temperature.
2
The instruction rate is the same as the internal processor core clock (CCLK) rate.