The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices icon bar and logo, VisualDSP++, the VisualDSP++
logo, Blackfin, the Blackfin logo, the CROSSCORE logo, EZ-KIT Lite,
and EZ-Extender are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF538F EZ-KIT Lite is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end
product or as a portion of a consumer end product. The board is an open
system design which does not include a shielded enclosure and therefore
may cause interference to other electrical devices in close proximity. This
board should not be used in or near any medical equipment or RF devices.
The ADSP-BF538F EZ-KIT Lite has been certified to comply with the
essential requirements of the European EMC directive 89/336/EEC
amended by 93/68/EEC and therefore carries the “CE” mark.
The ADSP-BF538F EZ-KIT Lite has been appended to Analog Devices,
Inc. Technical Construction File (TCF) referenced ‘DSPTOOLS1’ dated
December 21, 1997 and was awarded CE Certification by an appointed
European Competent Body as listed below.
Technical Certificate No: Z600ANA1.028
Issued by: Technology International (Europe) Limited
60 Shrivenham Hundred Business Park
Shrivenham, Swindon, SN6 8TY, UK
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)
sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without detection. Permanent
damage may occur on devices subjected to high-energy discharges. Proper
ESD precautions are recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards in the protective
shipping package.
CONTENTS
PREFACE
Purpose of This Manual ................................................................ xiii
Intended Audience ........................................................................ xiii
Manual Contents ........................................................................... xiv
What’s New in This Manual ........................................................... xiv
Technical or Customer Support ....................................................... xv
Supported Processors ....................................................................... xv
Product Information ...................................................................... xvi
MyAnalog.com ......................................................................... xvi
Processor Product Information .................................................. xvi
Related Documents ................................................................. xvii
Online Technical Documentation ........................................... xviii
Printed Manuals ........................................................................ xx
Notation Conventions .................................................................... xxi
Power ......................................................................................... B-13
INDEX
viiiADSP-BF538F EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-BF538F EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.
Blackfin processors embody a new type of embedded processor designed
specifically to meet the computational demands and power constraints of
today’s embedded audio, video, and communications applications. They
deliver breakthrough signal-processing performance and power efficiency
within a reduced instruction set computing (RISC) programming model.
Blackfin processors support a media instruction set computing (MISC)
architecture. This architecture is the natural merging of RISC, media
functions, and digital signal processing (DSP) characteristics. Blackfin
processors deliver signal-processing performance in a microprocessor-like
environment.
Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit RISC instruction set, dual 16-bit multiply accumulate
(MAC) DSP functionality, and 8-bit video processing performance that
had previously been the exclusive domain of very-long instruction word
(VLIW) media processors.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualix
The evaluation board is designed to be used in conjunction with the VisualDSP++
ADSP-BF538F Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code
development and debug, such as:
Access to the ADSP-BF538F processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-BF538F processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/processors/index.html.
®
development environment to test the capabilities of the
•Create, compile, assemble, and link application programs written
in C++, C, and ADSP-BF538F assembly
•Load, run, step, halt, and set breakpoints in application programs
•Read and write data and program memory
•Read and write core and peripheral registers
•Plot memory
The ADSP-BF538F EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.
L
xADSP-BF538F EZ-KIT Lite Evaluation System Manual
The ADSP-BF538F EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. For
details about evaluation license restrictions after the 90 days, refer
to “Evaluation License Restrictions” on page 1-7 and the Visu-alDSP++ Installation Quick Reference Card.
The board features:
•Analog Devices ADSP-BF538F processor
D Core performance up to 600 MHz
D External bus performance to 133 MHz
D 182-pin mini-BGA package
D 25 MHz crystal
•Synchronous dynamic random access memory (SDRAM)
D MT48LC32M8 – 64 MB (8M x 8-bits x 4 banks) x 2 chips
•Flash memory
D 4MB (2M x 16-bits)
•Analog audio interface
Preface
D AD1871 96 kHz analog-to-digital codec (ADC)
D AD1854 96 kHz digital-to-audio codec (DAC)
D 1 input stereo jack
D 1 output stereo jack
•Controller Area Network (CAN) interface
D Philips TJA1041 high-speed CAN transceiver
•National Instruments Educational Laboratory Virtual Instrumentation Suite (ELVIS) interface
D LabVIEW™-based virtual instruments
D Multifunction data acquisition device
D Bench-top workstation and prototype board
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxi
D ADM3202 RS-232 line driver/receiver
D DB9 female connector
•LEDs
D 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),
5 general-purpose (amber), and 1 USB monitor (amber)
•Push buttons
D 5 push buttons: 1 reset, 4 programmable flags with
debounce logic
•Expansion interface
D All processor signals
•Other features
D JTAG ICE 14-pin header
The EZ-KIT Lite board has flash memory with a total of 4 MB. Flash
memory can be used to store user-specific boot code, allowing the board
to run as a stand-alone unit. For more information, see “Flash Memory”
on page 1-10. The board also has 64 MB of SDRAM, which can be used
by the user at runtime.
SPORT0 interfaces with the audio circuit, facilitating development of audio
signal processing applications. SPORT0, SPORT1, and SPORT2 also interface
to an off-board connector for communication with other serial devices.
For more information, see “SPORT0 Interface” on page 2-4.
The UART of the processor connects to an RS-232 line driver and a DB9
female connector, providing an interface to a PC or other serial device.
xiiADSP-BF538F EZ-KIT Lite Evaluation System Manual
Preface
Additionally, the EZ-KIT Lite board provides access to all of the processor’s peripheral ports. Access is provided in the form of a three-connector
expansion interface. For more information, see “Expansion Interface” on
page 2-8.
Purpose of This Manual
The ADSP-BF538F EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF538F
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
The product software installation is detailed in the VisualDSP++ Installa-tion Quick Reference Card.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual but should supplement it with other texts
(such as the ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Ref-erence and Blackfin Processor Instruction Set Reference) that describe your
target architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxiii
Manual Contents
Manual Contents
The manual consists of:
•Chapter 1, “Using ADSP-BF538F EZ-KIT Lite” on page 1-1.
Describes EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map.
•Chapter 2, “ADSP-BF538F EZ-KIT Lite Hardware Reference” on
page 2-1.
Provides information on the EZ-KIT Lite hardware components.
•Appendix A, “ADSP-BF538F EZ-KIT Lite Bill Of Materials” on
page A-1.
Provides a list of components used to manufacture the EZ-KIT
Lite board.
•Appendix B, “ADSP-BF538F EZ-KIT Lite Schematic” on
page B-1.
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design. Appendix B is part of the online
Help.
What’s New in This Manual
The ADSP-BF538F EZ-KIT Lite Evaluation System Manual has been
updated to reflect the latest revision of the board.
xivADSP-BF538F EZ-KIT Lite Evaluation System Manual
Technical or Customer Support
You can reach Analog Devices, Inc. Customer Support in the following
ways:
•Visit the Embedded Processing and DSP products Web site at
•Contact your Analog Devices, Inc. local sales office or authorized
distributor
•Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This evaluation system supports Analog Devices ADSP-BF538F Blackfin
embedded processors.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxv
Product Information
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publica-
tions, data sheets, application notes, product overviews, and product
announcements.
xviADSP-BF538F EZ-KIT Lite Evaluation System Manual
Preface
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxvii
Product Information
Table 2. Related VisualDSP++ Publications
TitleDescription
ADSP-BF538F EZ-KIT Lite Evaluation System
Manual
VisualDSP++ User’s GuideDescription of the VisualDSP++ features and
VisualDSP++ Assembler and Preprocessor ManualsDescription of the assembler function and
VisualDSP++ C/C++ Complier and Library Manual for Blackfin Processors
VisualDSP++ Linker and Utilities ManualDescription of the linker function and com-
VisualDSP++ Loader and Utilities ManualDescription of the loader/splitter function
Description of the hardware capabilities of
the evaluation system; description of how to
access these capabilities in the VisualDSP++
environment.
usage.
commands.
Description of the complier function and
commands for Blackfin processors.
mands.
and commands.
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .pdf files of most manuals are provided in the
Docs folder on the VisualDSP++ installation CD.
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows® Explorer, or the Analog Devices
Web site. Each documentation file type is described as follows.
xviiiADSP-BF538F EZ-KIT Lite Evaluation System Manual
File Description
.chmHelp system files and manuals in Help format
Preface
.htm or
.html
.pdfVisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the
Internet Explorer 6.0 (or higher).
Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
.html files requires a browser, such as
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-BF538F EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.chm) are located in the Help folder, and .pdf files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
Your software installation kit includes online Help as part of the Windows
interface. These help files provide information about VisualDSP++ and
the ADSP-BF538F EZ-KIT Lite evaluation system.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxix
Select a processor family and book title. Download archive (.zip) files,
one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xxADSP-BF538F EZ-KIT Lite Evaluation System Manual
Notation Conventions
Text conventions used in this manual are identified and described as follows. Additional conventions, which apply only to specific chapters, may
appear throughout this document.
ExampleDescription
Preface
Close command
(File menu)
{this | that}Alternative required items in syntax descriptions appear within curly
[this | that]Optional items in syntax descriptions appear within brackets and sepa-
[this,…]Optional item lists in syntax descriptions appear within brackets delim-
.SECTIONCommands, directives, keywords, and feature names are in text with
filenameNon-keyword placeholders appear in text with italic style format.
L
a
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
rated by vertical bars; read the example as an optional this or that.
ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of
letter gothic font.
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
this.
Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
[
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-BF538F EZ-KIT Lite Evaluation System Manualxxi
Notation Conventions
xxiiADSP-BF538F EZ-KIT Lite Evaluation System Manual
1USING ADSP-BF538F EZ-KIT
LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-BF538F EZ-KIT Lite evaluation system.
The information appears in the following sections.
•“Package Contents” on page 1-3
Lists the items contained in the ADSP-BF538F EZ-KIT Lite
package.
•“Default Configuration” on page 1-3
Shows the default configuration of the ADSP-BF538F EZ-KIT
Lite.
•“Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing ADSP-BF538F
EZ-KIT Lite session using VisualDSP++.
•“Evaluation License Restrictions” on page 1-7
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
•“Memory Map” on page 1-7
Defines the ADSP-BF538F EZ-KIT Lite board’s memory map.
•“SDRAM Interface” on page 1-8·
Defines the register values to configure the on-board SDRAM.
•“Flash Memory” on page 1-10
Describes the internal and external flash memory.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-1
•“CAN Interface” on page 1-11
Describes the on-board Controller Area Network (CAN) interface.
•“ELVIS Interface” on page 1-12
Describes the on-board National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) interface.
•“Audio Interface” on page 1-12
Describes the on-board audio circuit.
•“LEDs and Push Buttons” on page 1-13
Describes the board’s general-purpose IO pins and buttons.
•“Example Programs” on page 1-14
Provides information about example programs included in the
ADSP-BF538F EZ-KIT Lite evaluation system.
•“Background Telemetry Channel” on page 1-14
Highlights the advantages of the background telemetry channel
(BTC) feature of VisualDSP++.
For information on the graphical user interface, including the boot loading, target options, and other facilities of the EZ-KIT Lite system, refer to
the online Help.
For more detailed information about programming the ADSP-BF538F
Blackfin processor, see the documents referred to as “Related
Documents”.
1-2ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Using ADSP-BF538F EZ-KIT Lite
Package Contents
Your ADSP-BF538F EZ-KIT Lite evaluation system package contains the
following items.
•ADSP-BF538F EZ-KIT Lite board
•VisualDSP++ Installation Quick Reference Card
•CD containing:
D VisualDSP++ software
D ADSP-BF538F EZ-KIT Lite debug software
D USB driver files
D Example programs
D ADSP-BF538F EZ-KIT Lite Evaluation System Manual (this
document)
•Universal 7V DC power supply
•6-foot 3.5 mm male-to-male audio cable
•3.5 mm headphones
•10-foot USB 2.0 cable
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The ADSP-BF538F EZ-KIT Lite board is designed to run outside your
personal computer as a stand-alone unit. You do not have to open your
computer case.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-3
Default Configuration
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)
sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without detection. Permanent
damage may occur on devices subjected to high-energy discharges. Proper
ESD precautions are recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards in the protective
shipping package.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings,
switches, connector locations, and LEDs used in installation. Confirm
that your board is in the default configuration before using the board.
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Using ADSP-BF538F EZ-KIT Lite
Installation and Session Startup
L
For correct operation, install the software and hardware in the
order presented in the VisualDSP++ Installation Quick Reference Card.
1. Verify that the yellow USB monitor LED (ZLED3, located near the
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. If you are running VisualDSP++ for the first time, navigate to the
VisualDSP++ environment via the Start –>Programs menu.
The main window appears. Note that VisualDSP++ does not connect to any session. Skip the rest of this step to step 3.
If you have run VisualDSP++ previously, the last opened session
appears on the screen. You can override the default behavior and
force VisualDSP++ to start a new session by pressing and holding
down the Ctrl key while starting VisualDSP++. Do not release the
Ctrl key until the Session Wizard appears on the screen. Go to
step 4.
3. To connect to a new EZ-KIT Lite session, start Session Wizard by
selecting one of the following.
•From the Session menu, New Session.
•From the Session menu, Session List. Then click New Ses-sion from the Session List dialog box.
•From the Session menu, Connect to Target.
4. The Select Processor page of the wizard appears on the screen.
Ensure Blackfin is selected in Processor family. In Choose a target processor, select ADSP-BF538F. Click Next.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-5
Installation and Session Startup
5. The Select Connection Type page of the wizard appears on the
screen. Select EZ-KIT Lite and click Next.
6. The Select Platform page of the wizard appears on the screen.
In the Select your platform list, select ADSP-BF538F EZ-KIT Lite via Debug Agent. In Session name, highlight or specify the
session name.
The session name can be a string of any length; although, the box
displays approximately 32 characters. The session name can
include space characters. If you do not specify a session name,
VisualDSP++ creates a session name by combining the name of the
selected platform with the selected processor. The only way to
change a session name later is to delete the session and to open a
new session.
Click Next.
7. The Finish page of the wizard appears on the screen. The page dis-
plays your selections. If you are satisfied, click Finish. If not, click Back to make changes.
L
1-6ADSP-BF538F EZ-KIT Lite Evaluation System Manual
To disconnect from a session, click the disconnect button
or select Session–>Disconnect from Target.
To delete a session, select Session –> Session List. Select the ses-
sion name from the list and click Delete. Click OK.
Using ADSP-BF538F EZ-KIT Lite
Evaluation License Restrictions
The ADSP-BF538F EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
•VisualDSP++ allows a connection to the ADSP-BF538F EZ-KIT
Lite via the USB debug agent interface only. Connections to simulators and emulation products are no longer allowed.
•The linker restricts a users program to 20 KB of internal memory
for code space with no restrictions for data space.
L
Refer to the VisualDSP++ Installation Quick Reference Card for details.
The EZ-KIT Lite hardware must be connected and powered up to
use VisualDSP++ with a valid evaluation or permanent license.
Memory Map
The ADSP-BF538F processor has internal SRAM that can be used for
instruction or data storage. SRAM configuration details can be found in
the ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Reference.
The ADSP-BF538F EZ-KIT Lite board includes two types of external
memory: SDRAM and flash.
The size of SDRAM is 64 Mbytes (32M x 16-bit). The processor’s memory select pin,
The size of the external flash memory is 4 Mbytes (2M x 16-bits), and the
size of the internal flash memory is 1 Mbyte. The processor’s asynchronous memory select pins (~AMS3–0) are configured for flash memory. Any
of the ~AMS signals can be mapped to internal or external flash memory.
~SMS0, is configured for SDRAM.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-7
SDRAM Interface
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start AddressEnd AddressContent
External
Memory
Internal
Memory
0x0000 0000 0x03FF FFFFSDRAM bank 0 (SDRAM). See “SDRAM Inter-
face” on page 1-8.
0x2000 0000 0x200F FFFFASYNC memory bank 0. See “Flash Memory” on
page 1-10.
0x2010 0000 0x201F FFFFASYNC memory bank 1. See “Flash Memory” on
page 1-10.
0x2020 0000 0x202F FFFFASYNC memory bank 2. See “Flash Memory” on
page 1-10.
0x2030 0000 0x203F FFFFASYNC memory bank 3. See “Flash Memory” on
page 1-10.
All other locationsNot used
0xFF80 0000 0xFF80 3FFFData bank A SRAM 16 KB
0xFF80 4000 0xFF80 7FFFData bank A SRAM/CACHE 16 KB
0xFF90 0000 0xFF90 7FFFData bank B SRAM 16 KB
0xFF90 4000 0xFF90 7FFFData bank B SRAM/CACHE 16 KB
0xFFA0 0000 0xFFA0 7FFFInstruction bank A SRAM 32 KB
0xFFA1 0000 0xFFA1 3FFFInstruction bank B SRAM 16 KB
0xFFA0 8000 0xFFA0 BFFFInstruction SRAM/CACHE 16 KB
0xFFB0 0000 0xFFB0 0FFF Scratch pad SRAM 4KB
0xFFC0 0000 0xFFDF FFFFSystem MM Rs 2 MB
0xFFE0 0000 0xFFFF FFFFCore MMRs 2 MB
All other locationsReserved
SDRAM Interface
The three SDRAM control registers must be initialized in order to use the
MT48LC32M8A2 32M x 16 bits (64 MB) SDRAM memory. When you
are in a VisualDSP++ session and connect to the EZ-KIT Lite board, the
1-8ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Using ADSP-BF538F EZ-KIT Lite
SDRAM registers are configured automatically through the debugger each
time the processor is reset. The values in Table 1-2 are used whenever
SDRAM bank 0 is accessed through the debugger (for example, when
viewing memory windows or loading a program). The numbers were
derived for maximum flexibility and work for a system clock frequency
between 54 MHz and 133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
RegisterValueFunction
EBIU_SDGCTL0x0091998DCalculated with SCLK = 133 MHz
16-bit data path
External buffering timing disabled
= 2 SCLK cycles
t
WR
t
= 3 SCLK cycles
RCD
tRP = 3 SCLK cycles
= 6 SCLK cycles
t
RAS
pre-fetch disabled
CAS latency = 3 SCLK cycles
SCLK1 disabled
EBIU_SDBCTL0x00000025Bank 0 ena b le d
Bank 0 size = 64 MB
Bank 0 column address width = 10 bits
EBIU_SDRRC0x000003A0Calculated with SCLK = 54 MHz
RDIV = 416 clock cycles
1 54 MHz <=SCLK <= 133 MHz.
1
To re-write the EBIU_SDGCTL register within the user code, first, place the
chip in self-refresh (see the ADSP-BF538/ADSP-BF538F Blackfin Processor
Hardware Reference). Clearing the appropriate checkbox on the Target
Options dialog box, which is accessible through the Settings pull-down
menu, disables the automatic and allows manual configuration. For more
information, see online Help.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-9
Flash Memory
Automatic configuration of SDRAM is not optimized for any
SCLK fre-
quency. Table 1-3 shows optimized configuration for the SDRAM
registers using a 125 MHz and 133 MHz SCLK. Only the EBIU_SDRRC register needs to be modified in the user code to achieve maximum
performance.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate the SDRAM memory setup.
Flash Memory
The flash memory interface of the ADSP-BF538F EZ-KIT Lite can connect to an external 4 MB (2M x 16-bits) ST Micro M29W320EB device
or the 1 MB internal flash memory. The size and connections of flash
memory are controlled by the flash address range switch (
chip enable (FCE) switch (SW14). See “Flash Enable Switch (SW6)” on
page 2-11 and “FCE Enable Switch (SW14)” on page 2-12.
SW6) and the flash
The default for the
SW6 switch is all positions ON, which allows the user to
have access to the full 4 MB of the external flash memory. The default for
SW14 switch is all positions OFF, which allows the user to have access to
the
the full 4 MB of the external flash memory. Each
~AMS signal accounts for
1 MB of flash memory. The amount of available flash memory decreases
~AMS signals are turned OFF.
as
1-10ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Using ADSP-BF538F EZ-KIT Lite
Example code is provided in the EZ-KIT Lite installation directory to
demonstrate how to program flash memory.
Table 1-4 shows a sample value for the asynchronous memory configura-
tion register,
EBIU_AMBCTL0.
Table 1-4. Asynchronous Memory Control Register Setting Example
RegisterValueFunction
EBIU_AMBCTL00x7BB07BB0Timing control for banks 1 and 0
CAN Interface
The Controller Area Network interface contains a Philips TJA1041
high-speed CAN transceiver. The PD9 programmable flag connects to the
error and power-on indication output (ERR). The PC1 of the processor connects to the receive data output (RXD), and PCO connects to the transmit
data input (TXD).
The CAN interface can be disconnected from the processor by turning
positions 1 though 4 of the SW2 switch OFF. When in the OFF position, the
signals can be used elsewhere on the board. See “CAN Enable Switch
(SW2)” on page 2-10 for more information.
The CAN interface contains two 4-position modular connectors (see
“CAN Connectors (J5 and J11)” on page 2-21).
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate CAN circuit operation.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-11
ELVIS Interface
ELVIS Interface
This EZ-KIT Lite board contains the National Instruments ELVIS interface. The interface features the DC voltage and current measurement
modules, oscilloscope and bode analyzer modules, function generator,
arbitrary waveform generator, and digital IO.
The ELVIS interface is a NI LabVIEW-based design and prototype environment for university science and engineering laboratories. The ELVIS
interface consists of the LabVIEW-based virtual instruments, a multifunction data acquisition (DAQ) device, and a custom-designed bench-top
workstation and prototype board. This combination provides a
ready-to-use suite of instruments found in most educational laboratories.
Because the interface is based on the LabVIEW and provides complete
data acquisition and prototyping capabilities, the system is ideal for academic coursework that range from lower-division classes to advanced
project-based curriculums.
For more information on ELVIS and example demonstration programs,
visit National Instruments Web site at www.ni.com.
Audio Interface
The audio circuit of the EZ-KIT Lite consists of an AD1871 analog-to-digital converter (ADC) and an AD1854 digital-to-analog
converter (DAC). The audio circuit provides one channel of stereo input
and one channel of stereo output via 3.5 mm stereo jacks. The
interface of the processor is linked with the stereo audio data input and
output pins of the audio circuit.
1-12ADSP-BF538F EZ-KIT Lite Evaluation System Manual
SPORT0
Using ADSP-BF538F EZ-KIT Lite
The frame sync and bit clocks are generated from the ADC and feed to the
processor because the ADC is operating in master mode. The audio interface samples data at a 48 kHz sample rate. The serial data interface
operates in 2-wire interface (TWI) mode and connects to
SPORT0 of the
processor.
The audio interface can be disconnected from the SPORT0 by turning
positions 1 and 5 of the SW7 switch OFF. When in the OFF position, the
SPORT0 signals can be used on the SPORT0 connector (P6) or on the expan-
sion interface (see “SPORT0 and SPORT1 Connectors (P6 and P7)” on
page 2-23 and “Audio Enable Switch (SW7)” on page 2-12 for more
information).
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate audio circuit operation.
LEDs and Push Buttons
The EZ-KIT Lite provides four push buttons and five LEDs for general-purpose IO.
The five LEDs, labeled LED2 through LED6, are accessed via the PC5–9 processor pins. For information on how to program the pins, refer to the
ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Reference.
The four general-purpose push button are labeled
status of each individual button can be read through the processor’s programmable flag inputs, PF0–3. The signal reads 1 when a corresponding
switch is being pressed-on. When the switch is released, the signal reads
A connection between the push button and programmable flag input is
established through the DIP switch,
SW5. See “LEDs and Push Buttons”
on page 2-17 for details.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate functionality of the LEDs and push buttons.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual1-13
SW10 through SW13. A
0.
Example Programs
Example Programs
Example programs are provided with the ADSP-BF538F EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
<install_path>\Blackfin\Examples\ADSP-BF538F EZ-KIT Lite Visu-
alDSP++ directory. Please refer to the readme file provided with each
example for more information.
Background Telemetry Channel
The ADSP-BF538F USB debug agent supports the background telemetry
channel (BTC), which facilitates data exchange between VisualDSP++ and
the processor without interrupting processor execution.
The BTC allows you to view a variable as it is updated or changed, all
while the processor continues to execute. For increased performance of the
BTC, including faster reading and writing, please check our latest line of
Blackfin processor emulators at:
channel, see the VisualDSP++ User’s Guide or online Help.
. For more information about the background telemetry
1-14ADSP-BF538F EZ-KIT Lite Evaluation System Manual
2ADSP-BF538F EZ-KIT LITE
HARDWARE REFERENCE
This chapter describes the hardware design of the ADSP-BF538F EZ-KIT
Lite board. The following topics are covered.
•“System Architecture” on page 2-2
Describes the ADSP-BF538F EZ-KIT Lite board configuration
and explains how the board components interface with the
processor.
•“Jumper and Switch Settings” on page 2-9
Shows the locations and describes the configuration jumpers and
switches.
•“LEDs and Push Buttons” on page 2-17
Shows the locations and describes the LEDs and push buttons.
•“Connectors” on page 2-20
Shows the locations and provides part numbers for the on-board
connectors. In addition, the manufacturer and part number information is provided for the mating parts.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-1
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
USB
Conn
(2)
(2)
RJ10
RS-232
Female
+7.0V
Connector
TWI
Conn
JTAG
Conn
Debug
CAN
Transceiver
Power
Regulation
Agent
RS-232
Interface
25 MHz
Oscillator
32.768 KHz
Oscillator
Port
JTAG
RTC
64 MB
SDRAM
(32M x 16)
4 MB
Flash
(2M x 16 )
EBUI
Connectors
ADSP-BF538F
(4)
SPORT
Conns
DSP
SPIs
(3)
SPI
Conns
PPI
PPI
Conn
GPIO
ADC/
DAC
Stereo
In/Out
Timers
CANTWI
UARTsSPORTsPBs (4)
(3)
UART
Conns
Expansion
(3)
LEDs (6)
ELVIS
Conn
Timer
Figure 2-1. System Architecture
This EZ-KIT Lite is designed to demonstrate capabilities of the
ADSP-BF538F Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage of the processor is supplied by the internal voltage
regulator.
2-2ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the
real-time clock (RTC) inputs of the processor. The default boot mode for
the processor is flash boot. See “Boot Mode Select Switch (SW3)” on
page 2-13 for information about changing the default boot mode.
External Bus Interface Unit
The external bus interface unit (EBIU) connects external memory to the
ADSP-BF538F processor. The unit includes a 16-bit wide data bus, an
address bus, and a control bus. On the EZ-KIT Lite, the EBIU connects
to the SDRAM, flash memory, and expansion interfaces.
The 64 Mbytes (32M x 16 bits) of SDRAM connect to the synchronous
memory select 0 pin (~SMS0). Refer to “SDRAM Interface” on page 1-8
for information about SDRAM configuration. Note that SDRAM clock is
the processor’s clock out (CLK OUT), which must not exceed 133 MHz.
The flash memory device connects to the asynchronous memory select signals, ~AMS3 through ~AMS0. The device provides a total of 4 MB of
external flash memory or 1 MB of internal flash memory. The processor
can use flash memory for both booting and storing information during a
standard mode of operation. Refer to “Flash Memory” on page 1-10 for
details.
All of the address, data, and control signals are available externally via the
expansion interface (J1–3). The pinout of these connectors can be found
in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-3
System Architecture
SPORT0 Interface
SPORT0 connects to the audio circuit, SPORT0 connector (P6), and expan-
sion interface. The audio circuit uses the primary data transmit and
receive pins to input and output data from the audio input and outputs.
SPORT1 and SPORT2 of the processor connect to the SPORT connectors (P3
and
P4) and expansion interface.
The pinout of the SPORT interface and expansion interface connectors
can be found in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1.
SPI Interface
The serial peripheral interface (SPI) of the processor connects to the SPI
connectors (P1, P2, and P9) and expansion interface.
UART Interface
The UART interface of the processor connects to the UART connectors
(P12, P14, and P15) and expansion interface.
Programmable Flags
The processor has 53 general-purpose input/output (GPIO) signals spread
across four ports (PC, PD, PE, and PF). The pins are multi-functional and
depend on the processor setup. Table 2-1 shows how the programmable
flag pins are used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections
Processor PinOther Processor FunctionEZ-KIT Lite Function
2-4ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor PinOther Processor FunctionEZ-KIT Lite Function
PC5LED (LED2) or ELVIS_PF1. See “LED and
Push Button Locations” on page 2-17 and
“Push Button Enable Switch (SW5)” on
page 2-11 for information on how to disable
the push button.
PC6LED (LED3) or ELVIS_PF2. See “LED and
Push Button Locations” on page 2-17 and
“Push Button Enable Switch (SW5)” on
page 2-11 for information on how to disable
the push button.
PC7LED (LED4) or ELVIS_PF5. See “LED and
Push Button Locations” on page 2-17 and
“Push Button Enable Switch (SW5)” on
page 2-11 for information on how to disable
the push button.
PC8LED (LED5) or ELVIS_PF6. See “LED and
Push Button Locations” on page 2-17 and
“Push Button Enable Switch (SW5)” on
page 2-11 for information on how to disable
the push button.
PC9LED (LED6) or ELVIS_PF7. See “LEDs and
Push Buttons” on page 1-13 and “Push Button Enable Switch (SW5)” on page 2-11 for
information on how to disable the push button.
PD0MOSI1Not used
PD1MISO1Not used
PD2SCK1Not us e d
PD3SPI1SSNot u sed
PD4SPI1SELAUDIO_RESET
PD5MOSI2Not used
PD6MISO2Not used
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-5
System Architecture
Table 2-1. Programmable Flag Connections (Cont’d)
Processor PinOther Processor FunctionEZ-KIT Lite Function
PD7SCK2PPI_DIR_CTL (for AV-Extender
PD8SPI2SSPPI_CLK_SEL (for AV-Extender)
PD9SPI2SELCAN_ERR
PD10RX1Not used
PD11TX1Not used
PD12RX2Not used
PD13TX2Not used
PE0RSCLK2Not u sed
PE1RFS2Not us e d
PE2DR2PRINot u sed
PE3DR2SECNot u sed
®
)
PE4TSCLK2Not u sed
PE5TFS2Not us e d
PE6DT2PRINot u sed
PE7DT2SECNot u sed
PE8RSCLK3Not u sed
PE9RFS3Not us e d
PE10
PE11
PE12
PE13
PE14DT3PRINot u sed
PE15
DR3PRI
DR3SEC
TSCLK3
TFS3
DT3SEC
Not used
Not used
Not used
Not used
Not used
2-6ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor PinOther Processor FunctionEZ-KIT Lite Function
PF0SPISSPush button (SW13). See “Programmable
Flag Push Buttons (SW10–13)” on
page 2-18.
PF1SPI0SEL1/TMRCLKPush button (SW12). See “Programmable
Flag Push Buttons (SW10–13)” on
page 2-18.
PF2SPI0SEL2Push button (SW11). See “Programmable
Flag Push Buttons (SW10–13)” on
page 2-18.
PF3PPI_FS3/SPI0SEL3Push button (SW10). See “Programmable
Flag Push Buttons (SW10–13)” on
page 2-18.
PF4PPI_D15/SPI0SEL4Not u sed
PF5PPI_D14/SPI0SEL5Not u sed
PF6PPI_D13/SPI0SEL6Not u sed
PF7PPI_D12/SPI0SEL7Not u sed
PF8PPI_D11Not used
PF9PPI_D10Not used
PF10PPI_D9Not u sed
PF11PPI_D8Not u sed
PF12PPI_D7Not u sed
PF13PPI_D6Not u sed
PF14PPI_D5No u sed
PF15PPI_D4Not u sed
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-7
System Architecture
UART Port
The universal asynchronous receiver/transmitter (UART) port of the processor connects to the ADM3202 RS-232 line driver as well as to the
expansion interface. The RS-232 line driver connects to the DB9 female
connector, providing an interface to a PC and other serial devices.
Expansion Interface
The expansion interface consists of three 90-pin connectors. Table 2-2
shows the interfaces each connector provides. For the exact pinout of the
connectors, refer to “ADSP-BF538F EZ-KIT Lite Schematic” on
page B-1. The mechanical dimensions of the connectors can be obtained
from Technical or Customer Support.
Analog Devices offers many EZ-Extender products that plug on to the
expansion interface. For more information on these products, visit the
Analog Devices Web site at www.analog.com.
Table 2-2. Expansion Interface Connectors
ConnectorInterfaces
J15V, GND, address, data, PPI
J23.3V, GND, SPI, NMI, TMR2–0, SPORT0, SPORT1, PF15–0, EBUI control signals
J35V, 3.3V, GND, UART, flash IO, reset, audio control signals
Limits to the current and to the interface speed must be taken into consideration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
also can add extra loading to signals, decreasing their maximum effective
speed.
[
2-8ADSP-BF538F EZ-KIT Lite Evaluation System Manual
Analog Devices does not support and is not responsible for the
effects of additional circuitry.
ADSP-BF538F EZ-KIT Lite Hardware Reference
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emulation port of the processor connects also to the USB debugging interface.
When an emulator connects to the board at ZP4, the USB debugging
interface is disabled. See “JTAG Connector (ZP4)” on page 2-23 for more
information about the connector.
To learn more about available emulators, contact Analog Devices (see
“Processor Product Information”).
Jumper and Switch Settings
The jumper and switch locations are shown in Figure 2-2.
Figure 2-2. Jumper and Switch Locations
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-9
Jumper and Switch Settings
CAN Enable Switch (SW2)
The Controller Area Network (CAN) enable switch (SW2) disconnects
CAN signals from the GPIO pins of the processor. When the SW2 switch is
in the OFF position, the associated GPIO signals (see Table 2-3) can be
used on the expansion interface.
Table 2-3. CAN Enable Switch (SW2)
CAN SignalSW2 Switch Position (Default)Processor Signal
ENABLE1 (ON)NU
STANDBY2 (ON)NU
ERROR3 (ON )PD9
RECEIVE DATA4 (ON)PC1
UART Enable Switch (SW4)
The UART enable switch (SW4) disconnects UART signals from the GPIO
pins of the processor. When the switch is in the OFF position, the associated GPIO signals (see Table 2-4) can be used on the expansion interface.
Table 2-4. UART Enable Switch (SW4)
EZ-KIT Lite SignalSW4 Switch Position (Default)Processor Signal
2-10ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
Push Button Enable Switch (SW5)
The push button enable switch (SW5) disconnects the associated signal and
the push button circuit drivers from the GPIO pins of the processor.
When the SW5 switch is in the OFF position, the GPIO signal
(see Table 2-5) can be used on the expansion interface.
Table 2-5. Push Button Enable Switch (SW5)
Push ButtonSW5 Switch Position (Default)Processor Signal
The flash enable switch (SW6) disconnects the ~AMS signals from the external flash memory, allowing other devices to utilize the signals via the
expansion interface. For each switch listed in Table 2-6 that is turned OFF,
the size of available flash memory is reduced by 1 MB.
Table 2-6. Flash Enable Switch (SW6)
Processor SignalSW6 Switch Position (Default)
~AMS01 (ON)
~AMS12 (ON)
~AMS23 (ON)
~AMS34 (ON)
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-11
Jumper and Switch Settings
FCE Enable Switch (SW14)
The flash chip enable (FCE) switch (SW14) selects which ~AMS signals connect to the internal flash memory. Since the internal memory is 1 MB,
only one ~AMS signal must be connected at a time. For each switch listed in
Table 2-7 that is turned ON, the size of available flash memory is reduced
The audio enable switch (SW7) disconnects the audio signals from the processor (positions 1–5) and determines how the clock for the audio circuit
generates and connects (positions 6–8). Position 8 determines if the ADC
is in master or slave mode. When in master mode (position 8 is ON), the
ADC generates the clock. When in slave mode (position 8 is OFF), the processor generates the clock. Positions 6 and 7 connect together the transmit
and receive clocks (see Table 2-8).
Table 2-8. Audio Enable Switch (SW7)
EZ-KIT Lite SignalSW7 Switch Position (Default)Processor Signal
The rotary switch (SW3) determines the boot mode of the processor.
Table 2-9 shows the available boot mode settings. By default, the
ADSP-BF538F processor boots from the on-board flash memory.
Table 2-9. Boot Mode Select Switch (SW3)
SW3 Position 1SW3 Position 2Processor Boot Mode
ON ONExecute from 16-bit external memory
ON OFF Boot from 16-bit flash memory (default)
OFFONBoot from SPI serial master
OFFOFFBoot from SPI serial slave
PPI Direction Control (JP1)
The PPI direction control jumper (JP1) is used when the board connects
to a Blackfin AV EZ-Extender. JP1 allows the GPIO signal PD7 to control
the direction of the PPI bus via a software flag. The default is positions 1
and 2. When connected to the extender, JP1 must be placed in positions 2
and 3.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-13
Jumper and Switch Settings
UART Loop Jumper (JP9)
The UART loop jumper (JP9) is for looping the transmit and receive signals. The default is OFF.
ELVIS Oscilloscope Configuration Switch (SW1)
The oscilloscope configuration switch (SW1) determines which audio circuit signals connect to channels A and B of the oscilloscope. The switch is
used when the board connects to the Educational Laboratory Virtual
Instrumentation Suite (ELVIS) station (see “ELVIS Interface” on
page 1-12). Each channel must have only one signal selected at a time (see
Table 2-10).
2-14ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
ELVIS Function Generator Configuration Switch
(SW8)
The function generator configuration switch (SW8) controls signals connecting to the left and right input signals of the audio interface. The
switch is used when the board connects to the ELVIS station (see “ELVIS
Interface” on page 1-12). Each channel must have only one signal selected
at a time, as described in Table 2-11.
Table 2-11. Function Generator Configuration Switch (SW8)
ChannelSW8 Switch Position (Default)Audio Circuit Signal
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-15
Jumper and Switch Settings
ELVIS Voltage Selection Jumper (JP6)
The ELVIS voltage selection jumper (JP6) is used to select the power
source for the EZ-KIT Lite. In a standard mode of operation, the board
receives its power from an external power supply. When JP6 is installed,
the board is powered from an ELVIS station, and no external power supply is required. The jumper setting is shown in Table 2-12.
Table 2-12. ELVIS Voltage Selection Jumper (JP6)
JP6 SettingMode
OFFPowered from an external power supply (default)
ONPowered from an ELVIS station
[
The external power supply must be disconnected from the board
when JP6 is installed. Otherwise, the power supply can cause damage to the EZ-KIT Lite board and ELVIS unit.
ELVIS Select Jumper (JP8)
The ELVIS select jumper (JP8) configures the EZ-KIT Lite’s connection
to an ELVIS station (see “ELVIS Interface” on page 1-12). When JP8 is
installed, the connections to the push buttons and LED are re-directed to
the ELVIS station, instead of the processor. The jumper setting is shown
in Table 2-13.
Table 2-13. ELVIS Select Jumper (JP8)
JP8 SettingMode
OFFNot connected to an ELVIS station (default)
ONConnected to an ELVIS station
2-16ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
LEDs and Push Buttons
This section describes functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons.
MONITOR
Figure 2-3. LED and Push Button Locations
Reset Push Button (SW9)
The RESET push button resets all of the ICs on the board. One exception is
the USB interface chip. The chip is not being reset when the push button
is pressed after the USB cable has been plugged in and communication
with the PC has been initialized correctly. After USB communication has
been initialized, the only way to reset the USB chip is by powering down
the board.
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-17
LEDs and Push Buttons
Programmable Flag Push Buttons (SW10–13)
Four push buttons, SW10–13, are provided for general-purpose user input.
The buttons connect to the PF0-3 programmable flag pins of the processor. The push buttons are active high and, when pressed, send a high (1)
to the processor. Refer to “LEDs and Push Buttons” on page 1-13 for
more information on how to use the flags to program the processor. The
push button enable switch (SW5) is capable of disconnecting the push buttons from its corresponding PF signal (refer to “Push Button Enable
Switch (SW5)” on page 2-11). The programmable flag signals and associ-
ated switches are shown in Table 2-14.
Table 2-14. Programmable Flag Switches
Processor Programmable Flag PinPush Button Reference Designator
PF0SW13
PF1SW12
PF2SW11
PF3SW10
Power LED (LED7)
When LED7 is lit (green), it indicates that power is being properly supplied
to the board.
Reset LED (LED8)
When LED8 is lit, it indicates that the master reset of all the major ICs is
active.
2-18ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
User LEDs (LED2–6)
Five LEDs connect to five general-purpose IO pins of the processor (see
Table 2-15). The LEDs are active high and are lit by writing a 1 to the
correct PC signal. Refer to “LEDs and Push Buttons” on page 1-13 for
more information about how to use flash memory when programming the
LEDs.
Table 2-15. User LEDs
LED Reference DesignatorProcessor Programmable Flag Pin
LED2PC5
LED3PC6
LED4PC7
LED5PC8
LED6PC9
USB Monitor LED (ZLED3)
The USB monitor LED (ZLED3) indicates that USB communication has
been initialized successfully, and you can connect to the processor using a
VisualDSP++ EZ-KIT Lite session. This takes approximately 15 seconds.
If the LED does not light, try cycling power on the board and/or
re-installing the USB driver (see the VisualDSP++ Installation Quick Refer-ence Card).
L
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-19
When VisualDSP++ is actively communicating with the EZ-KIT
Lite target board, the LED can flicker, indicating communications
handshake.
Connectors
Connectors
This section describes the connector functionality and provides information about mating connectors. The connector locations are shown in
Figure 2-4.
Figure 2-4. Connector Locations
2-20ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-21
Connectors
Power Connector (J7)
The power connector provides all of the power necessary to operate the
EZ-KIT Lite board.
Part DescriptionManufacturerPart Number
2.5 mm power jack SWITCHCRAFTRAPC712X
Mating Power Supply (shipped with EZ-KIT Lite)
7V power supplyCUI INC.DMS070214-P6P-SZ
Expansion Interface Connectors (J1–3)
Three board-to-board connector footprints provide signals for most of the
processor’s peripheral interfaces. The connectors are located at the bottom
of the board. For more information about the interface, see “Expansion
Interface” on page 2-8. For the availability and pricing of the J1, J12, and
2-22ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
JTAG Connector (ZP4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. When an emulator connects to the JTAG header, the USB debug
interface is disabled.
L
L
Pin 3 is missing to provide keying. Pin 3 in the mating connector
should have a plug.
When using an emulator with the EZ-KIT Lite board, follow the
connection instructions provided with the emulator.
SPORT0 and SPORT1 Connectors (P6 and P7)
The pinout of the P6 and P7 connectors can be found in “ADSP-BF538F
EZ-KIT Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC header FCI 68737-434HLF
Mating Connector
IDC socket DIGI-KEYS4217-ND
PPI Connector (P8)
The pinout of the P8 connector can be found in “ADSP-BF538F EZ-KIT
Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC headerFCI68737-440HLF
Mating Connector
IDC socket DIGI-KEYS4220-ND
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-23
Connectors
SPI Connector (P9)
The pinout of the P9 connector can be found in “ADSP-BF538F EZ-KIT
Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC headerFCI 68737-420HLF
Mating Connector
IDC socket DIGI-KEYS4210-ND
2-Wire Interface Connector (P10)
The pinout of the P10 connector can be found in “ADSP-BF538F
EZ-KIT Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC header FCI 68737-420HLF
Mating Connector
IDC socket DIGI-KEYS4210-ND
TIMERS Connector (P11)
The pinout of the P11 connector can be found in “ADSP-BF538F
EZ-KIT Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC headerFCI68737-410HLF
Mating Connector
IDC socket DIGI-KEYS4205-ND
2-24ADSP-BF538F EZ-KIT Lite Evaluation System Manual
ADSP-BF538F EZ-KIT Lite Hardware Reference
UART1 Connector (P12)
The pinout of the P12 connector can be found in “ADSP-BF538F
EZ-KIT Lite Schematic” on page B-1.
Part DescriptionManufacturerPart Number
IDC headerFCI68737-410HLF
Mating Connector
IDC socket DIGI-KEYS4205-ND
ADSP-BF538F EZ-KIT Lite Evaluation System Manual2-25
Connectors
2-26ADSP-BF538F EZ-KIT Lite Evaluation System Manual
AADSP-BF538F EZ-KIT LITE BILL
OF MATERIALS
The bill of materials corresponds to “ADSP-BF538F EZ-KIT Lite Sche-
ZP4 (JTAG), 2-9, 2-23
contents, of this EZ-KIT Lite package, 1-3
Controller Area Network, See CAN
core voltage, 2-2
CTS signals, 2-10
customer support,
I-2ADSP-BF538F EZ-KIT Lite Evaluation System Manual
INDEX
H
Help, online, xix
I
installation, of this EZ-KIT Lite, 1-5
interfaces, See audio, CAN, ELVIS, expansion,
SDRAM
internal memory
core/system MMRs, 1-8
data banks A, B SRAM, 1-8
data banks A, B SRAM/CACHE, 1-8
instruction banks A, B SRAM, 1-8
instruction SRAM/CACHE, 1-8
reserved, 1-8
scratch pad SRAM, 1-8
via JTAG, 2-9
internal regulator, 2-2
IO voltage, 2-2
monitor LED (ZLED3), 2-19
user LEDs (LED2-6), 2-19
V
very-long instruction word (VLIW), ix
VisualDSP++
environment, 1-5
online Help,
voltage regulators, 2-2
xix
ADSP-BF538F EZ-KIT Lite Evaluation System ManualI-5
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Processors in Applications
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Industrial
Portable Media Players (PMP)
Security
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Blackfin® Processors
embody a new breed of
16/32-bit embedded
processor, ideally suited for
products where a
convergence of capabilities
are necessary – multi-format
audio, video, voice and
image processing...
Go to Blackfin
SHARC® Processors,
dominate the floating-point
Digital Signal Processing
market, delivering exceptional
core and memory
performance complemented
by outstanding I/O throughput.
Starting at 319 MFLOPS per
dollar...
Go to SHARC
TigerSHARC® Processors
provide the highest
performance density for
multiprocessing applications
with peak performance well
above a billion floating-point
operations per second...
Go to TigerSHARC
ADSP-21xx Processors, are
code- and pin-compatible
families of Digital Signal
Processors with
performance up to 160MHz
and power as low as 184
micro-amps. The ADSP21XX family is ideal for...
Go to ADSP-21xx
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