ANALOG DEVICES ADSP-BF538, ADSP-BF538F Service Manual

a

ADSP-BF538/ADSP-BF538F Blackfin

Processor Hardware Reference

®

Revision 1.0, February 2009

Part Number

82-000002-01

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2009 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, the Blackfin logo, CrossCore,
SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of
Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xli

Intended Audience ......................................................................... xli

Manual Contents .......................................................................... xlii

What’s New in This Manual ........................................................... xlv

Technical or Customer Support ..................................................... xlvi

Supported Processors ..................................................................... xlvi

Product Information .................................................................... xlvii

Analog Devices Web Site ........................................................ xlvii

VisualDSP++ Online Documentation ................................... xlviii

Technical Library CD ........................................................... xlviii

Conventions ................................................................................. xlix

INTRODUCTION

Purpose of this Manual ................................................................. 1-1

Peripherals .................................................................................... 1-4

Core Architecture .......................................................................... 1-6

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Contents

Memory Architecture .................................................................... 1-9

Internal Memory ................................................................... 1-10

External Memory .................................................................. 1-10

I/O Memory Space ................................................................ 1-11

Event Handling .......................................................................... 1-11

Core Event Controller (CEC) ................................................ 1-12

System Interrupt Controllers (SICx) ...................................... 1-12

DMA Support ............................................................................ 1-13

External Bus Interface Unit ......................................................... 1-14

PC133 SDRAM Controller ................................................... 1-14

Asynchronous Controller ...................................................... 1-15

Parallel Peripheral Interface ......................................................... 1-15

General-Purpose Mode Descriptions ...................................... 1-16

Input Mode .......................................................................... 1-16

Frame Capture Mode ............................................................ 1-16

Output Mode ....................................................................... 1-17

ITU-R 656 Mode Descriptions .............................................. 1-17

Active Video Only Mode ....................................................... 1-17

Vertical Blanking Interval Mode ............................................ 1-17

Entire Field Mode ................................................................. 1-18

Serial Ports (SPORTs) ................................................................. 1-18

Serial Peripheral Interface (SPI) Ports .......................................... 1-20

Timers ....................................................................................... 1-20

UART Ports ............................................................................... 1-21

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Controller Area Network Port ..................................................... 1-22

Two Wire Interface Port .............................................................. 1-23

Real-Time Clock ......................................................................... 1-23

Watchdog Timer ......................................................................... 1-24

General-Purpose I/O ................................................................... 1-24

Clock Signals .............................................................................. 1-25

Dynamic Power Management ...................................................... 1-26

Full On Operating Mode (Maximum Performance) ................ 1-26

Active Operating Mode (Moderate Power Savings) ................. 1-26

Sleep Operating Mode (High Power Savings) ......................... 1-26

Deep Sleep Operating Mode (Maximum Power Savings) ......... 1-27

Hibernate State ..................................................................... 1-27

Voltage Regulation ...................................................................... 1-28

Boot Modes ................................................................................ 1-28

Instruction Set Description ......................................................... 1-29

Development Tools ..................................................................... 1-30

COMPUTATIONAL UNITS

Using Data Formats ...................................................................... 2-3

Binary String ........................................................................... 2-3

Unsigned ................................................................................. 2-4

Signed Numbers: Two’s-Complement ....................................... 2-4

Fractional Representation: 1.15 ................................................ 2-4

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Contents

Register Files ................................................................................ 2-5

Data Register File .................................................................... 2-6

Accumulator Registers ............................................................. 2-6

Pointer Register File ................................................................ 2-7

DAG Register Set .................................................................... 2-7

Register File Instruction Summary ........................................... 2-8

Data Types ................................................................................. 2-11

Endian Byte Order ................................................................ 2-11

ALU Data Types ................................................................... 2-13

Multiplier Data Types ........................................................... 2-13

Shifter Data Types ................................................................ 2-14

Arithmetic Formats Summary ................................................ 2-15

Using Multiplier Integer and Fractional Formats .................... 2-16

Rounding Multiplier Results ................................................. 2-17

Unbiased Rounding .......................................................... 2-18

Biased Rounding .............................................................. 2-20

Truncation ....................................................................... 2-22

Special Rounding Instructions ............................................... 2-22

Using Computational Status ....................................................... 2-23

ASTAT Register .......................................................................... 2-23

Arithmetic Logic Unit (ALU) ...................................................... 2-23

ALU Operations ................................................................... 2-25

Single 16-Bit Operations .................................................. 2-25

Dual 16-Bit Operations .................................................... 2-26

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Quad 16-Bit Operations .................................................... 2-26

Single 32-Bit Operations ................................................... 2-27

Dual 32-Bit Operations ..................................................... 2-28

ALU Instruction Summary .................................................... 2-29

ALU Data Flow Details ......................................................... 2-33

Dual 16-Bit Cross Options ................................................ 2-34

ALU Status Signals ............................................................ 2-35

ALU Division Support Features ............................................. 2-36

Special SIMD Video ALU Operations .................................... 2-37

Multiply Accumulators (Multipliers) ............................................ 2-37

Multiplier Operation ............................................................. 2-38

Placing Multiplier Results in Multiplier Accumulator

Registers ........................................................................ 2-39

Rounding or Saturating Multiplier Results ......................... 2-39

Saturating Multiplier Results on Overflow ............................. 2-40

Multiplier Instruction Summary ............................................ 2-40

Multiplier Instruction Options .......................................... 2-42

Multiplier Data Flow Details ................................................. 2-44

Multiply Without Accumulate ............................................... 2-46

Special 32-Bit Integer MAC Instruction ................................. 2-48

Dual MAC Operations .......................................................... 2-49

Barrel Shifter (Shifter) ................................................................. 2-50

Shifter Operations ................................................................. 2-50

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Contents

Two-Operand Shifts ......................................................... 2-51

Immediate Shifts .......................................................... 2-51

Register Shifts ............................................................... 2-52

Three-Operand Shifts ....................................................... 2-52

Immediate Shifts .......................................................... 2-52

Register Shifts ............................................................... 2-53

Bit Test, Set, Clear, Toggle ................................................ 2-54

Field Extract and Field Deposit ......................................... 2-54

Shifter Instruction Summary ................................................. 2-54

OPERATING MODES AND STATES

User Mode ................................................................................... 3-3

Protected Resources and Instructions ....................................... 3-4

Protected Memory .................................................................. 3-5

Entering User Mode ................................................................ 3-5

Example Code to Enter User Mode Upon Reset ................... 3-5

Return Instructions That Invoke User Mode ....................... 3-5

Supervisor Mode .......................................................................... 3-7

Non-OS Environments ........................................................... 3-7

Example Code for Supervisor Mode Coming Out

of Reset ........................................................................... 3-8

Emulation Mode .......................................................................... 3-9

Idle State ...................................................................................... 3-9

Example Code for Transition to Idle State .............................. 3-10

Reset State .................................................................................. 3-10

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System Reset and Power-up ......................................................... 3-12

Hardware Reset ..................................................................... 3-13

SYSCR Register ..................................................................... 3-14

Software Resets and Watchdog Timer ..................................... 3-15

SWRST Register ................................................................... 3-15

Core-Only Software Reset ...................................................... 3-16

Core and System Reset .......................................................... 3-17

Booting Methods ........................................................................ 3-18

PROGRAM SEQUENCER

Sequencer Related Registers ........................................................... 4-3

Sequencer Status (SEQSTAT) Register ..................................... 4-4

Zero-Overhead Loop (LCx, LTx, LBx) Registers ....................... 4-4

System Configuration (SYSCFG) Register ................................ 4-4

Instruction Pipeline ...................................................................... 4-6

Branches and Sequencing .............................................................. 4-9

Direct Short and Long Jumps ................................................ 4-10

Direct Call ............................................................................ 4-10

Indirect Branch and Call ........................................................ 4-11

PC-Relative Indirect Branch and Call ..................................... 4-11

Condition Code Flag ............................................................. 4-12

Conditional Branches ........................................................ 4-13

Conditional Register Move ................................................ 4-13

Branch Prediction .................................................................. 4-13

Loops and Sequencing ................................................................. 4-15

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Contents

Events and Sequencing ............................................................... 4-17

System Interrupt Processing .................................................. 4-20

System Peripheral Interrupts .................................................. 4-22

System Interrupt Wake-up Enable (SIC_IWRx) Registers ....... 4-26

System Interrupt Status (SIC_ISRx) Registers ........................ 4-29

System Interrupt Mask (SIC_IMASKx) Registers ................... 4-31

System Interrupt Assignment (SIC_IARx) Registers ............... 4-33

Core Event Controller Registers .................................................. 4-38

Core Interrupt Mask (IMASK) Register ................................. 4-38

Core Interrupt Latch (ILAT) Register .................................... 4-38

Core Interrupts Pending (IPEND) Register ............................ 4-39

Global Enabling/Disabling of Interrupts ..................................... 4-40

Event Vector Table ...................................................................... 4-41

Emulation ............................................................................. 4-43

Reset .................................................................................... 4-43

NMI (Non-Maskable Interrupt) ............................................ 4-44

Exceptions ............................................................................ 4-45

Exceptions While Executing an Exception Handler ................ 4-49

Hardware Error Interrupt ........................................................... 4-50

Core Timer ........................................................................... 4-51

General-Purpose Interrupts (IVG7-IVG15) ............................ 4-52

Servicing Interrupts .................................................................... 4-52

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Nesting of Interrupts ................................................................... 4-53

Non-Nested Interrupts .......................................................... 4-54

Nested Interrupts .................................................................. 4-55

Example Prolog Code for Nested Interrupt

Service Routine .............................................................. 4-55

Example Epilog Code for Nested Interrupt

Service Routine .............................................................. 4-56

Logging of Nested Interrupt Requests .................................... 4-57

Exception Handling .................................................................... 4-58

Deferring Exception Processing .............................................. 4-58

Example Code for an Exception Handler ................................ 4-59

Example Code for an Exception Routine ................................ 4-61

Example Code for Using Hardware Loops in an ISR ............... 4-61

Other Usability Issues ................................................................. 4-62

Executing RTX, RTN, or RTE in a Lower Priority Event ........ 4-62

Recommendation for Allocating the System Stack .................. 4-63

Latency in Servicing Events ................................................... 4-63

DATA ADDRESS GENERATORS

Addressing With DAGs ................................................................. 5-4

Frame and Stack Pointers ......................................................... 5-5

Addressing Circular Buffers ..................................................... 5-6

Addressing With Bit-Reversed Addresses .................................. 5-9

Indexed Addressing With Index and Pointer Registers ............. 5-10

Auto-Increment and Auto-Decrement Addressing ................... 5-11

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Pre-Modify Stack Pointer Addressing ..................................... 5-11

Indexed Addressing With Immediate Offset ........................... 5-12

Post-Modify Addressing ........................................................ 5-12

Modifying DAG and Pointer Registers ........................................ 5-13

Memory Address Alignment ........................................................ 5-13

DAG Instruction Summary ......................................................... 5-17

MEMORY

Memory Architecture .................................................................... 6-1

Overview of Internal Memory ................................................. 6-2

Overview of Scratchpad Data SRAM ....................................... 6-5

L1 Instruction Memory ................................................................ 6-5

Instruction Memory Control

(IMEM_CONTROL) Register ............................................. 6-6

L1 Instruction SRAM ............................................................. 6-8

L1 Instruction Cache ............................................................ 6-10

Cache Lines ...................................................................... 6-10

Cache Hits and Misses .................................................. 6-14

Cache Line Fills ............................................................ 6-15

Line Fill Buffer ............................................................. 6-15

Cache Line Replacement ............................................... 6-15

Instruction Cache Management ........................................ 6-17

Instruction Cache Locking by Line ................................ 6-17

Instruction Cache Locking by Way ................................ 6-18

Instruction Cache Invalidation ...................................... 6-19

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Instruction Test Registers ............................................................ 6-20

Instruction Test Command

(ITEST_COMMAND) Register ......................................... 6-21

Instruction Test Data (ITEST_DATA1) Register .................... 6-22

Instruction Test Data 0 (ITEST_DATA0) Register ................. 6-23

L1 Data Memory ........................................................................ 6-24

Data Memory Control (DMEM_CONTROL) Register .......... 6-24

L1 Data SRAM ..................................................................... 6-27

L1 Data Cache ...................................................................... 6-28

Example of Mapping Cacheable Address Space .................. 6-31

Data Cache Access ............................................................ 6-34

Cache Write Method ......................................................... 6-35

Interrupt Priority Register and Write Buffer Depth ............ 6-35

Data Cache Control Instructions ....................................... 6-37

Data Cache Invalidation .................................................... 6-37

Data Test Registers ...................................................................... 6-38

Data Test Command (DTEST_COMMAND) Register ......... 6-39

Data Test Data (DTEST_DATA1) Register ............................ 6-40

Data Test Data (DTEST_DATA0) Register ............................ 6-41

External Memory ........................................................................ 6-42

Memory Protection and Properties .............................................. 6-42

Memory Management Unit ................................................... 6-42

Memory Pages ....................................................................... 6-44

Memory Page Attributes .................................................... 6-44

Page Descriptor Table ............................................................ 6-46

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CPLB Management ............................................................... 6-46

MMU Application ................................................................ 6-48

Examples of Protected Memory Regions ................................ 6-49

Instruction CPLB Data (ICPLB_DATAx) Registers ............... 6-50

Data CPLB Data (DCPLB_DATAx) Registers ....................... 6-53

Data CPLB Address (DCPLB_ADDRx) Registers .................. 6-55

Instruction CPLB Address (ICPLB_ADDRx) Registers .......... 6-56

Instruction and Data CPLB Status

(ICPLB_STATUS, DCPLB_STATUS) Registers ................. 6-58

Instruction and Data CPLB Fault Address (ICPLB_FAULT_ADDR,

DCPLB_FAULT_ADDR) Registers .................................... 6-60

Memory Transaction Model ........................................................ 6-61

Load/Store Operation ................................................................. 6-62

Interlocked Pipeline .............................................................. 6-63

Ordering of Loads and Stores ................................................ 6-64

Synchronizing Instructions .................................................... 6-65

Speculative Load Execution ................................................... 6-66

Conditional Load Behavior ................................................... 6-67

Working With Memory .............................................................. 6-68

Alignment ............................................................................. 6-68

Cache Coherency .................................................................. 6-68

Atomic Operations ................................................................ 6-69

Memory-Mapped Registers .................................................... 6-69

Core MMR Programming Code Example .............................. 6-70

Terminology ............................................................................... 6-71

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CHIP BUS HIERARCHY

Internal Interfaces ......................................................................... 7-1

Internal Clocks ............................................................................. 7-1

Core Overview .............................................................................. 7-3

System Overview ........................................................................... 7-4

System Interfaces .......................................................................... 7-4

Peripheral Access Bus (PAB) ..................................................... 7-5

PAB Arbitration .................................................................. 7-5

PAB Performance ................................................................ 7-5

PAB Agents (Masters, Slaves) ............................................... 7-6

DMA Access (DAB0/DAB1), Core (DCB0/DCB1),

and External Buses (DEB0/DEB1) ........................................ 7-7

DABx, DCBx, and DEBx Arbitration .................................. 7-7

DAB, DCB, and DEB Performance ..................................... 7-9

DAB Bus Agents (Masters) ................................................ 7-10

External Access Bus (EAB) ..................................................... 7-10

EAB Arbitration ................................................................ 7-11

EAB Performance .............................................................. 7-11

DYNAMIC POWER MANAGEMENT

Clocking ....................................................................................... 8-1

Phase-Locked Loop and Clock Control .................................... 8-2

PLL Overview ..................................................................... 8-2

PLL Clock Multiplier Ratios .................................................... 8-3

Core Clock/System Clock Ratio Control ............................. 8-4

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Contents

PLL Registers .......................................................................... 8-6

PLL Divide (PLL_DIV) Register ......................................... 8-6

PLL Control (PLL_CTL) Register ....................................... 8-7

PLL Status (PLL_STAT) Register ........................................ 8-9

PLL Lock Count (PLL_LOCKCNT) Register ................... 8-10

Dynamic Power Management Controller ..................................... 8-11

Operating Modes .................................................................. 8-12

Dynamic Power Management Controller States ...................... 8-12

Full On Mode .................................................................. 8-13

Active Mode ..................................................................... 8-13

Sleep Mode ...................................................................... 8-13

Deep Sleep Mode ............................................................. 8-14

Hibernate State ................................................................. 8-15

Operating Mode Transitions .................................................. 8-15

Programming Operating Mode Transitions ........................ 8-18

PLL Programming Sequence ......................................... 8-19

PLL Programming Sequence Continues ......................... 8-21

Examples ...................................................................... 8-21

Dynamic Supply Voltage Control .......................................... 8-23

Power Supply Management ................................................... 8-24

Voltage Regulator Control (VR_CTL) Register ................ 8-25

Changing Voltage ............................................................. 8-28

Powering Down the Core (Hibernate State) ....................... 8-29

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DIRECT MEMORY ACCESS

DMA and Memory DMA MMRs .................................................. 9-3

Naming Conventions for DMA MMRs .................................... 9-5

Naming Conventions for Memory DMA Registers ......................... 9-7

Next Descriptor Pointer (DMAx_NEXT_DESC_PTR,

MDMAx_yy_NEXT_DESC_PTR) Registers ........................ 9-8

Start Address (DMAx_START_ADDR,

MDMAx_yy_START_ADDR) Registers ............................. 9-10

DMA Configuration (DMAx_CONFIG,

MDMAx_yy_CONFIG) Registers ...................................... 9-11

Inner Loop Count (DMAx_X_COUNT,

MDMAx_yy_X_COUNT) Registers ................................... 9-14

Inner Loop Address Increment (DMAx_X_MODIFY,

MDMAx_yy_X_MODIFY) Registers .................................. 9-15

Outer Loop Count (DMAx_Y_COUNT,

MDMAx_yy_Y_COUNT) Registers ................................... 9-16

Outer Loop Address Increment (DMAx_Y_MODIFY,

MDMAx_yy_Y_MODIFY) Registers .................................. 9-17

Current Descriptor Pointer (DMAx_CURR_DESC_PTR,

MDMAx_yy_CURR_DESC_PTR) Registers ...................... 9-17

Current Address (DMAx_CURR_ADDR,

MDMAx_yy_CURR_ADDR) Registers .............................. 9-18

Current Inner Loop Count (DMAx_CURR_X_COUNT,

MDMAx_yy_CURR_X_COUNT) Registers ....................... 9-19

Current Outer Loop Count (DMAx_CURR_Y_COUNT,

MDMAx_yy_CURR_Y_COUNT) Registers ....................... 9-20

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Peripheral Map (DMAx_PERIPHERAL_MAP,

MDMAx_yy_PERIPHERAL_MAP) Registers ..................... 9-21

Interrupt Status (DMAx_IRQ_STATUS,

MDMAx_yy_IRQ_STATUS) Registers ............................... 9-25

Flex Descriptor Structure ............................................................ 9-28

Two-Dimensional DMA ............................................................. 9-30

DMA Operation Flow ................................................................ 9-32

DMA Startup ........................................................................ 9-32

DMA Refresh ................................................................... 9-36

To Stop DMA Transfers .................................................... 9-37

Software Management of DMA ......................................... 9-38

Synchronization of Software and DMA ............................. 9-39

Single-Buffer DMA Transfers ........................................ 9-41

Continuous Transfers Using Auto Buffering .................. 9-41

Descriptor Structures .................................................... 9-43

Descriptor Queue Management .................................... 9-44

Descriptor Queue Using Interrupts on Every

Descriptor ................................................................. 9-45

Descriptor Queue Using Minimal Interrupts ................. 9-46

More 2D DMA Examples ................................................. 9-48

Memory DMA ........................................................................... 9-49

MDMA Bandwidth ............................................................... 9-51

MDMA Priority and Scheduling ............................................ 9-52

DMA Controller Errors (Aborts) ................................................. 9-53

DMA Performance: Prioritization and Optimization .................... 9-56

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Prioritization and Traffic Control ................................................ 9-58

DMA Traffic Control Counter Period (DMACx_TC_PER)

and Counter (DMACx_TC_CNT) Registers ....................... 9-60

Urgent DMA Transfers ................................................................ 9-63

SPI COMPATIBLE PORT CONTROLLERS

Interface Signals .......................................................................... 10-4

Serial Peripheral Interface Clock Signals (SCKx) ..................... 10-4

Serial Peripheral Interface Slave Select Input

Signals (SPIxSS) ................................................................. 10-4

Master Out Slave In (MOSIx) ................................................ 10-5

Master In Slave Out (MISOx) ................................................ 10-5

Interrupt Output ................................................................... 10-7

SPI Registers ............................................................................... 10-7

SPI BAUD Rate (SPIx_BAUD) Register ................................. 10-8

SPI Control (SPIx_CTL) Register .......................................... 10-9

SPI Flag (SPIx_FLG) Register .............................................. 10-10

Slave Select Inputs .......................................................... 10-14

Use of FLS Bits in SPI0_FLG for Multiple Slave

SPI Systems .................................................................. 10-14

Special Considerations for SPI1 and SPI2

Slave Control ............................................................... 10-16

SPI Status (SPIx_STAT) Register ......................................... 10-17

SPI Transmit Data Buffer (SPIx_TDBR) Register ................. 10-18

SPI Receive Data Buffer (SPIx_RDBR) Register ................... 10-19

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SPI Receive Data Buffer Shadow

(SPIx_SHADOW) Register .............................................. 10-19

Register Functions .............................................................. 10-21

SPI Transfer Formats ................................................................ 10-21

SPI General Operation ............................................................. 10-23

Clock Signals ...................................................................... 10-25

Master Mode Operation ...................................................... 10-26

Transfer Initiation From Master (Transfer Modes) ................ 10-27

Slave Mode Operation ......................................................... 10-28

Slave Ready for a Transfer .................................................... 10-29

Error Signals and Flags ............................................................. 10-30

Mode Fault Error (MODF) ................................................. 10-30

Transmission Error (TXE) ................................................... 10-31

Reception Error (RBSY) ...................................................... 10-31

Transmit Collision Error (TXCOL) ..................................... 10-32

Beginning and Ending an SPI Transfer ...................................... 10-32

DMA ....................................................................................... 10-34

DMA Functionality ............................................................ 10-34

Master Mode DMA Operation ............................................ 10-35

Slave Mode DMA Operation ............................................... 10-37

Timing ..................................................................................... 10-40

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PARALLEL PERIPHERAL INTERFACE

PPI Registers ............................................................................... 11-2

PPI_CONTROL Register ...................................................... 11-3

PPI_STATUS Register ........................................................... 11-8

PPI_DELAY Register ............................................................. 11-9

PPI_COUNT Register ........................................................ 11-10

PPI_FRAME Register .......................................................... 11-11

ITU-R 656 Modes .................................................................... 11-13

ITU-R 656 Background ....................................................... 11-13

ITU-R 656 Input Modes ..................................................... 11-16

Entire Field ..................................................................... 11-17

Active Video Only .......................................................... 11-18

Vertical Blanking Interval (VBI) only ............................... 11-18

ITU-R 656 Output Mode .................................................... 11-19

Frame Synchronization in ITU-R 656 Modes ....................... 11-19

General-Purpose PPI Modes ...................................................... 11-20

Data Input (RX) Modes ....................................................... 11-21

No Frame Syncs .............................................................. 11-22

1, 2, or 3 External Frame Syncs ....................................... 11-23

2 or 3 Internal Frame Syncs ............................................. 11-24

Data Output (TX) Modes .................................................... 11-24

No Frame Syncs .............................................................. 11-25

1 or 2 External Frame Syncs ............................................ 11-25

1, 2, or 3 Internal Frame Syncs ........................................ 11-26

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Frame Synchronization in GP Modes ................................... 11-26

Modes with Internal Frame Syncs .................................... 11-27

Modes With External Frame Syncs .................................. 11-29

DMA Operation ....................................................................... 11-30

Data Transfer Scenarios ............................................................ 11-31

UART PORT CONTROLLERS

Serial Communications ............................................................... 12-2

UART Control and Status Registers ............................................ 12-2

UART Line Control (UARTx_LCR) Register ........................ 12-3

UART Modem Control (UARTx_MCR) Register .................. 12-4

UART Line Status (UARTx_LSR) Register ............................ 12-4

UART Transmit Holding (UARTx_THR) Register ................ 12-6

UART Receive Buffer (UARTx_RBR) Register ...................... 12-7

UART Interrupt Enable (UARTx_IER) Register .................... 12-8

UART Interrupt Identification (UARTx_IIR) Register ......... 12-10

UARTx_DLL and UARTx_DLH Registers .......................... 12-12

UART Scratch (UARTx_SCR) Register ............................... 12-14

UART Global Control (UARTx_GCTL) Register ................ 12-14

Non-DMA Mode ..................................................................... 12-15

DMA Mode ............................................................................. 12-16

Mixing Modes .......................................................................... 12-17

IrDA Support ........................................................................... 12-18

IrDA Transmitter Description ............................................. 12-18

IrDA Receiver Description .................................................. 12-19

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SERIAL PORT CONTROLLERS

SPORT Operation ...................................................................... 13-9

SPORT Disable .......................................................................... 13-9

Setting SPORT Modes .............................................................. 13-11

Register Writes and Effective Latency ........................................ 13-11

SPORT Transmit Configuration

(SPORTx_TCR1, SPORTx_TCR2) Registers ......................... 13-12

SPORT Receive Configuration

(SPORTx_RCR1, SPORTx_RCR2) Registers ......................... 13-18

Data Word Formats ................................................................... 13-22

SPORT Transmit Data (SPORTx_TX) Register ......................... 13-23

SPORT Receive Data (SPORTx_RX) Register ........................... 13-25

SPORT Status (SPORTx_STAT) Register .................................. 13-28

SPORT RX, TX, and Error Interrupts ................................. 13-30

PAB Errors .......................................................................... 13-30

SPORT Transmit Serial Clock Divider

(SPORTx_TCLKDIV, SPORTx_RCLKDIV) Registers ........... 13-31

SPORT Transmit Frame Sync Divider

(SPORTx_TFSDIV, SPORTx_RFSDIV) Register .................. 13-32

Clock and Frame Sync Frequencies ............................................ 13-33

Maximum Clock Rate Restrictions ....................................... 13-35

Frame Sync & Clock Example ......................................... 13-35

Word Length ............................................................................ 13-35

Bit Order .................................................................................. 13-36

Data Type ................................................................................. 13-36

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Companding ............................................................................ 13-37

Clock Signal Options ................................................................ 13-38

Frame Sync Options ................................................................. 13-38

Framed Versus Unframed .................................................... 13-39

Internal Versus External Frame Syncs ................................... 13-40

Active Low Versus Active High Frame Syncs ........................ 13-41

Sampling Edge for Data and Frame Syncs ............................ 13-41

Early Versus Late Frame Syncs

(Normal Versus Alternate Timing) .................................... 13-43

Data Independent Transmit Frame Sync .............................. 13-45

Moving Data Between SPORTs and Memory ............................ 13-46

Stereo Serial Operation ............................................................. 13-46

Multichannel Operation ........................................................... 13-50

SPORT Multichannel Configuration

(SPORTx_MCMCn) Registers ......................................... 13-53

Multichannel Enable ........................................................... 13-54

Frame Syncs in Multichannel Mode ..................................... 13-55

The Multichannel Frame ..................................................... 13-57

Multichannel Frame Delay .................................................. 13-58

Window Size ....................................................................... 13-58

Window Offset ................................................................... 13-59

SPORT Current Channel (SPORTx_CHNL) Register ......... 13-59

Other Multichannel Fields in SPORTx_MCMC2 ................ 13-60

Channel Selection Register .................................................. 13-61

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SPORT Multichannel Receive Selection

(SPORTx_MRCSn) Registers ....................................... 13-62

SPORT Multichannel Transmit Selection

(SPORTx_MTCSn) Registers ....................................... 13-64

Multichannel DMA Data Packing ........................................ 13-66

Support for H.100 Standard Protocol ........................................ 13-67

2X Clock Recovery Control ................................................. 13-67

SPORT Pin/Line Terminations .................................................. 13-68

Timing Examples ...................................................................... 13-68

GENERAL-PURPOSE INPUT/OUTPUT PORT F

GPIO Port F Registers (MMRs) .................................................. 14-5

GPIO Port F Direction (PORTFIO_DIR) Register ................ 14-5

GPIO Port F Value Registers Overview .................................. 14-5

GPIO Port F Data (PORTFIO) Register ................................ 14-8

GPIO Port F Set (PORTFIO_SET), GPIO Port F Clear

(PORTFIO_CLEAR), and GPIO Port F Toggle

(PORTFIO_TOGGLE) Registers ........................................ 14-8

GPIO Port F Mask Interrupt Registers Overview .................. 14-11

GPIO Port F Interrupt Generation Flow .......................... 14-13

GPIO Port F Interrupt A (PORTFIO_MASKA,

PORTFIO_MASKA_CLEAR, PORTFIO_MASKA_SET,

PORTFIO_MASKA_TOGGLE) Registers .................... 14-15

GPIO Port F Interrupt B (PORTFIO_MASKB,

PORTFIO_MASKB_CLEAR, PORTFIO_MASKB_SET,

PORTFIO_MASKB_TOGGLE) Registers .................... 14-17

GPIO Port F Polarity (PORTFIO_POLAR) Register ............ 14-19

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Contents

GPIO Port F Interrupt Sensitivity

(PORTFIO_EDGE) Register ............................................ 14-19

GPIO Port F Set on Both Edges

(PORTFIO_BOTH) Register ........................................... 14-20

GPIO Port F Input Enable (PORTFIO_INEN) Register ...... 14-21

Performance/Throughput ......................................................... 14-22

GENERAL-PURPOSE INPUT/OUTPUT PORTS C, D, E

GPIO Memory-Mapped Registers (MMRs) ................................. 15-5

GPIO Function Enable (PORTxIO_FER) Register ................ 15-5

GPIO Direction (PORTxIO_DIR) Register ........................... 15-7

GPIO Input Enable (PORTxIO_INEN) Register ................. 15-10

GPIO Value Registers ............................................................... 15-12

GPIO Data (PORTxIO) Register ........................................ 15-13

GPIO Set (PORTxIO_SET), GPIO Clear (PORTxIO_CLEAR),

and GPIO Toggle (PORTxIO_TOGGLE) Registers .......... 15-15

Performance/Throughput ......................................................... 15-20

TIMERS

General-Purpose Timers .............................................................. 16-1

Timer Registers .......................................................................... 16-4

TIMER_ENABLE Register ................................................... 16-4

TIMER_DISABLE Register .................................................. 16-5

TIMER_STATUS Register .................................................... 16-6

TIMERx_CONFIG Registers ................................................ 16-8

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TIMERx_COUNTER Registers ............................................ 16-9

TIMERx_PERIOD and TIMERx_WIDTH Registers .......... 16-11

Using the Timer ........................................................................ 16-13

Pulse-Width Modulation (PWM_OUT) Mode .................... 16-16

Output Pad Disable ........................................................ 16-18

Single Pulse Generation ................................................... 16-18

Pulse-Width Modulation Waveform Generation .............. 16-18

Stopping the Timer in PWM_OUT Mode ....................... 16-20

Externally Clocked PWM_OUT ..................................... 16-21

PULSE_HI Toggle Mode ................................................ 16-22

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 16-26

Autobaud Mode .............................................................. 16-34

External Event (EXT_CLK) Mode ....................................... 16-36

Using the Timers With the PPI ............................................ 16-37

Interrupts ............................................................................ 16-37

Illegal States ........................................................................ 16-38

Summary ............................................................................ 16-40

Core Timer ............................................................................... 16-45

TCNTL Register ................................................................. 16-45

TCOUNT Register ............................................................. 16-47

TPERIOD Register ............................................................. 16-47

TSCALE Register ................................................................ 16-48

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Contents

Watchdog Timer ....................................................................... 16-49

Watchdog Timer Operation ................................................. 16-49

WDOG_CNT Register ....................................................... 16-49

WDOG_STAT Register ...................................................... 16-50

WDMOG_CTL Register .................................................... 16-52

REAL-TIME CLOCK

Interfaces .................................................................................... 17-2

RTC Clock Requirements ........................................................... 17-2

RTC Programming Model .......................................................... 17-4

Register Writes ...................................................................... 17-5

Write Latency ....................................................................... 17-6

Register Reads ....................................................................... 17-7

Deep Sleep ............................................................................ 17-7

Prescaler Enable .................................................................... 17-8

Event Flags ........................................................................... 17-8

Interrupts ........................................................................... 17-11

RTC Status (RTC_STAT) Register ............................................ 17-13

RTC Interrupt Control (RTC_ICTL) Register .......................... 17-13

RTC Interrupt Status (RTC_ISTAT) Register ............................ 17-15

RTC Stopwatch Count (RTC_SWCNT) Register ...................... 17-15

RTC Alarm (RTC_ALARM) Register ........................................ 17-17

RTC Prescaler Enable (RTC_PREN) Register ............................ 17-18

State Transitions Summary ........................................................ 17-20

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EXTERNAL BUS INTERFACE UNIT

Overview .................................................................................... 18-1

Block Diagram ...................................................................... 18-2

Internal Memory Interfaces .................................................... 18-4

External Memory Interfaces ................................................... 18-5

EBIU Programming Model .................................................... 18-7

Error Detection ..................................................................... 18-8

Asynchronous Memory Interface ................................................. 18-9

Asynchronous Memory Address Decode ................................. 18-9

EBIU_AMGCTL Register ................................................... 18-10

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............. 18-11

Avoiding Bus Contention .................................................... 18-12

ARDY Input Control ...................................................... 18-16

Programmable Timing Characteristics .................................. 18-16

Asynchronous Accesses by Core Instructions .................... 18-17

Asynchronous Reads .................................................... 18-17

Asynchronous Writes ................................................... 18-19

Adding Additional Wait States ......................................... 18-20

Byte Enables ................................................................... 18-22

On-Chip Flash Memory .................................................. 18-22

SDRAM Controller (SDC) ........................................................ 18-22

Definition of Terms ............................................................. 18-23

Bank Activate Command ................................................. 18-24

Burst Length ................................................................... 18-24

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Burst Stop Command ..................................................... 18-24

Burst Type ...................................................................... 18-25

CAS Latency (CL) .......................................................... 18-25

CBR (CAS Before RAS) Refresh or Auto-Refresh ............. 18-25

DQM Pin Mask Function ............................................... 18-26

Internal Bank ................................................................. 18-26

Mode Register ................................................................ 18-26

Page Size ........................................................................ 18-27

Pre-Charge Command .................................................... 18-27

SDRAM Bank ................................................................ 18-27

Self-Refresh .................................................................... 18-28

t

RAS

............................................................................... 18-28

tRC ................................................................................. 18-28

t

.............................................................................. 18-28

RCD

t

............................................................................... 18-29

RFC

tRP ................................................................................. 18-29

.............................................................................. 18-29

t

RRD

t

................................................................................ 18-29

WR

............................................................................... 18-30

t

XSR

SDRAM Configurations Supported ..................................... 18-30

Example SDRAM System Block Diagrams ........................... 18-31

Executing a Parallel Refresh Command ........................... 18-31

xxx ADSP-BF538 Blackfin Processor Hardware Reference