ANALOG DEVICES ADSP-BF537 Service Manual

Engineer-to-Engineer Note EE-262

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Technical notes on using Analog Devices DSPs, processors and development tools

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ADSP-BF537 Blackfin® Highlights for ADSP-BF533 Users

Contributed by Glen Ouellette and Benno Kusstatscher Rev 2 – May 10, 2005

Introduction

The Blackfin® family of processors from Analog
Devices have recently been enhanced by three
new members, the ADSP-BF534, the ADSP­BF536, and the ADSP-BF537 derivatives. These
new parts, which are code compatible with the
ADSP-BF531 / ADSP-BF532 / ADSP-BF533
devices, provide a different set of peripherals on
the identical platform, including:

• CAN 2.0B controller

• I2C-compatible TWI interface

• One additional UART controller

• Five more timers

• 32 additional GPIOs

• Handshaking Memory DMA capability

In addition, ADSP-BF536 and ADSP-BF537
derivatives also feature a 10/100 Mbps Ethernet
MAC.

Besides all these new peripherals, several
architectural enhancements have been made to
further improve system performance. The
intention of this application note is not to explain
the new peripherals, but rather highlight the
improvements that have been included in the new
ADSP-BF537 devices.

The target audience for this document is
expected to be familiar with ADSP-BF533
processors.

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General-Purpose Ports

The General-purpose Ports is probably the most
significant change from the ADSP-BF533. Due
to the number of on-chip peripherals featured by
ADSP-BF537 devices, there was a need to
multiplex pin functions.

The peripherals are organized into General­purpose Ports designated as Port F, Port G, Port
H, and Port J. In default mode, all pins of Port F,
Port G, and Port H are in general-purpose I/O
(GPIO) mode. Port J does not provide GPIO
functionality.

To enable Peripheral functionality, the Function
Enable registers (

PORTH_FER) must be explicitly written. Certain

pins on Port F, Port G, and Port H, are
multiplexed with more than one peripheral. In
these cases, the required peripheral is controlled
by the Multiplexer Control register (

Where ever this document refers to
ADSP-BF533 processors, it implicitly
relates to the memory derivatives,
ADSP-BF531 and ADSP-BF532, as
well.

Similarly, the name "ADSP-BF537" as
used in this document represents all of
the ADSP-BF536 memory derivatives
and pin-compatible ADSP-BF534 parts.

PORTF_FER, PORTG_FER, and

PORT_MUX).

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When porting code from ADSP-BF533

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Flag Pins vs. GPIOs

The ADSP-BF533 Flag Pins have not been
physically changed on ADSP-BF537 processors.
However, the nomenclature changed. Flag Pins
are now called GPIOs. The register names have
also been changed.

While ADSP-BF533 processors have one module
featuring 16 Flag Pins, ADSP-BF537 processors
feature three such modules, providing 48 GPIOs
in total. Each GPIO can also operate as an
interrupt input. GPIOs can control up to five
interrupt channels.

Most GPIOs are multiplexed with other
functions. After reset, the respective pins are
configured to operate as GPIOs. By default, both
the transmit and receive drivers are disabled. The

PORTxIO_DIR, PORTxIO_INEN, and PORTx_FER

register reset to zero.
Additionally, unlike the ADSP-BF533, the

ADSP-BF537 has eight high-current source/sink
pins to ease system cost and reduce part count.
These pins are found on Port F,
function as such regardless whether in GPIO or
peripheral function mode.

devices to ADSP-BF537 devices, ensure
that startup code manages the function
enable and port muxing registers
accordingly, prior to initializing on-chip
peripherals.

PF7 - PF0, and

enabling you to fully control 32 system interrupt
inputs.

Some of the interrupt sources are hard-wired
together. All DMA error and status interrupts
share one interrupt channel, requiring that you to
install one global DMA error handler for all
DMA channels. Similarly, all peripheral error
interrupt sources are ORed together. See Figure
4-1 of the ADSP-BF537 Blackfin Processor
Hardware Reference
manual dedicates a chapter to system interrupts.

Finally, the polarity of the
changed. Refer to NMI Polarity for details.

[1]

for details. Note that the

NMI input has

DMA Enhancements

Compared to ADSP-BF533 devices, the new
ADSP-BF537 parts have four more DMA
channels to support the numerous additional
peripherals. The new channels are identical to
others. All twelve peripheral DMA channels can
be assigned to any of the connected peripherals.
Consequently, the PMAP field in the

DMAx_PERIPHERAL_MAP registers takes any value

between 0 and 11, now.
The introduction of the four new DMA channels

required a shift in the Memory DMA channels'
register addresses. If used in a symbolic manner,
this has no impact to user code as the ADSP­BF537 header files will resolve the addresses.

SYNC Bit

System Interrupts

Although the Core Event Controller (CEC)
remains the same, the System Interrupt
Controller (SIC) has minor enhancements.

The ADSP-BF533 processor features 23 system
interrupt sources. The ADSP-BF537 features 47
of them! As a result, all 32 bits of the SIC_IWR,

SIC_ISR, and SIC_IMASK registers are now

populated. In addition, a fourth interrupt
assignment register (

ADSP-BF537 Blackfin® Highlights for ADSP-BF533 Users (EE-262) Page 2 of 11

SIC_IAR3) was added,

The operation of Bit 5 of the DMA configuration
registers was enhanced on the ADSP-BF537. On
ADSP-BF533 processors, this bit (called the

RESTART bit) controls receive (memory write)

operation of the DMA channels only.
On ADSP-BF537 processors, this bit is called the

SYNC bit. Though its meaning has almost

remained the same for receive operation, it now
plays an important role in transmit (memory
read) DMA modes of operation.

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When the SYNC bit is cleared on transmit DMAs,
the ADSP-BF537 behaves the same as the
ADSP-BF533. That is, the DMA engine
continues immediately when the last data of a
DMA work unit is transferred from memory into
the DMA FIFO.

This makes perfect sense when the current DMA
descriptor is followed by another DMA
descriptor. The new DMA descriptor is already
fetched while former descriptors final data is still
pending in the DMA FIFO, guaranteeing the
highest throughput.

If, however, a DMA is terminating in stop mode
(FLOW = 0) with interrupts enabled, the interrupt
is issued immediately after the final data have
been moved from the memory into the DMA
FIFO. By the time the interrupt service routine is
invoked, the final data are most likely still
pending in the 4-stage DMA FIFO. Therefore,
the service routine is not allowed to start a new
DMA sequence yet as old data still reside in the
DMA FIFO. The DMA_RUN bit in the

DMAx_IRQ_STATUS registers indicates whether

data still pending in the FIFO. In many cases the
service routine is required to poll this bit until it
goes low.

On the ADSP-BF537, the new SYNC bit enables
you to control the interrupt timing on transmit
DMAs: when set, it delays the interrupt until the
content of the DMA FIFO is drained to the
transmitting peripheral. In other words, the
bit controls whether the interrupt aligns to
memory side or to the peripheral side of the
DMA FIFO.

In the case of a transmit DMA running in stop
mode (
until the
set, the service routine can safely start a new
DMA sequence or reset the DMA configuration.
It is, however, still too early to disable the
connected peripheral, as this may have its own
transmit buffers that are still processing the data.

FLOW = 0), the interrupt does not issue

DMA_RUN bit goes low. With the SYNC bit

SYNC

state machine. If the SYNC bit is cleared, neither
receive nor transmit DMAs are allowed to
change certain settings, such as the transfer word
size between work units. Setting the SYNC bit
eliminates the restrictions for transmit channels.

For receive DMAs, the same recommendation is
valid as for ADSP-BF533 DMAs: do not set the

SYNC bit except in the first work unit of a

descriptor chain.

Descriptor Chains to Varying Memory Spaces

Similar to ADSP-BF533 devices, work units of a
receive DMA descriptor chain are permitted to
write to different memory spaces (i.e., one work
unit writes to internal L1 memory and the
subsequent one writes to any off-chip memory),
regardless of the
however, are traditionally not permitted to write
to different memory spaces. Although the
memory space is specified by the DMA’s start
address only, this operation is not permitted on
ADSP-BF533 processors.

On ADSP-BF537 DMAs, the SYNC bit also
enables a transmit work unit to read data from a
different memory space than the previous work
unit; if the previous one had the SYNC bit set.

It is worth more than just a side note, that with
the help of the SYNC bit, Memory DMAs that
transfer data from on-chip L1 memory to
external memories (or vice versa) can now
change the transfer direction without stopping an
on-going descriptor chain.

The memory write channel of a Memory DMA
behaves like a receive DMA and does not require

SYNC bit to be set. The memory read channel,

the
however, behaves like a transmit DMA. Set the

SYNC bit in descriptors there, if the start address

of subsequent descriptor points to a different
memory space.

SYNC setting. Transmit DMAs,

Digging deeper, the
just the interrupt timing, it impacts also the DMA

ADSP-BF537 Blackfin® Highlights for ADSP-BF533 Users (EE-262) Page 3 of 11

SYNC bit controls more than

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Peripheral-Mastered DMA Channels

On ADSP-BF533 processors, there is a single
control strobe from a peripheral to the DMA
controller: DATA REQUEST. With the addition of
the Ethernet MAC, the ADSP-BF537 DMA
controller has been enhanced to provide the
MAC further control over the assigned DMA
channels. The Ethernet MAC can emit four
different commands to the DMA channel:

• DATA REQUEST

• DATA REQUEST URGENT

• RESTART WORK UNIT

• FINISH WORK UNIT

For example, with the DATA REQUEST URGENT
command, the peripheral can signal to the DMA
channel that a certain high-water level in its
(receive) buffer has been reached and further
data reception would cause data loss, if the DMA
does not serve the peripheral in time.

With the RESTART and FINISH commands, the
peripheral can master the associated DMA
channel. Consider the case of a processor
DMAing in a data stream, and the peripheral
detects an incorrect checksum condition once
done. The peripheral can skip the data stream by
issuing a RESTART command to the DMA
channel. The DMA simply reloads its current
registers again. Upon further
commands, it overwrites the recently received
data again. Although the peripheral had used the
processor’s memory for buffering, the
processor’s core is not impacted by the failing
data stream.

The

FINISH command helps the peripheral

handle data streams with variable length.
Typically, the DMA count register is preloaded
with a maximum value. The peripheral starts
receiving data until it detects that the data unit is
complete. Then it issues a FINISH command. The
core is interrupted optionally, and the DMA
channel starts a new work unit for the new data
set.

DATA REQUEST

Handshaking Memory DMA

Memory-to-memory DMAs usually run at
maximal speed as permitted by system
throughput. The ADSP-BF537 processors'
Handshaking Memory DMA capability enables
the two Memory DMA units to be synchronized
by external hardware.

There are two edge-sensitive DMA request
inputs: DMAR0 and DMAR1. Each is associated with
one of the Memory DMA units: MDMA0 and

MDMA1.

Although DMA request inputs can be used to
control the timing of normal memory-to-memory
DMAs, more than likely, they control transfers,
such as asynchronous FIFOs or off-chip interface
controllers, between Blackfin memory and
hardware buffers.

When handshake operation is enabled, the
Memory DMA no longer runs freely. Rather, the

DATA REQUEST commands are gated by the

HMDMA unit. Options, such as whether to
initialize every individual DMA transfer by a

DMAR0 or DMAR1 edge, or whether such an event

triggers the transfer of an entire block of data, are
user- programmable.

The new handshake operation mode not only
reduces the need of core interaction, it also
increases data throughput, since GPIO polling or
GPIO-driven interrupts can be avoided in many
cases.

External Bus Interface Unit

Three minor, but important, enhancements to the
16-bit wide parallel interface to external
SDRAM and asynchronous memories have been
made:

• The ADSP-BF537 SDRAM controller now

supports SDRAM devices up to 512 MB.

• The

ARDY input does not have to be

synchronous with CLKOUT. This has changed
also on ADSP-BF533 revision 0.4.

ADSP-BF537 Blackfin® Highlights for ADSP-BF533 Users (EE-262) Page 4 of 11