Analog Devices ADSP BF536 7 prd Datasheet

Blackfin

Rev. PrD

Embedded Processor

Preliminary Technical Data

FEATURES

Up to 600 MHz High-Performance Blackfin Processor

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video

ALUs, 40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of

Programming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance-Monitoring

0.8V to 1.2V Core V

2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins 182-Ball MBGA and 208-Ball Sparse MBGA Packages Lead Bearing and Lead Free Package Choices

MEMORY

Up to 132K Bytes of On-Chip Memory:

16K Bytes of Instruction SRAM/Cache 48K Bytes of Instruction SRAM 32K Bytes of Data SRAM/Cache 32K Bytes of Data SRAM 4K Bytes of Scratchpad SRAM

External Memory Controller with Glueless Support for

SDRAM and Asynchronous 8/16-Bit Memories

Flexible Booting Options from External Flash, SPI and TWI

Memory or from SPI, TWI, and UART Host Devices

with On-chip Voltage Regulation

ADSP-BF536/ADSP-BF537

Two Dual-Channel Memory DMA Controllers Memory Management Unit Providing Memory Protection

PERIPHERALS

IEEE 802.3-Compliant 10/100 Ethernet MAC Controller Area Network (CAN) 2.0B Interface Parallel Peripheral Interface (PPI), Supporting ITU-R 656

Video Data Formats

Two Dual-Channel, Full-Duplex Synchronous Serial Ports

(SPORTs), Supporting Eight Stereo I 12 Peripheral DMAs, 2 Mastered by the Ethernet MAC Two Memory-to-Memory DMAs With External Request Lines Event Handler With 32 Interrupt Inputs Serial Peripheral Interface (SPI)-Compatible Two UARTs with IrDA® Support Two-Wire Interface (TWI) Controller Eight 32-Bit Timer/Counters with PWM Support Real-Time Clock (RTC) and Watchdog Timer 32-Bit Core Timer 48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers On-Chip PLL Capable of 1x to 63x Frequency Multiplication Debug/JTAG Interface

S Channels

JTAG TEST AND

EMULATION

VOLTAGE

REGULATOR

INSTRUCTION

MEMORY

CORE / SYSTEM BUS INTERFACE

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

EVENT

CONTROLLER/

CORE TIMER

MMU

CONTROLLER

Figure 1. Functional Block Diagram

MEMORY

DMA

BOOT ROM

DATA

WATCHDOG TIMER

RTC

ETHERNET MAC

CAN

TWI

SPORT0

SPORT1

PPI

UART 0-1

SPI

TIMERS 0-7

EXTERNAL PORT

FLASH, SDRAM

CONTROL

GPIO PORT

PORT

GPIO

PORT

GPIO

PORT

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF536/BF537 Processor Peripherals ... .............. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 4

Internal (On-chip) Memory ................................. 5

External (Off-Chip) Memory ................................ 5

I/O Memory Space ............................................. 5

Booting ........................................................... 6

Event Handling ................................................. 6

Core Event Controller (CEC) ................................ 7

System Interrupt Controller (SIC) .......................... 7

Event Control ................................................... 7

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports (UARTs) .......................................... 11

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

General-Purpose I/O (GPIO) .............................. 12

Parallel Peripheral Interface (PPI) ........................... 13

Dynamic Power Management ................................ 13

Full-On Operating Mode – Maximum Performance . 13

Active Operating Mode – Moderate Power Savings .. 13

Sleep Operating Mode – High Dynamic Power

Savings ....................................................... 13

Deep Sleep Operating Mode – Maximum Dynamic

Power Savings .............................................. 13

Hibernate Operating Mode – Maximum Static Power

Savings ....................................................... 14

Power Savings ................................................. 14

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 14

Booting Modes ................................................... 16

Instruction Set Description ................................... 16

Development Tools ............................................. 17

Designing an Emulator-Compatible Processor

Board(Target) ................................................. 17

Related Documents .............................................. 17

Pin Descriptions .................................................... 18

Specifications ........................................................ 22

Recommended Operating Conditions ...................... 22

Absolute Maximum Ratings ................................... 24

ESD Sensitivity ................................................... 24

Timing Specifications ........................................... 25

Asynchronous Memory Read Cycle Timing ............ 27

Asynchronous Memory Write Cycle Timing ........... 28

SDRAM Interface Timing .................................. 29

External Port Bus Request and Grant Cycle Timing . . 30

External DMA Request Timing ............................ 31

Parallel Peripheral Interface Timing ...................... 32

Serial Ports ..................................................... 33

Serial Peripheral Interface (SPI) Port—Master

Timing ....................................................... 38

Serial Peripheral Interface (SPI) Port—Slave Timing . 39

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing ..... 40

General-Purpose Port Timing ............................. 41

Timer Cycle Timing .......................................... 42

JTAG Test And Emulation Port Timing ................. 43

TWI Controller Timing ..................................... 44

10/100 Ethernet MAC Controller Timing ............... 48

Output Drive Currents ......................................... 51

Power Dissipation ............................................... 54

Test Conditions .................................................. 54

Output Enable Time ......................................... 54

Output Disable Time ......................................... 54

Example System Hold Time Calculation ................ 55

Environmental Conditions .................................... 55

182-Ball Mini-BGA Pinout ....................................... 56

208-Ball Sparse Mini-BGA Pinout .............................. 59

Outline Dimensions ................................................ 62

Ordering Guide ..................................................... 64

Rev. PrD | Page 2 of 64 | January 2005

REVISION HISTORY

Revision PrD: Corrections to PrC because of changes to Ordering Guide, addition of driver type to Table 9, other minor corrections.

Changes to:

Features ................................................................. 1

Clock Signals ......................................................... 14

Figure 6 ................................................................ 15

Figure 7 ................................................................ 15

Booting Modes ....................................................... 16

Table 9 ................................................................. 18

Figure 10 .............................................................. 26

GENERAL DESCRIPTION

ADSP-BF536/ADSP-BF537Preliminary Technical Data

Table 16 ............................................................... 26

Table 46 ................................................................48

Output Drive Currents ............................................ 51

Table 50 ............................................................... 56

Table 51 ............................................................... 57

208-Ball Sparse Mini-BA Pinout ................................ 59

Table 52 ............................................................... 59

Table 53 ............................................................... 60

Figure 54 title ........................................................ 63

Ordering Guide ..................................................... 64

The ADSP-BF536/BF537 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor

Table 1. Processor Comparison

ADSP-BF536 ADSP-BF537

Maximum performance 400 MHz 600 MHz Instruction SRAM/Cache 16K bytes 16K bytes Instruction SRAM 48K bytes 48K bytes Data SRAM/Cache 16K bytes 32K bytes Data SRAM 16K bytes 32K bytes Scratchpad 4K bytes 4K bytes

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature on-chip Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF536/BF537 processors are highly integrated system-on-a-chip solutions for the next generation of embedded network connected applications. By combining industry-stan-

instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

The ADSP-BF536/BF537 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.

dard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC, a CAN

2.0B controller, a TWI controller, two UART ports, an SPI port, two serial ports (SPORTs), nine general purpose 32-bit timers (eight with PWM capability), a real-time clock, a watchdog timer, and a Parallel Peripheral Interface.

ADSP-BF536/BF537 PROCESSOR PERIPHERALS

The ADSP-BF536/BF537 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram

on page 1). The general-purpose peripherals include functions

such as UARTs, SPI, TWI, Timers with PWM (Pulse Width Modulation) and pulse measurement capability, general purpose I/O pins, a Real-Time Clock, and a Watchdog Timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP-BF536/BF537 processor contains dedicated

Rev. PrD | Page 3 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

network communication modules and high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, CAN, TWI, Real-Time Clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.

The ADSP-BF536/BF537 processor includes an on-chip voltage regulator in support of the ADSP-BF536/BF537 processor Dynamic Power Management capability. The voltage regulator provides a range of core voltage levels when supplied from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 2 and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

multiply, divide primitives, saturation

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit Index, Modify, Length, and Base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.

In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.

The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while Supervisor mode has unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF536/BF537 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on page 6, and

Figure 4 on page 6.

Rev. PrD | Page 4 of 64 | January 2005

LD032BITS

LD132BITS

SD 3 2 BI TS

R7 R6 R5 R4 R3 R2 R1 R0

R7 .H R6 .H R5 .H R4 .H R3 .H R2 .H R1 .H R0 .H

ADSP-BF536/ADSP-BF537Preliminary Technical Data

ADDRE SS ARITHMETIC UNIT

SP FP

P5 P4 P3 P2 P1 P0

R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L

I3 I2 I1 I0

BARREL SHIF TER

B3 L2 L1 L0

A0 A1

88 8 8

40 40

DAG0 DA G 1

SEQUENCER

ALIGN

DECODE

LOOP BUF FER

CONTROL

UN IT

DATA ARITHMETIC UNI T

Figure 2. Blackfin Processor Core

The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 516M bytes of physical memory.

The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.

Internal (On-chip) Memory

The ADSP-BF536/BF537 processor has three blocks of on-chip memory providing high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed.

The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both Cache and SRAM functionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed to interface to up to 512M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance.

The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory.

I/O Memory Space

The ADSP-BF536/BF537 processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers

Rev. PrD | Page 5 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0800

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR RE GISTERS (2M BYT E)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

INSTRUCTION BANK B SRAM (16K BYTE)

INSTRUCTION BANK A SRAM (32K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

RESERVED

BOOT ROM (2K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 512M BYTE)

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M L A N R E T X E

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0800

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR RE GISTERS (2M BYT E)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

INSTRUCTION BANK B SRAM (16K BYTE)

INSTRUCTION BANK A SRAM (32K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

BOOT ROM (2K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 512M BYTE)

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M L A N R E T X E

Figure 3. ADSP-BF536 Internal/External Memory Map

needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.

Booting

The ADSP-BF536/BF537 processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF536/BF537 processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see

Booting Modes on page 16.

Event Handling

The event controller on the ADSP-BF536/BF537 processor handles all asynchronous and synchronous events to the processor. The ADSP-BF536/BF537 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events:

• Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface.

• Reset – This event resets the processor.

Figure 4. ADSP-BF537 Internal/External Memory Map

•Non-Maskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.

• Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.

The ADSP-BF536/BF537 processor Event Controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the generalpurpose interrupts of the CEC.

Rev. PrD | Page 6 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15– 7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF536/BF537 processor.

Table 2 describes the inputs to the CEC, identifies their names

in the Event Vector Table (EVT), and lists their priorities.

Table 2. Core Event Controller (CEC)

Priority (0 is Highest)

0Emulation/Test ControlEMU 1Reset RST 2 Non-Maskable Interrupt NMI 3ExceptionEVX 4Reserved— 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15

Event Class EVT Entry

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF536/BF537 processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event Default

Mapping

PLL Wakeup IVG7 0 DMA Error (generic) IVG7 1 DMAR0 Block Interrupt IVG7 1 DMAR1 Block Interrupt IVG7 1 DMAR0 Overflow Error IVG7 1 DMAR1 Overflow Error IVG7 1 CAN Error IVG7 2 Ethernet Error IVG7 2 SPORT 0 Error IVG7 2 SPORT 1 Error IVG7 2 PPI Error IVG7 2 SPI Error IVG7 2 UART0 Error IVG7 2 UART1 Error IVG7 2 Real-Time Clock IVG8 3 DMA Channel 0 (PPI) IVG8 4 DMA Channel 3 (SPORT 0 RX) IVG9 5 DMA Channel 4 (SPORT 0 TX) IVG9 6 DMA Channel 5 (SPORT 1 RX) IVG9 7 DMA Channel 6 (SPORT 1 TX) IVG9 8 TWI IVG10 9 DMA Channel 7 (SPI) IVG10 10 DMA Channel 8 (UART0 RX) IVG10 11 DMA Channel 9 (UART0 TX) IVG10 12 DMA Channel 10 (UART1 RX) IVG10 13 DMA Channel 11 (UART1 TX) IVG10 14 CAN RX IVG11 15 CAN TX IVG11 16 DMA Channel 1 (Ethernet RX) IVG11 17 Port H Interrupt A IVG11 17 DMA Channel 2 (Ethernet TX) IVG11 18

Peripheral Interrupt ID

Event Control

The ADSP-BF536/BF537 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide:

• CEC Interrupt Latch Register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system.

Rev. PrD | Page 7 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

Table 3. System Interrupt Controller (SIC) (Continued)

Peripheral Interrupt Event Default

Mapping

Port H Interrupt B IVG11 18 Timer 0 IVG12 19 Timer 1 IVG12 20 Timer 2 IVG12 21 Timer 3 IVG12 22 Timer 4 IVG12 23 Timer 5 IVG12 24 Timer 6 IVG12 25 Timer 7 IVG12 26 Port F, G Interrupt A IVG12 27 Port G Interrupt B IVG12 28 DMA Channels 12 and 13

(Memory DMA Stream 0) DMA Channels 14 and 15

(Memory DMA Stream 1) Software Watchdog Timer IVG13 31 Port F Interrupt B IVG13 31

IVG13 29

IVG13 30

Peripheral Interrupt ID

This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.

• CEC Interrupt Mask Register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.)

• CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on page 7.

• SIC Interrupt Mask Register (SIC_IMASK)– This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.

• SIC Interrupt Status Register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.

• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on page 13.)

Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF536/BF537 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF536/BF537 processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, SPORTs, SPI port, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.

The ADSP-BF536/BF537 processor DMA controller supports both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly.

Examples of DMA types supported by the ADSP-BF536/BF537 processor DMA controller include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer

Rev. PrD | Page 8 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

• 1-D or 2-D DMA using a linked list of descriptors

•2-D DMA using an array of descriptors, specifying only the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the ADSP-BF536/BF537 processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer mechanism.

The ADSP-BF536/BF537 processors also include an external DMA controller capability via dual external DMA request pins when used in conjunction with the External Bus Interface Unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memDMA. The number of transfers per edge is programmable. This feature can be programmed to allow memDMA to have an increased priority on the external bus relative to the core.

REAL-TIME CLOCK

The ADSP-BF536/BF537 processor Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a

32.768 KHz crystal external to the ADSP-BF536/BF537 processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.

The 32.768 KHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the ADSPBF536/BF537 processor from Sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the ADSP-BF536/BF537 processor from Deep Sleep mode, and wake up the on-chip internal voltage regulator from the Hibernate operating mode.

Connect RTC pins RTXI and RTXO with external components as shown in Figure 5.

RTXI

C1 C2

SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF

⍀

R1 = 10 M NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

Figure 5. External Components for RTC

RTXO

WATCHDOG TIMER

The ADSP-BF536/BF537 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF536/BF537 processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency of f

SCLK

TIMERS

There are nine general-purpose programmable timer units in the ADSP-BF536/BF537 processor. Eight timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels.

Rev. PrD | Page 9 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.

In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF536/BF537 processor incorporates two dualchannel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:

S capable operation.

•I

• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels

S stereo audio.

of I

• Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f

/131,070) Hz to (f

SCLK

• Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync.

• Companding in hardware – Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

• DMA operatio ns with single-cycle overhead – E ach SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA.

• Multichannel capability – Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

SCLK

/2) Hz.

The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (Serial Clock, SCK). An SPI chip select input pin (SPISS processor, and seven SPI chip select output pins (SPISEL7–1

) lets other SPI devices select the

) let the processor select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.

The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI’s DMA controller can only service unidirectional accesses at any given time.

The SPI port’s clock rate is calculated as:

SPI Clock Rate

---------------------------------=

2 SPI_Baud×

SCLK

Where the 16-bit SPI_Baud register contains a value of 2 to 65,535.

During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF536/BF537 processor has an SPI-compatible port that enables the processor to communicate with multiple SPIcompatible devices.

Rev. PrD | Page 10 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

UART PORTS (UARTS)

The ADSP-BF536/BF537 processor provides two full-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. Each UART port supports two modes of operation:

• PIO (Programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (Direct Memory Access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

/16) bits per second.

SCLK

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

UART Clock Rate

Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8bits).

In conjunction with the general-purpose timer functions, autobaud detection is supported.

The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.

------------------------------------------------=

16 UART_Divisor×

/ 1,048,576) to

SCLK

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF536/BF537 processor offers a CAN controller that is a communication controller implementing the Controller Area Network (CAN) 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network since the protocol incorporates CRC checking message error tracking, and fault node confinement.

The ADSP-BF536/BF537 CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats.

• Support for remote frames.

• Active or passive network support.

• CAN wakeup from Hibernation Mode (lowest static power consumption mode).

•Interrupts, including: TX Complete, RX Complete, Error, Global.

The electrical characteristics of each network connection are very demanding so the CAN interface is typically divided into two parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks. The ADSP-BF536/BF537 CAN module represents only the controller part of the interface. The controller interface supports connection to 3.3V high-speed, fault-tolerant, single-wire transceivers.

TWI CONTROLLER INTERFACE

The ADSP-BF536/BF537 processor includes a Two Wire Interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I the capabilities of simultaneous Master and Slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels.

Additionally, the ADSP-BF536/BF537 processor’s TWI module is fully compatible with Serial Camera Control Bus (SCCB) functionality for easier control of various CMOS camera sensor devices.

C bus standard. The TWI module offers

10/100 ETHERNET MAC

The ADSP-BF536/BF537 processor offers the capability to directly connect to a network by way of an embedded Fast Ethernet Medium Access Controller (MAC) that supports both 10-BaseT (10Mbits/sec) and 100-BaseT (100Mbits/sec) operation. The 10/100 Ethernet MAC peripheral on the ADSPBF536/BF537 is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus utilization, or message processing by the rest of the processor system.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full Duplex and Half Duplex modes.

Rev. PrD | Page 11 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

• Data framing and encapsulation: generation and detection of preamble, length padding, and FCS.

• Media access management (in Half-Duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing.

• Flow control (in Full-Duplex operation): generation and detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames for read-write access to PHY registers.

• SCLK operating range down to 25MHz (Active and Sleep operating modes).

• Internal loopback from TX to RX.

Some advanced features are:

• Buffered crystal output to external PHY for support of a single crystal system.

• Automatic checksum computation of IP header and IP payload fields of RX frames.

• Independent 32-bit descriptor-driven RX and TX DMA channels.

• Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software.

• TX DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit alignment of encapsulated RX or TX IP packet data in memory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any combination of:

• Any selected RX or TX frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at halffull.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value.

• Programmable RX address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames.

• Advanced power management supporting unattended transfer of RX and TX frames and status to/from external memory via DMA during low-power Sleep mode.

• System wakeup from Sleep operating mode upon magic packet or any of four user-definable wakeup frame filters.

• Support for 802.3Q tagged VLAN frames.

• Programmable MDC clock rate and preamble suppression.

• In RMII operation, 7 unused pins may be configured as GPIO pins for other purposes.

PORTS

Because of the rich set of peripherals, the ADSP-BF536/BF537 processor groups the many peripheral signals to four ports— Port F, Port G, Port H, and Port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls. Eight of the pins (Port F7–0) offer high source/high sink current capabilities.

General-Purpose I/O (GPIO)

The ADSP-BF536/BF537 processor has 48 bi-directional, general-purpose I/O (GPIO) pins

GPIO modules—PORTFIO, PORTGIO, and PORTHIO, asso-

ciated with Port F, Port G, and Port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other ADSP-BF536/BF537 processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output or input drivers are active by default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers:

• GPIO Direction Control Register – Specifies the direction of each individual GPIO pin as input or output.

• GPIO Control and Status Registers – The ADSPBF536/BF537 processor employs a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins.

• GPIO Interrupt Mask Registers – The two GPIO Interrupt Mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO Control Registers that are used to set and clear individual pin values, one GPIO Interrupt Mask Register sets bits to enable interrupt function, and the other GPIO Interrupt Mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts.

• GPIO Interrupt Sensitivity Registers – The two GPIO Interrupt Sensitivity Registers specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.

allocated across three separate

Rev. PrD | Page 12 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

PARALLEL PERIPHERAL INTERFACE (PPI)

The ADSP-BF536/BF537 processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R-601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins.

In ITU-R-656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported.

Three distinct ITU-R-656 modes are supported:

• Active Video Only Mode—The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.

• Vertical Blanking Only Mode—The PPI only transfers Vertical Blanking Interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.

• Entire Field Mode—The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals.

Though not explicitly supported, ITU-R-656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle:

• Data Receive with Internally Generated Frame Syncs.

• Data Receive with Externally Generated Frame Syncs.

• Data Transmit with Internally Generated Frame Syncs

• Data Transmit with Externally Generated Frame Syncs

These modes support ADC/DAC connections, as well as video communication with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF536/BF537 processor provides five operating modes, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each of the ADSP-BF536/BF537 processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode – Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Active Operating Mode – Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories.

In the Active mode, it is possible to disable the PLL through the PLL Control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes.

Table 4. Power Settings

Mode

Full On Enabled No Enabled Enabled On Active Enabled/

Sleep Enabled - Disabled Enabled On Deep Sleep Disabled - Disabled Disabled On Hibernate Disabled - Disabled Disabled Off

PLL

Disabled

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Ye s E na bl ed E na bl e d O n

Core

Sleep Operating Mode – High Dynamic Power Savings

The Sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the Full On mode. If BYPASS is enabled, the processor will transition to the Active mode.

When in the Sleep mode, system DMA access to L1 memory is not supported.

Deep Sleep Operating Mode – Maximum Dynamic Power Savings

The Deep Sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but will not be able to access

Power

Rev. PrD | Page 13 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET

) or by an asynchronous interrupt generated by the RTC. When in Deep Sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET

while in Deep Sleep mode causes the pro-

cessor to transition to the Full On mode.

Hibernate Operating Mode – Maximum Static Power Savings

The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (V

) to 0V to provide the greatest power savings mode.

DDINT

Any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved.

Since V

is still supplied in this mode, all of the external

DDEXT

pins tri-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current.

The internal supply regulator can be woken up by CAN or by Ethernet. It can also be woken up by a Real-Time Clock wakeup event or by asserting the RESET

pin, both of which initiate the

hardware reset sequence.

Power Savings

As shown in Table 5, the ADSP-BF536/BF537 processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF536/BF537 processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of Dynamic Power Management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V RTC internal logic and crystal I/O V All other I/O V

DDINT

DDRTC

DDEXT

The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic.

The Dynamic Power Management feature of the ADSPBF536/BF537 processor allows both the processor’s input voltage (V

) and clock frequency (f

DDINT

) to be dynamically

CCLK

controlled.

As explained above, the savings in power dissipation can be modeled by the following equations:

Power Savings Factor

CCLKRED

--------------------------------

CCLKNOM



DDINTRED

--------------------------------------





DDINTNOM



------------------





RED

NOM

  

% Power Savings 1 Power Savings Factor–()100%×=

where the variables in the equations are:

•f

•V

•T

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

DDINTNOM

DDINTRED

NOM

RED

is the nominal internal supply voltage

is the reduced internal supply voltage

is the duration running at f

CCLKNOM

CCLKRED

VOLTAGE REGULATION

The ADSP-BF536/BF537 processor provides an on-chip voltage regulator that can generate processor core voltage levels (0.85V to 1.2V guaranteed from -5% to 10%) from an external 2.25 V to

3.6 V supply. Figure 6 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in Hibernate mode, V

can still be applied,

DDEXT

eliminating the need for external buffers. The voltage regulator can be activated from this power down state by assertion of the RESET

pin, which will then initiate a boot sequence. The regula-

tor can also be disabled and bypassed at the user’s discretion.

CLOCK SIGNALS

The ADSP-BF536/BF537 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF536/BF537 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 7. Capacitor values are dependent on crystal type and should be

Rev. PrD | Page 14 of 64 | January 2005

DDEXT

DDINT

OUT

100 µF

10 µH

0.1 µF

100 µF

1µF

1-0

NOTE: VR

OUT

AND DESIG NER SHOULD MINI MIZE TRACE LENGTH TO F DS9431A.

Figure 6. Voltage Regulator Circuit

ZHCS1000

EXTERNAL COMPONEN TS

1-0 S HOULD BE TIED TOGETHER EXTERNALLY

2.25V - 3.6V INPU T VOLTA GE RANGE

FDS9431A

specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.

CLKIN

CLKBUF

Figure 7. External Crystal Connections

PROCESSOR

CLKOUTXTAL

The CLKBUF pin is an output pin, and is a buffer version of the input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the ADSP-BF536/BF537 processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. Note that with the 300 MHz version ADSP-BF536, the XTAL max that can be applied is 30 MHz.

The Blackfin core is running at a different clock rate than the on-chip peripherals. As shown in Figure 8 on page 15, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence in the PLL_CTL register.

On-the-fly CCLK and SCLK frequency changes can be effected by simply writing to the PLL_DIV register. Whereas the maximum allowed CCLK and SCLK rates depend on the applied voltages V

DDINT

and V

, the VCO is always permitted to run

DDEXT

up to the frequency specified by the part’s speed grade. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It belongs to the SDRAM interface, but it functions as reference

ADSP-BF536/ADSP-BF537Preliminary Technical Data

signal in other timing specifications as well. While active by default, it can be disabled by the EBIU_SDGCTL and EBIU_AMGCTL registers.

DYNAMIC MODIFICATION

RE QUIRES PLL SEQ UENCING

CLKI N

PLL

.5x - 64 x

SCLK CC LK

SCLK 133MHZ

Figure 8. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios:

Table 6. Example System Clock Ratios

Signal Name SSEL3–0

Divider Ratio VCO/SCLK

0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50

Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Signal Name CSEL1–0

Divider Ratio VCO/CCLK

00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25

DYNAM IC MODIFICATIO N

ON-THE-FLY

+ 1 , 2, 4, 8

VCO

+ 1:15

CCLK

SCLK

Example Frequency Ratios (MHz)

VCO SCLK

. The SSEL value can be

SCLK

Example Frequency Ratios

VCO CCLK

Rev. PrD | Page 15 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

The maximum CCLK frequency not only depends on the part's speed grade (see page 64), it also depends on the applied V

DDINT

voltage. See Table 10 - Table 13 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied V

voltage (see Table 15).

DDEXT

BOOTING MODES

The ADSP-BF536/BF537 processor has six mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. A seventh mode is provided to execute from external memory, bypassing the boot sequence.

Table 8. Booting Modes

BMODE2–0 Description

000 Execute from 16-bit external memory

(Bypass Boot ROM)

001 Boot from 8-bit or 16-bit memory

(EPROM/flash) 010 Reserved 011 Boot from serial SPI memory (EEPROM/flash) 100 Boot from SPI host (slave mode) 101 Boot from serial TWI memory

(EEPROM/flash) 110 Boot from TWI host (slave mode) 111 Boot from UART host (slave mode)

The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software-initiated resets, implement the following modes:

• Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit and 16-bit external flash memory – The 8-bit or 16-bit flash boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank

0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). The boot ROM evaluates the first byte of the boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot is performed. A 0x60 byte is required for 16-bit boot.

• Boot from serial SPI memory (EEPROM or flash). Eight-, 16-, or 24-bit addressable devices are supported as well as AT45DB041, AT45DB081, and AT45DB161 data flash devices from Atmel. The SPI uses the PF10/SPI SSEL1 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable device is detected, and begins clocking data into the processor.

• Boot from SPI host device – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the boot ROM is busy, the Blackfin processor will assert a flag pin to signal the host device not to send any more bytes until the flag is de-asserted. The flag is chosen by the user and this information will be transferred to the Blackfin processor via bits 8:5 of the FLAG header.

• Boot from UART – Using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the Host. The Host agent selects a baud rate within the UART’s clocking capabilities. When performing the autobaud, the UART expects a “@” (boot stream) character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate. It then replies with an acknowledgement which is composed of 4 bytes: 0xBF, the value of UART_DLL, the value of UART_DLH, 0x00. The Host can then download the boot stream. When the processor needs to hold off the Host, it de-asserts CTS. Therefore, the Host must monitor this signal.

• Boot from serial TWI memory (EEPROM/flash) – The Blackfin processor operates in master mode and selects the TWI slave with the unique id 0xA0. It submits successive read commands to the memory device starting at two byte internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with Philips I

C Bus Specification version 2.1 and have the capability to auto-increment its internal address counter such that the contents of the memory device can be read sequentially.

• Boot from TWI Host – The TWI Host agent selects the slave with the unique id 0x5F. The processor replies with an acknowledgement and the Host can then download the boot stream. The TWI Host agent should comply with Philips I

C Bus Specification version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI.

For each of the boot modes, a 10-byte header is first brought in from an external device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM.

In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader can be added to provide additional booting mechanisms. This secondary loader could provide the capability to boot from flash, variable baud rate, and other sources. In all boot modes except Bypass, program execution starts from on-chip L1 memory address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to pro-

Rev. PrD | Page 16 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

vide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.

• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers.

• Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices web site under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.

DEVELOPMENT TOOLS

The ADSP-BF536/BF537 processor is supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF536/BF537 processor.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

Rev. PrD | Page 17 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF536/BF537 processor pin definitions are listed in

Table 9. In order to maintain maximum functionality and

reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics. Pins shown with an asterisk after their name (*) offer high source/high sink current capabilities.

All pins are tristated during and immediately after reset with the exception of the external memory interface. On the external memory interface, the control and address lines are driven high during reset unless the BR

pin is asserted.

All I/O pins have their input buffers disabled with the exception of the pins noted in the data sheet that need pullups or pulldowns if unused.

Table 9. Pin Descriptions

Pin Name I/O Function Driver Type

Memory Interface

ADDR19–1 O Address Bus for Async Access A DATA15–0 I/O Data Bus for Async/Sync Access A ABE1–0

/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A

BR BG BGH

Asynchronous Memory Control

AMS3–0 O Bank Select A ARDY I Hardware Ready Control AOE ARE AWE

Synchronous Memory Control

SRAS O Row Address Strobe A SCAS SWE SCKE O Clock Enable A CLKOUT O Clock Output B SA10 O A10 Pin A SMS

IBus Request OBus Grant A O Bus Grant Hang A

O Output Enable A ORead Enable A OWrite Enable A

O Column Address Strobe A OWrite Enable A

O Bank Select A

Rev. PrD | Page 18 of 64 | January 2005

ADSP-BF536/ADSP-BF537Preliminary Technical Data

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function Driver Type

Port F: GPIO/UART1–0/Timer7–0/SPI/External DMA Request (* = High Source/High Sink Pin)

PF0* - GPIO/UART0 TX/DMAR0 I/O GPIO/UART0 Transmit/DMA Request 0 C PF1* - GPIO/UART0 RX/DMAR1/TAC I1 I/O GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture C PF2* - GPIO/UART1 TX/TMR7 I/O GPIO/UART1 Transmit/Timer7 C PF3* - GPIO/UART1 RX/TMR6/TA CI6 I/O GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture C PF4* - GPIO/TMR5/SPI SSEL6 I/O GPIO/Timer5/SPI Slave Select Enable 6 C PF5* - GPIO/TMR4/SPI SSEL5 I/O GPIO/Timer4/SPI Slave Select Enable 5 C PF6* - GPIO/TMR3/SPI SSEL4 I/O GPIO/Timer3/SPI Slave Select Enable 4 C PF7* - GPIO/TMR2/PPI FS3 I/O GPIO/Timer2/PPI Frame Sync 3 C PF8 - GPIO/TMR1/PPI FS2 I/O GPIO/Timer1/PPI Frame Sync 2 D PF9 - GPIO/TMR0/PPI FS1 I/O GPIO/Timer0/PPI Frame Sync 1 D PF10 - GPIO/SPI SSEL1 I/O GPIO/SPI Slave Select Enable 1 D PF11 - GPIO/SPI MOSI I/O GPIO/SPI Master Out Slave In D PF12 - GPIO/SPI MISO PF13 - GPIO/SPI SCK I/O GPIO/SPI Clock D PF14 - GPIO/SPI SS/TACLK0 I/O GPIO/SPI Slave Select/Alternate Timer0 Clock Input D PF15 - GPIO/PPI CLK/TMRCLK I/O GPIO/PPI Clock/External Timer Reference D

Port G: GPIO/PPI/SPORT1

PG0 - GPIO/PPI D0 I/O GPIO/PPI Data 0 D PG1 - GPIO/PPI D1 I/O GPIO/PPI Data 1 D PG2 - GPIO/PPI D2 I/O GPIO/PPI Data 2 D PG3 - GPIO/PPI D3 I/O GPIO/PPI Data 3 D PG4 - GPIO/PPI D4 I/O GPIO/PPI Data 4 D PG5 - GPIO/PPI D5 I/O GPIO/PPI Data 5 D PG6 - GPIO/PPI D6 I/O GPIO/PPI Data 6 D PG7 - GPIO/PPI D7 I/O GPIO/PPI Data 7 D PG8 - GPIO/PPI D8/DR1SEC I/O GPIO/PPI Data 8/SPORT1 Receive Data Secondary D PG9 - GPIO/PPI D9/DT1SEC I/O GPIO/PPI Data 9/SPORT1 Transmit Data Secondary D PG10 - GPIO/PPI D10/RSCLK1 I/O GPIO/PPI Data 10/SPORT1 Receive Serial Clock D PG11 - GPIO/PPI D11/RFS1 I/O GPIO/PPI Data 11/SPORT1 Receive Frame Sync D PG12 - GPIO/PPI D12/DR1PRI I/O GPIO/PPI Data 12/SPORT1 Receive Data Primary D PG13 - GPIO/PPI D13/TSCLK1 I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock D PG14 - GPIO/PPI D14/TFS1 I/O GPIO/PPI Data 14/SPORT1 Transmit Frame Sync D PG15 - GPIO/PPI D15/DT1PR I I/O GPIO/PPI Data 15/SPORT1 Transmit Data Primary D

Port H: GPIO/10/100 Ethernet MAC

PH0 - GPIO/ETxD0 I/O GPIO/Ethernet MII or RMII Transmit D0 D PH1 - GPIO/ETxD1 I/O GPIO/Ethernet MII or RMII Transmit D1 D PH2 - GPIO/ETxD2 I/O GPIO/Ethernet MII Transmit D2 D PH3 - GPIO/ETxD3 I/O GPIO/Ethernet MII Transmit D3 D PH4 - GPIO/ETxEN I/O GPIO/Ethernet MII or RMII Transmit Enable D

I/O GPIO/SPI Master In Slave Out D

Rev. PrD | Page 19 of 64 | January 2005

ADSP-BF536/ADSP-BF537 Preliminary Technical Data

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function Driver Type

Port H: GPIO/10/100 Ethernet MAC, continued PH5 - GPIO/MII TxCLK/RMII REF_CLK I/O GPIO/Ethernet MII Transmit Clock/RMII Reference Clock D PH6 - GPIO/MII PHYINT/RMII MDINT I/O GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt D PH7 - GPIO/COL I/O GPIO/Ethernet Collision D PH8 - GPIO/ERxD0 I/O GPIO/Ethernet MII or RMII Receive D0 D PH9 - GPIO/ERxD1 I/O GPIO/Ethernet MII or RMII Receive D1 D PH10 - GPIO/ERxD2 I/O GPIO/Ethernet MII Receive D2 D PH11 - GPIO/ERxD3 I/O GPIO/Ethernet MII Receive D3 D PH12 - GPIO/ERxDV/TACLK5 I/O GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock D PH13 - GPIO/ERxCLK/TACLK6 I/O GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock D PH14 - GPIO/ERxER/TACLK7 I/O GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock D PH15 - GPIO/MII CRS/RMII CRS_DV I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive

Data Valid

Port J: SPORT0/TWI/SPI Select/CAN

PJ0 - MDC O Ethernet Management Channel Clock D PJ1 - MDIO I/O Ethernet Management Channel Serial Data D PJ2 - SCL I/O TWI Serial Clock D PJ3 - SDA I/O TWI Serial Data D PJ4 - DR0SEC/CANRX/TA CI 0 I SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input

Capture

PJ5 - DT0SEC/CANTX/SPI SSEL7 O SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select

Enable 7

PJ6 - RS CLK0/TACLK2 I/O SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input E PJ7 - RFS0/TACLK3 I/O SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input D PJ8 - DR0PRI/TACLK4 I SPORT0 Receive Data Primary/Alternate Timer4 Clock Input PJ9 - TS CLK0/TACLK1 I/O SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input E PJ10 - TFS0/SPI SSEL3 I/O SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3 D PJ11 - DT0PRI/SPI SSEL2 O SPORT0 Transmit Data Primary/SPI Slave Select Enable 2 D

Real Time Clock

RTXI

I RTC Crystal Input

RTXO O RTC Crystal Output

JTAG Port

TCK I JTAG Clock TDO O JTAG Serial Data Out D TDI I JTAG Serial Data In TMS I JTAG Mode Select

TRST EMU

IJTAG Reset O Emulation Output D

Clock

CLKIN I Clock/Crystal Input XTAL O Crystal Output CLKBUF O Buffered XTAL Output

Mode Controls

RESET NMI

I Reset I Non-maskable Interrupt

BMODE2–0 I Boot Mode Strap 2-0

Rev. PrD | Page 20 of 64 | January 2005

+ 44 hidden pages

Analog Devices ADSP BF536 7 prd Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PORTABLE LOW-POWER ARCHITECTURE

SYSTEM INTEGRATION

ADSP-BF536/BF537 PROCESSOR PERIPHERALS

BLACKFIN PROCESSOR CORE

MEMORY ARCHITECTURE

Internal (On-chip) Memory

External (Off-Chip) Memory

I/O Memory Space

Booting

Event Handling

Core Event Controller (CEC)

System Interrupt Controller (SIC)

Event Control

DMA CONTROLLERS

REAL-TIME CLOCK

WATCHDOG TIMER

TIMERS

SERIAL PORTS (SPORTS)

SERIAL PERIPHERAL INTERFACE (SPI) PORT

UART PORTS (UARTS)

CONTROLLER AREA NETWORK (CAN)

TWI CONTROLLER INTERFACE

10/100 ETHERNET MAC

PORTS

General-Purpose I/O (GPIO)

PARALLEL PERIPHERAL INTERFACE (PPI)

DYNAMIC POWER MANAGEMENT

Power Savings

VOLTAGE REGULATION

CLOCK SIGNALS

BOOTING MODES

INSTRUCTION SET DESCRIPTION

RELATED DOCUMENTS

DEVELOPMENT TOOLS

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)

PIN DESCRIPTIONS