ANALOG DEVICES ADSP-BF533 Service Manual

ADSP-BF533 Blackfin® Processor

Hardware Reference

(Includes ADSP-BF531 and ADSP-BF532 Blackfin Processors)

Revision 3.4, April 2009

Part Number

82-002005-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, the Blackfin logo, CrossCore, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

PREFACE

Purpose of This Manual .............................................................. xxxv

Intended Audience ...................................................................... xxxv

Manual Contents ....................................................................... xxxvi

What’s New in This Manual ....................................................... xxxix

Technical or Customer Support .................................................. xxxix

Supported Processors ....................................................................... xl

Product Information ....................................................................... xl

Analog Devices Web Site ........................................................... xl

VisualDSP++ Online Documentation ....................................... xli

Technical Library CD .............................................................. xlii

Notation Conventions .................................................................. xliii

INTRODUCTION

Peripherals .................................................................................... 1-1

Core Architecture .......................................................................... 1-3

ADSP-BF533 Blackfin Processor Hardware Reference iii

Contents

Memory Architecture .................................................................... 1-6

Internal Memory ..................................................................... 1-7

External Memory .................................................................... 1-7

I/O Memory Space .................................................................. 1-8

Event Handling ............................................................................ 1-8

Core Event Controller (CEC) .................................................. 1-9

System Interrupt Controller (SIC) ........................................... 1-9

DMA Support ............................................................................ 1-10

External Bus Interface Unit ......................................................... 1-11

PC133 SDRAM Controller ................................................... 1-11

Asynchronous Controller ...................................................... 1-11

Parallel Peripheral Interface ......................................................... 1-12

Serial Ports (SPORTs) ................................................................. 1-14

Serial Peripheral Interface (SPI) Port ........................................... 1-15

Timers ....................................................................................... 1-16

UART Port ................................................................................. 1-17

Real-Time Clock ........................................................................ 1-18

Watchdog Timer ......................................................................... 1-19

Programmable Flags .................................................................... 1-20

Clock Signals .............................................................................. 1-21

Dynamic Power Management ..................................................... 1-21

Full On Mode (Maximum Performance) ................................ 1-22

Active Mode (Moderate Power Savings) ................................. 1-22

Sleep Mode (High Power Savings) ......................................... 1-22

iv ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Deep Sleep Mode (Maximum Power Savings) ......................... 1-23

Hibernate State ..................................................................... 1-23

Voltage Regulation ...................................................................... 1-23

Boot Modes ................................................................................ 1-24

Instruction Set Description ......................................................... 1-25

Development Tools ..................................................................... 1-26

COMPUTATIONAL UNITS

Using Data Formats ...................................................................... 2-3

Binary String ........................................................................... 2-3

Unsigned ................................................................................. 2-4

Signed Numbers: Two’s-Complement ....................................... 2-4

Fractional Representation: 1.15 ................................................ 2-4

Data Register File .................................................................... 2-6

Accumulator Registers ............................................................. 2-6

Pointer Register File ................................................................ 2-7

DAG Register Set .................................................................... 2-7

Data Types .................................................................................. 2-11

Endianess .............................................................................. 2-13

ALU Data Types .................................................................... 2-13

Multiplier Data Types ............................................................ 2-14

Shifter Data Types ................................................................. 2-15

Arithmetic Formats Summary ................................................ 2-15

ADSP-BF533 Blackfin Processor Hardware Reference v

Contents

Using Multiplier Integer and Fractional Formats .................... 2-16

Rounding Multiplier Results ................................................. 2-18

Unbiased Rounding .......................................................... 2-19

Biased Rounding .............................................................. 2-20

Truncation ....................................................................... 2-22

Special Rounding Instructions ............................................... 2-23

Using Computational Status ....................................................... 2-23

ASTAT Register .......................................................................... 2-24

Arithmetic Logic Unit (ALU) ...................................................... 2-25

ALU Operations ................................................................... 2-25

Single 16-Bit Operations .................................................. 2-26

Dual 16-Bit Operations .................................................... 2-26

Quad 16-Bit Operations ................................................... 2-27

Single 32-Bit Operations .................................................. 2-28

Dual 32-Bit Operations .................................................... 2-28

ALU Instruction Summary .................................................... 2-29

ALU Data Flow Details ......................................................... 2-34

Dual 16-Bit Cross Options ............................................... 2-36

ALU Status Signals ........................................................... 2-36

ALU Division Support Features ............................................. 2-37

Special SIMD Video ALU Operations ................................... 2-37

vi ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Multiply Accumulators (Multipliers) ............................................ 2-38

Multiplier Operation ............................................................. 2-38

Placing Multiplier Results in Multiplier Accumulator

Registers ........................................................................ 2-39

Rounding or Saturating Multiplier Results ......................... 2-39

Saturating Multiplier Results on Overflow ............................. 2-40

Multiplier Instruction Summary ............................................ 2-40

Multiplier Instruction Options .......................................... 2-42

Multiplier Data Flow Details ................................................. 2-44

Multiply Without Accumulate ............................................... 2-47

Special 32-Bit Integer MAC Instruction ................................. 2-48

Dual MAC Operations .......................................................... 2-49

Barrel Shifter (Shifter) ................................................................. 2-51

Shifter Operations ................................................................. 2-51

Two-Operand Shifts .......................................................... 2-51

Immediate Shifts ........................................................... 2-52

Three-Operand Shifts ....................................................... 2-53

Immediate Shifts ........................................................... 2-53

Bit Test, Set, Clear, Toggle ................................................ 2-55

Field Extract and Field Deposit ......................................... 2-55

Shifter Instruction Summary .................................................. 2-55

ADSP-BF533 Blackfin Processor Hardware Reference vii

Contents

OPERATING MODES AND STATES

User Mode ................................................................................... 3-3

Protected Resources and Instructions ....................................... 3-4

Protected Memory .................................................................. 3-5

Entering User Mode ................................................................ 3-5

Example Code to Enter User Mode Upon Reset ................... 3-5

Return Instructions That Invoke User Mode ....................... 3-5

Supervisor Mode .......................................................................... 3-6

Non-OS Environments ........................................................... 3-7

Example Code for Supervisor Mode Coming Out of

Reset ............................................................................... 3-8

Emulation Mode .......................................................................... 3-9

Idle State ...................................................................................... 3-9

Example Code for Transition to Idle State .............................. 3-10

Reset State .................................................................................. 3-10

System Reset and Powerup .......................................................... 3-12

Hardware Reset ..................................................................... 3-13

SYSCR Register .................................................................... 3-14

Software Resets and Watchdog Timer .................................... 3-15

SWRST Register ................................................................... 3-15

Core-Only Software Reset ..................................................... 3-17

Core and System Reset .......................................................... 3-17

Booting Methods ........................................................................ 3-18

viii ADSP-BF533 Blackfin Processor Hardware Reference

Contents

PROGRAM SEQUENCER

Sequencer Related Registers ........................................................... 4-3

SEQSTAT Register .................................................................. 4-5

Zero-Overhead Loop Registers (LC, LT, and LB) ...................... 4-5

SYSCFG Register .................................................................... 4-6

Instruction Pipeline ...................................................................... 4-7

Branches and Sequencing ............................................................ 4-10

Direct Short and Long Jumps ................................................ 4-11

Direct Call ............................................................................ 4-11

Indirect Branch and Call ........................................................ 4-12

PC-Relative Indirect Branch and Call ..................................... 4-12

Condition Code Flag ............................................................. 4-13

Conditional Branches ........................................................ 4-14

Conditional Register Move ................................................ 4-14

Branch Prediction .................................................................. 4-14

Loops and Sequencing ................................................................. 4-16

Events and Sequencing ................................................................ 4-18

System Interrupt Processing ................................................... 4-22

System Peripheral Interrupts .................................................. 4-24

SIC_IWR Register ................................................................. 4-26

SIC_ISR Register .................................................................. 4-28

SIC_IMASK Register ............................................................ 4-29

System Interrupt Assignment Registers (SIC_IARx) ................ 4-30

ADSP-BF533 Blackfin Processor Hardware Reference ix

Contents

Core Event Controller Registers .................................................. 4-34

IMASK Register .................................................................... 4-34

ILAT Register ....................................................................... 4-35

IPEND Register .................................................................... 4-36

Global Enabling/Disabling of Interrupts ..................................... 4-37

Event Vector Table ...................................................................... 4-38

Emulation ............................................................................. 4-39

Reset .................................................................................... 4-39

NMI (Nonmaskable Interrupt) .............................................. 4-41

Exceptions ............................................................................ 4-41

Exceptions While Executing an Exception Handler ................ 4-46

Hardware Error Interrupt ........................................................... 4-47

Core Timer ........................................................................... 4-48

General-Purpose Interrupts (IVG7-IVG15) ............................ 4-49

Servicing Interrupts .................................................................... 4-49

Nesting of Interrupts .................................................................. 4-50

Non-Nested Interrupts .......................................................... 4-50

Nested Interrupts .................................................................. 4-51

Example Prolog Code for Nested Interrupt Service

Routine ......................................................................... 4-53

Example Epilog Code for Nested Interrupt Service

Routine ......................................................................... 4-53

Logging of Nested Interrupt Requests ............................... 4-54

x ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Exception Handling .............................................................. 4-55

Deferring Exception Processing ......................................... 4-55

Example Code for an Exception Handler ........................... 4-56

Example Code for an Exception Routine ........................... 4-58

Example Code for Using Hardware Loops in an ISR .......... 4-58

Additional Usability Issues ..................................................... 4-59

Executing RTX, RTN, or RTE in a Lower Priority

Event ............................................................................. 4-59

Allocating the System Stack ............................................... 4-60

Latency in Servicing Events ................................................... 4-60

DATA ADDRESS GENERATORS

Addressing With DAGs ................................................................. 5-4

Frame and Stack Pointers ......................................................... 5-5

Addressing Circular Buffers ..................................................... 5-6

Addressing With Bit-Reversed Addresses .................................. 5-9

Indexed Addressing With Index and Pointer Registers ............. 5-10

Auto-Increment and Auto-Decrement Addressing ................... 5-10

Pre-Modify Stack Pointer Addressing ..................................... 5-11

Indexed Addressing With Immediate Offset ........................... 5-12

Post-Modify Addressing ......................................................... 5-12

Modifying DAG and Pointer Registers ......................................... 5-13

Memory Address Alignment ........................................................ 5-13

DAG Instruction Summary ......................................................... 5-17

ADSP-BF533 Blackfin Processor Hardware Reference xi

Contents

MEMORY

Memory Architecture .................................................................... 6-1

Overview of Internal Memory ................................................. 6-5

Overview of Scratchpad Data SRAM ....................................... 6-7

L1 Instruction Memory ................................................................ 6-8

IMEM_CONTROL Register .................................................. 6-8

L1 Instruction SRAM ........................................................... 6-10

L1 Instruction Cache ............................................................ 6-12

Cache Lines ...................................................................... 6-14

Cache Hits and Misses .................................................. 6-16

Cache Line Fills ............................................................ 6-17

Line Fill Buffer ............................................................. 6-17

Cache Line Replacement ............................................... 6-17

Instruction Cache Management ........................................ 6-19

Instruction Cache Locking by Line ................................ 6-19

Instruction Cache Locking by Way ................................ 6-20

Instruction Cache Invalidation ...................................... 6-21

Instruction Test Registers ............................................................ 6-22

ITEST_COMMAND Register .............................................. 6-23

ITEST_DATA1 Register ....................................................... 6-24

ITEST_DATA0 Register ....................................................... 6-25

L1 Data Memory ........................................................................ 6-26

DMEM_CONTROL Register ............................................... 6-26

L1 Data SRAM ..................................................................... 6-29

xii ADSP-BF533 Blackfin Processor Hardware Reference

Contents

L1 Data Cache ...................................................................... 6-31

Example of Mapping Cacheable Address Space .................. 6-33

Data Cache Access ............................................................ 6-37

Cache Write Method ......................................................... 6-38

IPRIO Register and Write Buffer Depth ............................ 6-38

Data Cache Control Instructions ....................................... 6-40

Data Cache Invalidation .................................................... 6-40

Data Test Registers ...................................................................... 6-41

DTEST_COMMAND Register ............................................. 6-42

DTEST_DATA1 Register ...................................................... 6-44

DTEST_DATA0 Register ...................................................... 6-45

External Memory ........................................................................ 6-46

Memory Protection and Properties .............................................. 6-46

Memory Management Unit ................................................... 6-46

Memory Pages ....................................................................... 6-48

Memory Page Attributes .................................................... 6-48

Page Descriptor Table ............................................................ 6-50

CPLB Management ............................................................... 6-50

MMU Application ................................................................. 6-52

Examples of Protected Memory Regions ................................. 6-54

ICPLB_DATAx Registers ....................................................... 6-55

DCPLB_DATAx Registers ..................................................... 6-57

DCPLB_ADDRx Registers .................................................... 6-59

ICPLB_ADDRx Registers ...................................................... 6-60

ADSP-BF533 Blackfin Processor Hardware Reference xiii

Contents

DCPLB_STATUS and ICPLB_STATUS Registers ................. 6-61

DCPLB_FAULT_ADDR and ICPLB_FAULT_ADDR

Registers ............................................................................ 6-63

Memory Transaction Model ........................................................ 6-65

Load/Store Operation ................................................................. 6-66

Interlocked Pipeline .............................................................. 6-66

Ordering of Loads and Stores ................................................ 6-67

Synchronizing Instructions .................................................... 6-68

Speculative Load Execution ................................................... 6-69

Conditional Load Behavior ................................................... 6-70

Working With Memory .............................................................. 6-71

Alignment ............................................................................. 6-71

Cache Coherency .................................................................. 6-71

Atomic Operations ................................................................ 6-72

Memory-Mapped Registers .................................................... 6-73

Core MMR Programming Code Example .............................. 6-73

Terminology ............................................................................... 6-74

CHIP BUS HIERARCHY

Internal Interfaces ......................................................................... 7-1

Internal Clocks ............................................................................. 7-1

Core Overview ............................................................................. 7-2

System Overview .......................................................................... 7-4

xiv ADSP-BF533 Blackfin Processor Hardware Reference

Contents

System Interfaces .......................................................................... 7-4

Peripheral Access Bus (PAB) ..................................................... 7-5

PAB Arbitration .................................................................. 7-5

PAB Performance ................................................................ 7-5

PAB Agents (Masters, Slaves) ............................................... 7-6

DMA Access Bus (DAB), DMA Core Bus (DCB), DMA

External Bus (DEB) .............................................................. 7-7

DAB Arbitration ................................................................. 7-7

DAB, DCB, and DEB Performance ..................................... 7-8

DAB Bus Agents (Masters) .................................................. 7-9

External Access Bus (EAB) ....................................................... 7-9

Arbitration of the External Bus .............................................. 7-10

DEB/EAB Performance ......................................................... 7-10

DYNAMIC POWER MANAGEMENT

Clocking ....................................................................................... 8-1

Phase Locked Loop and Clock Control .................................... 8-2

PLL Overview ..................................................................... 8-3

PLL Clock Multiplier Ratios .................................................... 8-3

Core Clock/System Clock Ratio Control ............................. 8-5

PLL Registers .......................................................................... 8-6

PLL_DIV Register .............................................................. 8-7

PLL_CTL Register .............................................................. 8-7

PLL_STAT Register .......................................................... 8-10

PLL_LOCKCNT Register ................................................. 8-11

ADSP-BF533 Blackfin Processor Hardware Reference xv

Contents

Dynamic Power Management Controller ..................................... 8-12

Operating Modes .................................................................. 8-13

Dynamic Power Management Controller States ...................... 8-13

Full On Mode .................................................................. 8-14

Active Mode ..................................................................... 8-14

Sleep Mode ...................................................................... 8-14

Deep Sleep Mode ............................................................. 8-15

Hibernate State ................................................................. 8-16

Operating Mode Transitions .................................................. 8-16

Programming Operating Mode Transitions ........................ 8-19

PLL Programming Sequence ......................................... 8-20

PLL Programming Sequence Continues ......................... 8-22

Examples ...................................................................... 8-22

Dynamic Supply Voltage Control .......................................... 8-24

Power Supply Management ................................................... 8-25

VR_CTL Register ............................................................. 8-26

Changing Voltage ............................................................. 8-29

Powering Down the Core (Hibernate State) ....................... 8-29

DIRECT MEMORY ACCESS

DMA and Memory DMA Registers ............................................... 9-3

Naming Conventions for DMA MMRs ................................... 9-5

Naming Conventions for Memory DMA Registers ................... 9-7

DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR

xvi ADSP-BF533 Blackfin Processor Hardware Reference

Contents

DMAx_START_ADDR/MDMA_yy_START_ADDR

DMAx_CONFIG/MDMA_yy_CONFIG Register ................. 9-12

DMAx_X_COUNT/MDMA_yy_X_COUNT Register .......... 9-16

DMAx_X_MODIFY/MDMA_yy_X_MODIFY Register ........ 9-17

DMAx_Y_COUNT/MDMA_yy_Y_COUNT Register .......... 9-19

DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY Register ........ 9-20

DMAx_CURR_DESC_PTR/MDMA_yy_CURR_DESC_PTR

DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR

DMAx_CURR_X_COUNT/MDMA_yy_CURR_X_COUNT

DMAx_CURR_Y_COUNT/MDMA_yy_CURR_Y_COUNT

DMAx_PERIPHERAL_MAP/MDMA_yy_PERIPHERAL_MAP

DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS

Flex Descriptor Structure ............................................................ 9-35

DMA Operation Flow ................................................................. 9-37

DMA Startup ........................................................................ 9-39

DMA Refresh ........................................................................ 9-41

To Stop DMA Transfers ......................................................... 9-43

To Trigger DMA Transfers ..................................................... 9-44

ADSP-BF533 Blackfin Processor Hardware Reference xvii

Contents

Two-Dimensional DMA ............................................................. 9-45

Examples .............................................................................. 9-46

More 2D DMA Examples ..................................................... 9-47

Memory DMA ........................................................................... 9-48

MDMA Bandwidth ............................................................... 9-50

DMA Performance Optimization ................................................ 9-50

Prioritization and Traffic Control .......................................... 9-52

DMA_TC_PER and DMA_TC_CNT Registers ................ 9-55

MDMA Priority and Scheduling ............................................ 9-57

Urgent DMA Transfers .......................................................... 9-59

Software Management of DMA ................................................... 9-60

Synchronization of Software and DMA .................................. 9-61

Single-Buffer DMA Transfers ............................................ 9-63

Continuous Transfers Using Autobuffering ........................ 9-64

Descriptor Structures ........................................................ 9-65

Descriptor Queue Management ........................................ 9-67

Descriptor Queue Using Interrupts on Every

Descriptor ................................................................. 9-67

Descriptor Queue Using Minimal Interrupts ................. 9-69

DMA Errors (Aborts) ................................................................. 9-71

SPI COMPATIBLE PORT CONTROLLERS

Interface Signals ......................................................................... 10-4

Serial Peripheral Interface Clock Signal (SCK) ....................... 10-4

Serial Peripheral Interface Slave Select Input Signal ................ 10-4

xviii ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Master Out Slave In (MOSI) ................................................. 10-5

Master In Slave Out (MISO) ................................................. 10-5

Interrupt Output ................................................................... 10-6

SPI Registers ............................................................................... 10-7

SPI_BAUD Register .............................................................. 10-7

SPI_CTL Register ................................................................. 10-8

SPI_FLG Register ................................................................ 10-11

Slave Select Inputs .......................................................... 10-13

Use of FLS Bits in SPI_FLG for Multiple Slave

SPI Systems .................................................................. 10-14

SPI_STAT Register .............................................................. 10-15

SPI_TDBR Register ............................................................ 10-17

SPI_RDBR Register ............................................................ 10-18

SPI_SHADOW Register ...................................................... 10-18

SPI Transfer Formats ................................................................. 10-20

SPI General Operation .............................................................. 10-22

Clock Signals ...................................................................... 10-23

Master Mode Operation ...................................................... 10-24

Transfer Initiation From Master (Transfer Modes) ................ 10-25

Slave Mode Operation ......................................................... 10-26

Slave Ready for a Transfer .................................................... 10-27

Error Signals and Flags .............................................................. 10-28

Mode Fault Error (MODF) ................................................. 10-28

Transmission Error (TXE) ................................................... 10-29

ADSP-BF533 Blackfin Processor Hardware Reference xix

Contents

Reception Error (RBSY) ...................................................... 10-29

Transmit Collision Error (TXCOL) ..................................... 10-29

Beginning and Ending an SPI Transfer ...................................... 10-30

DMA ....................................................................................... 10-32

DMA Functionality ............................................................ 10-32

Master Mode DMA Operation ............................................ 10-33

Slave Mode DMA Operation ............................................... 10-35

Timing ..................................................................................... 10-38

PARALLEL PERIPHERAL INTERFACE

PPI Registers .............................................................................. 11-2

PPI_CONTROL Register ..................................................... 11-3

PPI_STATUS Register .......................................................... 11-8

PPI_DELAY Register .......................................................... 11-10

PPI_COUNT Register ........................................................ 11-11

PPI_FRAME Register ......................................................... 11-12

ITU-R 656 Modes .................................................................... 11-13

ITU-R 656 Background ...................................................... 11-13

ITU-R 656 Input Modes ..................................................... 11-17

Entire Field .................................................................... 11-18

Active Video Only .......................................................... 11-18

Vertical Blanking Interval (VBI) Only ............................. 11-18

ITU-R 656 Output Mode ................................................... 11-19

Frame Synchronization in ITU-R 656 Modes ...................... 11-20

xx ADSP-BF533 Blackfin Processor Hardware Reference

Contents

General-Purpose PPI Modes ...................................................... 11-20

Data Input (RX) Modes ....................................................... 11-23

No Frame Syncs .............................................................. 11-24

1, 2, or 3 External Frame Syncs ....................................... 11-24

2 or 3 Internal Frame Syncs ............................................. 11-25

Data Output (TX) Modes .................................................... 11-26

No Frame Syncs .............................................................. 11-26

1 or 2 External Frame Syncs ............................................ 11-27

1, 2, or 3 Internal Frame Syncs ........................................ 11-28

Frame Synchronization in GP Modes ................................... 11-28

Modes with Internal Frame Syncs .................................... 11-29

Modes with External Frame Syncs ................................... 11-30

DMA Operation ....................................................................... 11-31

Data Transfer Scenarios ............................................................. 11-32

SERIAL PORT CONTROLLERS

SPORT Operation ...................................................................... 12-8

SPORT Disable .......................................................................... 12-9

Setting SPORT Modes .............................................................. 12-10

SPORTx_TCR1 and SPORTx_TCR2 Registers ......................... 12-11

SPORTx_RCR1 and SPORTx_RCR2 Registers ......................... 12-16

Data Word Formats ................................................................... 12-21

SPORTx_TX Register ............................................................... 12-22

SPORTx_RX Register ............................................................... 12-24

ADSP-BF533 Blackfin Processor Hardware Reference xxi

Contents

SPORTx_STAT Register ........................................................... 12-27

SPORT RX, TX, and Error Interrupts ................................. 12-28

PAB Errors .......................................................................... 12-29

SPORTx_TCLKDIV and SPORTx_RCLKDIV Registers .......... 12-29

SPORTx_TFSDIV and SPORTx_RFSDIV Register .................. 12-30

Clock and Frame Sync Frequencies ........................................... 12-31

Maximum Clock Rate Restrictions ...................................... 12-32

Frame Sync and Clock Example ...................................... 12-33

Word Length ............................................................................ 12-33

Bit Order ................................................................................. 12-34

Data Type ................................................................................ 12-34

Companding ............................................................................ 12-35

Clock Signal Options ................................................................ 12-35

Frame Sync Options ................................................................. 12-36

Framed Versus Unframed .................................................... 12-36

Internal Versus External Frame Syncs ................................... 12-38

Active Low Versus Active High Frame Syncs ........................ 12-39

Sampling Edge for Data and Frame Syncs ............................ 12-39

Early Versus Late Frame Syncs (Normal Versus Alternate

Timing) ........................................................................... 12-41

Data Independent Transmit Frame Sync .............................. 12-43

Moving Data Between SPORTs and Memory ............................ 12-44

Stereo Serial Operation ............................................................. 12-44

xxii ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Multichannel Operation ............................................................ 12-49

SPORTx_MCMCn Registers ............................................... 12-51

Multichannel Enable ........................................................... 12-52

Frame Syncs in Multichannel Mode ..................................... 12-53

The Multichannel Frame ..................................................... 12-55

Multichannel Frame Delay ................................................... 12-56

Window Size ....................................................................... 12-56

Window Offset .................................................................... 12-57

SPORTx_CHNL Register .................................................... 12-57

Other Multichannel Fields in SPORTx_MCMC2 ................ 12-58

Channel Selection Register .................................................. 12-58

SPORTx_MRCSn Registers ............................................ 12-60

SPORTx_MTCSn Registers ............................................ 12-62

Multichannel DMA Data Packing ........................................ 12-64

Support for H.100 Standard Protocol ........................................ 12-65

2X Clock Recovery Control ................................................. 12-65

SPORT Pin/Line Terminations .................................................. 12-66

Timing Examples ...................................................................... 12-66

UART PORT CONTROLLER

Serial Communications ............................................................... 13-2

UART Control and Status Registers ............................................. 13-3

UART_LCR Register ............................................................. 13-3

UART_MCR Register ........................................................... 13-4

UART_LSR Register ............................................................. 13-5

ADSP-BF533 Blackfin Processor Hardware Reference xxiii

Contents

UART_THR Register ........................................................... 13-6

UART_RBR Register ............................................................ 13-7

UART_IER Register ............................................................. 13-8

UART_IIR Register ............................................................ 13-10

UART_DLL and UART_DLH Registers ............................. 13-11

UART_SCR Register .......................................................... 13-13

UART_GCTL Register ....................................................... 13-14

Non-DMA Mode ..................................................................... 13-15

DMA Mode ............................................................................. 13-16

Mixing Modes .......................................................................... 13-17

IrDA Support ........................................................................... 13-17

IrDA Transmitter Description ............................................. 13-18

IrDA Receiver Description .................................................. 13-19

PROGRAMMABLE FLAGS

Programmable Flag Registers (MMRs) ........................................ 14-5

FIO_DIR Register ................................................................ 14-5

Flag Value Registers Overview ............................................... 14-6

FIO_FLAG_D Register ......................................................... 14-8

FIO_FLAG_S, FIO_FLAG_C, and FIO_FLAG_T

Registers ............................................................................ 14-8

FIO_MASKA_D, FIO_MASKA_C, FIO_MASKA_S,

FIO_MASKA_T, FIO_MASKB_D, FIO_MASKB_C,

FIO_MASKB_S, FIO_MASKB_T Registers ..................... 14-11

Flag Interrupt Generation Flow ....................................... 14-12

xxiv ADSP-BF533 Blackfin Processor Hardware Reference

Contents

FIO_MASKA_D, FIO_MASKA_C, FIO_MASKA_S,

FIO_MASKA_T Registers ............................................ 14-14

FIO_MASKB_D, FIO_MASKB_C, FIO_MASKB_S,

FIO_MASKB_T Registers ............................................ 14-16

FIO_POLAR Register ......................................................... 14-18

FIO_EDGE Register ........................................................... 14-18

FIO_BOTH Register ........................................................... 14-20

FIO_INEN Register ............................................................ 14-21

Performance/Throughput .......................................................... 14-21

TIMERS

General-Purpose Timers .............................................................. 15-1

Timer Registers ........................................................................... 15-3

TIMER_ENABLE Register .................................................... 15-4

TIMER_DISABLE Register ................................................... 15-5

TIMER_STATUS Register .................................................... 15-6

TIMERx_CONFIG Registers ................................................ 15-8

TIMERx_COUNTER Registers ............................................ 15-9

TIMERx_PERIOD and TIMERx_WIDTH Registers .......... 15-10

Using the Timer ........................................................................ 15-13

Pulse Width Modulation (PWM_OUT) Mode ..................... 15-15

Output Pad Disable ........................................................ 15-17

Single Pulse Generation ................................................... 15-17

Pulse Width Modulation Waveform Generation ............... 15-18

Stopping the Timer in PWM_OUT Mode ....................... 15-19

ADSP-BF533 Blackfin Processor Hardware Reference xxv

Contents

Externally Clocked PWM_OUT ..................................... 15-20

PULSE_HI Toggle Mode ................................................ 15-21

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 15-26

Autobaud Mode ............................................................. 15-34

External Event (EXT_CLK) Mode ....................................... 15-36

Using the Timers With the PPI ........................................... 15-37

Interrupts ........................................................................... 15-38

Illegal States ........................................................................ 15-40

Summary ............................................................................ 15-43

Core Timer .............................................................................. 15-45

TCNTL Register ................................................................. 15-46

TCOUNT Register ............................................................. 15-48

TPERIOD Register ............................................................. 15-48

TSCALE Register ................................................................ 15-49

Watchdog Timer ....................................................................... 15-50

Watchdog Timer Operation ................................................. 15-50

WDOG_CNT Register ....................................................... 15-50

WDOG_STAT Register ...................................................... 15-51

WDOG_CTL Register ........................................................ 15-53

REAL-TIME CLOCK

Interfaces .................................................................................... 16-2

RTC Clock Requirements ........................................................... 16-2

xxvi ADSP-BF533 Blackfin Processor Hardware Reference

Contents

RTC Programming Model ........................................................... 16-4

Write Latency ........................................................................ 16-6

Deep Sleep ............................................................................ 16-7

Prescaler Enable ..................................................................... 16-8

Event Flags ............................................................................ 16-8

Interrupts ............................................................................ 16-11

RTC_STAT Register ................................................................. 16-13

RTC_ICTL Register ................................................................. 16-13

RTC_ISTAT Register ................................................................ 16-15

RTC_SWCNT Register ............................................................ 16-15

RTC_ALARM Register ............................................................. 16-17

RTC_PREN Register ................................................................ 16-18

State Transitions Summary ........................................................ 16-20

EXTERNAL BUS INTERFACE UNIT

Overview .................................................................................... 17-1

Block Diagram ...................................................................... 17-4

Internal Memory Interfaces .................................................... 17-5

External Memory Interfaces ................................................... 17-6

EBIU Programming Model .................................................... 17-8

Error Detection ..................................................................... 17-9

ADSP-BF533 Blackfin Processor Hardware Reference xxvii

Contents

Asynchronous Memory Interface ................................................. 17-9

Asynchronous Memory Address Decode .............................. 17-10

EBIU_AMGCTL Register ................................................... 17-10

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............. 17-12

Avoiding Bus Contention .................................................... 17-15

ARDY Input Control ...................................................... 17-15

Programmable Timing Characteristics ................................. 17-16

Asynchronous Accesses by Core Instructions ................... 17-16

Asynchronous Reads ................................................... 17-17

Asynchronous Writes .................................................. 17-19

Adding Additional Wait States ........................................ 17-20

Byte Enables ................................................................... 17-22

SDRAM Controller (SDC) ....................................................... 17-22

Definition of Terms ............................................................ 17-23

Bank Activate Command ................................................ 17-23

Burst Length .................................................................. 17-24

Burst Stop Command ..................................................... 17-24

Burst Type ...................................................................... 17-24

CAS Latency (CL) .......................................................... 17-25

CBR (CAS Before RAS) Refresh or Auto-Refresh ............. 17-25

DQM Pin Mask Function ............................................... 17-25

Internal Bank ................................................................. 17-26

Mode Register ................................................................ 17-26

Page Size ........................................................................ 17-27

xxviii ADSP-BF533 Blackfin Processor Hardware Reference

Contents

Precharge Command ....................................................... 17-27

SDRAM Bank ................................................................. 17-27

Self-Refresh .................................................................... 17-27

................................................................................ 17-28

RAS

................................................................................. 17-28

............................................................................... 17-28

RCD

............................................................................... 17-28

RFC

tRP .................................................................................. 17-29

............................................................................... 17-29

RRD

................................................................................. 17-29

................................................................................ 17-29

XSR

SDRAM Configurations Supported ..................................... 17-30

Example SDRAM System Block Diagrams ........................... 17-30

Executing a Parallel Refresh Command ............................ 17-31

EBIU_SDGCTL Register .................................................... 17-32

Setting the SDRAM Clock Enable (SCTLE) .................... 17-37

Entering and Exiting Self-Refresh Mode (SRFS) .............. 17-37

Setting the SDRAM Buffering Timing Option

(EBUFE) ..................................................................... 17-39

Selecting the CAS Latency Value (CL) ............................. 17-39

Selecting the Bank Activate Command Delay (TRAS) ...... 17-40

Selecting the RAS to CAS Delay (TRCD) ........................ 17-41

Selecting the Precharge Delay (TRP) ............................... 17-42

Selecting the Write to Precharge Delay (TWR) ................ 17-43

ADSP-BF533 Blackfin Processor Hardware Reference xxix

Contents

EBIU_SDBCTL Register .................................................... 17-44

EBIU_SDSTAT Register ..................................................... 17-46

EBIU_SDRRC Register ...................................................... 17-47

SDRAM External Memory Size ........................................... 17-50

SDRAM Address Mapping .................................................. 17-50

16-Bit Wide SDRAM Address Muxing ............................ 17-51

Data Mask (SDQM[1:0]) Encodings ................................... 17-52

SDC Operation .................................................................. 17-52

SDC Configuration ............................................................ 17-53

SDC Commands ................................................................. 17-55

Precharge Commands ..................................................... 17-56

Bank Activate Command ................................................ 17-57

Load Mode Register Command ....................................... 17-57

Read/Write Command .................................................... 17-58

Auto-Refresh Command ................................................. 17-59

Self-Refresh Command ................................................... 17-59

No Operation/Command Inhibit Commands .................. 17-60

SDRAM Timing Specifications ............................................ 17-60

SDRAM Performance ......................................................... 17-61

Bus Request and Grant ............................................................. 17-62

Operation ........................................................................... 17-62

xxx ADSP-BF533 Blackfin Processor Hardware Reference

+ 856 hidden pages

ANALOG DEVICES ADSP-BF533 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS