ANALOG DEVICES ADSP-BF531, ADSP-BF532, ADSP-BF533 Service Manual

Blackfin

UART

SPORT0-1

WATCHDOG

TIMER

RTC

SPI

TIMER0-2

PPI

GPIO

PORT

EXTERNAL PORT

FLASH, SDRAM CONTROL

BOOT ROM

JTAG TEST AND EMULATION

VOLTAGE REGULATOR

DMA

CONTROLLER

INSTRUCTION

MEMORY

DATA

MEMORY

DMA CORE BUS

DMA

EXTERN AL

BUS

EXTERNAL ACCESS BUS

INTERRUPT

CONTROLLER

Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Wide range of operating voltages (see Operating Conditions

on Page 21)

Qualified for Automotive Applications (see Automotive Prod-

ucts on Page 63)

Programmable on-chip voltage regulator 160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP

packages

MEMORY

Up to 148K bytes of on-chip memory (see Table 1 on Page 3) Memory management unit providing memory protection External memory controller with glueless support for

SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and

external memory

PERIPHERALS

Parallel peripheral interface PPI, supporting

ITU-R 656 video data formats

2 dual-channel, full duplex synchronous serial ports, sup-

porting eight stereo I 2 memory-to-memory DMAs 8 peripheral DMAs SPI-compatible port Three 32-bit timer/counters with PWM support Real-time clock and watchdog timer 32-bit core timer Up to 16 general-purpose I/O pins (GPIO) UART with support for IrDA Event handler Debug/JTAG interface On-chip PLL capable of frequency multiplication

S channels

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Functional Block Diagram

ADSP-BF531/ADSP-BF532/ADSP-BF533

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 4

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 8

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ....................... 10

UART Port ........................................................ 10

General-Purpose I/O Port F ................................... 10

Parallel Peripheral Interface ................................... 11

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 13

Clock Signals ..................................................... 13

Booting Modes ................................................... 14

Instruction Set Description ................................... 15

Development Tools ............................................. 15

Designing an Emulator-Compatible Processor Board .. 16

Related Documents .............................................. 17

Related Signal Chains ........................................... 17

Pin Descriptions .................................................... 18

Specifications ........................................................ 21

Operating Conditions ........................................... 21

Electrical Characteristics ....................................... 23

Absolute Maximum Ratings ................................... 26

ESD Sensitivity ................................................... 26

Package Information ............................................ 27

Timing Specifications ........................................... 28

Output Drive Currents ......................................... 44

Test Conditions .................................................. 46

Thermal Characteristics ........................................ 50

160-Ball CSP_BGA Ball Assignment .. ......................... 51

169-Ball PBGA Ball Assignment . . . .............................. 54

176-Lead LQFP Pinout ............................................ 57

Outline Dimensions ................................................ 59

Surface-Mount Design .......................................... 62

Automotive Products .............................................. 63

Ordering Guide ..................................................... 64

REVISION HISTORY

1/11— Rev. G to Rev. H

Corrected all document errata.

Replaced Figure 7, Voltage Regulator Circuit ................ 13

Removed footnote 4 from V

ditions ................................................................. 21

Changed Internal (Core) Supply Voltage (V

Absolute Maximum Ratings ..................................... 26,

Replaced Figure 13, Asynchronous Memory Read Cycle Tim-

ing ..................................................................... 29

Replaced Figure 14, Asynchronous Memory Write Cycle Tim-

ing ..................................................................... 30

Replaced Figure 16, External Port Bus Request and Grant Cycle

Timing ................................................................ 32

To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processor’s product page on the www.analog.com website and use the View PCN link.

specifications in Operating Con-

) range in

DDINT

Rev. H | Page 2 of 64 | January 2011

GENERAL DESCRIPTION

ADSP-BF531/ADSP-BF532/ADSP-BF533

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are members of the Blackfin

family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.

Table 1. Processor Comparison

Features

SPORTs 2 2 2 UART 1 1 1 SPI 1 1 1 GP Timers 3 3 3 Watchdog Timers 1 1 1 RTC 1 1 1 Parallel Peripheral Interface 1 1 1 GPIOs 16 16 16

L1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes L1 Instruction SRAM 16K bytes 32K bytes 64K bytes L1 Data SRAM/Cache 16K bytes 32K bytes 32K bytes L1 Data SRAM 32K bytes L1 Scratchpad 4K bytes 4K bytes 4K bytes L3 Boot ROM 1K bytes 1K bytes 1K bytes

Memory Configuration Maximum Speed Grade 400 MHz 400 MHz 600 MHz Package Options:

CSP_BGA Plastic BGA LQFP

ADSP-BF531

160-Ball 169-Ball 176-Lead

ADSP-BF532

160-Ball 169-Ball 176-Lead

ADSP-BF533

160-Ball 169-Ball 176-Lead

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management—the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

PROCESSOR PERIPHERALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the functional block diagram in Figure 1 on Page 1). The generalpurpose peripherals include functions such as UART, timers with PWM (pulse-width modulation) and pulse measurement capability, general-purpose I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these generalpurpose peripherals, the processors contain high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, real-time clock, and timers, are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor’s various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.

The processors include an on-chip voltage regulator in support of the processor’s dynamic power management capability. The voltage regulator provides a range of core voltage levels from V

. The voltage regulator can be bypassed at the user’s

DDEXT

discretion.

Rev. H | Page 3 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 2 ration and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). Quad 16-bit operations are possible using the second ALU.

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.

multiply, divide primitives, satu-

In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.

The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3, Figure 4, and Figure 5 on Page 6.

The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory.

The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.

Internal (On-Chip) Memory

The processors have three blocks of on-chip memory that provide high bandwidth access to the core.

The first block is the L1 instruction memory, consisting of up to 80K bytes SRAM, of which 16K bytes can be configured as a four way set-associative cache. This memory is accessed at full processor speed.

Rev. H | Page 4 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

8888

40 40

A0 A1

BARREL SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

AS TAT

40 40

32 32 32LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

SP FP

P4 P3

DA1

DA0

PREG

RAB

TO MEMORY

Figure 2. Blackfin Processor Core

The second on-chip memory block is the L1 data memory, consisting of one or two banks of up to 32K bytes. The memory banks are configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the external bus interface unit (EBIU). This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance.

The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one containing the control MMRs for all core functions, and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.

Booting

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors contain a small boot kernel, which configures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Boot-

ing Modes on Page 14.

Rev. H | Page 5 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

SYSTEM MMR REGISTER S (2M BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

INSTRUCTION SRAM/CACHE (16K BYTE)

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA0 8000

0xFF90 8000

0xFF90 4000

0xFF80 80

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

0xFFA1 0000

INSTRUCTION SRAM (16K BYTE)

RESERVED

0xFFA0 C000

RESERVED

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

ASYNCMEMORYBANK3(1MBYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

INSTRUCTION SRAM/CACHE (16K BYTE)

0xFFFF FFFF

0xFFE0 0000

0xFFB0 00 00

0xFFA1 40 00

0xFFA0 80 00

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 00 00

0xFFB0 10 00

0xFFA0 00 00

RESERVED

0xFFA1 00 00

INSTRUCTION SRAM (32K BYTE)

RESERVED

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION SRAM (64K BYTE)

SYSTEM MMR REGISTERS (2M BYT E)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

DATA BANK A SRAM/CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE TO 128M BY TE)

INSTRUCTION SRAM/CACHE (16K BYTE)

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

DATA BANK A SRAM (16K BYTE)

0xFF90 0000

0xFF80 0000

RESERVED

Figure 3. ADSP-BF531 Internal/External Memory Map

Figure 4. ADSP-BF532 Internal/External Memory Map

Event Handling

The event controller on the processors handle all asynchronous and synchronous events to the processor. The ADSP-BF531/ ADSP-BF532/ADSP-BF533 processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events:

• Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface.

• Reset – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.

• Exceptions – Events that occur synchronously to program flow (i.e., the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program

Rev. H | Page 6 of 64 | January 2011

flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction.

Figure 5. ADSP-BF533 Internal/External Memory Map

ADSP-BF531/ADSP-BF532/ADSP-BF533

Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors’ event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15– 7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities.

Table 2. Core Event Controller (CEC)

Priority (0 is Highest) Event Class EVT Entry

0Emulation/Test ControlEMU 1Reset RST 2 Nonmaskable Interrupt NMI 3ExceptionEVX 4Reserved 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SIC and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event Default Mapping

PLL Wakeup IVG7 DMA Error IVG7 PPI Error IVG7 SPORT 0 Error IVG7 SPORT 1 Error IVG7 SPI Error IVG7 UART Error IVG7 Real-Time Clock IVG8 DMA Channel 0 (PPI) IVG8 DMA Channel 1 (SPORT 0 Receive) IVG9 DMA Channel 2 (SPORT 0 Transmit) IVG9 DMA Channel 3 (SPORT 1 Receive) IVG9 DMA Channel 4 (SPORT 1 Transmit) IVG9 DMA Channel 5 (SPI) IVG10 DMA Channel 6 (UART Receive) IVG10 DMA Channel 7 (UART Transmit) IVG10 Timer 0 IVG11 Timer 1 IVG11 Timer 2 IVG11 Port F GPIO Interrupt A IVG12 Port F GPIO Interrupt B IVG12 Memory DMA Stream 0 IVG13 Memory DMA Stream 1 IVG13 Software Watchdog Timer IVG13

Event Control

The processors provide a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 32 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it can also be written to clear (cancel) latched events. This register can be read while in supervisor mode and can only be written while in supervisor mode when the corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register can be read or written while in supervisor mode. Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.

Rev. H | Page 7 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

• CEC interrupt pending register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but can be read while in supervisor mode.

The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3.

• SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in this register, that peripheral event is unmasked and is processed by the system when asserted. A cleared bit in this register masks the peripheral event, preventing the processor from servicing the event.

• SIC interrupt status register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.

• SIC interrupt wakeup enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. See Dynamic

Power Management on Page 11.

Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general-purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable

peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.

The DMA controller supports both 1-dimensional (1-D) and 2dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly.

Examples of DMA types supported by the DMA controller include:

• A single, linear buffer that stops upon completion

• A circular, autorefreshing buffer that interrupts on each full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are two pairs of memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.

REAL-TIME CLOCK

The processor real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hour counter, and a 32,768 day counter.

When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. The two alarms are time of day and a day and time of that day.

Rev. H | Page 8 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

RTXO

C1 C2

SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

RTXI

The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.

Like other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state.

Connect RTC pins RTXI and RTXO with external components as shown in Figure 6.

Figure 6. External Components for RTC

WATCHDOG TIMER

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency of f

SCLK

TIMERS

There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. Three timers have an external pin that can be configured either as a pulse-width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin (TACLK), an external clock input to the PPI_CLK pin (TMRCLK), or to the internal SCLK.

The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel.

The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.

In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTs)

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:

•I

S capable operation.

• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels

of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f

• Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync.

• Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

• DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

Rev. H | Page 9 of 64 | January 2011

/131,070) Hz to (f

SCLK

/2) Hz.

ADSP-BF531/ADSP-BF532/ADSP-BF533

SPI Clock Rate

SCLK

2 SPI_BAUD

------------------------------------

UART Clock Rate

SCLK

16 UART_Divisor

-----------------------------------------------

• Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA.

• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

An additional 250 mV of SPORT input hysteresis can be enabled by setting Bit 15 of the PLL_CTL register. When this bit is set, all SPORT input pins have the increased hysteresis.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS sor, and seven SPI chip select output pins (SPISEL7–1

) lets other SPI devices select the proces-

) let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface which supports both master/slave modes and multimaster environments.

The baud rate and clock phase/polarities for the SPI port are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI DMA controller can only service unidirectional accesses at any given time.

The SPI port clock rate is calculated as:

where the 16-bit SPI_BAUD register contains a value of 2 to 65,535.

During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.

UART PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors provide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable.

The UART programmable features include:

• Supporting bit rates ranging from (f second to (f

/16) bits per second.

SCLK

/1,048,576) bits per

SCLK

• Supporting data formats from seven bits to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

where the 16-bit UART_Divisor comes from the UART_DLH register (most significant 8 bits) and UART_DLL register (least significant 8 bits).

In conjunction with the general-purpose timer functions, autobaud detection is supported.

The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA

) serial infrared physi-

cal layer link specification (SIR) protocol.

GENERAL-PURPOSE I/O PORT F

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have 16 bidirectional, general-purpose I/O pins on Port F (PF15–0). Each general-purpose I/O pin can be individually controlled by manipulation of the GPIO control, status and interrupt registers:

• GPIO direction control register – Specifies the direction of each individual PFx pin as input or output.

•GPIO control and status registers – The processor employs a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set GPIO pin values, one register is written in order to clear GPIO pin values, one register is written in order to toggle GPIO pin values, and one register is written in order to specify GPIO pin values. Reading the GPIO status register allows software to interrogate the sense of the GPIO pin.

• GPIO interrupt mask registers – The two GPIO interrupt mask registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual GPIO pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function.

Rev. H | Page 10 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processors provide a parallel peripheral interface (PPI) that can connect directly to parallel ADCs and DACs, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, onchip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications.

Three distinct sub modes are supported:

• Input mode – Frame syncs and data are inputs into the PPI.

• Frame capture mode – Frame syncs are outputs from the PPI, but data are inputs.

• Output mode – Frame syncs and data are outputs from the PPI.

Input Mode

Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct sub modes are supported:

•Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Video Only Mode

Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval (VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that can be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors provides four operating modes, each with a different performance/ power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Rev. H | Page 11 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

power savings factor

CCLKRED

CCLKNOM

---------------------

DDINTRED

DDINTNOM

--------------------------







RED

NOM

-----------











Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before it can transition to the full-on or sleep modes.

Table 4. Power Settings

Core

PLL

Mode PLL

Full On Enabled No Enabled Enabled On Active Enabled/

Disabled Sleep Enabled — Disabled Enabled On Deep

Sleep Hibernate Disabled — Disabled Disabled Off

Disabled — Disabled Disabled On

Bypassed

Ye s En ab l ed En a bl ed O n

Clock (CCLK)

System Clock (SCLK)

Internal Power (V

DDINT

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the sleep mode, assertion of wakeup causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled, the processor will transition to the active mode.

When in the sleep mode, system DMA access to L1 memory is not supported.

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET

) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode. Assertion of RESET

while in deep sleep mode causes the processor to transition to the fullon mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. In addition to disabling the clocks, this sets the internal power supply voltage (V

DDINT

) to

0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. Since V

is still supplied in this mode, all of the external

DDEXT

pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. The internal supply regulator can be woken up either by a real-time clock wakeup or by asserting the RESET

pin.

Power Savings

As shown in Table 5, the processors support three different

)

power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V RTC internal logic and crystal I/O V All other I/O V

DDINT

DDRTC

DDEXT

The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic.

The dynamic power management feature of the processor allows both the processor’s input voltage (V quency (f

) to be dynamically controlled.

CCLK

) and clock fre-

DDINT

The savings in power dissipation can be modeled using the power savings factor and % power savings calculations.

The power savings factor is calculated as:

where the variables in the equation are:

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

DDINTNOM

DDINTRED

is the nominal internal supply voltage

is the reduced internal supply voltage

Rev. H | Page 12 of 64 | January 2011

% power savings 1 power savings factor–100%=

DDEXT

(LOW-INDUCTANCE)

DDINT

OUT

100μF

OUT

GND

SHORT AND LOW-

INDUCTANCE WIRE

DDEXT

100μF

10μF

LOW ESR

100n F

SET OF DECOUPLING

CAPACITORS

FDS9431A

ZHCS1000

NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

10μH

CLKIN

CLKOUT

XTAL

18pF* 18pF*

FOR OVERTONE OPERATION ONLY

DDEXT

TO PLL CIRCUITRY

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY.

Blackfin

700

0 *

1M

is the duration running at f

NOM

is the duration running at f

RED

CCLKNOM

CCLKRED

The percent power savings is calculated as:

ADSP-BF531/ADSP-BF532/ADSP-BF533

For further details on the on-chip voltage regulator and related board design guidelines, see the Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228) applications note on the Analog Devices web site (www.ana-

log.com)—use site search on “EE-228”.

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator that can generate appropriate V V

supply. See Operating Conditions on Page 21 for regula-

DDEXT

tor tolerances and acceptable V

Figure 7 shows the typical external components required to

complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (V While in the hibernate state, I/O power is still being applied, eliminating the need for external buffers. The voltage regulator can be activated from this power-down state either through an RTC wakeup or by asserting RESET boot sequence. The regulator can also be disabled and bypassed at the user’s discretion.

voltage levels from the

DDINT

ranges for specific models.

DDEXT

) supplied.

DDEXT

, both of which initiate a

CLOCK SIGNALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL-compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processors include an on-chip oscillator circuit, an external crystal can be used. For fundamental frequency operation, use the circuit shown in Figure 8.

Figure 7. Voltage Regulator Circuit

Voltage Regulator Layout Guidelines

Regulator external component placement, board routing, and bypass capacitors all have a significant effect on noise injected into the other analog circuits on-chip. The VROUT1–0 traces and voltage regulator external components should be considered as noise sources when doing board layout and should not be routed or placed near sensitive circuits or components on the board. All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the processors as possible.

A parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in

Figure 8 fine tune the phase and amplitude of the sine fre-

quency. The capacitor and resistor values shown in Figure 8 are typical values only. The capacitor values are dependent upon the crystal manufacturer's load capacitance recommendations and the physical PCB layout. The resistor value depends on the drive level specified by the crystal manufacturer. System designs should verify the customized values based on careful investigation on multiple devices over the allowed temperature range.

A third-overtone crystal can be used at frequencies above 25 MHz. The circuit is then modified to ensure crystal operation

Rev. H | Page 13 of 64 | January 2011

only at the third overtone, by adding a tuned inductor circuit as shown in Figure 8.

Figure 8. External Crystal Connections

ADSP-BF531/ADSP-BF532/ADSP-BF533

PLL

0.5

to 64

÷1to15

÷1,2,4,8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK  CCLK

SCLK 

133 MHz

As shown in Figure 9, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 0.5 to 64 multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Table 6. Example System Clock Ratios

Signal Name SSEL3–0

0001 1:1 100 100 0101 5:1 400 80 1010 10:1 500 50

The maximum frequency of the system clock is f sor ratio must be chosen to limit the system clock frequency to its maximum of f cally without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). When the SSEL value is changed, it affects all of the peripherals that derive their clock signals from the SCLK signal.

The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Figure 9. Frequency Modification Methods

Example Frequency Ratios

Divider Ratio VCO/SCLK

. The SSEL value can be changed dynami-

SCLK

VCO SCLK

(MHz)

Table 7. Core Clock Ratios

Signal Name CSEL1–0

00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25

BOOTING MODES

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have two mechanisms (listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence.

Table 8. Booting Modes

BMODE1–0 Description

00 Execute from 16-bit external memory (bypass

01 Boot from 8-bit or 16-bit FLASH 10 Boot from serial master connected to SPI 11 Boot from serial slave EEPROM/flash (8-,16-, or 24-

The BMODE pins of the reset configuration register, sampled during power-on resets and software-initiated resets, implement the following modes:

• Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit or 16-bit external flash memory – The flash boot routine located in boot ROM memory space is set up

. The divi-

SCLK

Rev. H | Page 14 of 64 | January 2011

using asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit addressable, or Atmel AT45DB041, AT45DB081, or AT45DB161) – The SPI uses the PF2 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit addressable EEPROM/flash device is detected, and begins clocking data into the processor at the beginning of L1 instruction memory.

• Boot from SPI serial master – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor asserts a GPIO pin, called host wait (HWAIT), to signal the host device not to send any

Example Frequency Ratios

Divider Ratio VCO/CCLK

VCO CCLK

(MHz)

boot ROM)

bit address range, or Atmel AT45DB041, AT45DB081, or AT45DB161serial flash)

ADSP-BF531/ADSP-BF532/ADSP-BF533

more bytes until the flag is deasserted. The GPIO pin is chosen by the user and this information is transferred to the Blackfin processor via bits[10:5] of the FLAG header in the LDR image.

For each of the boot modes, a 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks can be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM.

In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.

• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers.

• Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

DEVELOPMENT TOOLS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are supported by a complete set of CROSSCORE hardware development tools, including Analog Devices emulators and VisualDSP++ emulator hardware that supports other Blackfin processors also fully emulates the processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to processor assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory, and stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

development environment. The same

software and

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ADSP-BF531/ADSP-BF532/ADSP-BF533

The VisualDSP++ IDDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, and examine runtime stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non intrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

For evaluation of ADSP-BF531/ADSP-BF532/ADSP-BF533 processors, use the EZ-KIT Lite board available from Analog Devices. Order part number ADDS-BF533-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the Analog Devices JTAG Emulation Technical Refer- ence (EE-68) on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

EZ-KIT Lite Evaluation Board

Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices

Rev. H | Page 16 of 64 | January 2011

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the "signal chain" entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

Lab

site (http://www.analog.com/circuits) provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. H | Page 17 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

PIN DESCRIPTIONS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin definitions are listed in Table 9.

All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. These pins are all driven high, with the exception of CLKOUT, which toggles at the system clock rate. During hibernate, all outputs are threestated unless otherwise noted in Table 9.

If BR is active (whether or not RESET is asserted), the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the exception of the pins that need pullups or pull-downs as noted in the table.

In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics.

Table 9. Pin Descriptions

Pin Name Type Function

Memory Interface

ADDR19–1 O Address Bus for Async/Sync Access A

DATA15–0 I/O Data Bus for Async/Sync Access A

ABE1–0

/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A

BGH

Asynchronous Memory Control

AMS3–0

ARDY I Hardware Ready Control (This pin should be pulled high if not used.)

AOE

ARE

AWE

Synchronous Memory Control

SRAS

SCAS

SWE

SCKE O Clock Enable (Requires pull-down if hibernate is used.) A

CLKOUT O Clock Output B

SA10 O A10 Pin A

SMS

Timers

TMR0 I/O Timer 0 C

TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C

TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C

PPI Port

PPI3–0 I/O PPI3–0 C

PPI_CLK/TMRCLK I PPI Clock/External Timer Reference

I Bus Request (This pin should be pulled high if not used.)

OBus Grant A

O Bus Grant Hang A

O Bank Select (Require pull-ups if hibernate is used.) A

O Output Enable A

ORead Enable A

OWrite Enable A

O Row Address Strobe A

O Column Address Strobe A

OWrite Enable A

O Bank Select A

Driver Typ e

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ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 9. Pin Descriptions (Continued)

Pin Name Type Function

Port F: GPIO/Parallel Peripheral Interface Port/SPI/Timers

PF0/SPISS I/O GPIO/SPI Slave Select Input C

PF1/SPISEL1

PF2/SPISEL2

PF3/SPISEL3/PPI_FS3 I/O GPIO/SPI Slave Select Enable 3/PPI Frame Sync 3 C

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8/PPI11 I/O GPIO/PPI 11 C

PF9/PPI10 I/O GPIO/PPI 10 C

PF10/PPI9 I/O GPIO/PPI 9 C

PF11/PPI8 I/O GPIO/PPI 8 C

PF12/PPI7 I/O GPIO/PPI 7 C

PF13/PPI6 I/O GPIO/PPI 6 C

PF14/PPI5 I/O GPIO/PPI 5 C

PF15/PPI4 I/O GPIO/PPI 4 C

JTAG Port

TCK I JTAG Clock

TDO O JTAG Serial Data Out C

TDI I JTAG Serial Data In

TMS I JTAG Mode Select

TRST

EMU

SPI Port

MOSI I/O Master Out Slave In C MISO I/O Master In Slave Out (This pin should be pulled high through a 4.7 k resistor if booting via the

SCK I/O SPI Clock D

Serial Ports

RSCLK0 I/O SPORT0 Receive Serial Clock D

RFS0 I/O SPORT0 Receive Frame Sync C

DR0PRI I SPORT0 Receive Data Primary

DR0SEC I SPORT0 Receive Data Secondary

TSCLK0 I/O SPORT0 Transmit Serial Clock D

TFS0 I/O SPORT0 Transmit Frame Sync C

DT0PRI O SPORT0 Transmit Data Primary C

DT0SEC O SPORT0 Transmit Data Secondary C

RSCLK1 I/O SPORT1 Receive Serial Clock D

/TACLK I/O GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input C

I/O GPIO/SPI Slave Select Enable 2 C

/PPI15 I/O GPIO/SPI Slave Select Enable 4/PPI 15 C

/PPI14 I/O GPIO/SPI Slave Select Enable 5/PPI 14 C

/PPI13 I/O GPIO/SPI Slave Select Enable 6/PPI 13 C

/PPI12 I/O GPIO/SPI Slave Select Enable 7/PPI 12 C

I JTAG Reset (This pin should be pulled low if JTAG is not used.)

O Emulation Output C

SPI port.)

Driver Typ e

Rev. H | Page 19 of 64 | January 2011

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 9. Pin Descriptions (Continued)

Pin Name Type Function

RFS1 I/O SPORT1 Receive Frame Sync C

DR1PRI I SPORT1 Receive Data Primary

DR1SEC I SPORT1 Receive Data Secondary

TSCLK1 I/O SPORT1 Transmit Serial Clock D

TFS1 I/O SPORT1 Transmit Frame Sync C

DT1PRI O SPORT1 Transmit Data Primary C

DT1SEC O SPORT1 Transmit Data Secondary C

UART Por t

RX I UART Receive

TX O UART Transmit C

Real-Time Clock

RTXI I RTC Crystal Input (This pin should be pulled low when not used.)

RTXO O RTC Crystal Output (Does not three-state in hibernate.)

Clock

CLKIN I Clock/Crystal Input (This pin needs to be at a level or clocking.)

XTAL O Crystal Output

Mode Controls

RESET

NMI I Nonmaskable Interrupt (This pin should be pulled low when not used.)

BMODE1–0 I Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)

Voltage Regulator

VROUT1–0 O External FET Drive (These pins should be left unconnected when unused and are driven high

Supplies

DDEXT

DDINT

DDRTC

GND G External Ground

Refer to Figure 32 on Page 44 to Figure 43 on Page 45.

I Reset (This pin is always active during core power-on.)

during hibernate.)

PI/O Power Supply

P Core Power Supply

P Real-Time Clock Power Supply (This pin should be connected to V

remain powered at all times.)

when not used and should

DDEXT

Driver Typ e

Rev. H | Page 20 of 64 | January 2011

+ 44 hidden pages

ANALOG DEVICES ADSP-BF531, ADSP-BF532, ADSP-BF533 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

MEMORY

FEATURES

PERIPHERALS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PORTABLE LOW POWER ARCHITECTURE

SYSTEM INTEGRATION

PROCESSOR PERIPHERALS

BLACKFIN PROCESSOR CORE

MEMORY ARCHITECTURE

Internal (On-Chip) Memory

External (Off-Chip) Memory

I/O Memory Space

Booting

Event Handling

Core Event Controller (CEC)

System Interrupt Controller (SIC)

Event Control

DMA CONTROLLERS

REAL-TIME CLOCK

WATCHDOG TIMER

TIMERS

SERIAL PORTS (SPORTs)

SERIAL PERIPHERAL INTERFACE (SPI) PORT

UART PORT

GENERAL-PURPOSE I/O PORT F

PARALLEL PERIPHERAL INTERFACE

General-Purpose Mode Descriptions

Input Mode

Frame Capture Mode

Output Mode

ITU-R 656 Mode Descriptions

Active Video Only Mode

Vertical Blanking Interval Mode

Entire Field Mode

DYNAMIC POWER MANAGEMENT

Full-On Operating Mode—Maximum Performance

Active Operating Mode—Moderate Power Savings

Sleep Operating Mode—High Dynamic Power Savings

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

Hibernate State—Maximum Static Power Savings

Power Savings

VOLTAGE REGULATION

CLOCK SIGNALS

Voltage Regulator Layout Guidelines

BOOTING MODES

INSTRUCTION SET DESCRIPTION

DEVELOPMENT TOOLS

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

EZ-KIT Lite Evaluation Board

RELATED DOCUMENTS

RELATED SIGNAL CHAINS

PIN DESCRIPTIONS