ANALOG DEVICES ADSP-BF52x Service Manual

a

ADSP-BF52x Blackfin® Processor

Hardware Reference

Revision 1.0, March 2010

Part Number

82-000525

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ................................................................ lix

Intended Audience ........................................................................ lix

What’s New in This Manual ........................................................... lx

Technical or Customer Support ....................................................... lx

Product Information ...................................................................... lxi

Analog Devices Web Site .......................................................... lxi

VisualDSP++ Online Documentation ..................................... lxi

Technical Library CD ............................................................. lxii

Social Networking Web Sites ................................................. lxiii

Notation Conventions ................................................................. lxiii

INTRODUCTION

Manual Contents .......................................................................... 1-1

Peripherals .................................................................................... 1-5

Memory Architecture .................................................................... 1-7

Internal Memory ..................................................................... 1-9

External Memory .................................................................... 1-9

I/O Memory Space .................................................................. 1-9

ADSP-BF52x Blackfin Processor Hardware Reference iii

Contents

One-Time-Programmable (OTP) Memory ............................. 1-10

DMA Support ............................................................................ 1-11

External Bus Interface Unit ......................................................... 1-12

SDRAM Controller ............................................................... 1-12

Asynchronous Controller ...................................................... 1-13

Ports .......................................................................................... 1-13

General-Purpose I/O (GPIO) ................................................ 1-13

Two-Wire Interface ..................................................................... 1-15

Ethernet MAC ............................................................................ 1-16

Parallel Peripheral Interface ......................................................... 1-16

SPORT Controllers .................................................................... 1-18

Serial Peripheral Interface (SPI) Port ........................................... 1-20

Timers ....................................................................................... 1-20

UART Ports ............................................................................... 1-21

Security ...................................................................................... 1-22

Real-Time Clock ........................................................................ 1-23

Watchdog Timer ......................................................................... 1-24

Clock Signals .............................................................................. 1-25

Dynamic Power Management ..................................................... 1-26

Full-On Mode (Maximum Performance) ................................ 1-26

Active Mode (Moderate Power Savings) ................................. 1-26

Sleep Mode (High Power Savings) ......................................... 1-26

Deep Sleep Mode (Maximum Power Savings) ........................ 1-27

Hibernate State .................................................................... 1-27

iv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Voltage Regulation ...................................................................... 1-27

Instruction Set Description ......................................................... 1-28

Development Tools ..................................................................... 1-29

CHIP BUS HIERARCHY

Overview ...................................................................................... 2-1

Interface Overview ........................................................................ 2-3

Internal Clocks ........................................................................ 2-3

Core Bus Overview .................................................................. 2-4

Peripheral Access Bus (PAB) ..................................................... 2-6

PAB Arbitration .................................................................. 2-6

PAB Agents (Masters, Slaves) ............................................... 2-6

PAB Performance ................................................................ 2-7

DMA Access Bus (DAB), DMA Core Bus (DCB),

DMA External Bus (DEB) .................................................... 2-8

DAB, DCB, DEB Arbitration ............................................. 2-8

DCB Sharing ...................................................................... 2-9

Using the CDPRIO Bit to Change Priorities .................. 2-13

DAB Bus Agents (Masters) ................................................ 2-13

DAB, DCB, and DEB Performance ................................... 2-14

External Access Bus (EAB) ..................................................... 2-14

Arbitration of the External Bus .............................................. 2-15

DEB/EAB Performance ......................................................... 2-15

MEMORY

Memory Architecture .................................................................... 3-1

ADSP-BF52x Blackfin Processor Hardware Reference v

Contents

L1 Instruction SRAM ................................................................... 3-3

L1 Data SRAM ............................................................................ 3-4

L1 Data Cache ............................................................................. 3-4

Boot ROM ................................................................................... 3-5

External Memory .......................................................................... 3-5

Processor-Specific MMRs .............................................................. 3-5

DMEM_CONTROL Register ................................................. 3-6

DTEST_COMMAND Register .............................................. 3-6

ONE-TIME PROGRAMMABLE MEMORY

OTP Memory Overview ............................................................... 4-1

OTP Memory Map ...................................................................... 4-2

Error Correction ........................................................................... 4-7

Error Correction Policy ........................................................... 4-8

OTP Access ................................................................................ 4-10

OTP Timing Parameters ....................................................... 4-12

Timing for the ADSP-BF523/525/527 Processors .............. 4-13

Timing for the ADSP-BF522/524/526 Processors .............. 4-14

OTP_TIMING Register ................................................... 4-17

Callable ROM Functions for OTP ACCESS .......................... 4-17

Initializing OTP ............................................................... 4-17

bfrom_OtpCommand ................................................... 4-17

Programming and Reading OTP ....................................... 4-19

bfrom_OtpRead ........................................................... 4-20

bfrom_OtpWrite .......................................................... 4-21

vi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Error Codes .................................................................. 4-24

Write-protecting OTP Memory ......................................... 4-25

Accessing Private OTP Memory ........................................ 4-28

OTP Programming Examples ...................................................... 4-28

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF52x ..................................... 5-1

Overview ...................................................................................... 5-1

Features ................................................................................... 5-2

Description of Operation .............................................................. 5-2

Events and Sequencing ............................................................ 5-2

System Peripheral Interrupts .................................................... 5-4

Programming Model ..................................................................... 5-7

System Interrupt Initialization ................................................. 5-8

System Interrupt Processing Summary ...................................... 5-8

System Interrupt Controller Registers .......................................... 5-10

System Interrupt Assignment (SIC_IAR) Register ................... 5-11

System Interrupt Mask (SIC_IMASK) Register ...................... 5-12

System Interrupt Status (SIC_ISR) Register ........................... 5-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 5-12

Programming Examples ............................................................... 5-13

Clearing Interrupt Requests ................................................... 5-13

Unique Behavior for the ADSP-BF52x Processor ......................... 5-15

Interfaces .............................................................................. 5-15

System Peripheral Interrupts .................................................. 5-18

ADSP-BF52x Blackfin Processor Hardware Reference vii

Contents

DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF52x .................................... 6-1

Overview and Features .................................................................. 6-2

DMA Controller Overview ........................................................... 6-4

External Interfaces .................................................................. 6-4

Internal Interfaces ................................................................... 6-5

Peripheral DMA ...................................................................... 6-6

Memory DMA ........................................................................ 6-7

Handshaked Memory DMA (HMDMA) Mode ................... 6-9

Modes of Operation ................................................................... 6-10

Register-Based DMA Operation ............................................ 6-10

Stop Mode ....................................................................... 6-11

Autobuffer Mode .............................................................. 6-12

Two-Dimensional DMA Operation ....................................... 6-12

Examples of Two-Dimensional DMA ................................ 6-13

Descriptor-based DMA Operation ......................................... 6-14

Descriptor List Mode ........................................................ 6-15

Descriptor Array Mode ..................................................... 6-16

Variable Descriptor Size .................................................... 6-16

Mixing Flow Modes .......................................................... 6-17

Functional Description ............................................................... 6-18

DMA Operation Flow ........................................................... 6-18

DMA Startup ................................................................... 6-18

DMA Refresh ................................................................... 6-23

viii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Work Unit Transitions ...................................................... 6-25

DMA Transmit and MDMA Source .............................. 6-26

DMA Receive ............................................................... 6-27

Stopping DMA Transfers ................................................... 6-29

DMA Errors (Aborts) ............................................................ 6-29

DMA Control Commands ..................................................... 6-32

Restrictions ....................................................................... 6-35

Transmit Restart or Finish ............................................. 6-35

Receive Restart or Finish ............................................... 6-36

Handshaked Memory DMA Operation .................................. 6-37

Pipelining DMA Requests ................................................. 6-38

HMDMA Interrupts ......................................................... 6-41

DMA Performance ................................................................ 6-42

DMA Throughput ............................................................ 6-43

Memory DMA Timing Details .......................................... 6-45

Static Channel Prioritization ............................................ 6-46

Temporary DMA Urgency ................................................. 6-46

Memory DMA Priority and Scheduling ............................. 6-48

Traffic Control .................................................................. 6-49

Programming Model .................................................................. 6-51

Synchronization of Software and DMA .................................. 6-52

Single-Buffer DMA Transfers ............................................ 6-54

Continuous Transfers Using Autobuffering ........................ 6-54

Descriptor Structures ........................................................ 6-57

ADSP-BF52x Blackfin Processor Hardware Reference ix

Contents

Descriptor Queue Management ........................................ 6-58

Descriptor Queue Using Interrupts on Every Descriptor 6-58

Descriptor Queue Using Minimal Interrupts ................. 6-60

Software Triggered Descriptor Fetches ............................... 6-62

DMA Registers ........................................................................... 6-64

DMA Channel Registers ........................................................ 6-64

DMA Peripheral Map Registers(DMAx_PERIPHERAL_MAP/

MDMA_yy_PERIPHERAL_MAP) ............................... 6-68

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 6-68

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ..... 6-73

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) . 6-76

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 6-76

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 6-77

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................ 6-78

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 6-79

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ............. 6-80

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 6-81

x ADSP-BF52x Blackfin Processor Hardware Reference

Contents

DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ............ 6-81

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 6-82

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) .................................. 6-83

HMDMA Registers ............................................................... 6-84

Handshake MDMA Control Registers (HMDMAx_CONTROL)

6-84

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 6-87

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ................................................ 6-87

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ................................................ 6-88

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 6-89

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ............................................ 6-89

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 6-90

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) .............................. 6-90

DMA_TC_PER Register ................................................... 6-91

DMA_TC_CNT Register ................................................. 6-92

Programming Examples ............................................................... 6-93

ADSP-BF52x Blackfin Processor Hardware Reference xi

Contents

Register-Based 2-D Memory DMA ........................................ 6-94

Initializing Descriptors in Memory ........................................ 6-97

Software-Triggered Descriptor Fetch Example ...................... 6-100

Handshaked Memory DMA Example .................................. 6-102

Unique Behavior for the ADSP-BF52x Processor ....................... 6-105

Static Channel Prioritization ............................................... 6-106

DMA Control Commands .................................................. 6-107

Handshaked Memory DMA Operation ................................ 6-107

HMDMA Interrupts ....................................................... 6-107

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 7-1

Block Diagram ........................................................................ 7-4

Internal Memory Interfaces ..................................................... 7-5

Registers ................................................................................. 7-6

Shared Pins ............................................................................. 7-6

System Clock .......................................................................... 7-7

Error Detection ....................................................................... 7-7

AMC Overview and Features ........................................................ 7-7

Features .................................................................................. 7-8

Asynchronous Memory Interface ............................................. 7-8

Asynchronous Memory Address Decode .............................. 7-9

AMC Pin Description ................................................................... 7-9

AMC Description of Operation .................................................. 7-10

Avoiding Bus Contention ...................................................... 7-10

xii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

External Access Extension .................................................. 7-11

AMC Functional Description ...................................................... 7-11

Programmable Timing Characteristics .................................... 7-11

Asynchronous Reads ......................................................... 7-11

Asynchronous Writes ......................................................... 7-13

Adding External Access Extension ..................................... 7-15

Byte Enables .......................................................................... 7-17

AMC Programming Model .......................................................... 7-17

AMC Registers ............................................................................ 7-19

EBIU_AMGCTL Register ..................................................... 7-20

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............... 7-20

AMC Programming Examples ..................................................... 7-23

SDC Overview and Features ........................................................ 7-24

Features ................................................................................. 7-24

SDRAM Configurations Supported ....................................... 7-25

SDRAM External Bank Size ................................................... 7-26

SDC Address Mapping .......................................................... 7-26

Internal SDRAM Bank Select ................................................ 7-27

Parallel Connection of SDRAMs ............................................ 7-28

SDC Interface Overview ............................................................. 7-28

SDC Pin Description ............................................................. 7-29

SDRAM Performance ............................................................ 7-30

SDC Description of Operation .................................................... 7-31

Definition of SDRAM Architecture Terms ............................. 7-31

ADSP-BF52x Blackfin Processor Hardware Reference xiii

Contents

Refresh ............................................................................. 7-31

Row Activation ................................................................. 7-31

Column Read/Write ......................................................... 7-31

Row Precharge .................................................................. 7-31

Internal Bank ................................................................... 7-32

External Bank ................................................................... 7-32

Memory Size .................................................................... 7-32

Burst Length .................................................................... 7-32

Burst Type ........................................................................ 7-32

CAS Latency .................................................................... 7-33

Data I/O Mask Function .................................................. 7-33

SDRAM Commands ........................................................ 7-33

Mode Register Set (MRS) command ................................. 7-33

Extended Mode Register Set (EMRS) command ................ 7-33

Bank Activate command ................................................... 7-33

Read/Write command ....................................................... 7-34

Precharge/Precharge All Command ................................... 7-34

Auto-refresh command ..................................................... 7-34

Enter Self-Refresh Mode ................................................... 7-34

Exit Self-Refresh Mode ..................................................... 7-34

SDC Timing Specifications ................................................... 7-35

t

................................................................................ 7-35

MRD

t

................................................................................. 7-35

RAS

tCL ................................................................................... 7-35

xiv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

t

................................................................................. 7-36

RCD

t

................................................................................. 7-36

RRD

tWR .................................................................................. 7-36

tRP .................................................................................... 7-36

tRC ................................................................................... 7-37

t

................................................................................. 7-37

RFC

t

.................................................................................. 7-37

XSR

t

.................................................................................. 7-37

REF

t

................................................................................. 7-38

REFI

SDC Functional Description ....................................................... 7-38

SDC Operation .................................................................... 7-38

SDC Address Muxing ........................................................ 7-41

Multibank Operation ........................................................ 7-42

Core and DMA Arbitration ............................................... 7-43

Changing System Clock During Runtime .......................... 7-44

Changing Power Management During Runtime ................. 7-45

Deep Sleep Mode .......................................................... 7-45

Hibernate State ............................................................. 7-45

SDC Commands ................................................................... 7-46

Mode Register Set Command ............................................ 7-47

Extended Mode Register Set Command (Mobile SDRAM) 7-48

Bank Activation Command ............................................... 7-49

Read/Write Command ...................................................... 7-49

ADSP-BF52x Blackfin Processor Hardware Reference xv

Contents

Write Command With Data Mask .................................... 7-50

Single Precharge Command .............................................. 7-51

Precharge All Command ................................................... 7-51

Auto-Refresh Command ................................................... 7-51

Self-Refresh Mode ............................................................ 7-52

Self-Refresh Entry Command ................................... 7-52

Self-Refresh Exit Command ..................................... 7-52

No Operation Command .................................................. 7-53

SDC SA10 Pin ...................................................................... 7-54

SDC Programming Model .......................................................... 7-54

SDC Configuration .............................................................. 7-54

Example SDRAM System Block Diagrams ............................. 7-56

SDC Register Definitions ........................................................... 7-59

EBIU_SDRRC Register ........................................................ 7-59

EBIU_SDBCTL Register ...................................................... 7-61

Using SDRAMs With Systems Smaller than 16M byte ....... 7-63

EBIU_SDGCTL Register ...................................................... 7-65

SDRAM clock enable (SCTLE) ....................................... 7-65

CAS latency (CL) ............................................................ 7-67

Partial array self refresh (PASR) ........................................ 7-67

Bank activate command delay (TRAS) ............................. 7-68

Bank precharge delay (TRP) ............................................ 7-68

RAS to CAS delay (TRCD) ............................................. 7-68

Write to precharge delay (TWR) ....................................... 7-69

xvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Power-Up Start Delay (PUPSD) ........................................ 7-69

Power-Up Sequence Mode (PSM) ...................................... 7-70

Power-Up Sequence Start Enable (PSSE) .......................... 7-70

Self-Refresh Setting (SRFS) .............................................. 7-71

Enter Self-Refresh Mode ................................................ 7-71

Exit Self-Refresh Mode .................................................. 7-72

External buffering enabled (EBUFE) ................................ 7-72

Fast Back-to-Back Read to Write (FBBRW) ....................... 7-73

Extended Mode Register Enabled (EMREN) ..................... 7-73

Temperature Compensated Self-Refresh (TCSR) ................ 7-74

EBIU_SDSTAT Register ........................................................ 7-74

SDC Programming Examples ...................................................... 7-76

HOST DMA PORT

Overview ...................................................................................... 8-1

Features ........................................................................................ 8-2

Interface Overview ........................................................................ 8-3

Description of Operation .............................................................. 8-3

Architecture ............................................................................ 8-4

Functional Description ............................................................ 8-5

HOSTDP Configuration .................................................... 8-5

HOSTDP Transactions ....................................................... 8-7

Host Read Status ............................................................. 8-8

Host Read Data and Host Write Data Operations ............ 8-9

HOSTDP Modes of Operation ......................................... 8-10

ADSP-BF52x Blackfin Processor Hardware Reference xvii

Contents

Acknowledge Mode ...................................................... 8-11

Acknowledge Mode Timing Diagrams ...................... 8-11

Host Bus Timeout .................................................... 8-13

Interrupt Mode ............................................................. 8-14

DMA STOP Mode and AUTOBUFFER Mode ................. 8-16

Bus Widths and Endian Order .......................................... 8-16

Access Control .................................................................. 8-17

Improving HOSTDP DMA Bus Bandwidth ...................... 8-18

Control Commands Between the

External Host and HOSTDP ......................................... 8-19

Programming Model ................................................................... 8-21

Host DMA Port Registers ........................................................... 8-26

HOSTDP Control (HOST_CONTROL) Register ................ 8-26

HOSTDP Status (HOST_STATUS) Register ........................ 8-28

HOSTDP Timeout (HOST_TIMEOUT) Register ................ 8-31

Programming Examples .............................................................. 8-32

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 9-1

Features ........................................................................................ 9-2

Interface Overview ....................................................................... 9-3

External Interface .................................................................... 9-4

Port F Structure .................................................................. 9-4

Port G Structure ................................................................. 9-5

Port H Structure ................................................................. 9-7

xviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Port J Structure ................................................................... 9-9

Input Tap Considerations .................................................... 9-9

Internal Interfaces ................................................................. 9-10

Internal Signals ................................................................. 9-10

Performance/Throughput ...................................................... 9-11

Description of Operation ............................................................ 9-12

Operation ............................................................................. 9-12

General-Purpose I/O Modules ............................................... 9-13

GPIO Interrupt Processing .................................................... 9-16

Programming Model ................................................................... 9-22

GPIO Drive Hysteresis Control ................................................... 9-24

Portx Control (PORTx_HYSTERESIS) Register .................... 9-24

Hysteresis Control Register .................................................... 9-26

TWI Drive Strength Control Register .......................................... 9-27

Memory-Mapped GPIO Registers ............................................... 9-27

Port Multiplexer Control Register (PORTx_MUX) ................ 9-28

Function Enable Registers (PORTx_FER) .............................. 9-30

GPIO Direction Registers (PORTxIO_DIR) .......................... 9-31

GPIO Input Enable Registers (PORTxIO_INEN) .................. 9-32

GPIO Data Registers (PORTxIO) .......................................... 9-32

GPIO Set Registers (PORTxIO_SET) .................................... 9-33

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-33

GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 9-34

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-34

ADSP-BF52x Blackfin Processor Hardware Reference xix

Contents

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................ 9-35

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ........ 9-35

GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 9-36

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 9-37

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 9-39

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 9-41

Programming Examples .............................................................. 9-42

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF52x .................................. 10-1

Overview .................................................................................... 10-2

External Interface .................................................................. 10-3

Internal Interface .................................................................. 10-4

Description of Operation ............................................................ 10-4

Interrupt Processing .............................................................. 10-5

Illegal States .......................................................................... 10-7

Modes of Operation ................................................................. 10-10

Pulse Width Modulation (PWM_OUT) Mode .................... 10-10

Output Pad Disable ........................................................ 10-12

Single Pulse Generation .................................................. 10-12

Pulse Width Modulation Waveform Generation .............. 10-13

PULSE_HI Toggle Mode ................................................ 10-15

Externally Clocked PWM_OUT ..................................... 10-20

xx ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Using PWM_OUT Mode With the PPI .......................... 10-21

Stopping the Timer in PWM_OUT Mode ....................... 10-21

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 10-23

Autobaud Mode .............................................................. 10-31

External Event (EXT_CLK) Mode ....................................... 10-31

Programming Model ................................................................. 10-33

Timer Registers ......................................................................... 10-34

Timer Enable Register (TIMER_ENABLE) .......................... 10-35

Timer Disable Register (TIMER_DISABLE) ........................ 10-36

Timer Status Register (TIMER_STATUS) ............................ 10-37

Timer Configuration Register (TIMER_CONFIG) .............. 10-40

Timer Counter Register (TIMER_COUNTER) ................... 10-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................. 10-43

Summary ............................................................................ 10-46

Programming Examples ............................................................. 10-48

Unique Behavior for the ADSP-BF52x Processor ....................... 10-57

Interface Overview .............................................................. 10-58

External Interface ............................................................ 10-58

CORE TIMER

Specific Information for the ADSP-BF52x ................................... 11-1

Overview and Features ................................................................ 11-1

Timer Overview .......................................................................... 11-2

External Interfaces ................................................................. 11-2

ADSP-BF52x Blackfin Processor Hardware Reference xxi

Contents

Internal Interfaces ................................................................. 11-3

Description of Operation ............................................................ 11-3

Interrupt Processing .............................................................. 11-3

Core Timer Registers .................................................................. 11-4

Core Timer Control Register (TCNTL) ................................. 11-5

Core Timer Count Register (TCOUNT) ............................... 11-5

Core Timer Period Register (TPERIOD) ............................... 11-6

Core Timer Scale Register (TSCALE) .................................... 11-7

Programming Examples .............................................................. 11-7

Unique Behavior for the ADSP-BF52x Processor ......................... 11-9

WAT CH DOG TIMER

Specific Information for the ADSP-BF52x .................................. 12-1

Overview and Features ................................................................ 12-1

Interface Overview ..................................................................... 12-3

External Interface .................................................................. 12-3

Internal Interface .................................................................. 12-3

Description of Operation ............................................................ 12-4

Register Definitions .................................................................... 12-5

Watchdog Count (WDOG_CNT) Register ........................... 12-5

Watchdog Status (WDOG_STAT) Register ........................... 12-6

Watchdog Control (WDOG_CTL) Register .......................... 12-7

Programming Examples .............................................................. 12-8

Unique Information for the ADSP-BF52x Processor .................. 12-11

xxii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

GENERAL-PURPOSE COUNTER

Specific Information for the ADSP-BF52x ................................... 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ...................................................................... 13-3

Description of Operation ............................................................ 13-4

Quadrature Encoder Mode .................................................... 13-4

Binary Encoder Mode ............................................................ 13-5

Up/Down Counter Mode ...................................................... 13-6

Direction Counter Mode ....................................................... 13-7

Timed Direction Mode .......................................................... 13-7

Functional Description ............................................................... 13-7

Input Noise Filtering (Debouncing) ....................................... 13-8

Zero Marker (Push Button) Operation ................................... 13-9

Boundary Comparison Modes .............................................. 13-10

Control and Signaling Events ............................................... 13-12

Illegal Gray/Binary Code Events ...................................... 13-12

Up/Down Count Events .................................................. 13-12

Zero-Count Events ......................................................... 13-13

Overflow Events .............................................................. 13-13

Boundary Match Events .................................................. 13-13

Zero Marker Events ......................................................... 13-14

Capturing Timing Information ............................................ 13-14

ADSP-BF52x Blackfin Processor Hardware Reference xxiii

Contents

Capturing Time Interval Between

Successive Counter Events ............................................ 13-15

Capturing Counter Interval and

CNT_COUNTER Read Timing .................................. 13-16

Programming Model ................................................................. 13-18

Registers ................................................................................... 13-19

Counter Module Register Overview ..................................... 13-19

Counter Configuration Register (CNT_CONFIG) .............. 13-20

Counter Interrupt Mask Register (CNT_IMASK) ................ 13-20

Counter Status Register (CNT_STATUS) ............................ 13-21

Counter Command Register (CNT_COMMAND) ............. 13-22

Counter Debounce Register (CNT_DEBOUNCE) .............. 13-24

Counter Count Value Register (CNT_COUNTER) ............ 13-25

Counter Boundary Registers (CNT_MIN and CNT_MAX) . 13-26

Programming Examples ............................................................ 13-27

Unique Behavior for the ADSP-BF52x Processor ....................... 13-38

REAL-TIME CLOCK

Specific Information for the ADSP-BF52x .................................. 14-1

Overview .................................................................................... 14-1

Interface Overview ..................................................................... 14-3

Description of Operation ............................................................ 14-4

RTC Clock Requirements ..................................................... 14-5

Prescaler Enable .................................................................... 14-5

RTC Programming Model .......................................................... 14-7

xxiv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Register Writes ...................................................................... 14-8

Write Latency ........................................................................ 14-9

Register Reads ..................................................................... 14-10

Deep Sleep .......................................................................... 14-10

Event Flags .......................................................................... 14-11

Setting Time of Day ............................................................ 14-13

Using the Stopwatch ............................................................ 14-13

Interrupts ............................................................................ 14-14

State Transitions Summary ................................................... 14-16

Register Definitions .................................................................. 14-19

RTC Status (RTC_STAT) Register ....................................... 14-20

RTC Interrupt Control (RTC_ICTL) Register ..................... 14-20

RTC Interrupt Status (RTC_ISTAT) Register ....................... 14-21

RTC Stopwatch Count (RTC_SWCNT) Register ................. 14-21

RTC Alarm (RTC_ALARM) Register ................................... 14-22

RTC Prescaler Enable (RTC_PREN) Register ....................... 14-22

Programming Examples ............................................................. 14-22

Enable RTC Prescaler .......................................................... 14-23

RTC Stopwatch For Exiting Deep Sleep Mode ..................... 14-23

RTC Alarm to Come Out of Hibernate State ....................... 14-25

Unique Information for the ADSP-BF52x Processor .................. 14-27

PARALLEL PERIPHERAL INTERFACE

Specific Information for the ADSP-BF52x ................................... 15-1

Overview .................................................................................... 15-2

ADSP-BF52x Blackfin Processor Hardware Reference xxv

Contents

Features ...................................................................................... 15-2

Interface Overview ..................................................................... 15-3

Description of Operation ............................................................ 15-4

Functional Description ............................................................... 15-5

ITU-R 656 Modes ................................................................ 15-5

ITU-R 656 Background .................................................... 15-5

ITU-R 656 Input Modes .................................................. 15-9

Entire Field .................................................................. 15-9

Active Video Only ...................................................... 15-10

Vertical Blanking Interval (VBI) only .......................... 15-10

ITU-R 656 Output Mode ............................................... 15-11

Frame Synchronization in ITU-R 656 Modes .................. 15-11

General-Purpose PPI Modes ................................................ 15-12

Data Input (RX) Modes .................................................. 15-14

No Frame Syncs .......................................................... 15-15

1, 2, or 3 External Frame Syncs ................................... 15-16

2 or 3 Internal Frame Syncs ........................................ 15-16

Data Output (TX) Modes ............................................... 15-17

No Frame Syncs .......................................................... 15-17

1 or 2 External Frame Syncs ........................................ 15-18

1, 2, or 3 Internal Frame Syncs ................................... 15-19

Frame Synchronization in GP Modes .............................. 15-20

Modes With Internal Frame Syncs ............................... 15-20

Modes With External Frame Syncs .............................. 15-21

xxvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Programming Model ................................................................. 15-22

DMA Operation .................................................................. 15-23

PPI Registers ............................................................................. 15-26

PPI Control Register (PPI_CONTROL) ............................. 15-26

PPI Status Register (PPI_STATUS) ...................................... 15-31

PPI Delay Count Register (PPI_DELAY) ............................. 15-34

PPI Transfer Count Register (PPI_COUNT) ....................... 15-34

PPI Lines Per Frame Register (PPI_FRAME) ........................ 15-35

Programming Examples ............................................................. 15-37

Unique Behavior for the ADSP-BF52x Processor ....................... 15-39

SECURITY

Overview .................................................................................... 16-1

Features ...................................................................................... 16-4

Description of Operation ............................................................ 16-6

Secure State Machine ............................................................. 16-7

Open Mode ...................................................................... 16-8

Secure Entry Mode ........................................................... 16-8

Secure Mode ..................................................................... 16-9

SecureMode Control ....................................................... 16-11

Security Features ................................................................. 16-13

Digital Signature Authentication ..................................... 16-13

Digital Signature Authentication

Performance Measurement ............................................ 16-16

Protection Features .............................................................. 16-16

ADSP-BF52x Blackfin Processor Hardware Reference xxvii

Contents

Operating in Secure Mode ................................................... 16-20

Entering Secure Mode .................................................... 16-20

Exiting Secure Mode ....................................................... 16-21

Reset Handling in Secure Mode ........................................... 16-21

Hardware Reset .............................................................. 16-21

Clearing Private Data ...................................................... 16-22

Public Key Requirements .................................................... 16-24

Storing Public Cipher Key in Public OTP ....................... 16-26

Cryptographic Ciphers ........................................................ 16-27

Keys ................................................................................... 16-27

Debug Functionality .......................................................... 16-27

Programming Examples .................................................. 16-31

Programming Model ................................................................. 16-32

Secure Entry Service Routine (SESR) API ............................ 16-32

Starting Authentication ....................................................... 16-33

Memory Configuration ....................................................... 16-34

Message Placement ......................................................... 16-35

Digital Signature ............................................................ 16-35

Message Size Constraints ................................................ 16-35

Memory Usage ............................................................... 16-36

Memory Protection ......................................................... 16-36

Secure Function and Secure Entry Service Routine Arguments 16-36

Secure Function Arguments ............................................ 16-37

Secure Entry Service Routine Arguments ......................... 16-38

xxviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

usFlags ............................................................................ 16-38

uslRQMask ..................................................................... 16-39

ulMessageSize ................................................................. 16-40

ulSFEntryPoint ............................................................... 16-40

ulMessagePtr ................................................................... 16-40

Secure Message Execution ............................................... 16-40

Return Codes .................................................................. 16-41

Secure Hash Algorithm (SHA-1) API ............................... 16-43

ADI_SHA1 Data Type ................................................ 16-43

bfrom_Sha1Init ROM Routine .................................... 16-44

bfrom_Sha1Hash ROM Routine ................................. 16-44

Security Registers ...................................................................... 16-45

Secure System Switch (SECURE_SYSSWT) Register ............ 16-46

Secure Control (SECURE_CONTROL) Register ................. 16-52

Secure Status (SECURE_STATUS) Register ......................... 16-55

SYSTEM RESET AND BOOTING

Overview .................................................................................... 17-1

Reset and Power-up .................................................................... 17-4

Hardware Reset ..................................................................... 17-6

Software Resets ...................................................................... 17-7

Reset Vector .......................................................................... 17-8

Servicing Reset Interrupts .................................................... 17-10

Preboot ..................................................................................... 17-11

Factory Page Settings (FPS) ................................................. 17-14

ADSP-BF52x Blackfin Processor Hardware Reference xxix

Contents

Preboot Page Settings (PBS) ................................................ 17-14

Alternative PBS Pages ..................................................... 17-16

Programming PBS Pages ................................................. 17-16

Recovering From Misprogrammed PBS Pages .................. 17-17

Customizing Power Management .................................... 17-17

Customizing Booting Options ........................................ 17-18

Customizing the Asynchronous Port ................................ 17-19

Customizing the Synchronous Port ................................. 17-20

Basic Booting Process ............................................................... 17-21

Block Headers ..................................................................... 17-23

Block Code .................................................................... 17-25

DMA Code Field ........................................................ 17-25

Block Flags Field ......................................................... 17-27

Header Checksum Field .............................................. 17-28

Header Sign Field ....................................................... 17-29

Target Address ................................................................ 17-29

Byte Count ..................................................................... 17-30

Argument ....................................................................... 17-31

Boot Host Wait (HWAIT) Feedback Strobe ......................... 17-31

Using HWAIT as Reset Indicator .................................... 17-32

Boot Termination ............................................................... 17-33

Single Block Boot Streams ................................................... 17-34

Direct Code Execution ................................................... 17-34

Advanced Boot Techniques ....................................................... 17-37

xxx ADSP-BF52x Blackfin Processor Hardware Reference