ANALOG DEVICES ADSP-BF52x Service Manual

a

ADSP-BF52x Blackfin® Processor

Hardware Reference

Revision 1.0, March 2010

Part Number

82-000525

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ................................................................ lix

Intended Audience ........................................................................ lix

What’s New in This Manual ........................................................... lx

Technical or Customer Support ....................................................... lx

Product Information ...................................................................... lxi

Analog Devices Web Site .......................................................... lxi

VisualDSP++ Online Documentation ..................................... lxi

Technical Library CD ............................................................. lxii

Social Networking Web Sites ................................................. lxiii

Notation Conventions ................................................................. lxiii

INTRODUCTION

Manual Contents .......................................................................... 1-1

Peripherals .................................................................................... 1-5

Memory Architecture .................................................................... 1-7

Internal Memory ..................................................................... 1-9

External Memory .................................................................... 1-9

I/O Memory Space .................................................................. 1-9

ADSP-BF52x Blackfin Processor Hardware Reference iii

Contents

One-Time-Programmable (OTP) Memory ............................. 1-10

DMA Support ............................................................................ 1-11

External Bus Interface Unit ......................................................... 1-12

SDRAM Controller ............................................................... 1-12

Asynchronous Controller ...................................................... 1-13

Ports .......................................................................................... 1-13

General-Purpose I/O (GPIO) ................................................ 1-13

Two-Wire Interface ..................................................................... 1-15

Ethernet MAC ............................................................................ 1-16

Parallel Peripheral Interface ......................................................... 1-16

SPORT Controllers .................................................................... 1-18

Serial Peripheral Interface (SPI) Port ........................................... 1-20

Timers ....................................................................................... 1-20

UART Ports ............................................................................... 1-21

Security ...................................................................................... 1-22

Real-Time Clock ........................................................................ 1-23

Watchdog Timer ......................................................................... 1-24

Clock Signals .............................................................................. 1-25

Dynamic Power Management ..................................................... 1-26

Full-On Mode (Maximum Performance) ................................ 1-26

Active Mode (Moderate Power Savings) ................................. 1-26

Sleep Mode (High Power Savings) ......................................... 1-26

Deep Sleep Mode (Maximum Power Savings) ........................ 1-27

Hibernate State .................................................................... 1-27

iv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Voltage Regulation ...................................................................... 1-27

Instruction Set Description ......................................................... 1-28

Development Tools ..................................................................... 1-29

CHIP BUS HIERARCHY

Overview ...................................................................................... 2-1

Interface Overview ........................................................................ 2-3

Internal Clocks ........................................................................ 2-3

Core Bus Overview .................................................................. 2-4

Peripheral Access Bus (PAB) ..................................................... 2-6

PAB Arbitration .................................................................. 2-6

PAB Agents (Masters, Slaves) ............................................... 2-6

PAB Performance ................................................................ 2-7

DMA Access Bus (DAB), DMA Core Bus (DCB),

DMA External Bus (DEB) .................................................... 2-8

DAB, DCB, DEB Arbitration ............................................. 2-8

DCB Sharing ...................................................................... 2-9

Using the CDPRIO Bit to Change Priorities .................. 2-13

DAB Bus Agents (Masters) ................................................ 2-13

DAB, DCB, and DEB Performance ................................... 2-14

External Access Bus (EAB) ..................................................... 2-14

Arbitration of the External Bus .............................................. 2-15

DEB/EAB Performance ......................................................... 2-15

MEMORY

Memory Architecture .................................................................... 3-1

ADSP-BF52x Blackfin Processor Hardware Reference v

Contents

L1 Instruction SRAM ................................................................... 3-3

L1 Data SRAM ............................................................................ 3-4

L1 Data Cache ............................................................................. 3-4

Boot ROM ................................................................................... 3-5

External Memory .......................................................................... 3-5

Processor-Specific MMRs .............................................................. 3-5

DMEM_CONTROL Register ................................................. 3-6

DTEST_COMMAND Register .............................................. 3-6

ONE-TIME PROGRAMMABLE MEMORY

OTP Memory Overview ............................................................... 4-1

OTP Memory Map ...................................................................... 4-2

Error Correction ........................................................................... 4-7

Error Correction Policy ........................................................... 4-8

OTP Access ................................................................................ 4-10

OTP Timing Parameters ....................................................... 4-12

Timing for the ADSP-BF523/525/527 Processors .............. 4-13

Timing for the ADSP-BF522/524/526 Processors .............. 4-14

OTP_TIMING Register ................................................... 4-17

Callable ROM Functions for OTP ACCESS .......................... 4-17

Initializing OTP ............................................................... 4-17

bfrom_OtpCommand ................................................... 4-17

Programming and Reading OTP ....................................... 4-19

bfrom_OtpRead ........................................................... 4-20

bfrom_OtpWrite .......................................................... 4-21

vi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Error Codes .................................................................. 4-24

Write-protecting OTP Memory ......................................... 4-25

Accessing Private OTP Memory ........................................ 4-28

OTP Programming Examples ...................................................... 4-28

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF52x ..................................... 5-1

Overview ...................................................................................... 5-1

Features ................................................................................... 5-2

Description of Operation .............................................................. 5-2

Events and Sequencing ............................................................ 5-2

System Peripheral Interrupts .................................................... 5-4

Programming Model ..................................................................... 5-7

System Interrupt Initialization ................................................. 5-8

System Interrupt Processing Summary ...................................... 5-8

System Interrupt Controller Registers .......................................... 5-10

System Interrupt Assignment (SIC_IAR) Register ................... 5-11

System Interrupt Mask (SIC_IMASK) Register ...................... 5-12

System Interrupt Status (SIC_ISR) Register ........................... 5-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 5-12

Programming Examples ............................................................... 5-13

Clearing Interrupt Requests ................................................... 5-13

Unique Behavior for the ADSP-BF52x Processor ......................... 5-15

Interfaces .............................................................................. 5-15

System Peripheral Interrupts .................................................. 5-18

ADSP-BF52x Blackfin Processor Hardware Reference vii

Contents

DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF52x .................................... 6-1

Overview and Features .................................................................. 6-2

DMA Controller Overview ........................................................... 6-4

External Interfaces .................................................................. 6-4

Internal Interfaces ................................................................... 6-5

Peripheral DMA ...................................................................... 6-6

Memory DMA ........................................................................ 6-7

Handshaked Memory DMA (HMDMA) Mode ................... 6-9

Modes of Operation ................................................................... 6-10

Register-Based DMA Operation ............................................ 6-10

Stop Mode ....................................................................... 6-11

Autobuffer Mode .............................................................. 6-12

Two-Dimensional DMA Operation ....................................... 6-12

Examples of Two-Dimensional DMA ................................ 6-13

Descriptor-based DMA Operation ......................................... 6-14

Descriptor List Mode ........................................................ 6-15

Descriptor Array Mode ..................................................... 6-16

Variable Descriptor Size .................................................... 6-16

Mixing Flow Modes .......................................................... 6-17

Functional Description ............................................................... 6-18

DMA Operation Flow ........................................................... 6-18

DMA Startup ................................................................... 6-18

DMA Refresh ................................................................... 6-23

viii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Work Unit Transitions ...................................................... 6-25

DMA Transmit and MDMA Source .............................. 6-26

DMA Receive ............................................................... 6-27

Stopping DMA Transfers ................................................... 6-29

DMA Errors (Aborts) ............................................................ 6-29

DMA Control Commands ..................................................... 6-32

Restrictions ....................................................................... 6-35

Transmit Restart or Finish ............................................. 6-35

Receive Restart or Finish ............................................... 6-36

Handshaked Memory DMA Operation .................................. 6-37

Pipelining DMA Requests ................................................. 6-38

HMDMA Interrupts ......................................................... 6-41

DMA Performance ................................................................ 6-42

DMA Throughput ............................................................ 6-43

Memory DMA Timing Details .......................................... 6-45

Static Channel Prioritization ............................................ 6-46

Temporary DMA Urgency ................................................. 6-46

Memory DMA Priority and Scheduling ............................. 6-48

Traffic Control .................................................................. 6-49

Programming Model .................................................................. 6-51

Synchronization of Software and DMA .................................. 6-52

Single-Buffer DMA Transfers ............................................ 6-54

Continuous Transfers Using Autobuffering ........................ 6-54

Descriptor Structures ........................................................ 6-57

ADSP-BF52x Blackfin Processor Hardware Reference ix

Contents

Descriptor Queue Management ........................................ 6-58

Descriptor Queue Using Interrupts on Every Descriptor 6-58

Descriptor Queue Using Minimal Interrupts ................. 6-60

Software Triggered Descriptor Fetches ............................... 6-62

DMA Registers ........................................................................... 6-64

DMA Channel Registers ........................................................ 6-64

DMA Peripheral Map Registers(DMAx_PERIPHERAL_MAP/

MDMA_yy_PERIPHERAL_MAP) ............................... 6-68

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 6-68

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ..... 6-73

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) . 6-76

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 6-76

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 6-77

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................ 6-78

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 6-79

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ............. 6-80

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 6-81

x ADSP-BF52x Blackfin Processor Hardware Reference

Contents

DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ............ 6-81

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 6-82

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) .................................. 6-83

HMDMA Registers ............................................................... 6-84

Handshake MDMA Control Registers (HMDMAx_CONTROL)

6-84

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 6-87

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ................................................ 6-87

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ................................................ 6-88

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 6-89

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ............................................ 6-89

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 6-90

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) .............................. 6-90

DMA_TC_PER Register ................................................... 6-91

DMA_TC_CNT Register ................................................. 6-92

Programming Examples ............................................................... 6-93

ADSP-BF52x Blackfin Processor Hardware Reference xi

Contents

Register-Based 2-D Memory DMA ........................................ 6-94

Initializing Descriptors in Memory ........................................ 6-97

Software-Triggered Descriptor Fetch Example ...................... 6-100

Handshaked Memory DMA Example .................................. 6-102

Unique Behavior for the ADSP-BF52x Processor ....................... 6-105

Static Channel Prioritization ............................................... 6-106

DMA Control Commands .................................................. 6-107

Handshaked Memory DMA Operation ................................ 6-107

HMDMA Interrupts ....................................................... 6-107

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 7-1

Block Diagram ........................................................................ 7-4

Internal Memory Interfaces ..................................................... 7-5

Registers ................................................................................. 7-6

Shared Pins ............................................................................. 7-6

System Clock .......................................................................... 7-7

Error Detection ....................................................................... 7-7

AMC Overview and Features ........................................................ 7-7

Features .................................................................................. 7-8

Asynchronous Memory Interface ............................................. 7-8

Asynchronous Memory Address Decode .............................. 7-9

AMC Pin Description ................................................................... 7-9

AMC Description of Operation .................................................. 7-10

Avoiding Bus Contention ...................................................... 7-10

xii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

External Access Extension .................................................. 7-11

AMC Functional Description ...................................................... 7-11

Programmable Timing Characteristics .................................... 7-11

Asynchronous Reads ......................................................... 7-11

Asynchronous Writes ......................................................... 7-13

Adding External Access Extension ..................................... 7-15

Byte Enables .......................................................................... 7-17

AMC Programming Model .......................................................... 7-17

AMC Registers ............................................................................ 7-19

EBIU_AMGCTL Register ..................................................... 7-20

EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............... 7-20

AMC Programming Examples ..................................................... 7-23

SDC Overview and Features ........................................................ 7-24

Features ................................................................................. 7-24

SDRAM Configurations Supported ....................................... 7-25

SDRAM External Bank Size ................................................... 7-26

SDC Address Mapping .......................................................... 7-26

Internal SDRAM Bank Select ................................................ 7-27

Parallel Connection of SDRAMs ............................................ 7-28

SDC Interface Overview ............................................................. 7-28

SDC Pin Description ............................................................. 7-29

SDRAM Performance ............................................................ 7-30

SDC Description of Operation .................................................... 7-31

Definition of SDRAM Architecture Terms ............................. 7-31

ADSP-BF52x Blackfin Processor Hardware Reference xiii

Contents

Refresh ............................................................................. 7-31

Row Activation ................................................................. 7-31

Column Read/Write ......................................................... 7-31

Row Precharge .................................................................. 7-31

Internal Bank ................................................................... 7-32

External Bank ................................................................... 7-32

Memory Size .................................................................... 7-32

Burst Length .................................................................... 7-32

Burst Type ........................................................................ 7-32

CAS Latency .................................................................... 7-33

Data I/O Mask Function .................................................. 7-33

SDRAM Commands ........................................................ 7-33

Mode Register Set (MRS) command ................................. 7-33

Extended Mode Register Set (EMRS) command ................ 7-33

Bank Activate command ................................................... 7-33

Read/Write command ....................................................... 7-34

Precharge/Precharge All Command ................................... 7-34

Auto-refresh command ..................................................... 7-34

Enter Self-Refresh Mode ................................................... 7-34

Exit Self-Refresh Mode ..................................................... 7-34

SDC Timing Specifications ................................................... 7-35

t

................................................................................ 7-35

MRD

t

................................................................................. 7-35

RAS

tCL ................................................................................... 7-35

xiv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

t

................................................................................. 7-36

RCD

t

................................................................................. 7-36

RRD

tWR .................................................................................. 7-36

tRP .................................................................................... 7-36

tRC ................................................................................... 7-37

t

................................................................................. 7-37

RFC

t

.................................................................................. 7-37

XSR

t

.................................................................................. 7-37

REF

t

................................................................................. 7-38

REFI

SDC Functional Description ....................................................... 7-38

SDC Operation .................................................................... 7-38

SDC Address Muxing ........................................................ 7-41

Multibank Operation ........................................................ 7-42

Core and DMA Arbitration ............................................... 7-43

Changing System Clock During Runtime .......................... 7-44

Changing Power Management During Runtime ................. 7-45

Deep Sleep Mode .......................................................... 7-45

Hibernate State ............................................................. 7-45

SDC Commands ................................................................... 7-46

Mode Register Set Command ............................................ 7-47

Extended Mode Register Set Command (Mobile SDRAM) 7-48

Bank Activation Command ............................................... 7-49

Read/Write Command ...................................................... 7-49

ADSP-BF52x Blackfin Processor Hardware Reference xv

Contents

Write Command With Data Mask .................................... 7-50

Single Precharge Command .............................................. 7-51

Precharge All Command ................................................... 7-51

Auto-Refresh Command ................................................... 7-51

Self-Refresh Mode ............................................................ 7-52

Self-Refresh Entry Command ................................... 7-52

Self-Refresh Exit Command ..................................... 7-52

No Operation Command .................................................. 7-53

SDC SA10 Pin ...................................................................... 7-54

SDC Programming Model .......................................................... 7-54

SDC Configuration .............................................................. 7-54

Example SDRAM System Block Diagrams ............................. 7-56

SDC Register Definitions ........................................................... 7-59

EBIU_SDRRC Register ........................................................ 7-59

EBIU_SDBCTL Register ...................................................... 7-61

Using SDRAMs With Systems Smaller than 16M byte ....... 7-63

EBIU_SDGCTL Register ...................................................... 7-65

SDRAM clock enable (SCTLE) ....................................... 7-65

CAS latency (CL) ............................................................ 7-67

Partial array self refresh (PASR) ........................................ 7-67

Bank activate command delay (TRAS) ............................. 7-68

Bank precharge delay (TRP) ............................................ 7-68

RAS to CAS delay (TRCD) ............................................. 7-68

Write to precharge delay (TWR) ....................................... 7-69

xvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Power-Up Start Delay (PUPSD) ........................................ 7-69

Power-Up Sequence Mode (PSM) ...................................... 7-70

Power-Up Sequence Start Enable (PSSE) .......................... 7-70

Self-Refresh Setting (SRFS) .............................................. 7-71

Enter Self-Refresh Mode ................................................ 7-71

Exit Self-Refresh Mode .................................................. 7-72

External buffering enabled (EBUFE) ................................ 7-72

Fast Back-to-Back Read to Write (FBBRW) ....................... 7-73

Extended Mode Register Enabled (EMREN) ..................... 7-73

Temperature Compensated Self-Refresh (TCSR) ................ 7-74

EBIU_SDSTAT Register ........................................................ 7-74

SDC Programming Examples ...................................................... 7-76

HOST DMA PORT

Overview ...................................................................................... 8-1

Features ........................................................................................ 8-2

Interface Overview ........................................................................ 8-3

Description of Operation .............................................................. 8-3

Architecture ............................................................................ 8-4

Functional Description ............................................................ 8-5

HOSTDP Configuration .................................................... 8-5

HOSTDP Transactions ....................................................... 8-7

Host Read Status ............................................................. 8-8

Host Read Data and Host Write Data Operations ............ 8-9

HOSTDP Modes of Operation ......................................... 8-10

ADSP-BF52x Blackfin Processor Hardware Reference xvii

Contents

Acknowledge Mode ...................................................... 8-11

Acknowledge Mode Timing Diagrams ...................... 8-11

Host Bus Timeout .................................................... 8-13

Interrupt Mode ............................................................. 8-14

DMA STOP Mode and AUTOBUFFER Mode ................. 8-16

Bus Widths and Endian Order .......................................... 8-16

Access Control .................................................................. 8-17

Improving HOSTDP DMA Bus Bandwidth ...................... 8-18

Control Commands Between the

External Host and HOSTDP ......................................... 8-19

Programming Model ................................................................... 8-21

Host DMA Port Registers ........................................................... 8-26

HOSTDP Control (HOST_CONTROL) Register ................ 8-26

HOSTDP Status (HOST_STATUS) Register ........................ 8-28

HOSTDP Timeout (HOST_TIMEOUT) Register ................ 8-31

Programming Examples .............................................................. 8-32

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 9-1

Features ........................................................................................ 9-2

Interface Overview ....................................................................... 9-3

External Interface .................................................................... 9-4

Port F Structure .................................................................. 9-4

Port G Structure ................................................................. 9-5

Port H Structure ................................................................. 9-7

xviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Port J Structure ................................................................... 9-9

Input Tap Considerations .................................................... 9-9

Internal Interfaces ................................................................. 9-10

Internal Signals ................................................................. 9-10

Performance/Throughput ...................................................... 9-11

Description of Operation ............................................................ 9-12

Operation ............................................................................. 9-12

General-Purpose I/O Modules ............................................... 9-13

GPIO Interrupt Processing .................................................... 9-16

Programming Model ................................................................... 9-22

GPIO Drive Hysteresis Control ................................................... 9-24

Portx Control (PORTx_HYSTERESIS) Register .................... 9-24

Hysteresis Control Register .................................................... 9-26

TWI Drive Strength Control Register .......................................... 9-27

Memory-Mapped GPIO Registers ............................................... 9-27

Port Multiplexer Control Register (PORTx_MUX) ................ 9-28

Function Enable Registers (PORTx_FER) .............................. 9-30

GPIO Direction Registers (PORTxIO_DIR) .......................... 9-31

GPIO Input Enable Registers (PORTxIO_INEN) .................. 9-32

GPIO Data Registers (PORTxIO) .......................................... 9-32

GPIO Set Registers (PORTxIO_SET) .................................... 9-33

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-33

GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 9-34

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-34

ADSP-BF52x Blackfin Processor Hardware Reference xix

Contents

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................ 9-35

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ........ 9-35

GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 9-36

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 9-37

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 9-39

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 9-41

Programming Examples .............................................................. 9-42

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF52x .................................. 10-1

Overview .................................................................................... 10-2

External Interface .................................................................. 10-3

Internal Interface .................................................................. 10-4

Description of Operation ............................................................ 10-4

Interrupt Processing .............................................................. 10-5

Illegal States .......................................................................... 10-7

Modes of Operation ................................................................. 10-10

Pulse Width Modulation (PWM_OUT) Mode .................... 10-10

Output Pad Disable ........................................................ 10-12

Single Pulse Generation .................................................. 10-12

Pulse Width Modulation Waveform Generation .............. 10-13

PULSE_HI Toggle Mode ................................................ 10-15

Externally Clocked PWM_OUT ..................................... 10-20

xx ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Using PWM_OUT Mode With the PPI .......................... 10-21

Stopping the Timer in PWM_OUT Mode ....................... 10-21

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 10-23

Autobaud Mode .............................................................. 10-31

External Event (EXT_CLK) Mode ....................................... 10-31

Programming Model ................................................................. 10-33

Timer Registers ......................................................................... 10-34

Timer Enable Register (TIMER_ENABLE) .......................... 10-35

Timer Disable Register (TIMER_DISABLE) ........................ 10-36

Timer Status Register (TIMER_STATUS) ............................ 10-37

Timer Configuration Register (TIMER_CONFIG) .............. 10-40

Timer Counter Register (TIMER_COUNTER) ................... 10-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................. 10-43

Summary ............................................................................ 10-46

Programming Examples ............................................................. 10-48

Unique Behavior for the ADSP-BF52x Processor ....................... 10-57

Interface Overview .............................................................. 10-58

External Interface ............................................................ 10-58

CORE TIMER

Specific Information for the ADSP-BF52x ................................... 11-1

Overview and Features ................................................................ 11-1

Timer Overview .......................................................................... 11-2

External Interfaces ................................................................. 11-2

ADSP-BF52x Blackfin Processor Hardware Reference xxi

Contents

Internal Interfaces ................................................................. 11-3

Description of Operation ............................................................ 11-3

Interrupt Processing .............................................................. 11-3

Core Timer Registers .................................................................. 11-4

Core Timer Control Register (TCNTL) ................................. 11-5

Core Timer Count Register (TCOUNT) ............................... 11-5

Core Timer Period Register (TPERIOD) ............................... 11-6

Core Timer Scale Register (TSCALE) .................................... 11-7

Programming Examples .............................................................. 11-7

Unique Behavior for the ADSP-BF52x Processor ......................... 11-9

WAT CH DOG TIMER

Specific Information for the ADSP-BF52x .................................. 12-1

Overview and Features ................................................................ 12-1

Interface Overview ..................................................................... 12-3

External Interface .................................................................. 12-3

Internal Interface .................................................................. 12-3

Description of Operation ............................................................ 12-4

Register Definitions .................................................................... 12-5

Watchdog Count (WDOG_CNT) Register ........................... 12-5

Watchdog Status (WDOG_STAT) Register ........................... 12-6

Watchdog Control (WDOG_CTL) Register .......................... 12-7

Programming Examples .............................................................. 12-8

Unique Information for the ADSP-BF52x Processor .................. 12-11

xxii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

GENERAL-PURPOSE COUNTER

Specific Information for the ADSP-BF52x ................................... 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ...................................................................... 13-3

Description of Operation ............................................................ 13-4

Quadrature Encoder Mode .................................................... 13-4

Binary Encoder Mode ............................................................ 13-5

Up/Down Counter Mode ...................................................... 13-6

Direction Counter Mode ....................................................... 13-7

Timed Direction Mode .......................................................... 13-7

Functional Description ............................................................... 13-7

Input Noise Filtering (Debouncing) ....................................... 13-8

Zero Marker (Push Button) Operation ................................... 13-9

Boundary Comparison Modes .............................................. 13-10

Control and Signaling Events ............................................... 13-12

Illegal Gray/Binary Code Events ...................................... 13-12

Up/Down Count Events .................................................. 13-12

Zero-Count Events ......................................................... 13-13

Overflow Events .............................................................. 13-13

Boundary Match Events .................................................. 13-13

Zero Marker Events ......................................................... 13-14

Capturing Timing Information ............................................ 13-14

ADSP-BF52x Blackfin Processor Hardware Reference xxiii

Contents

Capturing Time Interval Between

Successive Counter Events ............................................ 13-15

Capturing Counter Interval and

CNT_COUNTER Read Timing .................................. 13-16

Programming Model ................................................................. 13-18

Registers ................................................................................... 13-19

Counter Module Register Overview ..................................... 13-19

Counter Configuration Register (CNT_CONFIG) .............. 13-20

Counter Interrupt Mask Register (CNT_IMASK) ................ 13-20

Counter Status Register (CNT_STATUS) ............................ 13-21

Counter Command Register (CNT_COMMAND) ............. 13-22

Counter Debounce Register (CNT_DEBOUNCE) .............. 13-24

Counter Count Value Register (CNT_COUNTER) ............ 13-25

Counter Boundary Registers (CNT_MIN and CNT_MAX) . 13-26

Programming Examples ............................................................ 13-27

Unique Behavior for the ADSP-BF52x Processor ....................... 13-38

REAL-TIME CLOCK

Specific Information for the ADSP-BF52x .................................. 14-1

Overview .................................................................................... 14-1

Interface Overview ..................................................................... 14-3

Description of Operation ............................................................ 14-4

RTC Clock Requirements ..................................................... 14-5

Prescaler Enable .................................................................... 14-5

RTC Programming Model .......................................................... 14-7

xxiv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Register Writes ...................................................................... 14-8

Write Latency ........................................................................ 14-9

Register Reads ..................................................................... 14-10

Deep Sleep .......................................................................... 14-10

Event Flags .......................................................................... 14-11

Setting Time of Day ............................................................ 14-13

Using the Stopwatch ............................................................ 14-13

Interrupts ............................................................................ 14-14

State Transitions Summary ................................................... 14-16

Register Definitions .................................................................. 14-19

RTC Status (RTC_STAT) Register ....................................... 14-20

RTC Interrupt Control (RTC_ICTL) Register ..................... 14-20

RTC Interrupt Status (RTC_ISTAT) Register ....................... 14-21

RTC Stopwatch Count (RTC_SWCNT) Register ................. 14-21

RTC Alarm (RTC_ALARM) Register ................................... 14-22

RTC Prescaler Enable (RTC_PREN) Register ....................... 14-22

Programming Examples ............................................................. 14-22

Enable RTC Prescaler .......................................................... 14-23

RTC Stopwatch For Exiting Deep Sleep Mode ..................... 14-23

RTC Alarm to Come Out of Hibernate State ....................... 14-25

Unique Information for the ADSP-BF52x Processor .................. 14-27

PARALLEL PERIPHERAL INTERFACE

Specific Information for the ADSP-BF52x ................................... 15-1

Overview .................................................................................... 15-2

ADSP-BF52x Blackfin Processor Hardware Reference xxv

Contents

Features ...................................................................................... 15-2

Interface Overview ..................................................................... 15-3

Description of Operation ............................................................ 15-4

Functional Description ............................................................... 15-5

ITU-R 656 Modes ................................................................ 15-5

ITU-R 656 Background .................................................... 15-5

ITU-R 656 Input Modes .................................................. 15-9

Entire Field .................................................................. 15-9

Active Video Only ...................................................... 15-10

Vertical Blanking Interval (VBI) only .......................... 15-10

ITU-R 656 Output Mode ............................................... 15-11

Frame Synchronization in ITU-R 656 Modes .................. 15-11

General-Purpose PPI Modes ................................................ 15-12

Data Input (RX) Modes .................................................. 15-14

No Frame Syncs .......................................................... 15-15

1, 2, or 3 External Frame Syncs ................................... 15-16

2 or 3 Internal Frame Syncs ........................................ 15-16

Data Output (TX) Modes ............................................... 15-17

No Frame Syncs .......................................................... 15-17

1 or 2 External Frame Syncs ........................................ 15-18

1, 2, or 3 Internal Frame Syncs ................................... 15-19

Frame Synchronization in GP Modes .............................. 15-20

Modes With Internal Frame Syncs ............................... 15-20

Modes With External Frame Syncs .............................. 15-21

xxvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Programming Model ................................................................. 15-22

DMA Operation .................................................................. 15-23

PPI Registers ............................................................................. 15-26

PPI Control Register (PPI_CONTROL) ............................. 15-26

PPI Status Register (PPI_STATUS) ...................................... 15-31

PPI Delay Count Register (PPI_DELAY) ............................. 15-34

PPI Transfer Count Register (PPI_COUNT) ....................... 15-34

PPI Lines Per Frame Register (PPI_FRAME) ........................ 15-35

Programming Examples ............................................................. 15-37

Unique Behavior for the ADSP-BF52x Processor ....................... 15-39

SECURITY

Overview .................................................................................... 16-1

Features ...................................................................................... 16-4

Description of Operation ............................................................ 16-6

Secure State Machine ............................................................. 16-7

Open Mode ...................................................................... 16-8

Secure Entry Mode ........................................................... 16-8

Secure Mode ..................................................................... 16-9

SecureMode Control ....................................................... 16-11

Security Features ................................................................. 16-13

Digital Signature Authentication ..................................... 16-13

Digital Signature Authentication

Performance Measurement ............................................ 16-16

Protection Features .............................................................. 16-16

ADSP-BF52x Blackfin Processor Hardware Reference xxvii

Contents

Operating in Secure Mode ................................................... 16-20

Entering Secure Mode .................................................... 16-20

Exiting Secure Mode ....................................................... 16-21

Reset Handling in Secure Mode ........................................... 16-21

Hardware Reset .............................................................. 16-21

Clearing Private Data ...................................................... 16-22

Public Key Requirements .................................................... 16-24

Storing Public Cipher Key in Public OTP ....................... 16-26

Cryptographic Ciphers ........................................................ 16-27

Keys ................................................................................... 16-27

Debug Functionality .......................................................... 16-27

Programming Examples .................................................. 16-31

Programming Model ................................................................. 16-32

Secure Entry Service Routine (SESR) API ............................ 16-32

Starting Authentication ....................................................... 16-33

Memory Configuration ....................................................... 16-34

Message Placement ......................................................... 16-35

Digital Signature ............................................................ 16-35

Message Size Constraints ................................................ 16-35

Memory Usage ............................................................... 16-36

Memory Protection ......................................................... 16-36

Secure Function and Secure Entry Service Routine Arguments 16-36

Secure Function Arguments ............................................ 16-37

Secure Entry Service Routine Arguments ......................... 16-38

xxviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

usFlags ............................................................................ 16-38

uslRQMask ..................................................................... 16-39

ulMessageSize ................................................................. 16-40

ulSFEntryPoint ............................................................... 16-40

ulMessagePtr ................................................................... 16-40

Secure Message Execution ............................................... 16-40

Return Codes .................................................................. 16-41

Secure Hash Algorithm (SHA-1) API ............................... 16-43

ADI_SHA1 Data Type ................................................ 16-43

bfrom_Sha1Init ROM Routine .................................... 16-44

bfrom_Sha1Hash ROM Routine ................................. 16-44

Security Registers ...................................................................... 16-45

Secure System Switch (SECURE_SYSSWT) Register ............ 16-46

Secure Control (SECURE_CONTROL) Register ................. 16-52

Secure Status (SECURE_STATUS) Register ......................... 16-55

SYSTEM RESET AND BOOTING

Overview .................................................................................... 17-1

Reset and Power-up .................................................................... 17-4

Hardware Reset ..................................................................... 17-6

Software Resets ...................................................................... 17-7

Reset Vector .......................................................................... 17-8

Servicing Reset Interrupts .................................................... 17-10

Preboot ..................................................................................... 17-11

Factory Page Settings (FPS) ................................................. 17-14

ADSP-BF52x Blackfin Processor Hardware Reference xxix

Contents

Preboot Page Settings (PBS) ................................................ 17-14

Alternative PBS Pages ..................................................... 17-16

Programming PBS Pages ................................................. 17-16

Recovering From Misprogrammed PBS Pages .................. 17-17

Customizing Power Management .................................... 17-17

Customizing Booting Options ........................................ 17-18

Customizing the Asynchronous Port ................................ 17-19

Customizing the Synchronous Port ................................. 17-20

Basic Booting Process ............................................................... 17-21

Block Headers ..................................................................... 17-23

Block Code .................................................................... 17-25

DMA Code Field ........................................................ 17-25

Block Flags Field ......................................................... 17-27

Header Checksum Field .............................................. 17-28

Header Sign Field ....................................................... 17-29

Target Address ................................................................ 17-29

Byte Count ..................................................................... 17-30

Argument ....................................................................... 17-31

Boot Host Wait (HWAIT) Feedback Strobe ......................... 17-31

Using HWAIT as Reset Indicator .................................... 17-32

Boot Termination ............................................................... 17-33

Single Block Boot Streams ................................................... 17-34

Direct Code Execution ................................................... 17-34

Advanced Boot Techniques ....................................................... 17-37

xxx ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Initialization Code ............................................................... 17-37

Quick Boot ......................................................................... 17-41

Indirect Booting .................................................................. 17-42

Callback Routines ............................................................... 17-43

Error Handler ..................................................................... 17-46

CRC Checksum Calculation ................................................ 17-46

Load Functions ................................................................... 17-47

Calling the Boot Kernel at Runtime ..................................... 17-48

Debugging the Boot Process ................................................ 17-49

Boot Management ..................................................................... 17-51

Booting a Different Application ........................................... 17-52

Multi-DXE Boot Streams ................................................ 17-53

Determining Boot Stream Start Addresses ........................ 17-57

Initialization Hook Routine ............................................ 17-57

Specific Boot Modes .................................................................. 17-58

No Boot Mode .................................................................... 17-59

Flash Boot Modes ................................................................ 17-59

SDRAM Boot Mode ............................................................ 17-63

FIFO Boot Mode ................................................................ 17-63

SPI Master Boot Modes ....................................................... 17-65

SPI Device Detection Routine ......................................... 17-67

SPI Slave Boot Mode ........................................................... 17-69

TWI Master Boot Mode ...................................................... 17-72

TWI Slave Boot Mode ......................................................... 17-75

ADSP-BF52x Blackfin Processor Hardware Reference xxxi

Contents

UART Slave Mode Boot ...................................................... 17-78

OTP Boot Mode ................................................................. 17-80

Host DMA Boot Modes ...................................................... 17-81

NAND Flash Boot Mode .................................................... 17-86

Supported Devices .......................................................... 17-86

NAND Flash Page Structure ........................................... 17-89

Auto Detection ............................................................... 17-91

Boot Stream Processing ................................................... 17-91

Software Configurable NAND Flash Boot Modes ............ 17-93

Sequential Block Mode ............................................... 17-94

Block Skip Mode ........................................................ 17-95

Multiple Image Mode ................................................. 17-96

Reset and Booting Registers ...................................................... 17-98

Software Reset (SWRST) Register ....................................... 17-99

System Reset Configuration (SYSCR) Register ................... 17-100

Boot Code Revision Control (BK_REVISION) ................. 17-103

Boot Code Date Code (BK_DATECODE) ........................ 17-104

Zero Word (BK_ZEROS) .................................................. 17-105

Ones Word (BK_ONES) ................................................... 17-106

OTP Memory Pages for Booting ............................................. 17-106

Lower PBS00 Half Page .................................................... 17-106

Upper PBS00 Half Page .................................................... 17-110

Lower PBS01 Half Page .................................................... 17-111

Upper PBS01 Half Page .................................................... 17-111

xxxii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Lower PBS02 Half Page ..................................................... 17-114

Upper PBS02 Half Page ..................................................... 17-115

Reserved Half Pages ........................................................... 17-115

Data Structures ....................................................................... 17-115

ADI_BOOT_HEADER .................................................... 17-115

ADI_BOOT_BUFFER ...................................................... 17-116

ADI_BOOT_DATA .......................................................... 17-116

dFlags Word ................................................................. 17-120

ADI_BOOT_NAND ........................................................ 17-121

ADI_BOOT_NAND_DEVICE ........................................ 17-122

ADI_BOOT_NAND_BUFFER ........................................ 17-124

ADI_BOOT_NAND_ACCESS ......................................... 17-125

ADI_BOOT_NAND_ADDRESS ...................................... 17-125

ADI_BOOT_NAND_ECC ............................................... 17-127

Callable ROM Functions for Booting ...................................... 17-129

BFROM_FINALINIT ....................................................... 17-129

BFROM_PDMA ............................................................... 17-129

BFROM_MDMA ............................................................ 17-130

BFROM_MEMBOOT ...................................................... 17-130

BFROM_TWIBOOT ....................................................... 17-132

BFROM_SPIBOOT .......................................................... 17-132

BFROM_OTPBOOT ....................................................... 17-133

BFROM_NANDBOOT .................................................... 17-134

BFROM_BOOTKERNEL ................................................ 17-135

ADSP-BF52x Blackfin Processor Hardware Reference xxxiii

Contents

BFROM_CRC32 .............................................................. 17-136

BFROM_CRC32POLY ..................................................... 17-136

BFROM_CRC32CALLBACK ........................................... 17-137

BFROM_CRC32INITCODE ........................................... 17-137

Programming Examples .......................................................... 17-138

System Reset ..................................................................... 17-138

Exiting Reset to User Mode ............................................... 17-139

Exiting Reset to Supervisor Mode ...................................... 17-139

Initcode (SDRAM Controller Setup) ................................. 17-140

Initcode (Power Management Control) .............................. 17-142

Initcode (NAND Flash Boot Mode Configuration) ............ 17-144

Quickboot With Restore From SDRAM ............................ 17-145

XOR Checksum ................................................................ 17-146

Direct Code Execution ...................................................... 17-148

Managing PBS Pages in OTP Memory ............................... 17-149

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control ....................................... 18-1

PLL Overview ....................................................................... 18-2

PLL Clock Multiplier Ratios ................................................. 18-3

Core Clock/System Clock Ratio Control ........................... 18-5

Dynamic Power Management Controller ..................................... 18-7

Operating Modes .................................................................. 18-8

Dynamic Power Management Controller States ...................... 18-8

Full-On Mode ................................................................. 18-8

xxxiv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Active Mode .................................................................... 18-9

Sleep Mode ...................................................................... 18-9

Deep Sleep Mode ........................................................... 18-10

Hibernate State .............................................................. 18-11

Operating Mode Transitions ................................................ 18-11

Programming Operating Mode Transitions ........................... 18-14

Dynamic Supply Voltage Control ......................................... 18-16

Power Supply Management .................................................. 18-17

Controlling the Internal Voltage Regulator ...................... 18-19

Changing Voltage on

ADSP-BF523/ADSP-BF525/ADSP-BF527 ................... 18-19

Changing Voltage on

ADSP-BF522/ADSP-BF524/ADSP-BF526 ................... 18-21

Powering Down the Core (Hibernate State) ..................... 18-22

PLL and VR Registers ............................................................... 18-25

PLL_DIV Register ............................................................... 18-26

PLL_CTL Register .............................................................. 18-26

PLL_STAT Register ............................................................. 18-28

PLL_LOCKCNT Register ................................................... 18-28

VR_CTL Register ................................................................ 18-28

System Control ROM Function ................................................. 18-30

Programming Model ............................................................ 18-32

Accessing the System Control ROM Function in C/C++ ...... 18-32

Accessing the System Control ROM Function in Assembly ... 18-33

Programming Examples ............................................................. 18-36

ADSP-BF52x Blackfin Processor Hardware Reference xxxv

Contents

Full-on Mode to Active Mode and Back ............................... 18-37

Transition to Sleep Mode or Deep Sleep Mode ..................... 18-39

Set Wakeups and Entering Hibernate State .......................... 18-40

Perform a System Reset or Soft-Reset ................................... 18-42

In Full-on Mode, Change VCO Frequency,

Core Clock Frequency, and System

Clock Frequency .............................................................. 18-43

Changing Voltage Levels ..................................................... 18-45

SYSTEM DESIGN

Pin Descriptions ......................................................................... 19-1

Managing Clocks ........................................................................ 19-1

Managing Core and System Clocks ........................................ 19-2

Configuring and Servicing Interrupts .......................................... 19-2

Semaphores ................................................................................ 19-2

Example Code for Query Semaphore ..................................... 19-3

Data Delays, Latencies and Throughput ...................................... 19-4

Bus Priorities .............................................................................. 19-4

External Memory Design Issues ................................................... 19-4

Example Asynchronous Memory Interfaces ............................ 19-5

Avoiding Bus Contention ..................................................... 19-7

High-Frequency Design Considerations ...................................... 19-7

Signal Integrity ..................................................................... 19-8

Decoupling Capacitors and Ground Planes ............................ 19-9

5 Volt Tolerance .................................................................. 19-11

xxxvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Test Point Access ................................................................. 19-11

Oscilloscope Probes ............................................................. 19-11

Recommended Reading ....................................................... 19-11

Resetting the Processor .............................................................. 19-13

Recommendations for Unused Pins ........................................... 19-13

Programmable Outputs ............................................................. 19-13

USB System Hardware Design ................................................... 19-14

Voltage Regulator System Hardware Design ............................... 19-15

For VRSEL = Logic 0, Internal Regulator, SS Mode ............. 19-16

For VRSEL = Logic 1, External Regulator, PG Mode ............ 19-16

NAND FLASH CONTROLLER

Overview .................................................................................... 20-1

Features ...................................................................................... 20-2

Interface Overview ...................................................................... 20-3

Description of Operation ............................................................ 20-3

Internal Bus Interfaces ........................................................... 20-3

Bus Access Types ................................................................... 20-4

Access Timing ....................................................................... 20-5

Functional Description ............................................................... 20-6

Page Write ............................................................................. 20-6

Page Read ............................................................................. 20-7

Additional Operations ........................................................... 20-8

Write Protection .................................................................... 20-9

Chip Enable Don’t Care ........................................................ 20-9

ADSP-BF52x Blackfin Processor Hardware Reference xxxvii

Contents

NFC Error Detection ............................................................ 20-9

Error Analysis ................................................................. 20-10

Large Page Size Support .................................................. 20-12

NFC SmartMedia Support .................................................. 20-12

Programming Model ................................................................. 20-13

NFC Registers .......................................................................... 20-14

NFC Control (NFC_CTL) Register .................................... 20-16

NFC Status (NFC_STAT) Register ...................................... 20-16

NFC Interrupt Status (NFC_IRQSTAT) Register ................ 20-17

NFC Interrupt Mask (NFC_IRQMASK) Register ................ 20-19

NFC ECC (NFC_ECCx) Registers ..................................... 20-19

NFC Count (NFC_COUNT) Register ................................ 20-20

NFC Reset (NFC_RST) Register ......................................... 20-21

NFC Page Control (NFC_PGCTL) Register ........................ 20-21

NFC Read Data (NFC_READ) Register .............................. 20-22

NFC Address (NFC_ADDR) Register ................................. 20-23

NFC Command (NFC_CMD) Register .............................. 20-23

NFC Data Write (NFC_DATA_WR) Register ..................... 20-24

NFC Data Read (NFC_DATA_RD) Register ....................... 20-25

NFC Programming Examples ................................................... 20-25

ETHERNET MAC

Specific Information for the ADSP-BF52x .................................. 21-1

Overview .................................................................................... 21-2

Features ................................................................................ 21-2

xxxviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Interface Overview ...................................................................... 21-3

External Interface .................................................................. 21-4

Clocking ........................................................................... 21-4

Pins .................................................................................. 21-5

Internal Interface ................................................................... 21-7

Power Management ........................................................... 21-7

Description of Operation ............................................................ 21-7

Protocol ................................................................................ 21-8

MII Management Interface ................................................ 21-8

Operation ........................................................................... 21-10

MII Management Interface Operation ............................. 21-10

Receive DMA Operation ................................................. 21-11

Frame Reception and Filtering ..................................... 21-13

Discarded Frames ................................................... 21-15

Aborted Frames ...................................................... 21-16

Control Frames ....................................................... 21-16

Examples ................................................................ 21-16

RX Automatic Pad Stripping ....................................... 21-17

RX DMA Data Alignment ........................................... 21-17

RX DMA Buffer Structure ........................................... 21-18

RX Frame Status Buffer ............................................... 21-19

RX Frame Status Classification .................................... 21-19

RX IP Frame Checksum Calculation ............................ 21-21

RX DMA Direction Errors .......................................... 21-22

ADSP-BF52x Blackfin Processor Hardware Reference xxxix

Contents

Transmit DMA Operation .............................................. 21-23

Power Management ........................................................ 21-30

Ethernet Event Interrupts ............................................... 21-39

Flexible Descriptor Structure ....................................... 21-26

TX DMA Data Alignment .......................................... 21-27

Late Collisions ............................................................ 21-28

TX Frame Status Classification ................................... 21-28

TX DMA Direction Errors .......................................... 21-29

Ethernet Operation in the Sleep State .......................... 21-32

Magic Packet Detection .............................................. 21-34

Remote Wake-up Filters .............................................. 21-34

RX/TX Frame Status Interrupt Operation ................... 21-42

RX Frame Status Register Operation at

Startup and Shutdown ............................................. 21-42

TX Frame Status Register Operation at

Startup and Shutdown ............................................. 21-43

MAC Management Counters .......................................... 21-43

Programming Model ................................................................. 21-46

Configure MAC Pins .......................................................... 21-46

Multiplexing Scheme ...................................................... 21-46

CLKBUF ....................................................................... 21-47

Configure Interrupts .......................................................... 21-47

Configure MAC Registers ................................................... 21-48

MAC Address ................................................................. 21-48

MII Station Management ................................................ 21-48

xl ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Configure PHY ................................................................... 21-49

Receive and Transmit Data .................................................. 21-50

Receiving Data ................................................................ 21-50

Transmitting Data ........................................................... 21-51

Ethernet MAC Register Definitions ........................................... 21-51

Control-Status Register Group ............................................. 21-60

MAC Operating Mode (EMAC_OPMODE) Register ...... 21-61

MAC Address Low (EMAC_ADDRLO) Register ............. 21-67

MAC Address High Register (EMAC_ADDRHI) Register 21-68

MAC Multicast Hash Table High (EMAC_HASHHI)

and Low (EMAC_HASHLO) Registers ......................... 21-69

MAC Station Management Address

(EMAC_STAADD) Register ......................................... 21-72

MAC Station Management Data

(EMAC_STADAT) Register ......................................... 21-74

MAC Flow Control (EMAC_FLC) Register ..................... 21-75

MAC VLAN1 Tag (EMAC_VLAN1)

and MAC VLAN2 Tag (EMAC_VLAN2)Registers ........ 21-77

MAC Wakeup Frame Control and Status

(EMAC_WKUP_CTL) Register ................................... 21-78

MAC Wakeup Frame0 Byte Mask (EMAC_WKUP_FFMSK0)

MAC Wakeup Frame1 Byte Mask (EMAC_WKUP_FFMSK1)
MAC Wakeup Frame2 Byte Mask (EMAC_WKUP_FFMSK2)
MAC Wakeup Frame3 Byte Mask (EMAC_WKUP_FFMSK3)

Registers ...................................................................... 21-81

MAC Wakeup Frame Filter Commands

(EMAC_WKUP_FFCMD) Register ............................. 21-86

ADSP-BF52x Blackfin Processor Hardware Reference xli

Contents

Ethernet MAC Wakeup Frame Filter Offsets

(EMAC_WKUP_FFOFF) Register ............................... 21-88

MAC Wakeup Frame Filter CRC0/1 (EMAC_WKUP_FFCRC0)

and CRC2/3 (EMAC_WKUP_FFCRC1) Registers ....... 21-88

System Interface Register Group .......................................... 21-89

MAC System Control (EMAC_SYSCTL) Register ........... 21-90

MAC System Status (EMAC_SYSTAT) Register .............. 21-91

Ethernet MAC Frame Status Registers ................................. 21-94

Ethernet MAC RX Current Frame Status

(EMAC_RX_STAT) Register ....................................... 21-94

Ethernet MAC RX Sticky Frame Status

(EMAC_RX_STKY) Register ..................................... 21-100

Ethernet MAC RX Frame Status Interrupt Enable

(EMAC_RX_IRQE) Register ..................................... 21-104

Ethernet MAC TX Current Frame Status (EMAC_TX_STAT)

Register ..................................................................... 21-105

Ethernet MAC TX Sticky Frame Status

(EMAC_TX_STKY) Register ..................................... 21-109

Ethernet MAC TX Frame Status Interrupt Enable

(EMAC_TX_IRQE) Register ..................................... 21-112

Ethernet MAC MMC RX Interrupt Status

(EMAC_MMC_RIRQS) Register ............................... 21-112

Ethernet MAC MMC RX Interrupt Enable

(EMAC_MMC_RIRQE) Register .............................. 21-114

Ethernet MAC MMC TX Interrupt Status

(EMAC_MMC_TIRQS) Register .............................. 21-116

Ethernet MAC MMC TX Interrupt Enable

(EMAC_MMC_TIRQE) Register .............................. 21-118

xlii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

MAC Management Counter Registers ................................ 21-120

MAC Management Counters Control

(EMAC_MMC_CTL) Register ................................... 21-121

Programming Examples ........................................................... 21-122

Ethernet Structures ............................................................ 21-123

MAC Address Setup .......................................................... 21-126

PHY Control Routines ...................................................... 21-126

Unique Behavior for the ADSP-BF52x Processor ..................... 21-128

SPI-COMPATIBLE PORT CONTROLLER

Specific Information for the ADSP-BF52x ................................... 22-1

Overview .................................................................................... 22-2

Features ...................................................................................... 22-2

Interface Overview ...................................................................... 22-3

External Interface .................................................................. 22-4

SPI Clock Signal (SCK) ................................................... 22-4

Master-Out, Slave-In (MOSI) Signal ................................. 22-5

Master-In, Slave-Out (MISO) Signal ................................. 22-5

SPI Slave Select Input Signal (SPISS) ................................. 22-6

SPI Slave Select Enable Output Signals .............................. 22-7

Slave Select Inputs ............................................................ 22-8

Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems 22-8

Internal Interfaces ............................................................... 22-11

DMA Functionality ........................................................ 22-11

Description of Operation .......................................................... 22-12

ADSP-BF52x Blackfin Processor Hardware Reference xliii

Contents

SPI Transfer Protocols ......................................................... 22-12

SPI General Operation ........................................................ 22-15

Clock Signals ...................................................................... 22-16

Interrupt Output ................................................................ 22-17

Functional Description ............................................................. 22-17

Master Mode Operation (Non-DMA) .................................. 22-18

Transfer Initiation From Master (Transfer Modes) ................ 22-19

Slave Mode Operation (Non-DMA) .................................... 22-20

Slave Ready for a Transfer .................................................... 22-22

Programming Model ................................................................. 22-22

Beginning and Ending an SPI Transfer ................................ 22-22

Master Mode DMA Operation ............................................ 22-24

Slave Mode DMA Operation ............................................... 22-27

SPI Registers ............................................................................ 22-34

SPI Baud Rate (SPI_BAUD) Register .................................. 22-34

SPI Control (SPI_CTL) Register ......................................... 22-35

SPI Flag (SPI_FLG) Register ............................................... 22-38

SPI Status (SPI_STAT) Register ........................................... 22-40

Mode Fault Error (MODF) ............................................. 22-41

Transmission Error (TXE) .............................................. 22-42

Reception Error (RBSY) ................................................. 22-42

Transmit Collision Error (TXCOL) ................................. 22-42

SPI Transmit Data Buffer (SPI_TDBR) Register .................. 22-42

SPI Receive Data Buffer (SPI_RDBR) Register .................... 22-43

xliv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

SPI RDBR Shadow (SPI_SHADOW) Register ..................... 22-44

Programming Examples ............................................................. 22-45

Core-Generated Transfer ...................................................... 22-45

Initialization Sequence .................................................... 22-45

Starting a Transfer ........................................................... 22-46

Post Transfer and Next Transfer ....................................... 22-47

Stopping ......................................................................... 22-48

DMA-Based Transfer ........................................................... 22-48

DMA Initialization Sequence .......................................... 22-48

SPI Initialization Sequence .............................................. 22-49

Starting a Transfer ........................................................... 22-51

Stopping a Transfer ......................................................... 22-51

Unique Behavior for the ADSP-BF52x Processor ....................... 22-53

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF52x ................................... 23-1

Overview .................................................................................... 23-2

Interface Overview ...................................................................... 23-3

External Interface .................................................................. 23-4

Serial Clock Signal (SCL) .................................................. 23-4

Serial Data Signal (SDA) ................................................... 23-4

TWI Pins .......................................................................... 23-5

Internal Interfaces ................................................................. 23-5

Description of Operation ............................................................ 23-6

TWI Transfer Protocols ......................................................... 23-6

ADSP-BF52x Blackfin Processor Hardware Reference xlv

Contents

Clock Generation and Synchronization ............................. 23-7

Bus Arbitration ................................................................. 23-8

Start and Stop Conditions ................................................. 23-9

General Call Support ...................................................... 23-10

Fast Mode ...................................................................... 23-10

Functional Description ............................................................. 23-10

General Setup ..................................................................... 23-11

Slave Mode ......................................................................... 23-11

Master Mode Clock Setup ................................................... 23-12

Master Mode Transmit ........................................................ 23-13

Master Mode Receive .......................................................... 23-14

Repeated Start Condition ............................................... 23-15

Transmit/Receive Repeated Start Sequence .................. 23-15

Receive/Transmit Repeated Start Sequence .................. 23-17

Clock Stretching ............................................................. 23-18

Clock Stretching During FIFO Underflow ...................... 23-18

Clock Stretching During FIFO Overflow ........................ 23-20

Clock Stretching During Repeated Start Condition ......... 23-21

Programming Model ................................................................. 23-24

Register Descriptions ................................................................ 23-26

TWI CONTROL Register (TWI_CONTROL) ................... 23-26

SCL Clock Divider Register (TWI_CLKDIV) ..................... 23-27

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ..... 23-28

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) .. 23-30

xlvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 23-30

TWI Master Mode Control Register (TWI_MASTER_CTL) 23-32

TWI Master Mode Address Register (TWI_MASTER_ADDR) 23-34

TWI Master Mode Status Register (TWI_MASTER_STAT) . 23-35

TWI FIFO Control Register (TWI_FIFO_CTL) ................. 23-38

TWI FIFO Status Register (TWI_FIFO_STAT) ................... 23-40

TWI FIFO Status ........................................................... 23-40

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 23-41

TWI Interrupt Status Register (TWI_INT_STAT) ............... 23-42

TWI FIFO Transmit Data Single Byte

Register (TWI_XMT_DATA8) ......................................... 23-45

TWI FIFO Transmit Data Double Byte

Register (TWI_XMT_DATA16) ....................................... 23-45

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8) .......................................... 23-46

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16) ........................................ 23-47

Programming Examples ............................................................. 23-48

Master Mode Setup ............................................................. 23-48

Slave Mode Setup ................................................................ 23-53

Electrical Specifications ............................................................. 23-60

Unique Information for the ADSP-BF52x Processor .................. 23-60

SPORT CONTROLLER

Specific Information for the ADSP-BF52x ................................... 24-1

Overview .................................................................................... 24-2

ADSP-BF52x Blackfin Processor Hardware Reference xlvii

Contents

Features ................................................................................ 24-2

Interface Overview ..................................................................... 24-4

SPORT Pin/Line Terminations .............................................. 24-9

Description of Operation .......................................................... 24-10

SPORT Disable .................................................................. 24-10

Setting SPORT Modes ........................................................ 24-11

Stereo Serial Operation ....................................................... 24-11

Multichannel Operation ...................................................... 24-15

Multichannel Enable ....................................................... 24-18

Frame Syncs in Multichannel Mode ................................ 24-19

The Multichannel Frame ................................................ 24-20

Multichannel Frame Delay .............................................. 24-21

Window Size .................................................................. 24-21

Window Offset ............................................................... 24-22

Other Multichannel Fields in SPORT_MCMC2 ............. 24-22

Channel Selection Register .............................................. 24-23

Multichannel DMA Data Packing ................................... 24-24

Support for H.100 Standard Protocol .................................. 24-25

2× Clock Recovery Control ............................................. 24-25

Functional Description ............................................................. 24-26

Clock and Frame Sync Frequencies ...................................... 24-26

Maximum Clock Rate Restrictions .................................. 24-27

Word Length ...................................................................... 24-28

Bit Order ............................................................................ 24-28

xlviii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Data Type ........................................................................... 24-29

Companding ....................................................................... 24-29

Clock Signal Options .......................................................... 24-30

Frame Sync Options ............................................................ 24-31

Framed Versus Unframed ................................................ 24-31

Internal Versus External Frame Syncs ............................... 24-33

Active Low Versus Active High Frame Syncs .................... 24-34

Sampling Edge for Data and Frame Syncs ........................ 24-34

Early Versus Late Frame Syncs (Normal Versus

Alternate Timing) ........................................................ 24-36

Data Independent Transmit Frame Sync .......................... 24-38

Moving Data Between SPORTs and Memory ....................... 24-39

SPORT RX, TX, and Error Interrupts ................................. 24-39

Peripheral Bus Errors ........................................................... 24-40

Timing Examples ................................................................ 24-40

SPORT Registers ...................................................................... 24-46

Register Writes and Effective Latency ................................... 24-47

SPORT Transmit Configuration

(SPORT_TCR1 and SPORT_TCR2) Registers ................. 24-48

SPORT Receive Configuration

(SPORT_RCR1 and SPORT_RCR2) Registers ................. 24-54

Data Word Formats ............................................................. 24-58

SPORT Transmit Data (SPORT_TX) Register ..................... 24-59

SPORT Receive Data (SPORT_RX) Register ....................... 24-61

SPORT Status (SPORT_STAT) Register .............................. 24-64

ADSP-BF52x Blackfin Processor Hardware Reference xlix

Contents

SPORT Transmit and Receive Serial Clock Divider

(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers ... 24-65

SPORT Transmit and Receive Frame Sync Divider

(SPORT_TFSDIV and SPORT_RFSDIV) Registers ......... 24-66

SPORT Multichannel Configuration

(SPORT_MCMC1 and SPORT_MCMC2) Registers ....... 24-67

SPORT Current Channel (SPORT_CHNL) Register ........... 24-68

SPORT Multichannel Receive Selection

(SPORT_MRCSn) Registers ............................................. 24-69

SPORT Multichannel Transmit Selection

(SPORT_MTCSn) Registers ............................................. 24-70

Programming Examples ............................................................ 24-71

SPORT Initialization Sequence ........................................... 24-72

DMA Initialization Sequence .............................................. 24-74

Interrupt Servicing .............................................................. 24-76

Starting a Transfer ............................................................... 24-77

Unique Information for the ADSP-BF52x Processor .................. 24-78

UART PORT CONTROLLERS

Specific Information for the ADSP-BF52x .................................. 25-1

Overview .................................................................................... 25-2

Features ...................................................................................... 25-2

Interface Overview ..................................................................... 25-3

External Interface .................................................................. 25-3

Internal Interface .................................................................. 25-4

Description of Operation ............................................................ 25-5

l ADSP-BF52x Blackfin Processor Hardware Reference

Contents

UART Transfer Protocol ........................................................ 25-5

UART Transmit Operation .................................................... 25-6

UART Receive Operation ...................................................... 25-7

IrDA Transmit Operation ...................................................... 25-9

IrDA Receive Operation ........................................................ 25-9

Interrupt Processing ............................................................ 25-11

Bit Rate Generation ............................................................. 25-13

Autobaud Detection ............................................................ 25-14

Programming Model ................................................................. 25-16

Non-DMA Mode ................................................................ 25-16

DMA Mode ........................................................................ 25-18

Mixing Modes ..................................................................... 25-19

UART Registers ........................................................................ 25-20

UART Line Control (UART_LCR) Register ......................... 25-22

UART Modem Control (UART_MCR) Register .................. 25-24

UART Line Status (UART_LSR) Register ............................ 25-25

UART Transmit Holding (UART_THR) Register ................ 25-26

UART Receive Buffer (UART_RBR) Register ...................... 25-27

UART Interrupt Enable (UART_IER) Register .................... 25-27

UART Interrupt Identification (UART_IIR) Register ........... 25-29

UART Divisor Latch

(UART_DLL and UART_DLH) Registers ......................... 25-30

UART Scratch (UART_SCR) Register ................................. 25-32

UART Global Control (UART_GCTL) Register .................. 25-32

Programming Examples ............................................................. 25-33

ADSP-BF52x Blackfin Processor Hardware Reference li

Contents

Unique Information for the ADSP-BF52x Processor .................. 25-43

USB OTG CONTROLLER

Overview .................................................................................... 26-1

Features ................................................................................ 26-2

Interface Overview ..................................................................... 26-3

FIFO Configuration ............................................................. 26-7

Interrupts ............................................................................. 26-8

Resets ................................................................................. 26-11

Description of Operation .......................................................... 26-12

Peripheral Mode Operation ................................................. 26-12

Endpoint Setup .............................................................. 26-12

IN Transactions as a Peripheral ...................................... 26-14

OUT Transactions as a Peripheral ................................... 26-15

Peripheral Transfer Workflows ........................................ 26-16

Control Transactions as a Peripheral ............................ 26-18

Write Requests ............................................................ 26-18

Read Requests ............................................................ 26-20

Zero Data Requests ..................................................... 26-21

ENDPOINT 0 States ................................................. 26-22

Endpoint 0 Service Routine as Peripheral .................... 26-24

Idle Mode .............................................................. 26-27

TX Mode ............................................................... 26-27

RX Mode ............................................................... 26-29

Peripheral Mode, Bulk IN, Transfer Size Known .......... 26-32

lii ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Peripheral Mode, Bulk IN, Transfer Size Unknown ...... 26-32

Peripheral Mode, ISO IN, Small MaxPktSize ............... 26-33

Peripheral Mode, ISO IN, Large MaxPktSize ............... 26-34

Peripheral Mode, Bulk OUT, Transfer Size Known ....... 26-35

Peripheral Mode, Bulk OUT, Transfer Size Unknown ... 26-35

Peripheral Mode, ISO OUT, Small MaxPktSize ............ 26-36

Peripheral Mode, ISO OUT, Large MaxPktSize ............ 26-37

Peripheral Mode Suspend ................................................ 26-37

Start-of-frame (SOF) Packets ........................................... 26-38

Soft Connect/Soft Disconnect ......................................... 26-38

Error Handling As a Peripheral ........................................ 26-39

Stalls Issued to Control Transfers ..................................... 26-40

Zero Length OUT Data Packets in Control Transfers ....... 26-41

Host Mode Operation ......................................................... 26-41

Endpoint Setup and Data Transfer ................................... 26-41

Control Transaction as a Host ......................................... 26-42

Setup Phase as a Host ...................................................... 26-43

IN Data Phase as a Host .................................................. 26-44

OUT Data as a Host (Control) ........................................ 26-45

IN Status Phase as a Host

(Following SETUP Phase or OUT Data Phase) ............. 26-46

OUT Status Phase as a Host (following IN Data Phase) ... 26-47

Host IN Transactions ...................................................... 26-48

Host OUT Transactions .................................................. 26-49

Transaction Scheduling ................................................... 26-49

ADSP-BF52x Blackfin Processor Hardware Reference liii

Contents

Babble ............................................................................ 26-50

Host Mode Reset ............................................................ 26-51

Host Mode Suspend ....................................................... 26-51

Functional Description ............................................................. 26-51

On-Chip Bus Interfaces ...................................................... 26-51

Interface Pins ...................................................................... 26-53

Power and Clocking ............................................................ 26-53

UTMI Interface .................................................................. 26-54

Programming Model ................................................................. 26-54

Peripheral Mode Flow Charts .............................................. 26-55

Host Mode Flow Charts ...................................................... 26-64

DMA Mode Flow Charts ..................................................... 26-73

OTG Session Request ......................................................... 26-78

Starting a Session ............................................................ 26-78

Detecting Activity .......................................................... 26-79

Host Negotiation/Configuration ......................................... 26-80

Software Clock Control ....................................................... 26-81

Wakeup from Hibernate State ............................................. 26-81

Wakeup Without Re-Enumeration ...................................... 26-83

Data Transfer ...................................................................... 26-85

Loading/Unloading Packets from Endpoints ........................ 26-86

DMA Master Channels ....................................................... 26-87

DMA Bus Cycles ................................................................ 26-89

Transferring Packets Using DMA ......................................... 26-90

liv ADSP-BF52x Blackfin Processor Hardware Reference

Contents

Individual Packet: RX Endpoint ..................................... 26-91

Individual Packet: TX Endpoint ...................................... 26-92

Multiple Packets: RX Endpoint ....................................... 26-92

Multiple Packets: TX Endpoints ...................................... 26-94

USB OTG Registers .................................................................. 26-95

USB Global Control (USB_GLOBAL_CTL) Register .......... 26-95

USB Power Management (USB_POWER) Register .............. 26-98

USB Function Address (USB_FADDR) Register ................ 26-100

USB Test Mode (USB_TESTMODE) Register ................... 26-101

USB Global Interrupt (USB_GLOBINTR) Register ........... 26-102

USB Transmit Interrupt (USB_INTRTX) Register ............ 26-103

USB Receive Interrupt (USB_INTRRX) Register ............... 26-103

USB Transmit Interrupt Enable (USB_INTRTXE) Register 26-105

USB Receive Interrupt Enable (USB_INTRRXE) Register .. 26-106

USB Common Interrupts (USB_INTRUSB) Register ......... 26-107

USB Common Interrupt Enable (USB_INTRUSBE) Register 26-107

USB Frame Number (USB_FRAME) Register .................... 26-109

USB Index (USB_INDEX) Register ................................... 26-109

USB TX Max Packet (USB_TX_MAX_PACKET) Register 26-110

USB Control/Status EP0 (USB_CSR0) Register ................. 26-110

USB TX Control/Status EPx (USB_TXCSR) Register ........ 26-115

USB RX Max Packet (USB_RX_MAX_PACKET) Register . 26-120

USB RX Control/Status (USB_RXCSR) Register ............... 26-121

USB Count 0 (USB_COUNT0) Register ........................... 26-126

ADSP-BF52x Blackfin Processor Hardware Reference lv

Contents

USB RX Byte Count EPx (USB_RXCOUNT) Register ...... 26-126

USB TX Type (USB_TXTYPE) Register ........................... 26-127

USB NAK Limit 0 (USB_NAKLIMIT0) Register .............. 26-128

USB TX Interval (USB_TXINTERVAL) Register .............. 26-128

USB RX Type (USB_RXTYPE) Register ............................ 26-129

USB RX Interval (USB_RXINTERVAL) Register .............. 26-130

USB TX Byte Count EPx (USB_TXCOUNT) Register ..... 26-131

USB Endpoint FIFO (USB_EPx_FIFO) Registers ............. 26-132

USB OTG Device Control (USB_OTG_DEV_CTL) Register 26-132

USB OTG VBUS Interrupt (USB_OTG_VBUS_IRQ) Register 26-134

USB OTG VBUS Mask (USB_OTG_VBUS_MASK) Register 26-136

USB Link Info (USB_LINKINFO) Register ...................... 26-137

USB VBUS Pulse Length (USB_VPLEN) Register ............. 26-137

USB High-Speed EOF 1 (USB_HS_EOF1) Register .......... 26-138

USB Full-Speed EOF 1 (USB_FS_EOF1) Register ............. 26-138

USB Low-Speed EOF 1 (USB_LS_EOF1) Register ............ 26-139

USB APHY Control 2 (USB_APHY_CNTRL2) Register ... 26-140

USB PLL OSC Control (USB_PLLOSC_CTRL) Registers 26-140

USB SRP Clock Divider (USB_SRP_CLKDIV) Register ... 26-142

USB DMA Interrupt (USB_DMA_INTERRUPT) Register 26-143

USB DMAx Control (USB_DMA_CONTROL) Registers . 26-143

USB DMAx Address Low (USB_DMAxADDRLOW) Registers 26-146

USB DMAx Address High (USB_DMAxADDRHIGH) Registers ..

26-146

lvi ADSP-BF52x Blackfin Processor Hardware Reference

Contents

USB DMAx Count Low (USB_DMAxCOUNTLOW) Registers ....

26-147

USB DMAx Count High (USB_DMAxCOUNTHIGH) Registers .

26-147

References .............................................................................. 26-148

Glossary of USB Terms .......................................................... 26-148

SYSTEM MMR ASSIGNMENTS

Dynamic Power Management Registers ......................................... A-3

System Reset and Interrupt Control

Registers ................................................................................... A-4

OTP Memory Registers ................................................................ A-5

Watchdog Timer Registers ............................................................ A-5

Real-Time Clock Registers ........................................................... A-6

UART0 Controller Registers ........................................................ A-6

SPI Controller Registers ............................................................... A-7

Timer Registers ............................................................................ A-8

Ports Registers .............................................................................. A-9

SPORT0 Controller Registers ..................................................... A-12

SPORT1 Controller Registers ..................................................... A-13

External Bus Interface Unit Registers .......................................... A-14

DMA/Memory DMA Control Registers ..................................... A-15

PPI Registers .............................................................................. A-17

Security Registers ....................................................................... A-18

Reset and Booting Registers ........................................................ A-18

TWI Registers ............................................................................ A-19

ADSP-BF52x Blackfin Processor Hardware Reference lvii

Contents

UART1 Controller Registers ....................................................... A-20

Ethernet MAC Registers ............................................................. A-20

Handshake MDMA Control Registers ......................................... A-24

HOST DMA Port Registers ........................................................ A-25

GP Counter Registers ................................................................. A-25

NFC Registers ............................................................................ A-26

USB Registers ............................................................................. A-27

Processor-Specific Memory Registers ........................................... A-35

Core Timer Registers .................................................................. A-35

TEST FEATURES

JTAG Standard ............................................................................. B-1

Boundary-Scan Architecture ......................................................... B-2

Instruction Register ................................................................. B-4

Public Instructions .................................................................. B-5

EXTEST – Binary Code 00000 ........................................... B-6

SAMPLE/PRELOAD – Binary Code 10000 ....................... B-6

BYPASS – Binary Code 11111 ............................................ B-6

Boundary-Scan Register .......................................................... B-7

GLOSSARY

INDEX

lviii ADSP-BF52x Blackfin Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using an enhanced
Blackfin® processor from Analog Devices.

Purpose of This Manual

The ADSP-BF52x Blackfin Processor Hardware Reference provides architec-
tural information about the ADSP-BF522, ADSP-BF523, ADSP-BF524,
ADSP-BF525, ADSP-BF526, and ADSP-BF527 processors. This hard­ware reference provides architectural information about these processors
and the peripherals contained within the ADSP-BF52x Blackfin packages.
The architectural descriptions cover functional blocks, buses, and ports,
including all features and processes that they support. For programming
information, see the Blackfin Processor Programming Reference. For timing,
electrical, and package specifications, see the
ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet.

Intended Audience

The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the appropriate instruction set reference manuals and data sheets)
that describe your target architecture.

ADSP-BF52x Blackfin Processor Hardware Reference lix

What’s New in This Manual

This is Revision 1.0 of the ADSP-BF52x Blackfin Processor Hardware
Reference. Peripheral chapters have been expanded and reorganized, and
modifications and corrections based on errata reports against this manual
have been made.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technical_support

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

lx ADSP-BF52x Blackfin Processor Hardware Reference

Product Information

Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a
link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.

Also note, MyAnalog.com is a free feature of the Analog Devices Web site
that allows customization of a Web page to display only the latest infor­mation about products you are interested in. You can choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals. MyAn-

alog.com

examples, and more.

provides access to books, application notes, data sheets, code

MyAnalog.com to sign up. If you are a registered user, just log on.

Visit
Your user name is your e-mail address.

VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, Dinkum
Abridged C++ library, and FLEXnet License Tools software documenta-

ADSP-BF52x Blackfin Processor Hardware Reference lxi

tion. You can search easily across the entire VisualDSP++ documentation
set for any topic of interest.

For easy printing, supplementary Portable Documentation Format (.
files for all manuals are provided on the VisualDSP++ installation CD.

Each documentation file type is described as follows.

File Description

.chm Help system files and manuals in Microsoft help format

.htm or
.html

.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the

Dinkum Abridged C++ library and FLEXnet License Tools software documenta­tion. Viewing and printing the .html files requires a browser, such as Internet
Explorer 6.0 (or higher).

.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

Technical Library CD

The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals, Visu­alDSP++ software manuals, and hardware tools manuals for the following
processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and
ADSP-219x.

pdf)

To order the technical library CD, go to

sors/technical_library

, navigate to the manuals page for your

http://www.analog.com/proces-

processor, click the request CD check mark, and fill out the order form.

Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.

EngineerZone

lxii ADSP-BF52x Blackfin Processor Hardware Reference

EngineerZone is a technical support forum from Analog Devices. It allows
you direct access to ADI technical support engineers. You can search
FAQs and technical information to get quick answers to your embedded
processing and DSP design questions.

Use EngineerZone to connect with other DSP developers who face similar
design challenges. You can also use this open forum to share knowledge
and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

Social Networking Web Sites

You can now follow Analog Devices processor development on Twitter
and LinkedIn. To access:

• Twitter: http://twitter.com/ADISHARC and

http://twitter.com/blackfin

• LinkedIn: Network with the LinkedIn group, Analog Devices
SHARC or Analog Devices Blackfin: http://www.linkedin.com

Notation Conventions

Text conventions used in this manual are identified and described as fol­lows. Additional conventions, which apply only to specific chapters, may
appear throughout this document.

Example Description

Close command
(File menu)

{this | that} Alternative required items in syntax descriptions appear within curly

ADSP-BF52x Blackfin Processor Hardware Reference lxiii

Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close com­mand appears on the File menu).

brackets and separated by vertical bars; read the example as this or that.
One or the other is required.

Example Description







[this | that] Optional items in syntax descriptions appear within brackets and sepa-

rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delim-

ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.

.

SECTION Commands, directives, keywords, and feature names are in text with let-

ter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this symbol.

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product that
could lead to undesirable results or product damage. In the online version
of this book, the word Caution appears instead of this symbol.

War ni ng : Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the devices
users. In the online version of this book, the word War ni ng appears
instead of this symbol.

lxiv ADSP-BF52x Blackfin Processor Hardware Reference

ADSP-BF52x Blackfin Processor Hardware Reference lxv

lxvi ADSP-BF52x Blackfin Processor Hardware Reference

1 INTRODUCTION

The ADSP-BF52x processors are members of the Blackfin processor fam­ily that offer significant high performance and low power while retaining
their ease-of-use benefits. All parts within the family are pin-compatible,
but only the ADSP-BF526 and ADSP-BF527 include an embedded
Ethernet MAC module.

Manual Contents

This manual consists of one volume.

• Chapter 1, “Introduction”
Provides a high level overview of the processor, including peripher­als, power management, and development tools.

• Chapter 2, “Chip Bus Hierarchy”
Describes on-chip buses, including how data moves through the
system.

• Chapter 3, “Memory”
Describes processor-specific memory topics, including L1
memories and processor-specific memory MMRs.

• Chapter 4, “One-Time Programmable Memory”
Describes the on-chip, one-time-programmable memory array
which provides 64k-bits of non-volatile memory for developers to
store both public and private data on-chip.

ADSP-BF52x Blackfin Processor Hardware Reference 1-1

• Chapter 5, “System Interrupts”
Describes the system peripheral interrupts, including setup and
clearing of interrupt requests.

• Chapter 6, “Direct Memory Access”
Describes the peripheral DMA and Memory DMA controllers.
Includes performance, software management of DMA, and DMA
errors.

• Chapter 7, “External Bus Interface Unit”
Describes the external bus interface unit of the processor. The
chapter also discusses the asynchronous memory interface, the
SDRAM controller (SDC), related registers, and SDC configura­tion and commands.

• Chapter 8, “Host DMA Port”
Describes the Host DMA port of the processor. The Host DMA
Port (HOSTDP) allows an external host device to be the DMA
master to transfer data to and from the Blackfin device. The host
device masters the transactions and the Blackfin is a DMA slave
device.

• Chapter 9, “General-Purpose Ports”
Describes the general-purpose I/O ports, including the structure of
each port, multiplexing, configuring the pins, and generating
interrupts.

• Chapter 10, “General-Purpose Timers”
Describes the general-purpose timers.

• Chapter 11, “Core Timer”
Describes the core timer.

• Chapter 12, “Watchdog Timer”
Describes the watchdog timer.

1-2 ADSP-BF52x Blackfin Processor Hardware Reference

• Chapter 13, “General-Purpose Counter”
Describes the general purpose up/down counter which provides
support for manually controlled rotary controllers, such as the vol­ume wheel on a radio device. This unit also supports industrial or
motor-control type of wheels.

• Chapter 14, “Real-Time Clock”
The RTC provides a set of digital watch features to the processor,
including time of day, alarm, and stopwatch countdown. It is typi­cally used to implement either a real-time watch or a life counter,
which counts the elapsed time since the last system reset.

• Chapter 16, “Security”
Describes the Lockbox

TM

Secure Technology for Analog Devices
Blackfin processors. This comprises a mix of hardware and software
mechanisms designed to prevent unauthorized accesses and allow
trusted code to execute on the processor.

• Chapter 17, “System Reset and Booting”
Describes the booting methods, booting process and specific boot
modes for the processor.

• Chapter 18, “Dynamic Power Management”
Describes the clocking, including the PLL, and the dynamic power
management controller.

• Chapter 19, “System Design”
Describes how to use the processor as part of an overall system. It
includes information about bus timing and latency numbers, sema­phores, and a discussion of the treatment of unused pins.

• Chapter 21, “Ethernet MAC”
Describes the Ethernet Media Access Controller (MAC) peripheral
which provides a 10/100M bit/s Ethernet interface, compliant to
IEEE Std. 802.3-2002, between an MII (Media Independent Inter­face) and the Blackfin peripheral subsystem.

ADSP-BF52x Blackfin Processor Hardware Reference 1-3

• Chapter 20, “NAND Flash Controller”
Describes the NAND Flash Controller (NFC)—which is part of
the External Bus Interface—of the processor. NAND Flash devices
provide high-density, low-cost memory.

• Chapter 15, “Parallel Peripheral Interface”
Describes the Parallel Peripheral Interface (PPI) of the processor.
The PPI is a half-duplex, bidirectional port accommodating up to
16 bits of data and is used for digital video and data converter
applications.

• Chapter 22, “SPI-Compatible Port Controller”
Describes the Serial Peripheral Interface (SPI) port that provides an
I/O interface to a variety of SPI compatible peripheral devices.

• Chapter 23, “Two Wire Interface Controller”
Describes the Two Wire Interface (TWI) controller, which allows a
device to interface to an Inter IC bus as specified by the Philips I
Bus Specification version 2.1 dated January 2000.

• Chapter 24, “SPORT Controller”
Describes the independent, synchronous Serial Port Controller
which provides an I/O interface to a variety of serial peripheral
devices.

2

C

• Chapter 25, “UART Port Controllers”
Describes the Universal Asynchronous Receiver/Transmitter port
that converts data between serial and parallel formats. The UART
supports the half-duplex IrDA® SIR protocol as a mode-enabled
feature.

• Chapter 26, “USB OTG Controller”
Describes the USB OTG interface of the processor. This interface
provides a low-cost connectivity solution for consumer mobile
devices such as cell phones, digital still cameras and MP3 players,
allowing these devices to transfer data via a point-to-point USB
connection without the need for a PC host.

1-4 ADSP-BF52x Blackfin Processor Hardware Reference

• Appendix A, “System MMR Assignments”
Lists the memory-mapped registers included in this manual, their
addresses, and cross-references to text.

• Appendix B, “Test Features”
Describes test features for the processor, discusses the JTAG stan­dard, boundary-scan architecture, instruction and boundary
registers, and public instructions.

• Appendix G, “Glossary”
Contains definitions of terms used in this book, including
acronyms.



This hardware reference is a companion document to the Blackfin
Processor Programming Reference.

Peripherals

The processor system peripherals include:

• Two memory-to-memory DMAs with handshake DMA

• Event handler with 54 interrupt inputs

• 12 peripheral DMAs (2 mastered by the Ethernet MAC on
ADSP-BF527 processors)

• Host DMA port (HOSTDP)

• 48 General-Purpose I/Os (GPIOs)

• Eight 32-bit timer/counters with PWM support

• 32-bit core timer

• Real-Time Clock (RTC) and watchdog timer

•Rotary counter

ADSP-BF52x Blackfin Processor Hardware Reference 1-5

• Lockbox™ Secure Technology

• OTP Memory

• On-chip PLL capable of 0.5× to 64× frequency multiplication

• Debug/JTAG interface

• IEEE 802.3-compliant 10/100 Ethernet MAC (only on the
ADSP-BF527)

• NAND flash controller

• Parallel Peripheral Interface (PPI), supporting ITU-R 656 video
data formats

• Serial Peripheral Interface (SPI)-compatible port

• Two-Wire Interface (TWI) controller

• Two dual-channel, full-duplex synchronous Serial Ports
(SPORTs), supporting eight stereo I

2

S channels

• Two UARTs with IrDA® support

• USB 2.0 high-speed on-the-go (OTG) interface with integrated
PHY

These peripherals are connected to the core via several high bandwidth
buses, as shown in Figure 1-1.

All of the peripherals, except for general-purpose I/O, TWI, RTC, and
timers, are supported by a flexible DMA structure. There are also two sep­arate memory DMA channels dedicated to data transfers between the
processor’s memory spaces, which include external SDRAM and asynchro­nous memory. Multiple on-chip buses provide enough bandwidth to keep

1-6 ADSP-BF52x Blackfin Processor Hardware Reference

the processor core running even when there is also activity on all of the

VOLTAGE REGULATOR

JTAG TEST AND EMULATION

PERIPHERAL
ACCESS BUS

OTP

WATCHDOG TIMER

RTC

TWI

SPORT1-0

NFC

PPI

UART1-0

SPI

TIMERS7-0

EMAC/HOST DMA

BOOT

ROM

DMA

EXTERNAL

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1

DATA

MEMORY

L1

INSTRUCTION

MEMORY

USB

16

DMA CORE BUS

EXTERNAL ACCESS BUS

EXTERNAL PORT

FLASH, SDRAM CONTROL

PORTS

B

on-chip and external peripherals.

Figure 1-1. ADSP-BF52x Processor Block Diagram

Memory Architecture

The Blackfin processor architecture structures memory as a single, unified
4G byte address space using 32-bit addresses. All resources, including
internal memory, external memory, and I/O control registers, occupy sep­arate sections of this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide a good
cost/performance balance of some very fast, low latency on-chip memory
as cache or SRAM, and larger, lower cost and lower performance off-chip

ADSP-BF52x Blackfin Processor Hardware Reference 1-7

memory systems. Table 1-1 shows the memory for the ADSP-BF52x
processors.

Table 1-1. Memory Configurations

Type of Memory ADSP-BF52x

Instruction SRAM/cache, lockable by way or line 16K byte

Instruction SRAM 48K byte

Data SRAM/cache 32K byte

Data SRAM 32K byte

Data scratchpad SRAM 4K byte

L3 Boot ROM 32K byte

Total 164K byte

The L1 memory system is the primary highest performance memory avail­able to the core. The off-chip memory system, accessed through the
external bus interface unit (EBIU), provides expansion with SDRAM,
flash memory, and SRAM, optionally accessing up to 132M bytes of phys­ical memory.

The memory DMA controller provides high bandwidth data movement
capability. It can perform block transfers of code or data between the
internal memory and the external memory spaces.

1-8 ADSP-BF52x Blackfin Processor Hardware Reference

Internal Memory

The processor has three blocks of on-chip memory that provide high
bandwidth access to the core:

• L1 instruction memory, consisting of SRAM and a 4-way set-asso­ciative cache. This memory is accessed at full processor speed.

• L1 data memory, consisting of SRAM and/or a 2-way set-associa­tive cache. This memory block is accessed at full processor speed.

• L1 scratchpad RAM, which runs at the same speed as the L1 mem­ories but is only accessible as data SRAM and cannot be configured
as cache memory.

External Memory

External (off-chip) memory is accessed via the external bus interface unit
(EBIU). This 16-bit interface provides a glueless connection to a bank of
synchronous DRAM (SDRAM) and as many as four banks of asynchro­nous memory devices including flash memory, EPROM, ROM, SRAM,
and memory-mapped I/O devices.

The SDRAM controller can be programmed to interface to up to
128M bytes of SDRAM.

The asynchronous memory controller can be programmed to control up
to four banks of devices. Each bank occupies a 1M byte segment regardless
of the size of the devices used, so that these banks are only contiguous if
each is fully populated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are
mapped through the flat 32-bit address space. Control registers for
on-chip I/O devices are mapped into memory-mapped registers (MMRs)

ADSP-BF52x Blackfin Processor Hardware Reference 1-9

at addresses near the top of the 4G byte address space. These are separated
into two smaller blocks: one contains the control MMRs for all core func­tions and the other contains the registers needed for setup and control of
the on-chip peripherals outside of the core. The MMRs are accessible only
in supervisor mode. They appear as reserved space to on-chip peripherals.

One-Time-Programmable (OTP) Memory

ADSP-BF52x processors also include an on-chip OTP memory array
which provides 64K bits of non-volatile memory that can be programmed
by the developer one time only. It includes the array and logic to support
read access and programming. A mechanism for error correction is pro­vided. Additionally, its pages can be write protected.

The OTP is not part of the Blackfin linear memory map. OTP memory is
not accessed directly using the Blackfin memory map; rather, it is accessed
via four 32-bit-wide registers (OTP_DATA3–0) that act as the OTP memory
read/write buffer.

This memory is organized into 512 pages, each comprised of 128 bits and
equally separated into two distinct areas with privileged access dependant
upon modes of operation when security features are utilized. Approxi­mately 400 pages are available for developer use. The remaining 100 pages
are utilized for page protection bits, error correction, and Analog Devices
factory-reserved areas. One area is read/write accessible at all time (Public
OTP Memory). The second area maintains privileged access and can only
be accessed (read/write) upon entry to Secure Mode when security features
are utilized (Private OTP Memory).

All together, OTP memory provides a means to store Public Keys in Pub­lic OTP Memory or secrets such as Private Keys or Symmetric Keys in
Private OTP Memory. One page of the Public OTP Memory is initialized
in the Analog Devices factory with a Unique Chip ID.

This OTP memory provides a means to store public and private cipher
keys as well as chip, customer, and factory identification data.

1-10 ADSP-BF52x Blackfin Processor Hardware Reference

DMA Support

The processor has a DMA controller which supports automated data
transfers with minimal overhead for the core. DMA transfers can occur
between the internal memories and any of its DMA-capable peripherals.
Additionally, DMA transfers can be accomplished between any of the
DMA-capable peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the asynchro­nous memory controller. DMA-capable peripherals include the SPORTs,
SPI ports, UARTs, and PPI. For the ADSP-BF527 processor, Ethernet is
also a DMA-capable peripheral. Each individual DMA-capable peripheral
has at least one dedicated DMA channel.

The DMA controller supports both one-dimensional (1D) and
two-dimensional (2-D) DMA transfers. DMA transfer initialization can
be implemented from registers or from sets of parameters called descriptor
blocks.

The 2-D DMA capability supports arbitrary row and column sizes up to
64K elements by 64K elements, and arbitrary row and column step sizes
up to +/- 32K elements. Furthermore, the column step size can be less
than the row step size, allowing implementation of interleaved data­streams. This feature is especially useful in video applications where data
can be de-interleaved on the fly.

Examples of DMA types supported include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each full or
fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors specifying only the base
DMA address within a common page

ADSP-BF52x Blackfin Processor Hardware Reference 1-11

In addition to the dedicated peripheral DMA channels, there are two sep­arate pairs of memory DMA channels provided for transfers between the
various memories of the system. This enables transfers of blocks of data
between any of the memories—including external SDRAM, ROM,
SRAM, and flash memory—with minimal processor intervention. Mem­ory DMA transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer mechanism.

The ADSP-BF52x processors also include a handshake DMA capability
via dual external DMA request pins when used in conjunction with the
external bus interface unit (EBIU). This functionality can be used when a
high speed interface is required for external FIFOs and high bandwidth
communications peripherals such as USB 2.0. It allows control of the
number of data transfers for MDMA. The number of transfers per edge is
programmable. This feature can be programmed to allow MDMA to have
an increased priority on the external bus relative to the core.

External Bus Interface Unit

The external bus interface unit (EBIU) on the processor interfaces with a
wide variety of industry-standard memory devices. The controller consists
of an SDRAM controller and an asynchronous memory controller.

SDRAM Controller

The SDRAM controller provides an interface to a single bank of indus­try-standard SDRAM devices or DIMMs. The bank can be configured to
contain between 16M and 128M bytes of memory.

A set of programmable timing parameters is available to configure the
SDRAM bank to support slower memory devices. The memory bank is
16 bits wide for minimum device count and lower system cost.

1-12 ADSP-BF52x Blackfin Processor Hardware Reference

Asynchronous Controller

The asynchronous memory controller provides a configurable interface for
up to four separate banks of memory or I/O devices. Each bank can be
independently programmed with different timing parameters. This allows
connection to a wide variety of memory devices, including SRAM, ROM,
and flash EPROM, as well as I/O devices that interface with standard
memory control lines. Each bank occupies a 1M byte window in the pro­cessor address space, but if not fully populated, these are not made
contiguous by the memory controller. The banks are 16 bits wide, for
interfacing to a range of memories and I/O devices.

Ports

Because of the rich set of peripherals, the ADSP-BF52x processor groups
the many peripheral signals to four ports—port F, port G, port H, and
port J. Most of the associated pins are shared by multiple signals. The
ports function as multiplexer controls. The ports have programmable
hysteresis.

General-Purpose I/O (GPIO)

The ADSP-BF52x processors have 48 bi-directional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—PORTFIO,
PORTGIO, and PORTHIO, associated with port F, port G, and port H,
respectively. Port J does not provide GPIO functionality. Each
GPIO-capable pin shares functionality with other ADSP-BF52x processor
peripherals via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon powerup. Neither GPIO output or
input drivers are active by default. Each general-purpose port pin can be

ADSP-BF52x Blackfin Processor Hardware Reference 1-13

individually controlled by manipulation of the port control, status, and
interrupt registers:

• GPIO direction control register – Specifies the direction of each
individual GPIO pin as input or output.

• GPIO control and status registers – The ADSP-BF52x processors
employ a “write one to modify” mechanism that allows any combi­nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO pins.
Four control registers are provided. One register is written in order
to set pin values, one register is written in order to clear pin values,
one register is written in order to toggle pin values, and one register
is written in order to specify a pin value. Reading the GPIO status
register allows software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt mask
registers allow each individual GPIO pin to function as an inter­rupt to the processor. Similar to the two GPIO control registers
that are used to set and clear individual pin values, one GPIO
interrupt mask register sets bits to enable interrupt function, and
the other GPIO interrupt mask register clears bits to disable inter­rupt function. GPIO pins defined as inputs can be configured to
generate hardware interrupts, while output pins can be triggered by
software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO interrupt sen­sitivity registers specify whether individual pins are level- or
edge-sensitive and specify—if edge-sensitive—whether just the ris­ing edge or both the rising and falling edges of the signal are
significant. One register selects the type of sensitivity, and one reg­ister selects which edges are significant for edge-sensitivity.

1-14 ADSP-BF52x Blackfin Processor Hardware Reference

Two-Wire Interface

The Two-Wire Interface (TWI) is fully compatible with the widely used
I2C bus standard. It was designed with a high level of functionality and is

compatible with multi-master, multi-slave bus configurations. To preserve
processor bandwidth, the TWI controller can be set up and a transfer ini­tiated with interrupts only to service FIFO buffer data reads and writes.
Protocol related interrupts are optional.

The TWI externally moves 8-bit data while maintaining compliance with
the I2C bus protocol. The Philips I2C Bus Specification version 2.1 covers
many variants of I2C. The TWI controller includes these features:

• Simultaneous master and slave operation on multiple device
systems

• Support for multi-master data arbitration

• 7-bit addressing

• 100K bits/second and 400K bit/second data rates

• General call address support

• Master clock synchronization and support for clock low extension

• Separate multiple-byte receive and transmit FIFOs

• Low interrupt rate

• Individual override control of data and clock lines in the event of
bus lock-up

• Input filter for spike suppression

• Serial camera control bus support as specified in the OmniVision

Serial Camera Control Bus (SCCB) Functional Specification version

2.1

ADSP-BF52x Blackfin Processor Hardware Reference 1-15

Ethernet MAC

The Ethernet Media Access Controller (MAC) peripheral for the
ADSP-BF527 processors provides a 10/100M bit/second Ethernet inter­face, compliant with IEEE Std. 802.3-2002, between a Media
Independent Interface (MII) and the Blackfin peripheral subsystem. The
MAC operates in both half-duplex and full-duplex modes. It provides pro­grammable enhanced features designed to minimize bus utilization and
pre- or post-message processing. The connection to the external physical
layer device (PHY) is achieved via the MII or a Reduced Media Indepen­dent Interface (RMII). The RMII provides data buses half as wide (2 bit
vs. 4 bit) as those of an MII, operating at double the frequency.

The MAC is clocked internally from the CLKIN pin on the processor. A
buffered version of this clock can also be used to drive the external PHY
via the CLKBUF pin. A 25 MHz source should be used with an MII PHY.
A 50 MHz clock source is required to drive an RMII PHY.

Parallel Peripheral Interface

The processor provides a Parallel Peripheral Interface (PPI) that can con­nect directly to parallel A/D and D/A converters, ITU-R 601/656 video
encoders and decoders, and other general-purpose peripherals. The PPI
consists of a dedicated input clock pin and three multiplexed frame sync
pins. The input clock supports parallel data rates up to half the system
clock rate.

In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or
10-bit data elements. On-chip decode of embedded preamble control and
synchronization information is supported.

1-16 ADSP-BF52x Blackfin Processor Hardware Reference

Three distinct ITU-R 656 modes are supported:

• Active video only - The PPI does not read in any data between the
End of Active Video (EAV) and Start of Active Video (SAV) pre­amble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored to
memory; they are filtered by the PPI.

• Vertical blanking only - The PPI only transfers Vertical Blanking
Interval (VBI) data, as well as horizontal blanking information and
control byte sequences on VBI lines.

• Entire field - The entire incoming bitstream is read in through the
PPI. This includes active video, control preamble sequences, and
ancillary data that may be embedded in horizontal and vertical
blanking intervals.

Though not explicitly supported, ITU-R 656 output functionality can be
achieved by setting up the entire frame structure (including active video,
blanking, and control information) in memory and streaming the data out
the PPI in a frame sync-less mode. The processor’s 2-D DMA features
facilitate this transfer by allowing the static frame buffer (blanking and
control codes) to be placed in memory once, and simply updating the
active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety
of data capture and transmission applications. The modes are divided into
four main categories, each allowing up to 16 bits of data transfer per

PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

ADSP-BF52x Blackfin Processor Hardware Reference 1-17

These modes support ADC/DAC connections, as well as video communi­cation with hardware signalling. Many of the modes support more than
one level of frame synchronization. If desired, a programmable delay can
be inserted between assertion of a frame sync and reception/transmission
of data.

SPORT Controllers

The processor incorporates two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor communications.
The SPORTs support these features:

• Bidirectional, I2S capable operation

Each SPORT has two sets of independent transmit and receive
pins, which enable eight channels of I2S stereo audio.

• Buffered (eight-deep) transmit and receive ports

Each port has a data register for transferring data words to and
from other processor components and shift registers for shifting
data in and out of the data registers.

• Clocking

Each transmit and receive port can either use an external serial
clock or can generate its own in a wide range of frequencies.

• Word length

Each SPORT supports serial data words from 3 to 32 bits in
length, transferred in most significant bit first or least significant
bit first format.

1-18 ADSP-BF52x Blackfin Processor Hardware Reference

• Framing

Each transmit and receive port can run with or without frame sync
signals for each data word. Frame sync signals can be generated
internally or externally, active high or low, and with either of two
pulse widths and early or late frame sync.

• Companding in hardware

Each SPORT can perform A-law or µ-law companding according
to ITU recommendation G.711. Companding can be selected on
the transmit and/or receive channel of the SPORT without addi­tional latencies.

• DMA operations with single cycle overhead

Each SPORT can automatically receive and transmit multiple buff­ers of memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.

• Interrupts

Each transmit and receive port generates an interrupt upon com­pleting the transfer of a data word or after transferring an entire
data buffer or buffers through DMA.

• Multichannel capability

Each SPORT supports 128 channels out of a 1024-channel win­dow and is compatible with the H.100, H.110, MVIP-90, and
HMVIP standards.

ADSP-BF52x Blackfin Processor Hardware Reference 1-19

Serial Peripheral Interface (SPI) Port

The processor has an SPI-compatible port that enables the processor to
communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins and a
clock pin. An SPI chip select input pin lets other SPI devices select the
processor, and seven SPI chip select output pins let the processor select
other SPI devices. The SPI select pins are reconfigured general-purpose
I/O pins. Using these pins, the SPI port provides a full-duplex, synchro­nous serial interface, which supports both master and slave modes and
multimaster environments.

The SPI port’s baud rate and clock phase/polarities are programmable,
and it has an integrated DMA controller, configurable to support either
transmit or receive datastreams. The SPI’s DMA controller can only ser­vice unidirectional accesses at any given time.

During transfers, the SPI port simultaneously transmits and receives by
serially shifting data in and out of its two serial data lines. The serial clock
line synchronizes the shifting and sampling of data on the two serial data
lines.

Timers

There are nine general-purpose programmable timer units in the proces­sor. Eight timers have an external pin that can be configured either as a
Pulse Width Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths of external events.
These timer units can be synchronized to an external clock input con­nected to the PF1 pin, an external clock input to the PPI_CLK pin, or to the
internal

1-20 ADSP-BF52x Blackfin Processor Hardware Reference

SCLK.

The timer units can be used in conjunction with the UARTs to measure
the width of the pulses in the datastream to provide an autobaud detect
function for a serial channel.

The timers can generate interrupts to the processor core to provide peri­odic events for synchronization, either to the processor clock or to a count
of external signals.

In addition to the eight general-purpose programmable timers, a 9th timer
is also provided. This extra timer is clocked by the internal processor clock
and is typically used as a system tick clock for generation of operating sys­tem periodic interrupts.

UART Ports

The processor provides two half-duplex Universal Asynchronous
Receiver/Transmitter (UART) ports, which are fully compatible with
PC-standard UARTs. The UART ports provide a simplified UART inter­face to other peripherals or hosts, providing half-duplex, DMA-supported,
asynchronous transfers of serial data. The UART ports include support for
5 to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The
UART ports support two modes of operation:

• Programmed I/O

The processor sends or receives data by writing or reading
I/O-mapped UART registers. The data is double buffered on both
transmit and receive.

• Direct Memory Access (DMA)

The DMA controller transfers both transmit and receive data. This
reduces the number and frequency of interrupts required to trans­fer data to and from memory. Each of the two UARTs have two

ADSP-BF52x Blackfin Processor Hardware Reference 1-21

dedicated DMA channels, one for transmit and one for receive.
These DMA channels have lower priority than most DMA chan­nels because of their relatively low service rates.

The UARTs’ baud rate, serial data format, error code generation and sta­tus, and interrupts can be programmed to support:

• Wide range of bit rates

• Data formats from 7 to 12 bits per frame

• Generation of maskable interrupts to the processor by both trans­mit and receive operations

In conjunction with the general-purpose timer functions, autobaud detec­tion is supported.

The capabilities of the UART ports are further extended with support for
the Infrared Data Association (IrDA

Specification (SIR) protocol.

®

) Serial Infrared Physical Layer Link

Security

ADSP-BF52x processors provides security features (Blackfin Lockbox™
Secure Technology) that enable customer applications to use secure proto­cols, consisting of code authentication and execution of code within a
secure environment. Implementing secure protocols on Blackfin proces­sors involves a combination of hardware and software components.

1-22 ADSP-BF52x Blackfin Processor Hardware Reference

Together these components protect secure memory spaces and restrict
control of security features to authenticated developer code.

• Blackfin Lockbox Secure Technology incorporates a secure hard­ware platform for confidentiality and integrity protection of secure
code and data with authenticity maintained by secure software.

• This secure platform provides:

• A secure execution mode

• Secure storage for on-chip keys

• On-chip secure ROM

• Secure RAM

• Access to code and data in the secure domain is monitored by the
hardware and any unauthorized access to the secure domain is
prevented.

• The secure ROM code establishes the root of trust for the secure
software in the system.

• The secure RAM provides integrity protection and confidentiality
for authenticated code and data.

• User-defined cipher key(s) and ID(s) can be securely stored in the
on-chip OTP memory.

• Every processor ships from the ADI factory with a unique chip ID
value stored in publicly accessible OTP memory area.

Real-Time Clock

The processor’s Real-Time Clock (RTC) provides a robust set of digital
watch features, including current time, stopwatch, and alarm. The RTC is

ADSP-BF52x Blackfin Processor Hardware Reference 1-23

clocked by a 32.768 kHz crystal external to the processor. The RTC
peripheral has dedicated power supply pins, so that it can remain powered
up and clocked even when the rest of the processor is in a low power state.
The RTC provides several programmable interrupt options, including
interrupt per second, minute, hour, or day clock ticks, interrupt on pro­grammable stopwatch countdown, or interrupt at a programmed alarm
time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal
by a prescaler. The counter function of the timer consists of four counters:
a 60 second counter, a 60 minute counter, a 24 hours counter, and a
32768 day counter.

When enabled, the alarm function generates an interrupt when the output
of the timer matches the programmed value in the alarm control register.
There are two alarms. The first alarm is for a time of day. The second
alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one
minute resolution. When the stopwatch is enabled and the counter under­flows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor from sleep
mode or deep sleep mode upon generation of any RTC wakeup event. An
RTC wakeup event can also wake up the on-chip internal voltage regula­tor from a powered down state.

Watchdog Timer

The processor includes a 32-bit timer that can be used to implement a
software watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through generation
of a hardware reset, nonmaskable interrupt (NMI), or general-purpose
interrupt, if the timer expires before being reset by software. The pro­grammer initializes the count value of the timer, enables the appropriate

1-24 ADSP-BF52x Blackfin Processor Hardware Reference

interrupt, then enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value. This protects
the system from remaining in an unknown state where software that
would normally reset the timer has stopped running due to an external
noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both
the CPU and the peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating a status bit
in the watchdog control register.

The timer is clocked by the system clock (
of f

SCLK

.

SCLK), at a maximum frequency

Clock Signals

The processor can be clocked by an external crystal, a sine wave input, or a
buffered, shaped clock derived from an external clock oscillator.

This external clock connects to the processor CLKIN pin. The CLKIN input
cannot be halted, changed, or operated below the specified frequency dur­ing normal operation. This clock signal should be a TTL-compatible
signal.

The core clock (
the input clock (CLKIN) signal. An on-chip Phase Locked Loop (PLL) is
capable of multiplying the
64×) multiplication factor (bounded by specified minimum and maxi-

VCO frequencies). The default multiplier is 10×, but it can be

mum
modified by a software instruction sequence. On-the-fly frequency
changes can be made by simply writing to the PLL_DIV register.

CCLK) and system peripheral clock (SCLK) are derived from

CLKIN signal by a user-programmable (0.5× to

All on-chip peripherals are clocked by the system clock (

SCLK). The system

clock frequency is programmable by means of the SSEL[3:0] bits of the

PLL_DIV register.

ADSP-BF52x Blackfin Processor Hardware Reference 1-25

Dynamic Power Management

The processor provides four operating modes, each with a different perfor­mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt­age to further reduce power dissipation. Control of clocking to each of the
peripherals also reduces power consumption.

Full-On Mode (Maximum Performance)

In the full-on mode, the PLL is enabled, not bypassed, providing the max­imum operational frequency. This is the normal execution state in which
maximum performance can be achieved. The processor core and all
enabled peripherals run at full speed.

Active Mode (Moderate Power Savings)

In the active mode, the PLL is enabled, but bypassed. Because the PLL is
bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at
the input clock (CLKIN) frequency. In this mode, the CLKIN to VCO multi­plier ratio can be changed, although the changes are not realized until the
full on mode is entered. DMA access is available to appropriately config­ured L1 memories.

In the active mode, it is possible to disable the PLL through the PLL con­trol register (
transitioning to the full on or sleep modes.

PLL_CTL). If disabled, the PLL must be re-enabled before

Sleep Mode (High Power Savings)

The sleep mode reduces power dissipation by disabling the clock to the
processor core (
tinue to operate in this mode. Typically an external event or RTC activity
will wake up the processor. When in the sleep mode, assertion of any

1-26 ADSP-BF52x Blackfin Processor Hardware Reference

CCLK). The PLL and system clock (SCLK), however, con-

interrupt causes the processor to sense the value of the bypass bit (
in the PLL control register (PLL_CTL). If bypass is disabled, the processor
transitions to the full on mode. If bypass is enabled, the processor transi­tions to the active mode.

When in the sleep mode, system DMA access to L1 memory is not
supported.

Deep Sleep Mode (Maximum Power Savings)

The deep sleep mode maximizes dynamic power savings by disabling the
processor core and synchronous system clocks (CCLK and SCLK). Asynchro­nous systems, such as the RTC, may still be running, but cannot access
internal resources or external memory. This powered-down mode can only
be exited by assertion of the reset interrupt or by an asynchronous inter­rupt generated by the RTC. When in deep sleep mode, an RTC
asynchronous interrupt causes the processor to transition to the active
mode. Assertion of RESET while in deep sleep mode causes the processor to
transition to the full on mode.

Hibernate State

BYPASS)

For lowest possible power dissipation, this state allows the internal supply
(V

DDINT

running. Although not strictly an operating mode like the four modes
detailed above, it is illustrative to view it as such.

) to be powered down, while keeping the I/O supply (V

DDEXT

)

Voltage Regulation

The ADSP-BF523, ADSP-BF525, ADSP-BF527 processors provide an
on-chip voltage regulator that can generate V

ply. Figure 18-3 on page 18-18 shows the typical external components
required to complete the power management system. The regulator con-

ADSP-BF52x Blackfin Processor Hardware Reference 1-27

DDINT

from an external sup-

trols the internal logic voltage levels and is programmable with the voltage
regulator control register (
standby power consumption, the internal voltage regulator can be pro­grammed to remove power to the processor core while keeping I/O power
supplied. While in this state, V

need for external buffers. The regulator can also be disabled and bypassed
at the user’s discretion.

VR_CTL) in increments of 50 mV. To reduce

DDEXT

can still be applied, eliminating the

Instruction Set Description

The Blackfin processor family assembly language instruction set employs
an algebraic syntax designed for ease of coding and readability. Refer to
the Blackfin Processor Programming Reference for detailed information.
The instructions have been specifically tuned to provide a flexible, densely
encoded instruction set that compiles to a very small final memory size.
The instruction set also provides fully featured multifunction instructions
that allow the programmer to use many of the processor core resources in
a single instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C
and C++ source code. In addition, the architecture supports both user
(algorithm/application code) and supervisor (O/S kernel, device drivers,
debuggers, ISRs) modes of operation, allowing multiple levels of access to
core resources.

The assembly language, which takes advantage of the processor’s unique
architecture, offers these advantages:

• Embedded 16/32-bit microcontroller features, such as arbitrary bit
and bit field manipulation, insertion, and extraction; integer opera­tions on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers

• Seamlessly integrated DSP/CPU features optimized for both 8-bit
and 16-bit operations

1-28 ADSP-BF52x Blackfin Processor Hardware Reference

• A multi-issue load/store modified Harvard architecture, which sup­ports two 16-bit MAC or four 8-bit ALU + two load/store + two
pointer updates per cycle

• All registers, I/O, and memory mapped into a unified 4G byte
memory space, providing a simplified programming model

Code density enhancements include intermixing of 16- and 32-bit
instructions with no mode switching or code segregation. Frequently used
instructions are encoded in 16 bits.

Development Tools

The processor is supported with a complete set of CROSSCORE® soft­ware and hardware development tools, including Analog Devices

emulators and the VisualDSP++® development environment. The same
emulator hardware that supports other Analog Devices products also fully
emulates the Blackfin processor family.

The VisualDSP++ project management environment lets programmers
develop and debug an application. This environment includes an
easy-to-use assembler that is based on an algebraic syntax, an archiver
(librarian/library builder), a linker, a loader, a cycle-accurate instruc­tion-level simulator, a C/C++ compiler, and a C/C++ runtime library that
includes DSP and mathematical functions. A key point for these tools is
C/C++ code efficiency. The compiler has been developed for efficient
translation of C/C++ code to Blackfin processor assembly. The Blackfin
processor has architectural features that improve the efficiency of com­piled C/C++ code.

ADSP-BF52x Blackfin Processor Hardware Reference 1-29

Debugging both C/C++ and assembly programs with the VisualDSP++
debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and
object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ Integrated Development and Debugging Environment
(IDDE) lets programmers define and manage software development. Its
dialog boxes and property pages let programmers configure and manage all
development tools, including color syntax highlighting in the Visu­alDSP++ editor. These capabilities permit programmers to:

• Control how the development tools process inputs and generate
outputs

• Maintain a one-to-one correspondence with the tool’s com­mand-line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource
management tailored specifically to address the memory and timing con­straints of DSP programming. These capabilities enable engineers to
develop code more effectively, eliminating the need to start from the very
beginning, when developing new application code. The VDK features
include threads, critical and unscheduled regions, semaphores, events, and
device flags. The VDK also supports priority-based, pre-emptive, coopera-

1-30 ADSP-BF52x Blackfin Processor Hardware Reference

tive and time-sliced scheduling approaches. In addition, the VDK was
designed to be scalable. If the application does not use a specific feature,
the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or
not. The VDK is integrated into the VisualDSP++ development environ­ment but can also be used with standard command-line tools. The VDK
development environment assists in managing system resources, automat­ing the generation of various VDK-based objects, and visualizing the
system state during application debug.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of
the processor to monitor and control the target board processor during
emulation. The emulator provides full speed emulation, allowing inspec­tion and modification of memory, registers, and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system loading or
timing.

In addition to the software and hardware development tools available
from Analog Devices, third parties provide a wide range of tools support­ing the Blackfin processor family. Hardware tools include the
ADSP-BF52x EZ-KIT Lite standalone evaluation/development cards.
Third party software tools include DSP libraries, real-time operating sys­tems, and block diagram design tools.

ADSP-BF52x Blackfin Processor Hardware Reference 1-31

1-32 ADSP-BF52x Blackfin Processor Hardware Reference

2 CHIP BUS HIERARCHY

This chapter discusses on-chip buses, how data moves through the system,
and other factors that determine the system organization. Following an
overview and a list of key features is a block diagram of the chip bus hier­archy and a description of its operation. The chapter concludes with
details about the system interconnects and associated system buses.

Overview

The ADSP-BF52x Blackfin processors feature a powerful chip bus hierar­chy on which all data movement between the processor core, internal
memory, external memory, and its rich set of peripherals occurs. The chip
bus hierarchy includes the controllers for system interrupts, test/emula­tion, and clock and power management. Synchronous clock domain
conversion is provided to support clock domain transactions between the
core and the system.

The processor system includes:

• The peripheral set (timers, real-time clock, TWI, Ethernet MAC
(ADSP-BF527), USB 2.0, GPIOs, UARTs, SPORTs, PPI, watch­dog timer, and SPI)

• The external bus interface unit (EBIU)

• The host DMA port (HOSTDP)

ADSP-BF52x Blackfin Processor Hardware Reference 2-1

• The Direct Memory Access (DMA) controller

• The interfaces between these, the system, and the optional external
(off-chip) resources

The following sections describe the on-chip interfaces between the system
and the peripherals via the:

• Peripheral Access Bus (PAB)

• DMA Access Bus (DAB)

• DMA Core Bus (DCB)

• DMA External Bus (DEB)

• External Access Bus (EAB)

The external bus interface unit (EBIU) is the primary chip pin bus and is
discussed in Chapter 7, “External Bus Interface Unit”.

2-2 ADSP-BF52x Blackfin Processor Hardware Reference