ANALOG DEVICES ADSP-2192 Service Manual

ADSP-219x/2192 DSP

Hardware Reference

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 1.1, April 2004

Part Number

82-002001-01

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo and VisualDSP++ are registered trademarks of Analog Devices, Inc.

EZ-KIT Lite is a trademark of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

INTRODUCTION

Purpose ......................................................................................... 1-1

Audience ...................................................................................... 1-1

Overview—Why Fixed-Point DSP? ............................................... 1-2

ADSP-219x Design Advantages ..................................................... 1-2

ADSP-219x Architecture Overview ............................................... 1-5

DSP Core Architecture ............................................................ 1-7

DSP Peripherals Architecture ................................................... 1-9

Memory Architecture .............................................................. 1-9

Internal (On-Chip) Memory ............................................. 1-11

Interrupts .............................................................................. 1-12

DMA Controller ................................................................... 1-12

PCI Port ............................................................................... 1-12

USB Port .............................................................................. 1-13

AC’97 Interface ..................................................................... 1-13

Low Power Operation ............................................................ 1-13

Clock Signals ........................................................................ 1-13

Reset Modes .......................................................................... 1-14

JTAG Port ............................................................................. 1-15

ADSP-219x/2192 DSP Hardware Reference i

CONTENTS

Development Tools ..................................................................... 1-15

Differences from Previous DSPs .................................................. 1-17

Computational Units and Data Register File ..................... 1-17

Shifter Result (SR) Register as Multiplier

Dual Accumulator ......................................................... 1-18

Shifter Exponent (SE) Register is not

Memory Accessible ........................................................ 1-18

Conditions (SWCOND) and Condition Code

(CCODE) Register ........................................................ 1-19

Unified Memory Space ..................................................... 1-20

Data Memory Page (DMPG1 and DMPG2) Registers ....... 1-20

Data Address Generator (DAG) Addressing Modes ............ 1-21

Base Registers for Circular Buffers. .................................... 1-21

Program Sequencer, Instruction Pipeline, and Stacks ......... 1-22

Conditional Execution (Difference in Flag

Input Support) .............................................................. 1-22

Execution Latencies (Different for JUMP Instructions) ...... 1-23

Instruction Set Enhancements ........................................... 1-24

For More Information About Analog Products ............................. 1-24

For Technical or Customer Support ........................................... 1-25

What’s New in This Manual ....................................................... 1-25

Related Documents .................................................................... 1-25

Conventions ............................................................................... 1-27

ii ADSP-219x/2192 DSP Hardware Reference

CONTENTS

COMPUTATIONAL UNITS

Overview ...................................................................................... 2-1

Using Data Formats ...................................................................... 2-4

Binary String ........................................................................... 2-4

Unsigned ................................................................................. 2-4

Signed Numbers: Two’s Complement ....................................... 2-5

Fractional Representation: 1.15 ................................................ 2-5

ALU Data Types ...................................................................... 2-5

Multiplier Data Types .............................................................. 2-6

Shifter Data Types ................................................................... 2-7

Arithmetic Formats Summary .................................................. 2-8

Setting Computational Modes ..................................................... 2-10

Latching ALU Result Overflow Status .................................... 2-10

Saturating ALU Results on Overflow ...................................... 2-11

Using Multiplier Integer and Fractional Formats .................... 2-12

Rounding Multiplier Results .................................................. 2-14

Unbiased Rounding .......................................................... 2-14

Biased Rounding ............................................................... 2-15

Using Computational Status ........................................................ 2-16

Arithmetic Logic Unit (ALU) ...................................................... 2-17

ALU Operation ..................................................................... 2-17

ALU Status Flags ................................................................... 2-18

ALU Instruction Summary .................................................... 2-19

ADSP-219x/2192 DSP Hardware Reference iii

CONTENTS

ALU Data Flow Details ......................................................... 2-21

ALU Division Support Features ............................................. 2-23

Multiply—Accumulator (Multiplier) ........................................... 2-28

Multiplier Operation ............................................................. 2-28

Placing Multiplier Results in MR or SR Registers .............. 2-29

Clearing, Rounding, or Saturating Multiplier Results ......... 2-30

Multiplier Status Flags ........................................................... 2-31

Saturating Multiplier Results on Overflow ............................. 2-31

Multiplier Instruction Summary ............................................ 2-33

Multiplier Data Flow Details ................................................. 2-34

Barrel-Shifter (Shifter) ................................................................ 2-37

Shifter Operations ................................................................. 2-37

Derive Block Exponent ..................................................... 2-39

Immediate Shifts .............................................................. 2-40

Denormalize ..................................................................... 2-42

Normalize, Single Precision Input ..................................... 2-44

Normalize, ALU Result Overflow ...................................... 2-45

Normalize, Double Precision Input ................................... 2-47

Shifter Status Flags ................................................................ 2-50

Shifter Instruction Summary ................................................. 2-50

Shifter Data Flow Details ...................................................... 2-52

Data Register File ....................................................................... 2-57

Secondary (Alternate) Data Registers ........................................... 2-59

Multifunction Computations ...................................................... 2-60

iv ADSP-219x/2192 DSP Hardware Reference

CONTENTS

PROGRAM SEQUENCER

Overview ...................................................................................... 3-1

Instruction Pipeline ...................................................................... 3-7

Instruction Cache ......................................................................... 3-9

Using The Cache ................................................................... 3-11

Optimizing Cache Usage ....................................................... 3-12

Branches and Sequencing ............................................................ 3-14

Indirect Jump Page (IJPG) Register ........................................ 3-15

Conditional Branches ............................................................ 3-16

Delayed Branches .................................................................. 3-16

Loops and Sequencing ................................................................. 3-20

Managing Loop Stacks ........................................................... 3-24

Restrictions On Ending Loops ............................................... 3-24

Interrupts and Sequencing ........................................................... 3-24

Sensing Interrupts ................................................................. 3-30

Masking Interrupts ................................................................ 3-31

Latching Interrupts ................................................................ 3-31

Stacking Status During Interrupts .......................................... 3-32

Nesting Interrupts ................................................................. 3-32

Interrupting Idle .................................................................... 3-34

Stacks and Sequencing ................................................................ 3-34

Conditional Sequencing .............................................................. 3-39

Sequencer Instruction Summary .................................................. 3-42

ADSP-219x/2192 DSP Hardware Reference v

CONTENTS

DATA ADDRESS GENERATORS

Overview ...................................................................................... 4-1

Setting DAG Modes ..................................................................... 4-4

Secondary (Alternate) DAG Registers ...................................... 4-4

Bit-Reverse Addressing Mode .................................................. 4-6

DAG Page Registers (DMPGx) ................................................ 4-6

Using DAG Status ........................................................................ 4-8

DAG Operations .......................................................................... 4-9

Addressing with DAGs ............................................................ 4-9

Addressing Circular Buffers ................................................... 4-11

Addressing With Bit-Reversed Addresses ................................ 4-15

Modifying DAG Registers ..................................................... 4-19

DAG Register Transfer Restrictions ............................................. 4-20

DAG Instruction Summary ......................................................... 4-21

MEMORY

Overview ...................................................................................... 5-1

Internal Address and Data Buses .............................................. 5-3

Internal Data Bus Exchange .................................................... 5-5

ADSP-2192 Memory Map ............................................................ 5-8

P0 DSP Core Internal Memory Space .................................... 5-10

P1 DSP Core Internal Memory Space .................................... 5-11

Shared Memory .................................................................... 5-11

Host (PCI/USB) and DSP Internal Memory Space ................ 5-12

vi ADSP-219x/2192 DSP Hardware Reference

CONTENTS

System Control Registers ....................................................... 5-13

Shared I/O Memory-mapped Registers ................................... 5-13

Arranging Data in Memory ......................................................... 5-13

Data Move Instruction Summary ................................................. 5-14

DUAL DSP CORES

Overview ...................................................................................... 6-1

Shared Dual DSP Core Settings ............................................... 6-1

Unique DSP Core Settings ....................................................... 6-2

Setting Dual DSP Core Features .................................................... 6-3

System Control ....................................................................... 6-3

Power Down Mode Control ..................................................... 6-5

Clock Multiplier Mode Control ............................................. 6-10

GPIO and Serial EEPROM Mode Control ............................. 6-11

Using Dual-DSP Interrupts and Flags .......................................... 6-13

Controlling I/O Register Bus Accesses ......................................... 6-17

Using DSP and PCI Mailbox Registers ........................................ 6-20

Mailbox Status (MBXSTAT) Register ................................ 6-21

Mailbox Interrupt Control (MBXCTL) Register ................ 6-24

InBox 0 - PCI/USB to DSP Mailbox 0

(MBX_IN0) Register ...................................................... 6-26

InBox 1 - PCI/USB to DSP Mailbox 1

(MBX_IN1) Register ...................................................... 6-26

ADSP-219x/2192 DSP Hardware Reference vii

CONTENTS

OutBox 0 - DSP to PCI/USB Mailbox 0

(MBX_OUT0) Register ................................................. 6-26

OutBox 1 - DSP to PCI/USB Mailbox 1

(MBX_OUT1) Register ................................................. 6-26

I/O PROCESSOR

Overview ...................................................................................... 7-1

Setting I/O Processor—Host Port Modes .................................... 7-12

Host Port Buffer Modes ........................................................ 7-14

Host Port Scatter-Gather DMA Mode ................................... 7-16

Setting I/O Processor—AC’97 Port Modes .................................. 7-18

Host Port DMA Status ............................................................... 7-19

DMA Controller Operation ........................................................ 7-20

Managing DMA Channel Priority ......................................... 7-21

Chaining DMA Processes ...................................................... 7-22

Host Port DMA .......................................................................... 7-22

AC’97 Port DMA ....................................................................... 7-24

HOST (PCI/USB) PORT

Overview ...................................................................................... 8-1

Host Port Selection ................................................................. 8-1

Mode Strap Pin Connections ................................................... 8-2

PCI Parallel Interface .................................................................... 8-2

Configuration Spaces .............................................................. 8-2

Interactions Between Functions ........................................... 8-5

Base Address Registers ........................................................ 8-8

Peripheral Device Control Registers .................................... 8-9

viii ADSP-219x/2192 DSP Hardware Reference

CONTENTS

Power Management Interactions .............................................. 8-9

PCI Clock Domain ............................................................... 8-11

Peripheral Device Control Register Access .............................. 8-12

Resets .................................................................................... 8-14

Interrupts .............................................................................. 8-14

PCI Control Register ............................................................. 8-16

PCI Port Priority on the PDC Bus ..................................... 8-18

DSP Mailbox Registers .......................................................... 8-18

InBoxes ............................................................................ 8-18

OutBoxes .......................................................................... 8-19

Status ............................................................................... 8-19

Control ............................................................................. 8-21

Indirect Access to I/O Space .................................................. 8-23

USB Interface ............................................................................. 8-25

Overview .............................................................................. 8-25

USB Requirements ................................................................ 8-25

Implementation ..................................................................... 8-26

Block Diagram of USB Module ............................................. 8-27

USB-SIE ........................................................................... 8-27

Endpoint 0 Control .......................................................... 8-28

MCU ............................................................................... 8-28

I/O REG Interface ............................................................ 8-29

DSP DMA Interface ......................................................... 8-29

DSP Code/Data Endpoint Control .................................... 8-29

ADSP-219x/2192 DSP Hardware Reference ix

CONTENTS

Features and Modes ............................................................... 8-30

Endpoint Types ................................................................ 8-30

Data Transfers .................................................................. 8-30

References ............................................................................. 8-32

MCU Register Definitions .................................................... 8-33

Config USB Device Definitions and

Descriptor Tables ............................................................... 8-52

Vendor-Specific Commands .................................................. 8-55

DSP Register Definitions ...................................................... 8-58

USB DSP Register Definitions .............................................. 8-58

DSP Code Download ............................................................ 8-65

General Comments ........................................................... 8-67

Starting DSP Code Execution ........................................... 8-67

MCU ROM Firmware Structure ....................................... 8-70

MCU Firmware Programmers Model (Endpoint 0) ............ 8-72

Example Initialization Process ............................................... 8-81

Config Device Definition ................................................. 8-85

Modem Device Definition ................................................ 8-85

Serial EEPROM Interface ................................................. 8-86

Serial EEPROM Changeable Fields for USB Descriptors ... 8-86

ADSP-2192 USB Data Pipe Operations ................................ 8-87

OUT Transactions (Host to Device) .................................. 8-91

IN Transactions (Device to Host) ..................................... 8-92

x ADSP-219x/2192 DSP Hardware Reference

CONTENTS

AC’97 CODEC PORT

Overview ...................................................................................... 9-1

ADSP-2192 Features and Functionality ......................................... 9-1

FIFO Control and Status Register ................................................. 9-3

FIFO Transmit Control and Status Register ............................. 9-3

FIFO Receive Control and Status Register ................................ 9-5

FIFO DMA Address Registers .................................................. 9-8

FIFO DMA Current Count Registers ....................................... 9-8

FIFO DMA Count Registers .................................................... 9-9

FIFO DMA Next Address Registers ......................................... 9-9

16-bit Transmit Data Register ............................................. 9-9

16-bit Receive Data Register ................................................ 9-9

AC-Link Digital Serial Interface Protocol ............................... 9-10

Resetting the AC’97 .......................................................... 9-12

ADSP-2192 AC’97 Control Registers .......................................... 9-13

AC’97 Link Control/Status Register (AC97LCTL) ................. 9-15

AC’97 Link Status Register (AC97STAT) ............................... 9-19

AC’97 Slot Enable Register (AC97SEN) ................................ 9-21

AC’97 Input Slot Valid Register (AC97SVAL) ........................ 9-22

AC’97 AC97STAT:REG and Frame Interrupt Timing ........ 9-22

AC’97 External Codec Register Spaces ............................... 9-23

AC’97 Slot Request Register (AC97SREQ) ............................ 9-24

AC’97 GPIO Status Register (AC97SIF) ................................ 9-24

ADSP-219x/2192 DSP Hardware Reference xi

CONTENTS

ADSP-2192 AC’97 Audio Interface ............................................. 9-25

External Audio Codec (AC’97) Subsystem ............................. 9-25

Resource Allocation .......................................................... 9-25

AC’97 2.1 Protocol Summary ..................................................... 9-27

Access to AC’97 Codec Control/Status Registers .................... 9-28

AC’97 2.1 Link Powerdown States ......................................... 9-30

State Transitions ............................................................... 9-33

Configuring AC’97 Sample Data Streams .................................... 9-36

JTAG TEST-EMULATION PORT

SYSTEM DESIGN

Overview .................................................................................... 11-1

Sources for Additional Information ............................................. 11-1

Pin Descriptions ......................................................................... 11-3

Clock Signals .............................................................................. 11-7

Synchronization Delay .......................................................... 11-9

Configurable Clock Multiplier Considerations .................... 11-10

Maximizing Performance of DSP Algorithms ............................. 11-11

Resetting the Processor ............................................................. 11-13

Power On Reset .................................................................. 11-13

Forced Reset Via PCI/USB .................................................. 11-14

Software Reset .................................................................... 11-14

Reset Progression ................................................................ 11-14

Resets and Software-Forced Rebooting ................................. 11-16

xii ADSP-219x/2192 DSP Hardware Reference

CONTENTS

Interrupts ................................................................................. 11-22

Flag Pins ................................................................................... 11-22

Powerup and Powerdown .......................................................... 11-23

Powerup Issues .......................................................................... 11-24

Powerup Sequence ............................................................... 11-24

Power Regulators ................................................................. 11-26

2.5V Regulator Options .................................................. 11-27

Power Management Description .......................................... 11-28

Powerdown ............................................................................... 11-29

Powerdown Control ............................................................. 11-30

Entering and Exiting Powerdown ......................................... 11-31

Powering Down the USB ..................................................... 11-32

Powering Down the PCI ...................................................... 11-32

Powering Down the AC’97 Link .......................................... 11-33

Entering Powerdown ........................................................... 11-34

Exiting Powerdown .............................................................. 11-35

Ending Powerdown ......................................................... 11-35

Ending Powerdown with the PORST Pin ......................... 11-35

Startup Time after Powerdown ............................................. 11-36

Using an External TTL/CMOS Clock ............................. 11-36

Processor Operation During Powerdown .............................. 11-36

Interrupts And Flags ....................................................... 11-37

Conditions for Lowest Power Consumption ......................... 11-37

AC’97 Low Power Mode ................................................ 11-38

Using Powerdown as A Non-Maskable Interrupt ................... 11-39

ADSP-219x/2192 DSP Hardware Reference xiii

CONTENTS

Emulation ................................................................................ 11-39

EZ-KIT Lite ............................................................................. 11-40

Recommended Reading ............................................................ 11-41

ADSP-219X DSP CORE REGISTERS

Overview ...................................................................................... A-1

Core Registers Summary ......................................................... A-2

Core Status Registers .................................................................... A-8

Arithmetic Status (ASTAT) Register ........................................ A-9

Mode Status (MSTAT) Register ............................................. A-11

System Status (SSTAT) Register ............................................. A-14

Computational Unit Registers ..................................................... A-15

Data Register File (DREG) Registers ..................................... A-16

ALU X- and Y-Input (AX0, AX1, AY0, AY1) Registers ........... A-16

ALU Results (AR) Register .................................................... A-17

Multiplier X- and Y-Input (MX0, MX1, MY0, MY1)

Registers ............................................................................ A-17

Multiplier Results (MR2, MR1, MR0) Registers .................... A-17

Shifter Input (SI) Register ..................................................... A-17

Shifter Exponent (SE) and Block Exponent (SB) Registers ...... A-18

Program Sequencer Registers ....................................................... A-18

Interrupt Mask (IMASK) and Interrupt

Latch (IRPTL) Registers ..................................................... A-19

Interrupt Control (ICNTL) Register ...................................... A-20

xiv ADSP-219x/2192 DSP Hardware Reference

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Indirect Jump Page (IJPG) Register ....................................... A-21

PC Stack Page (STACKP) and

PC Stack Address (STACKA) Registers ............................... A-21

Loop Stack Page (LPSTACKP) and

Loop Stack Address (LPSTACKA) Register ......................... A-22

Counter (CNTR) Register .................................................... A-22

Condition Code (CCODE) Register ..................................... A-23

Cache Control (CACTL) Register ......................................... A-23

Data Address Generator Registers ............................................... A-24

Index Registers (Ix) ............................................................... A-24

Modify Registers (Mx) .......................................................... A-24

Length and Base (Lx,Bx) Registers ........................................ A-25

Data Memory Page (DMPGx) Register ................................. A-25

Memory Interface Registers ........................................................ A-26

PM Bus Exchange (PX) Register ........................................... A-26

I/O Memory Page (IOPG) Register ....................................... A-26

ADSP-2192 DSP PERIPHERAL REGISTERS

Overview ..................................................................................... B-1

Peripheral Registers ...................................................................... B-2

DSP Peripherals Architecture .................................................. B-3

Peripheral Device Register Groups ................................................ B-4

Summary ............................................................................... B-4

ADSP-219x/2192 DSP Hardware Reference xv

CONTENTS

ADSP-2192 System Control Registers ........................................... B-6

STCTLx FIFO Transmit Control Register ........................... B-9

SRCTLx FIFO Receive Control Register ............................. B-9

xxxADDR DMA Address Register ..................................... B-10

xxxNXTADDR DMA Next Address Register ..................... B-10

xxxCNT DMA Count Register ......................................... B-10

xxxCURCNT DMA Current Count Register ..................... B-10

ADSP-2192 Peripheral Device Control Registers ......................... B-11

ADSP-2192 Chip Control Registers ...................................... B-13

Chip Control (SYSCON) Registers ................................... B-14

Power Management Functions .......................................... B-18

DSP Powerdown (PWRPx) Registers ................................. B-19

DSP PLL Control (PLLCTL) Register ............................... B-23

General-purpose I/O (GPIO) Control Registers ..................... B-24

GPIO Configuration (GPIOCFG) Register ....................... B-25

GPIO Polarity (GPIOPOL) Register ................................. B-25

GPIO Sticky (GPIOSTKY) Register .................................. B-26

GPIO Wakeup Control (GPIOWAKECTL) Register ......... B-26

GPIO Status (GPIOSTAT) Register .................................. B-26

GPIO Control (GPIOCTL) Register ................................. B-27

GPIO Pullup (GPIOPUP) Register ................................... B-27

GPIO Pulldown (GPIOPDN) Register .............................. B-27

EEPROM I/O Control/Status (SPROMCTL) Register ........... B-28

xvi ADSP-219x/2192 DSP Hardware Reference

CONTENTS

Host Mailbox Registers ......................................................... B-30

Overview ......................................................................... B-30

CardBus Function Event Registers ........................................ B-32

CSTSCHG Signal ............................................................ B-33

INTA Signal .................................................................... B-34

CIS Tuple Requirements .................................................. B-35

AC’97 Controller Registers ................................................... B-41

AC’97 Link Control/Status Register (AC97LCTL) ............ B-42

AC’97 Link Status Register (AC97STAT) ......................... B-42

AC’97 Slot Enable Register (AC97SEN) ........................... B-43

AC’97 Input Slot Valid Register (AC97SVAL) .................. B-43

AC’97 Slot Request Register (AC97SREQ) ....................... B-44

AC’97 GPIO Status Register (AC97SIF) ........................... B-44

AC’97 Codec Registers ........................................................ B-45

AC’97 Codec Register Space-Primary Codec 0

(AC97EXT0) Register .................................................. B-45

AC’97 Codec Register Space, Secondary Codec 1

(AC97EXT1) Register .................................................. B-45

AC’97 Codec Register Space, Secondary Codec 2

(AC97EXT2) Register .................................................. B-46

PCI DMA Address, Count Registers ..................................... B-46

DMA Control Registers ................................................... B-46

PCI DMA Control Registers ............................................ B-46

PCI Interrupt, Control Registers ........................................... B-47

ADSP-219x/2192 DSP Hardware Reference xvii

CONTENTS

DMA Transfer Count 0 - Bus Master Sample Transfer

Count (PCI_MSTRCNT0) Register ............................... B-48

DMA Transfer Count 1 - Bus Master Sample Transfer

Count (PCI_MSTRCNT1) Register ............................... B-48

DMA Control X - Bus Master Control and Status

(PCI_DMACx) Register ................................................. B-49

PCI Interrupt (PCI_IRQSTAT) Register ........................... B-50

PCI Control (PCI_CFGCTL) Register .............................. B-53

PCI Configuration Register Space ......................................... B-54

Commonalities Between the Three Functions .................... B-54

Interactions Between the Three Functions ......................... B-55

PCI Configuration Register Space, Function 0 .................. B-56

PCI Configuration Register Space, Function 1 .................. B-58

PCI Configuration Register Space, Function 2 .................. B-59

PCI Configuration Space .................................................. B-60

Interaction Between Registers ........................................... B-67

USB DSP Registers ............................................................... B-71

Overview .......................................................................... B-71

DSP Register Definitions ...................................................... B-72

DSP Memory Buffer Base Addr Register ................................ B-74

DSP Memory Buffer Size Register .................................... B-75

DSP Memory Buffer RD Pointer Offset Register .................... B-75

DSP Memory Buffer WR Pointer Offset Register .................. B-76

MCU Register Definitions .................................................... B-76

USB Endpoint Description Register ...................................... B-79

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CONTENTS

USB Endpoint NAK Counter Register .................................. B-80

USB Endpoint Stall Policy Register ....................................... B-81

USB Endpoint 1 Code Download Base Address Register ........ B-82

USB Endpoint 2 Code Download Base Address Register ........ B-83

USB Endpoint 3 Code Download Base Address Register ........ B-84

USB Endpoint 1 Code Download Current Write

Pointer Offset Register ....................................................... B-85

USB Endpoint 2 Code Download Current Write

Pointer Offset Register ...................................................... B-86

USB Endpoint 3 Code Download Current Write

Pointer Offset Register ...................................................... B-87

USB SETUP Token Command Register ................................ B-88

USB SETUP Token Data Register ......................................... B-89

USB SETUP Counter Register .............................................. B-90

USB Register I/O Address Register ....................................... B-91

USB Register I/O Data Register ........................................... B-92

USB Control Register ........................................................... B-93

USB Address/Endpoint Register ............................................ B-94

USB Frame Number Register ................................................ B-94

ADSP-219x/2192 DSP Hardware Reference xix

CONTENTS

NUMERIC FORMATS

Overview ...................................................................................... C-1

Un/Signed: Twos-Complement Format ......................................... C-1

Integer or Fractional ..................................................................... C-1

Binary Multiplication ................................................................... C-5

Fractional Mode And Integer Mode ......................................... C-6

Block Floating-Point Format ......................................................... C-7

ADSP-2192 TIMER

Overview ..................................................................................... D-1

Timer Architecture ...................................................................... D-2

Resolution ................................................................................... D-4

Timer Operation ......................................................................... D-4

Enabling the Timer ...................................................................... D-6

ADSP-2192 INTERRUPTS

Overview ...................................................................................... E-1

Peripheral Interrupts ..................................................................... E-1

Other Interrupt Types ................................................................... E-4

GLOSSARY

Terms .......................................................................................... G-1

INDEX

xx ADSP-219x/2192 DSP Hardware Reference

1 INTRODUCTION

Figure 1-0.

Table 1-0.

Listing 1-0.

Purpose

The ADSP-219x/2192 DSP Hardware Reference provides architectural information on the ADSP-219x modified Harvard architecture Digital Signal Processor (DSP) core and ADSP-2192 DSP product. The architectural descriptions cover functional blocks, buses, and ports, including all features and processes they support. For programming information, see the ADSP-219x DSP Instruction Set Reference.

Audience

DSP system designers and programmers who are familiar with signal processing concepts are the primary audience for this manual. This manual assumes that the audience has a working knowledge of microcomputer technology and DSP-related mathematics.

DSP system designers and programmers who are unfamiliar with signal processing can use this manual, but they should supplement this manual with other texts that describe DSP techniques.

All readers, particularly system designers, should refer to the DSP’s data sheet for timing, electrical, and package specifications. For additional suggested reading, see “For More Information About Analog Products” on

page 1-24.

ADSP-219x/2192 DSP Hardware Reference 1-1

Overview—Why Fixed-Point DSP?

A digital signal processor’s data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios. Because 16-bit, fixed-point DSP math is required for certain DSP coding algorithms, using a 16-bit, fixed-point DSP can provide all the features needed for certain algorithm and software development efforts. Also, a narrower bus width (16-bit as opposed to 32- or 64-bit wide) leads to reduced power consumption and other design savings. The extent to which this is true depends on the fixed-point processor’s architecture. High-level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and error handling. The ADSP-2192 DSP is a highly integrated, 16-bit fixed-point DSP that provides many of these design advantages.

ADSP-219x Design Advantages

The ADSP-219x family DSPs are high-performance 16-bit DSPs for communications, instrumentation, industrial/control, voice/speech, medical, military, and other applications. These DSPs provide a DSP core that is compatible with previous ADSP-2100 family DSPs, but they also provide many additional features. The ADSP-219x core combines with on-chip peripherals to form a complete system-on-a-chip. The off-core peripherals add on-chip SRAM, integrated I/O peripherals, timer, and interrupt controller.

The ADSP-219x architecture balances a high performance processor core with high performance buses (PM, DM, DMA). In the core, every computational instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate.

1-2 ADSP-219x/2192 DSP Hardware Reference

Introduction

Figure 1-1 shows a detailed block diagram of the ADSP-2192 processor.

MEMORY

ⴛ24 PM

16K

ⴛ16 DM

32K BOOT ROM

ADDR DATAADDR DATA

P1 DMA

CONTROLLER

FIFOS

ADSP-21 9X

DSP CORE

DAG2

DAG1

4X4X 16

4X4X16

BUS

CONNEC

(PX)

DATA

FILE

MULT

PM ADDRESS BUS

DM ADDRESS BUS

INPUT

REGISTERS

RESULT

REGISTERS

16 X 16-BIT

INTERRUPT CONTROLLER/

TIMER/FLA GS

CACHE 64 X 24-

BIT

PROGRAM

SEQUENCER

2 4

PM DATA BUS

DM DATA BUS

BARREL SHIFTER

2 4

1 6

ALU

MEMORY

16K

ⴛ24 PM

64K

ⴛ16 DM

BOOT ROM

ADDR DATA ADDR DATA

CORE

INTERFACE

P0 DMA

CONTROLLER

FIFOS

SHARED

MEMORY

ⴛ16 DM

ADDR DATA

SHARED DSP

I/O MA P P E D REGISTERS

PROCESSOR P 0 PROCESSOR P1

GP I/O PINS

(& OPTIONAL

SERIAL

EEPROM)

SERIAL PORT

AC'97

COMPLIANT

HOST PORT

PCI 2.2

USB 1.1

JTAG

EMULATION

PORT

Figure 1-1. ADSP-2192 Block Diagram

This diagram illustrates the following ADSP-2192 architectural features:

• Computation units for the ADSP-219x family—multiplier, ALU, shifter, and data register file

• Program sequencer for the ADSP-219x family, with related instruction cache, interval timer, and Data Address Generators (DAG1 and DAG2)

• PCI/USB Host port

ADSP-219x/2192 DSP Hardware Reference 1-3

ADSP-219x Design Advantages

• AC’97 codec port

• SRAM for the ADSP-2192

• Input/Output (I/O) processor with integrated DMA controllers

• JTAG Test Access Port for board test and emulation on the ADSP-2192

Figure 1-1 also shows the two cores of the ADSP-2192 (processors P0 and

P1). Additionally, it shows the four on-chip buses of the ADSP-2192: the Program Memory Address (PMA) bus, Program Memory Data (PMD) bus, Data Memory Address (DMA) bus, and the Data Memory Data (DMD) bus. During a single cycle, these buses let the processor access two data operands (one from PMD and one from DMD), and access an instruction (from the cache).

Further, the ADSP-219x addresses the five central requirements for DSPs:

• Fast, flexible arithmetic computation units

• Unconstrained data flow to and from the computation units

• Extended precision and dynamic range in the computation units

• Dual address generators with circular buffering support

• Efficient program sequencing

Unconstrained Data Flow. The ADSP-219x has a modified Harvard architecture combined with a data register file. In every cycle, the DSP can:

• Read two values from memory or write one value to memory

• Complete one computation

• Write up to three values back to the register file

1-4 ADSP-219x/2192 DSP Hardware Reference

Introduction

Fast, Flexible Arithmetic. The ADSP-219x family DSPs execute all computational instructions in a single cycle. They provide both fast cycle times and a complete set of arithmetic operations.

40-Bit Extended Precision. The DSP handles 16-bit integer and fractional formats (twos-complement and unsigned). The processors carry extended precision through result registers in their computation units, limiting intermediate data truncation errors.

Dual Address Generators. The DSP has two data address generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus and bit-reverse operations are supported with only memory page constraints on data buffer placement.

Efficient Program Sequencing. In addition to zero-overhead loops, the DSP supports quick setup and exit for loops. Loops are both nestable (eight levels in hardware) and interruptable. The processors support both delayed and non-delayed branches.

ADSP-219x Architecture Overview

An ADSP-219x is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. These DSPs provide a complete system-on-a-chip, integrating a large, high-speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the ADSP-219x architecture, which appears in

Figure 1-1 on page 1-3.

The ADSP-2192 combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with PCI/USB interface, AC’97 serial port, a programmable timer, a DMA controller, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory blocks.

ADSP-219x/2192 DSP Hardware Reference 1-5

ADSP-219x Architecture Overview

The ADSP-2192 architecture is code compatible with ADSP-218x family DSPs. Though the architectures are compatible, the ADSP-2192 architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2192 more flexible and even easier to program than the ADSP-218x DSPs.

Indirect addressing options provide addressing flexibility—pre-modify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering.

The ADSP-2192 integrates 128K words of on-chip memory configured as 32K words (24-bit) of program RAM (16K words each on DSP P0 and DSP P1) and 96K words (16-bit) of data RAM (64K words on DSP P0 and 32K words on DSP P1). Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment.

The ADSP-2192’s flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, each core of the ADSP-2192 can:

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

1-6 ADSP-219x/2192 DSP Hardware Reference

Introduction

DSP Core Architecture

The ADSP-219x instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-219x assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

Figure 1-1 on page 1-3 shows the architecture of the ADSP-219x core. It

contains three independent computational units: the ALU, the multiplier/accumulator, and the shifter.

The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives also are supported. The multiplier performs single-cycle multiply, multiply/add, and multiply/subtract operations. The multiplier now has two 40-bit accumulator results. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can efficiently implement numeric format control, including multiword and block floating-point representations.

Register-usage rules influence placement of input and results within the computational units. For all unconditional, non-multi-function instructions, the computational units’ data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions limiting which data registers may provide inputs or receive results from each computational unit. For more information, see “Multifunction

Computations” on page 2-60.

ADSP-219x/2192 DSP Hardware Reference 1-7

ADSP-219x Architecture Overview

A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2192 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers.

Page registers in the DAGs allow circular addressing within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved by using internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• IO or DMA Address Bus

• IO or DMA Data Bus

1-8 ADSP-219x/2192 DSP Hardware Reference

+ 598 hidden pages

ANALOG DEVICES ADSP-2192 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

INTRODUCTION

COMPUTATIONAL UNITS

PROGRAM SEQUENCER

DATA ADDRESS GENERATORS

MEMORY

DUAL DSP CORES

I/O PROCESSOR

HOST (PCI/USB) PORT

AC’97 CODEC PORT

JTAG TEST-EMULATION PORT

SYSTEM DESIGN

ADSP-219X DSP CORE REGISTERS

ADSP-2192 DSP PERIPHERAL REGISTERS

NUMERIC FORMATS

ADSP-2192 TIMER

ADSP-2192 INTERRUPTS

GLOSSARY

INDEX

1 INTRODUCTION

Purpose

Audience

Overview—Why Fixed-Point DSP?

ADSP-219x Design Advantages

Figure 1-1. ADSP-2192 Block Diagram

ADSP-219x Architecture Overview

DSP Core Architecture