Datasheet ADSP-2191M Datasheet (Analog Devices)

a

DSP Microcomputer

ADSP-2191M

PERFORMANCE FEATURES

6.25 ns Instruction Cycle Time, for up to 160 MIPS
Sustained Performance

ADSP-218x Family Code Compatible with the Same

Easy to Use Algebraic Syntax

Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-

putation and Memory Instructions

Instruction Cache Allows Dual Operand Fetches in Every

Instruction Cycle

FUNCTIONAL BLOCK DIAGRAM

ADSP-219x
DSP CORE

DAG1

4 ⴛ 4 ⴛ 16

REGISTER

MULT

DATA

FILE

4ⴛ 4 ⴛ 16

PX

DAG2

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

INPUT

REGISTERS

RESULT

REGISTERS

16 ⴛ 16-BIT

64ⴛ 24-BIT

PROGRAM

SEQUENCER

DMA

CONNECT

BARREL
SHIFTER

CACHE

24

24

24

24

16

ALU

Multifunction Instructions
Pipelined Architecture Supports Efficient Code

Execution

Architectural Enhancements for Compiled C and C++

Code Efficiency

Architectural Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for
Added Registers, and Peripherals

Flexible Power Management with User-Selectable

Power-Down and Idle Modes

FOUR INDEPENDENT BLOCKS

ADDRESS

ADDRESS

ADDRESS

DMA ADDRESS

DMA DATA

24

16

I/O DATA

24 BIT

ADDRESS

I/O ADDRESS

I/O REGISTERS

(MEMORY-MAPPED)

CONTROL

BUFFERS

SYSTEM INTERRUPT CONTROLLER

INTERNAL MEMORY

16 BIT

16 BIT

DATA

DATA

DATA

18

DMA

CONTROLLER 6

24 BIT

STATUS

DATA

0
K
C

1

O

K

L

2

C

B

K

O

3

C

L

K

O

B

C

L

O

B

L
B

PROGRAMMABLE

FLAGS (16)

JTAG

TEST &

EMULATION

EXTERNAL PORT

ADDR BUS

MUX

DATA BUS

MUX

I/O PROCESSOR

HOST PORT

SERIAL PORTS

(3)

SPI PORTS

(2)

UART PORT

(1)

TIMERS (3)

6

22

16

24

18

2

3

REV. 0

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ADSP-2191M

INTEGRATION FEATURES
160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit

Memory RAM and 32K Words 16-Bit Memory RAM

Dual-Purpose 24-Bit Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit
Accumulators

Unified Memory Space Allows Flexible Address Genera-

tion, Using Two Independent DAG Units

Powerful Program Sequencer Provides Zero-Overhead

Looping and Conditional Instruction Execution

Enhanced Interrupt Controller Enables Programming of

Interrupt Priorities and Nesting Modes

SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit

Host Interface

16-Bit External Memory Interface for up to 16M Words of

Addressable Memory Space

Three Full-Duplex Multichannel Serial Ports, with

Support for H.100 and up to 128 TDM Channels with
A-Law and ␮-Law Companding Optimized for Telecom-

munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Inter-

rupt Support
Three Programmable Interval Timers with PWM

Generation, PWM Capture/Pulsewidth Measurement,

and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time

for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External

8- or 16-Bit Host Device, SPI ROM, or UART with

Autobaud Detection
Programmable PLL Supports 1ⴛ to 32ⴛ Input Frequency

Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports

On-Chip Emulation and System Debugging

2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3

DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3

DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9

Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9

UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10

Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12

Instruction Set Description . . . . . . . . . . . . . . . . . . . .13

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13

Additional Information . . . . . . . . . . . . . . . . . . . . . . .15

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19

ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Environmental Conditions . . . . . . . . . . . . . . . . . . . .42

144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44

144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49

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ADSP-2191M

GENERAL DESCRIPTION

The ADSP-2191M DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.

The ADSP-2191M combines the ADSP-219x family base
architecture (three computational units, two data address gener­ators, and a program sequencer) with three serial ports, two
SPI-compatible ports, one UART port, a DMA controller, three
programmable timers, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.

The ADSP-2191M architecture is code-compatible with DSPs
of the ADSP-218x family. Although the architectures are
compatible, the ADSP-2191M architecture has a number of
enhancements over the ADSP-218x architecture. The enhance­ments to computational units, data address generators, and
program sequencer make the ADSP-2191M more flexible and
even easier to program.

Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, two’s-complement value and base address registers for
easier implementation of circular buffering.

The ADSP-2191M integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also
provided to reduce power consumption. The ADSP-2191M is
available in 144-lead LQFP and 144-ball mini-BGA packages.

Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2191M operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except single-word instructions,
execute in one processor.

The ADSP-2191M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2191M can:

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

These operations take place while the processor continues to:

• Receive and transmit data through two serial ports

• Receive and/or transmit data from a Host

• Receive or transmit data through the UART

• Receive or transmit data over two SPI ports

• Access external memory through the external memory

interface

• Decrement the timers

DSP Core Architecture

The ADSP-2191M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-2191M assembly language

uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.

The functional block diagram on page 1 shows the architecture
of the ADSP-219x core. It contains three independent compu­tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from the
register file and have provisions to support multiprecision com­putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi­ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith­metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.

Register-usage rules influence placement of input and results
within the computational units. For most operations, the com­putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor­mation, see the

A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou­tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-2191M executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to access
data (indirect addressing), it is pre- or post-modified by the value
of one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word bound­aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of
internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• DMA Address Bus

• DMA Data Bus

ADSP-219x DSP Instruction Set Reference

.

–3–REV. 0

ADSP-2191M

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit­ting the ADSP-2191M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
DSP’s dual memory buses also let the ADSP-219x core fetch an
operand from data memory and the next instruction from
program memory in a single cycle.

DSP Peripherals Architecture

The functional block diagram on page 1 shows the DSP’s
on-chip peripherals, which include the external memory inter­face, Host port, serial ports, SPI-compatible ports, UART port,
JTAG test and emulation port, timers, flags, and interrupt con­troller. These on-chip peripherals can connect to off-chip devices
as shown in Figure 1.

The ADSP-2191M has a 16-bit Host port with DMA capability
that lets external Hosts access on-chip memory. This 24-pin
parallel port consists of a 16-pin multiplexed data/address bus
and provides a low-service overhead data move capability. Con­figurable for 8 or 16 bits, this port provides a glueless interface
to a wide variety of 8- and 16-bit microcontrollers. Two
chip-selects provide Hosts access to the DSP’s entire memory
map. The DSP is bootable through this port.

The ADSP-2191M also has an external memory interface that is
shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The exter nal
port consists of a 16-bit data bus, a 22-bit address bus, and
control signals. The data bus is configurable to provide an 8 or
16 bit interface to external memory. Support for word packing
lets the DSP access 16- or 24-bit words from external memory
regardless of the external data bus width. When configured for
an 8-bit interface, the unused eight lines provide eight program­mable, bidirectional general-purpose Programmable Flag lines,
six of which can be mapped to software condition signals.

The memory DMA controller lets the ADSP-2191M move data
and instructions from between memory spaces: internal-to-exter­nal, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.

The ADSP-2191M can respond to up to seventeen interrupts at
any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. The programmer assigns a
peripheral to one of the 12 user-defined interrupts. The priority
of each peripheral for interrupt service is determined by these
assignments.

There are three serial ports on the ADSP-2191M that provide a
complete synchronous, full-duplex serial interface. This interface
includes optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of opera-

CLOCK

OR

CRYSTAL

TIMER

OUT OR

CAPTURE

CLOCK

MULTIPLY

AND

RANGE

BOOT

AND OP

MODE

SERIAL
DEVICE

(OPTIONAL)

SERIAL
DEVICE

(OPTION AL)

SERIAL
DEVICE

(OPTIONAL)

UART

DEVICE

(OPTIONAL)

ADSP-2191M

CLKIN
XTAL

TMR2–0

MSEL6–0/PF6–0
DF/PF7
BYPASS
BMODE1–0
OPMODE

SPORT0
TCLK0
TFS0
DT0
RCLK0
RFS0
DR0

SPORT1
TCLK1
TFS1
DT1
RCLK1
RFS1
DR1

SPORT2
TCLK2/SCK0
TFS2/MOSI0
DT2/MISO0
RCLK2/SCK1
RFS2/MOSI 1
DR2/MISO1

UART
RXD
TXD

RESET

6

JTAG

CLKOUT

ADDR21–0

DATA15–8

DATA7–0

MS3–0

RD

WR

ACK

BMS

BR
BG

BGH

IOMS

SPI0

SPI1

HAD15–0

HA16

HCMS

HCIOMS

HRD

HWR

HACK

HALE

HACK_P

L
O
R
T
N
O
C

S
S
E
R
D
D
A

A
T
A
D

PROCESSOR

EXTERNAL

MEMORY

(OPTIONAL)

ADDR21–0
DATA15–8
DATA7–0

CS

OE
WE

ACK

BOOT

MEMORY

(OPTIONAL)

ADDR21–0
DATA15–8
DATA7–0

CS
OE
WE

ACK

EXTERNAL

I/O MEMORY

(OPTIONAL)

ADDR17–0
DATA15–8
DATA7–0

CS
OE
WE

ACK

HOST

(OPTIONAL)

ADDR15–0/
DATA15–0
ADDR16

CS0

CS1

RD
WR

ACK
ALE

Figure 1. System Diagram

tion. Each serial port can transmit or receive an internal or
external, programmable serial clock and frame syncs. Each serial
port supports 128-channel Time Division Multiplexing.

The ADSP-2191M provides up to sixteen general-purpose I/O
pins, which are programmable as either inputs or outputs. Eight
of these pins are dedicated-general purpose Programmable Flag
pins. The other eight of them are multifunctional pins, acting as
general-purpose I/O pins when the DSP connects to an 8-bit
external data bus and acting as the upper eight data pins when
the DSP connects to a 16-bit external data bus. These Program­mable Flag pins can implement edge- or level-sensitive
interrupts, some of which can be used to base the execution of
conditional instructions.

–4– REV. 0

ADSP-2191M

Three programmable interval timers generate periodic inter­rupts. Each timer can be independently set to operate in one of
three modes:

• Pulse Waveform Generation mode

• Pulsewidth Count/Capture mode

• External Event Watchdog mode

Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer’s configuration register enables or
disables the corresponding timer independently of the others.

Memory Architecture

The ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page 0 in the DSP’s memory map. In addition to the

LOGICAL

ADDRESS

0ⴛFF FFFF
0ⴛFF 0400

0ⴛFF 03FF

0ⴛFF 0000

INTERNAL

MEMORY

64K WORD

MEMORY

PAGES

PAGE 255

RESERVED

BOOT ROM, 24-BIT

internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.

As shown in Figure 2, the DSP’s two internal memory blocks
populate all of Page 0. The entire DSP memory map consists of
256 pages (Pages 0

−

255), and each page is 64K words long.
External memory space consists of four memory banks (banks
0–3) and supports a wide variety of SRAM memory devices. Each

MS3–0

bank is selectable using the memory select pins (

) and has
configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page 255 while the remaining 254 pages are addressable off-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their

IOMS

own select pin (

). Pages 0–7 of I/O memory space reside
on-chip and contain the configuration registers for the peripher­als. Both the core and DMA-capable peripherals can access the
DSP’s entire memory map.

LOWER PAGE BO UNDARIES

ARE CONFIGURABLE FOR

BANKS OF EXTERNAL MEMORY.

BOUNDARIES SHOWN ARE

BANK SIZES AT RES ET.

MEMORY SELECTS (MS)
FOR PORTIONS OF THE

MEMORYMAP APPEAR

WITH THE SELECTED

MEMORY.

BANK3

(MS3)

BANK2

(MS2)

BANK1

(MS1)

BANK0

(MS0)

BLOCK3, 16-BIT
BLOCK2, 16-BIT

BLOCK1, 24-BIT
BLOCK0, 24-BIT

0ⴛC0 0000

0ⴛ80 0000

0ⴛ40 0000

0ⴛ01 0000
0ⴛ00 C000
0ⴛ00 8000
0ⴛ00 4000
0ⴛ00 0000

EXTERNAL

MEMORY

(16- BIT)

INTERNAL

MEMORY

PAGES 192–254

PAGES 128–191

PAGES 64–127

PAGES 1–63

PAGE 0

Figure 2. Memory Map

Internal (On-Chip) Memory

The ADSP-2191M’s unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly

BOOT MEMORY

16-BIT

(BMS)

64K WORD

PAGES 1–254

LOGICAL

ADDRESS

0ⴛFE FFFF

0ⴛ01 0000

I/O MEMORY

16- BIT

1K WORD

PAGES 8–255

1K WORD

PAGES 0–7

EXTERNAL

(IOMS)

INTERNAL

LOGICAL

ADDRESS

0ⴛFF 3FF

0ⴛ08 000
0ⴛ07 3FF

0ⴛ00 000

8-BIT 10-BIT

–5–REV. 0

ADSP-2191M

different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.

The ADSP-2191M has 1K word of on-chip ROM that holds boot
routines. If peripheral booting is selected, the DSP starts
executing instructions from the on-chip boot ROM, which starts
the boot process from the selected peripheral. For more informa-

tion, see “Booting Modes” on page 11. The on-chip boot ROM

is located on Page 255 in the DSP’s memory space map.

External (Off-Chip) Memory

Each of the ADSP-2191M’s off-chip memory spaces has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memor y access strobe widths. For more information,

see “Clock Signals” on page 11. The off-chip memor y spaces are:

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through the
External Port, which can be configured for data widths of
8 or 16 bits.

External Memory Space

External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0

−

containing pages 1
containing pages 128

−

254. The

192
respectively. The external memory interface is byte-addressable
and decodes the 8 MSBs of the DSP program address to select
one of the four banks. Both the ADSP-219x core and DMA-capa­ble peripherals can access the DSP’s external memory space.

I/O Memory Space

The ADSP-2191M supports an additional external memory
called I/O memory space. This space is designed to support
simple connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports a total of 256K locations. The first 8K addresses
are reserved for on-chip peripherals. The upper 248K addresses
are available for external peripheral devices. The DSP’s instruc­tion set provides instructions for accessing I/O space. These
instructions use an 18-bit address that is assembled from an
8-bit I/O page (IOPG) register and a 10-bit immediate value
supplied in the instruction. Both the ADSP-219x core and a Host
(through the Host Port Interface) can access I/O memory space.

Boot Memory Space

Boot memory space consists of one off-chip bank with 63 pages.

BMS

The
the ADSP-219x core and DMA-capable peripherals can access
the DSP’s off-chip boot memory space. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
Depending on the boot configuration, the boot ROM code can
start booting the DSP from boot memory. For more information,

see “Booting Modes” on page 11.

Interrupts

The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in Table 1. Applications can use the
unassigned slots for software and peripheral interrupts.

Table 2 shows the ID and priority at reset of each of the periph-

eral interrupts. To assign the peripheral interrupts a different
priority, applications write the new priority to their correspond­ing control bits (determined by their ID) in the Interrupt Priority
Control register. The peripheral interrupt’s position in the
IMASK and IRPTL register and its vector address depend on its
priority level, as shown in Table 1. Because the IMASK and
IRPTL registers are limited to 16 bits, any peripheral interrupts

memory bank pin selects boot memory space. Both

63, Bank1 containing pages 64−127, Bank2

−

191, and Bank3 that contains pages

MS3–0

memory bank pins select Banks 3–0,

–6– REV. 0

ADSP-2191M

assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x00 01E0.

Table 1. Interrupt Priorities/Addresses

Interrupt

Emulator (NMI)—

IMASK/
IRPTL

NA NA

Vector
Address

1

Highest Priority
Reset (NMI) 0 0x00 0000
Power-Down (NMI) 1 0x00 0020
Loop and PC Stack 2 0x00 0040
Emulation Kernel 3 0x00 0060
User Assigned Interrupt 4 0x00 0080
User Assigned Interrupt 5 0x00 00A0
User Assigned Interrupt 6 0x00 00C0
User Assigned Interrupt 7 0x00 00E0
User Assigned Interrupt 8 0x00 0100
User Assigned Interrupt 9 0x00 0120
User Assigned Interrupt 10 0x00 0140
User Assigned Interrupt 11 0x00 0160
User Assigned Interrupt 12 0x00 0180
User Assigned Interrupt 13 0x00 01A0
User Assigned Interrupt 14 0x00 01C0
User Assigned Interrupt—

15 0x00 01E0

Lowest Priority

1

These interrupt vectors start at address 0x10000 when the DSP is in

“no-boot,” run from external memory mode.

Table 2. Peripheral Interrupts and Priority at Reset

Reset

Interrupt ID

Priority

Slave DMA/Host Port Interface 0 0
SPORT0 Receive 1 1
SPORT0 Transmit 2 2
SPORT1 Receive 3 3
SPORT1 Transmit 4 4
SPORT2 Receive/SPI0 5 5
SPORT2 Transmit/SPI1 6 6
UART Receive 7 7
UART Transmit 8 8
Timer 0 9 9
Timer 1 10 10
Timer 2 11 11
Programmable Flag A (any PFx) 12 11
Programmable Flag B (any PFx) 13 11
Memory DMA port 14 11

Interrupt routines can either be nested with higher priority inter­rupts taking precedence or processed sequentially. Interr upts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.

The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.

The general-purpose Programmable Flag (PFx) pins can be con­figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitive operation.

Table 3. Interrupt Control (ICNTL) Register Bits

Bit Description

0–3 Reserved
4Interrupt Nesting Enable
5Global Interrupt Enable
6 Reserved
7 MAC-Biased Rounding Enable
8–9 Reserved
10 PC Stack Interrupt Enable
11 Loop Stack Interrupt Enable
12–15 Reserved

The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main­tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack-level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.

The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.

ENA INT;
DIS INT;

At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and

computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.

DMA Controller

The ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M’s internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa­ble peripherals include the Host port, SPORTs, SPI ports, and
UART. Each individual DMA-capable peripheral has a dedicated
DMA channel. To describe each DMA sequence, the DMA con­troller uses a set of parameters—called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one DMA
sequence auto-initiates and starts the next sequence. DMA
sequences do not contend for bus access with the DSP core;
instead DMAs “steal” cycles to access memory.

–7–REV. 0

ADSP-2191M

All DMA transfers use the DMA bus shown in the functional
block diagram on page 1. Because all of the peripherals use the
same bus, arbitration for DMA bus access is needed. The arbi­tration for DMA bus access appears in Table 4.

Table 4. I/O Bus Arbitration Priority

DMA Bus Master Arbitration Priority

SPORT0 Receive DMA 0—Highest
SPORT1 Receive DMA 1
SPORT2 Receive DMA 2
SPORT0 Transmit DMA 3
SPORT1 Transmit DMA 4
SPORT2 Transmit DMA 5
SPI0 Receive/Transmit DMA 6
SPI1 Receive/Transmit DMA 7
UART Receive DMA 8
UART Transmit DMA 9
Host Port DMA 10
Memory DMA 11—Lowest

Host Port

The ADSP-2191M’s Host port functions as a slave on the
external bus of an external Host. The Host port interface lets a
Host read from or write to the DSP’s memory space, boot space,
or internal I/O space. Examples of Hosts include external micro­controllers, microprocessors, or ASICs.

The Host port is a multiplexed address and data bus that provides
both an 8-bit and a 16-bit data path and operates using an asyn­chronous transmission protocol. Through this port, an off-chip
Host can directly access the DSP’s entire memory space map,
boot memory space, and internal I/O space. To access the DSP’s
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP’s core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP’s I/O mapped
peripherals.

The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans­ferred from the Host for every data transfer.

Host Port Acknowledge (HACK) Modes

The Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready Modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC Mode from the HALE and

HWR

inputs.

The Ho st port H ACK signa l pol arit y is s elected (onl y at res et) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
configuration register as a read only bit.

The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac­tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.

Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini­tialized at reset based on the values driven on HACK and
HACK_P pins (shown in Table 5); HPCR7 is always cleared (0)
at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configuration register.

Table 5. Host Port Acknowledge Mode Selection

Values Driven At
Reset

0 0 0 1 Ready Mode
0100ACK Mode
1000ACK Mode
1 1 0 1 Ready Mode

The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):

• ACK Mode—Acknowledge is active on strobes; HACK

goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes the HACK.

• Ready Mode— R e a d y a c t i v e o n s t r o b e s , g o e s l o w t o i n s e r t

waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.

While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.

Host Port Chip Selects

There are two chip-select signals associated with the Host port:

HCMS

and

HCIOMS

lets the Host select the DSP and directly access the DSP’s inter­nal/external memory space or boot memory space. The Host
Chip I/O Memory Select (
and directly access the DSP’s internal I/O memory space.

Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
combines the data from one, two, or three consecutive Host
accesses (up to one 24-bit value) into a single DMA bus access
to prefetch Host direct reads or to post direct writes. During
assembly of larger words, the Host port interface asserts ACK for

HPCR [7:6]
Initial Values

. The Host Chip Memory Select (

HCIOMS

) lets the Host select the DSP

Acknowledge
ModeHACK_P HACK Bit 7 Bit 6

HCMS

)

–8– REV. 0

ADSP-2191M

each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.

DSP Serial Ports (SPORTs)

The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:

• Bidirectional operation—each SPORT has independent

transmit and receive pins.

• Double-buffered transmit and receive ports—each port

has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.

• Clocking—each transmit and receive port can either use
an external serial clock (40 MHz) or generate its own, in
frequencies ranging from 19 Hz to 40 MHz.

• Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.

• Framing—each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.

• Companding in hardware—each SPORT can perform
A-law or µ-law companding according to ITU recommen­dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.

• DMA operations with single-cycle overhead—each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
Either the DSP’s core or a Host processor can link or chain
sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.

• Interrupts—each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.

• Multichannel capability—each SPORT supports the
H.100 standard.

Serial Peripheral Interface (SPI) Ports

The DSP has two SPI-compatible ports that enable the DSP to
communicate with multiple SPI-compatible devices. These ports
are multiplexed with SPORT2, so either SPORT2 or the SPI
ports are active, depending on the state of the OPMODE pin
during hardware reset.

The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,

SPISSx

SCKx). Two SPI chip select input pins (
devices select the DSP, and fourteen SPI chip select output pins
(SPIxSEL7–1) let the DSP select other SPI devices. The SPI
select pins are reconfigured Programmable Flag pins. Using these
pins, the SPI ports provide a full duplex, synchronous serial inter­face, which supports both master and slave modes and
multimaster environments.

Each SPI port’s baud rate and clock phase/polarities are program­mable (see equation below for SPI clock rate calculation), and
each has an integrated DMA controller, configurable to support
both transmit and receive data streams. The SPI’s DMA control­ler can only service unidirectional accesses at any given time.

HCLK

SPI Clock Rate

During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial data
lines. The serial clock line synchronizes the shifting and sampling
of data on the two serial data lines.

UART Port

The UART port provides a simplified UART interface to another
peripheral or Host. It performs full duplex, asynchronous
transfers of serial data. Options for the UART include support
for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity.
The UART port supports two modes of operation:

• Programmed I/O

The DSP’s core sends or receives data by writing or
reading I/O-mapped THR or RBR registers, respectively.
The data is double-buffered on both transmit and receive.

• DMA (direct memory access)

The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter­rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.

The UART’s baud rate (see following equation for UART clock
rate calculation), serial data format, error code generation and
status, and interrupts are programmable:

• Supported bit rates range from 9.5 bits to 5M bits per

second (80 MHz peripheral clock).

• Supported data formats are 7- to 12-bit frames.

• Transmit and receive status can be configured to generate

maskable interrupts to the DSP’s core.

The timers can be used to provide a hardware-assisted autobaud
detection mechanism for the UART interface.

UART Clock Rate

Where D is the programmable divisor = 1 to 65536.

-------------------------------------- -

=

2 SPIBAUD×

HCLK

------------------

=

16 D×

) let other SPI

–9–REV. 0

ADSP-2191M

Programmable Flag (PFx) Pins

The ADSP-2191M has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve either
as general-purpose I/O pins (if the DSP is connected to an 8-bit
external data bus) or serve as DATA15–8 lines (if the DSP is
connected to a 16-bit external data bus). The Programmable Flag
pins have special functions for clock multiplier selection and for
SPI port operation. For more information, see Serial Peripheral

Interface (SPI) Ports on page 9 and Clock Signals on page 11.

Ten memory-mapped registers control operation of the Program­mable Flag pins:

• Flag Direction register

Specifies the direction of each individual PFx pin as input
or output.

• Flag Control and Status registers

Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.

• Flag Interrupt Mask registers

Enable and disable each individual PFx pin to function
as an interrupt to the DSP’s core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts—latching in the IMASK and IRPTL
registers.

• Flag Interrupt Polarity register

Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin.

• Flag Sensitivity registers

Specify whether individual PFx pins are level- or
edge-sensitive and specify—if edge-sensitive—whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif­icant for edge-sensitivity.

Low Power Operation

The ADSP-2191M has four low-power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-2191M uses configu­ration of the PDWN, STOPCK, and STOPALL bits in the
PLLCTL register to select between the low-power modes as the
DSP executes the IDLE. Depending on the mode, an IDLE shuts
off clocks to different parts of the DSP in the different modes.
The low power modes are:

• Idle

• Power-Down Core

• Power-Down Core/Peripherals

• Power-Down All

Idle Mode

When the ADSP-2191M is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.

To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.

Power-Down Core Mode

When the ADSP-2191M is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.

To enter Power-Down Core mode, the DSP executes an IDLE
instruction after performing the following tasks:

• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

• Clear (= 0) the PDWN bit in the PLLCTL register

• Clear (= 0) the STOPALL bit in the PLLCTL register

• Set (= 1) the STOPCK bit in the PLLCTL register

To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.

Power-Down Core/Peripherals Mode

When the ADSP-2191M is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.

To enter Power-Down Core/Peripherals mode, the DSP executes
an IDLE instruction after performing the following tasks:

• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

• Clear (= 0) the PDWN bit in the PLLCTL register

• Set (= 1) the STOPALL bit in the PLLCTL register

To exit Power-Down Core/Peripherals mode, the DSP responds
to a wake-up event and (after five to six cycles of latency) resumes
executing instructions with the instruction after the IDLE.

Power-Down All Mode

When the ADSP-2191M is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.

To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:

• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

• Set (= 1) the PDWN bit in the PLLCTL register

–10– REV. 0

ADSP-2191M

To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after the
IDLE.

Clock Signals

The ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a

Ω

shunt resistor connected as shown in Figure 3. Capacitor

1M
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre­quency, microprocessor-grade crystal should be used for this
configuration.

If a buffered, shaped clock is used, this external clock connects
to the DSP’s CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.

ⴛ

The DSP provides a user-programmable 1

to 32ⴛ multiplica­tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL6–0, BYPASS, and DF pins decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be con­trolled in software. The combination of pullup and pull-down
resistors in Figure sets up a core clock ratio of 6:1, which
produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the

Hardware Reference

.

ADSP-219x/2191 DSP

The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2191M operate at the rate

set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is 160 MHz and the maximum periph­eral clock is 80 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.

Reset

The

RESET

signal initiates a master reset of the ADSP-2191M.

RESET

The
sequence to assure proper initialization.

signal must be asserted during the powerup

RESET

during initial
powerup must be held long enough to allow the internal clock to
stabilize.

The powerup sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

is applied

DD

to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100 µs
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the

RESET
RESET

tion, t

signal should be held low. On any subsequent resets, the
signal must meet the minimum pulsewidth specifica-

.

WRST

1M⍀

25MHz

XTAL

ADSP-2191M

THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASSPINS
SELECTTHECORECLOCK
RATIO.

HERE, THE SELECTION (6:1)
AND 25MHzINPUT CLOCK
PRODUCE A 150MHz CORE
CLOCK.

RUNTIME
PF PIN I/O

RESET
SOURCE

CLKIN CLKOUT

V

DD

V

DD

MSEL0 (PF0)

MSEL1 (PF1)

MSEL2 (PF2)

MSEL3 (PF3)

MSEL4 (PF4)

MSEL5 (PF5)

MSEL6 (PF6)

DF (PF7)

BYPASS

RESET

Figure 3. External Crystal Connections

RESET

The
circuit to generate your

input contains some hysteresis. If using an RC

RESET

signal, the circuit should use an

external Schmidt trigger.
The master reset sets all internal stack pointers to the empty stack

condition, masks all interrupts, and resets all registers to their

RESET

default values (where applicable). When

is released, if
there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF 0000).

Power Supplies

The ADSP-2191M has separate power supply connections for
the internal (V

) and external (V

DDINT

DDEXT

) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply must be connected to a 3.3 V supply. All external
supply pins must be connected to the same supply.

Powerup Sequence

Power up together the two supplies V

DDEXT

and V

DDINT

. If
they cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.

Booting Modes

The ADSP-2191M has five mechanisms (listed in Table 6) for
automatically loading internal program memory after reset. Two
No-boot modes are also supported.

–11–REV. 0

ADSP-2191M

Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)

OPMODE

BMODE1

BMODE0

Function

0 0 0 Execute from external memory 16 bits

(No Boot)
0 0 1 Boot from EPROM
0 1 0 Boot from Host
0 1 1 Reserved
1 0 0 Execute from external memory 8 bits

(No Boot)
1 0 1 Boot from UART
1 1 0 Boot from SPI, up to 4K bits
1 1 1 Boot from SPI, >4K bits up to

512K bits

The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configuration
Register implement these modes:

• Execute from memory external 16 bits—The memory

boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x010000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).

• Boot from EPROM—The EPROM boot routine located

in boot ROM memory space fetches a boot-stream-for­matted program located at physical address 0x00 0000 of
boot memory space, packing 8- or 16-bit external data
into 24-bit internal data. The External Port Interface is
configured for the default clock multiplier (32) and read
waitstates (7).

• Boot from Host—The (8- or 16-bit) Host downloads a

boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.

The internal boot ROM sets semaphore A (an IO register
within the Host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page 0 internal memory and
jump to address 0x00 0000 internal memory. From the
point of view of the host interface, an external host has
full control of the DSP's memory map. The Host has the
freedom to directly write internal memory, external
memory, and internal I/O memory space. The DSP core
execution is held off until the Host clears the semaphore
register. This strategy allows the maximum flexibility for
the Host to boot in the program and data code, by leaving
it up to the programmer.

• Execute from memory external 8 bits (No Boot)—

Execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is config­ured for the default clock multiplier (128) and read
waitstates (7).

• Boot from UART—The Host downloads

boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
within the UART’s clocking capabilities. After a hardware
reset, the DSP’s UART expects a 0xAA character (eight
bits data, one start bit, one stop bit, no parity bit) on the
RXD pin to determine the bit rate; and then replies with
an OK string. Once the host receives this OK it downloads
the boot stream without further handshake.The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.

• Boot from SPI, up to 4K bits—The SPI0 port uses the

SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EEPROM device, submits a read command
at address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EEPROMs of ≤ 4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu­ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.

• Boot from SPI, from >4K bits to 512K bits—The SPI0

port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EEPROM device, submits a read
command at address 0x00, and begins clocking consecu­tive data into internal or external memory. Use only
SPI-compatible EEPROMs of ≥ 4K bit (16-bit address
range). The SPI0 boot routine, located in internal ROM
memory space, executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.

As indicated in Table 6, the OPMODE pin has a dual role, acting
as a boot mode select during reset and determining SPORT or
SPI operation at runtime. If the OPMODE pin at reset is the
opposite of what is needed in an application during runtime, the
application needs to set the OPMODE bit appropriately during
runtime prior to using the corresponding peripheral.

Bus Request and Bus Grant

The ADSP-2191M can relinquish control of the data and address
buses to an external device. When the external device requires

BR

access to the bus, it asserts the bus request (
signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Because of

) signal. The (BR)

–12– REV. 0

ADSP-2191M

synchronizer and arbitration delays, bus grants will be provided
with a minimum of three peripheral clock delays. ADSP-2191M
DSPs will respond to the bus grant by:

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.
The ADSP-2191M will halt program execution if the bus is

granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or periph­eral memory spaces. If an instruction requires two external
memory read accesses, bus requests will not be granted between
the two accesses. If an instruction requires an external memory
read and an external memory write access, the bus may be
granted between the two accesses. The external memory
interface can be configured so that the core will have exclusive
use of the interface. DMA and Bus Requests will be granted.

BR

When the external device releases
continues program execution from the point at which it stopped.

The bus request feature operates at all times, even while the DSP
is booting and

The ADSP-2191M asserts the
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.

Instruction Set Description

The ADSP-2191M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read­ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:

• ADSP-219x assembly language syntax is a superset of and

source-code-compatible (except for two data registers
and DAG base address registers) with ADSP-218x family
syntax. It may be necessary to restructure ADSP-218x
programs to accommodate the ADSP-2191M’s unified
memory space and to conform to its interrupt vector map.

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16­or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.

RESET

is active.

, the DSP releases BG and

BGH

pin when it is ready to start

Development Tools

The ADSP-2191M is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++® development environment. The
same emulator hardware that supports other ADSP-219x DSPs,
also fully emulates the ADSP-2191M.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat­ical functions. Two key points for these tools are:

• Compiled ADSP-219x C/C++ code efficiency—the

compiler has been developed for efficient translation of
C/C++ code to ADSP-219x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.

• ADSP-218x family code compatibility—The assembler

has legacy features to ease the conversion of existing
ADSP-218x applications to the ADSP-219x.

Debugging both C/C++ and assembly programs with the Visu­alDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the syntax highlighting in the Visu­alDSP++ editor. This capability permits:

• Control how the development tools process inputs and

generate outputs.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-2191M processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonin­trusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.

–13–REV. 0

ADSP-2191M

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x PC plug-in cards. Third party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.

Designing an Emulator-Compatible DSP Board
(Target)

The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.

Target Board Header

The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in Figure 4. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"

ⴛ

square post header, set on 0.1"

0.1" spacing, with a minimum
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.

Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

12

34

56

78

910

9

11 12

13 14

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

Figure 4. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in
Place)

As can be seen in Figure 4, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,

TRST

, and

EMU

TDO,

used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and

BTRST

that are optionally used for

board-level (boundary scan) testing.
When the emulator is not connected to this header, place jumpers

across BTMS, BTCK,

BTRST

, and BTDI as shown in Figure 5.
This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

12

34

56

78

910

9

11 12

13 14

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

Figure 5. JTAG Target Board Connector with No Local

Boundary Scan

JTAG Emulator Pod Connector

Figure 6 details the dimensions of the JTAG pod connector at the

14-pin target end. Figure 7 displays the keep-out area for a target
board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.25" square
post pin.

0.64"

0.88"

0.24"

Figure 6. JTAG Pod Connector Dimensions

–14– REV. 0

Additional Information

This data sheet provides a general overview of the ADSP-2191M

0.10"

architecture and functionality. For detailed information on the
core architecture of the ADSP-219x family, refer to the

ADSP-219x/2191 DSP Hardware Reference

0.15"

Figure 7. JTAG Pod Connector Keep-Out Area

Design-for-Emulation Circuit Information

For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff­ering, signal termination, and emulator pod logic, see the

Analog Devices JTAG Emulation Technical Reference

EE-68:

on the Analog
Devices website (www.analog.com)—use site search on
“EE-68.” This document is updated regularly to keep pace with
improvements to emulator support.

instruction set, refer to the

PIN FUNCTION DESCRIPTIONS

ADSP-2191M pin definitions are listed in Table 7. All
ADSP-2191M inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for

Tie or pull unused inputs to V
ADDR21–0, DATA15–0, PF7-0, and inputs that have internal
pull-up or pull-down resistors (
OPMODE, BYPASS, TCK, TMS, TDI, and
pins can be left floating. These pins have a logic-level hold circuit
that prevents input from floating internally.

The following symbols appear in the Type column of Table : G
= Ground, I = Input, O = Output, P = Power Supply, and T =
Three-State.

Table 7. Pin Function Descriptions

Pin Type Function

A21–0 O/T External Port Address Bus
D7–0 I/O/T External Port Data Bus, least significant 8 bits
D15
/PF15
/SPI1SEL7
D14
/PF14
/SPI0SEL7
D13
/PF12
/SPI1SEL6
D12
/PF12
/SPI0SEL6
D11
/PF11
/SPI1SEL5
D10
/PF10
/SPI0SEL5
D9
/PF9
/SPI1SEL4
D8
/PF8
/SPI0SEL4
PF7
/SPI1SEL3
/DF
PF6
/SPI0SEL3
/MSEL6

I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I/O
I
I/O/T
I
I
I/O/T
I
I

Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave
Select output 7 (if 8-bit external bus, when SPI1 enabled)

Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave
Select output 7 (if 8-bit external bus, when SPI0 enabled)

Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave
Select output 6 (if 8-bit external bus, when SPI1 enabled)

Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave
Select output 6 (if 8-bit external bus, when SPI0 enabled)

Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave
Select output 5 (if 8-bit external bus, when SPI1 enabled)

Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave
Select output 5 (if 8-bit external bus, when SPI0 enabled)

Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select
output 4 (if 8-bit external bus, when SPI1 enabled)

Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select
output 4 (if 8-bit external bus, when SPI0 enabled)

Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency
(divisor select for PLL input during boot)

Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6
(during boot)

ADSP-2191M

. For details on the

ADSP-219x Instruction Set Reference

TRST

).

or GND, except for

DDEXT

TRST

, BMODE0, BMODE1,

RESET

)—these

.

–15–REV. 0

ADSP-2191M

Table 7. Pin Function Descriptions (continued)

Pin Type Function

PF5
/SPI1SEL2
/MSEL5
PF4
/SPI0SEL2
/MSEL4
PF3
/SPI1SEL1
/MSEL3
PF2
/SPI0SEL1
/MSEL2
PF1
/SPISS1
/MSEL1
PF0
/SPISS0
/MSEL0

RD
WR

ACK I External Port Access Ready Acknowledge

BMS
IOMS
MS3–0
BR
BG
BGH

HAD15–0 I/O/T Host Port Multiplexed Address and Data Bus
HA16 I Host Port MSB of Address Bus
HACK_P I Host Port ACK Polarity

HRD
HWR

HACK O Host Port Access Ready Acknowledge
HALE I Host Port Address Latch Strobe or Address Cycle Control

HCMS
HCIOMS

CLKIN I Clock Input/Oscillator input
XTAL O Oscillator output
BMODE1–0 I Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 kΩ internal pull-up resistors.
OPMODE I Operating Mode. The OPMODE pin has a 85 kΩ internal pull-up resistor.
CLKOUT O Clock Output
BYPASS I Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 kΩ internal pull-up resistor.
RCLK1–0 I/O/T SPORT1–0 Receive Clock
RCLK2/SCK1 I/O/T SPORT2 Receive Clock/SPI1 Serial Clock
RFS1–0 I/O/T SPORT1–0 Receive Frame Sync
RFS2/MOSI1 I/O/T SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data
TCLK1–0 I/O/T SPORT1–0 Transmit Clock
TCLK2/SCK0 I/O/T SPORT2 Transmit Clock/SPI0 Serial Clock
TFS1–0 I/O/T SPORT1–0 Transmit Frame Sync
TFS2/MOSI0 I/O/T SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data
DR1–0 I/T SPORT1–0 Serial Data Receive
DR2/MISO1 I/O/T SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data
DT1–0 O/T SPORT1–0 Serial Data Transmit
DT2/MISO0 I/O/T SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data
TMR2–0 I/O/T Timer output or capture

I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
O/T External Port Read Strobe
O/T External Port Write Strobe

O/T External Port Boot Space Select
O/T External Port IO Space Select
O/T External Port Memory Space Selects
I External Port Bus Request
OExternal Port Bus Grant
O External Port Bus Grant Hang

I Host Port Read Strobe
I Host Port Write Strobe

I Host Port Internal Memory–Internal I/O Memory–Boot Memory Select
I Host Port Internal I/O Memory Select

Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5
(during boot)

Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4
(during boot)

Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3
(during boot)

Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2
(during boot)

Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1
(during boot)

Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0
(during boot)

–16– REV. 0

ADSP-2191M

Table 7. Pin Function Descriptions (continued)

Pin Type Function

RXD I UART Serial Receive Data
TXD O UART Serial Transmit Data

RESET

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85 kΩ
TMS I Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85 kΩ

TDI I Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

EMU

V

DDINT

V

DDEXT

GND G Power Supply Return. (twelve pins)
NC Do Not Connect. Reserved pins that must be left open and unconnected.

I Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the

program memory location specified by the hardware reset vector address. The RESET input
must be asserted (low) at powerup. The RESET pin has an 85 kΩ internal pull-up resistor.

internal pull-up resistor.

internal pull-up resistor.
85 kΩ internal pull-up resistor.

I Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after

powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65 kΩ
internal pull-down resistor.

O Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board

connector only.
P Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor. (four pins)
P I/O Power Supply. Nominally 3.3 V dc. (nine pins)

–17–REV. 0

ADSP-2191M
SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

V

DDINT

1

Internal (Core) Supply

Test Conditions

K Grade (Commercial)
Min Max

2.37 2.63 2.37 2.63 V

B Grade (Industrial)
Min Max Unit

Vo lt a ge

V

DDEXT

External (I/O) Supply

2.97 3.6 2.97 3.6 V

Vo lt a ge

V

V

T

IH

IL

AMB

High Level Input Voltage @ V

V

Low Level Input Voltage @ V

V

Ambient Operating

DDINT

DDEXT

DDINT

DDEXT

= max,

= max

= min,

= min

2.0 V

DDEXT

+0.3 2.0 V

DDEXT

+0.3 V

–0.3 0.8 –0.3 0.8 V

070 –40+85 ºC

Te m p erat u r e

1

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

Parameter

V

OH

V

OL

I

IH

I

IL

I

IHP

I

ILP

I

OZH

I

OZL

C

IN

1

Specifications subject to change without notice.

2

Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,

BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,
RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1.

3

Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P.

4

Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.

5

Applies to input pin with internal pull-down: TRST.

6

Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx,

HAD15–0, TMR2–0.

7

Applies to all signal pins.

8

Guaranteed, but not tested.

1

High Level Output Voltage2

Low Level Output Voltage

High Level Input Current

Low Level Input Current

High Level Input Current

Low Level Input Current

Three-State Leakage Current

Three-State Leakage Current

Input Capacitance

7, 8

2

3, 4

3, 5

5

4

6

6

Test Conditions

@ V
I
@ V
I
@ V
V
@ V
V
@ V
V
@ V
V
@ V
V
@ V
V

DDEXT

OH

DDEXT

OL

DDEXT

IN

DDEXT

IN

DDEXT

IN

DDEXT

IN

DDEXT

IN

DDEXT

IN

= min,

= –0.5 mA

= min,

= 2.0 mA

= max,

= VDD max

= max,

= 0 V

= max,

= VDD max

= max,

= 0 V

= max,

= VDD max

= max,

= 0 V
fIN = 1 MHz,
T
V

CASE

= 2.5 V

IN

= 25°C,

K and B Grades
Min Typ Max Unit

2.4 V

0.4 V

10 µA

10 µA

30 100 µA

20 70 µA

10 µA

10 µA

8pF

–18– REV. 0

ADSP-2191M

ABSOLUTE MAXIMUM RATINGS

V
V
V
V
T
T

1

Specifications subject to change without notice.

2

Stresses greater than those listed above may cause permanent damage to the dev ice.

These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Internal (Core) Supply Voltage

DDINT

External (I/O) Supply Voltage . . . . –0.3 V to 4.6 V

DDEXT

Input Voltage . . . . . . . . –0.5 V to V

IL–VIH
OL–VOH
STORE
LEAD

Output Voltage Swing . –0.5 V to V

Storage Temperature Range . . . . . .–65ºC to 150ºC

Lead Temperature of ST-144 (5 seconds) . . . . 185ºC

1,2

. . –0.3 V to 3.0 V

DDEXT
DDEXT

+0.5 V
+0.5 V

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor­mance degradation or loss of functionality.

Power Dissipation

Using the operation-versus-current information in Table 8, designers can estimate the ADSP-2191M’s internal power supply
(V

DDINT

) input current for a specific application, according to the formula for I

calculation beneath Table 8. For calculation

DDINT

of external supply current and total supply current, see Power Dissipation on page 41.

Table 8. Operation Types Versus Input Current

K-Grade
I

DDINT

(mA) CCLK = 160 MHz

B-Grade
I

DDINT

(mA)1 CCLK = 140 MHz

Core Peripheral Core Peripheral

Activity Typ

6

3

I

DDINT

DDINT
DDINT

Power Down

4

Idle 1

5

Idle 2
Typi cal

7

Peak

1

Test conditions: V

2

Test conditions: V

3

PLL, Core, peripheral clocks, and CLKIN are disabled.

4

PLL is enabled and Core and peripheral clocks are disabled.

5

Core CLK is disabled and peripheral clock is enabled.

6

All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using

a linear address sequence. 50% of the instructions are type 3 instructions.

7

All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear

address sequence.

1

100µA 600µA 0 50µA 100µA 500µA 0 50µA
12581247
126070125562
184 210 60 70 165 185 55 62
215 240 60 70 195 210 55 62

= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T

%Typical I

×()= %Idle I

2

Max

DDINT-TYPICAL

Ty p

1

2

Max

×()%Power Down I

DDINT-IDLE

Ty p

1

Max

2

AMB
AMB

Ty p

= 25ºC.
= 25ºC.

×()++

DDINT-PWRDWN

1

Max

2

–19–REV. 0

ADSP-2191M
TIMING SPECIFICATIONS

This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.

Switching characteristics

processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.

Timing requirements

operation.Timing requirements guarantee that the processor operates correctly with other devices.

Clock In and Clock Out Cycle Timing

Table 9 and Figure 8 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-

eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.

When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.

Table 9. Clock In and Clock Out Cycle Timing

Parameter Min Max Unit

specify how the processor changes its signals. No control is possible over this timing; circuitry external to the

apply to signals that are controlled by circuitry external to the processor, such as the data input for a read

Switching Characteristics

t

CKOD

t

CKO

Timing Requirements

t

CK

t

CKL

t

CKH

t

WRST

t

MSS

t

MSH

t

MSD

t

PFD

1

CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

2

In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), tCK=t

3

In bypass mode, tCK=t

CLKOUT Delay from CLKIN 0 5.8 ns
CLKOUT Period

CLKIN Period2,

1

3

12.5 ns

10 200 ns
CLKIN Low Pulse 4.5 ns
CLKIN High Pulse 4.5 ns
RESET Asserted Pulsewidth Low 200t

CLKOUT

ns
MSELx/BYPASS Stable Before RESET Deasserted Setup 40 µs
MSELx/BYPASS Stable After RESET Deasserted Hold 1000 ns

MSELx/BYPASS Stable After RESET Asserted 200 ns
Flag Output Disable Time After RESET Asserted 10 ns

.

CCLK

.

CCLK

–20– REV. 0

CLKIN

ADSP-2191M

t

CK

RESET

MSEL6–0

BYPASS

DF

CLKOUT

t

CKL

t

CKH

t

WRST

t

t

PFD

MSD

t

MSS

t

CKOD

t

MSH

Figure 8. Clock In and Clock Out Cycle Timing

t

CKO

–21–REV. 0

ADSP-2191M

Programmable Flags Cycle Timing

Table 10 and Figure 9 describe Programmable Flag operations.

Table 10. Programmable Flags Cycle Timing

Parameter Min Max Unit

Switching Characteristics

t

DFO

t

HFO

Timing Requirement

t

HFI

Flag Output Delay with Respect to CLKOUT 7 ns
Flag Output Hold After CLKOUT High 6 ns

Flag Input Hold is asynchronous 3 ns

CLKOUT

PF

(OUTPUT)

PF

(INPUT)

t

DFO

FLAG OUTPUT

t

HFI

FLAG INPUT

t

HFO

Figure 9. Programmable Flags Cycle Timing

Timer PWM_OUT Cycle Timing

Table 11 and Figure 10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an

absolute maximum input frequency of 40 MHz.

Table 11. Timer PWM_OUT Cycle Timing

Parameter Min Max Unit

Switching Characteristic

t

HTO

1

The minimum time for t

Timer Pulsewidth Output

HCLK

is one cycle, and the maximum time for t

HTO

1

equals (232–1) cycles.

HTO

12.5 (232–1) cycles ns

PWM_OUT

t

HTO

Figure 10. Timer PWM_OUT Cycle Timing

–22– REV. 0

ADSP-2191M

External Port Write Cycle Timing

Table 12 and Figure 11 describe external port write operations.

The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP
requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the

ADSP-219x/2191 DSP Hardware Reference

Table 12. External Port Write Cycle Timing

Parameter

1, 2

Switching Characteristics

t

CSWS

t

AWS

t

WSCS

t

WSA

t

WW

t

CDA

t

CDD

t

DSW

t

DHW

t

DHW

t

WWR

Chip Select Asserted to WR Asserted Delay 0.5t
Address Valid to WR Setup and Delay 0.5t

WR Deasserted to Chip Select Deasserted 0.5t
WR Deasserted to Address Invalid 0.5t
WR Strobe Pulsewidth t
WR to Data Enable Access Delay 0ns
WR to Data Disable Access Delay 0.5t
Data Valid to WR Deasserted Setup t
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to WR, RD Asserted t

Timing Requirements

t

AKW

t

DWSAK

1

t

is the peripheral clock period.

HCLK

2

These are timing parameters that are based on worst-case operating conditions.

3

W = (number of waitstates specified in wait register) ⴛ t

4

Write hold cycle–memory select control registers (MS ⴛ CTL).

ACK Strobe Pulsewidth 12.5 ns
ACK Delay from WR Low 0 ns

.

Min Max Unit

–4 ns

HCLK

–3 ns

HCLK

–4 ns

HCLK

–3 ns

HCLK.

HCLK

HCLK

HCLK

4
4

HCLK

3.4 ns
t

HCLK
HCLK

3

–2+W

–3 0.5t

3

+1+W

t

HCLK

HCLK

+7+W

+4 ns

ns

3

ns

+3.4 ns

MS3–0

IOM S

BMS

A21–0

WR

ACK

D15–0

RD

t

AWS

t

CSWS

t

DWSAK

t

CDA

t

WW

t

AKW

t

DSW

Figure 11. External Port Write Cycle Timing

t

t
t

CDD

DHW

t

WSCS

t

WSA

WWR

–23–REV. 0

ADSP-2191M

External Port Read Cycle Timing

Table 13 and Figure 12 describe external port read operations. For additional information on the ACK signal, see the discussion
on page 23.

Table 13. External Port Read Cycle Timing

Parameter

Switching Characteristics

t

CSRS

t

ARS

t

RSCS

t

RW

t

RSA

t

RWR

Timing Requirements

t

AKW

t

RDA

t

ADA

t

SDA

t

SD

t

HRD

t

DRSAK

1

t

HCLK

2

These are timing parameters that are based on worst-case operating conditions.

3

W = (number of waitstates specified in wait register) ⴛ t

1, 2

Chip Select Asserted to RD Asserted Delay 0.5t
Address Valid to RD Setup and Delay 0.5t

RD Deasserted to Chip Select Deasserted Setup 0.5t
RD Strobe Pulsewidth t
RD Deasserted to Address Invalid Setup 0.5t
RD Deasserted to WR, RD Asserted t

ACK Strobe Pulsewidth t
RD Asserted to Data Access Setup t
Address Valid to Data Access Setup t
Chip Select Asserted to Data Access Setup t
Data Valid to RD Deasserted Setup 7 ns
RD Deasserted to Data Invalid Hold 0 ns

ACK Delay from RD Low 0 ns

is the peripheral clock period.

HCLK

Min Max Unit

–3 ns

HCLK

–3 ns

HCLK

–2 ns

HCLK

HCLK

HCLK

HCLK

HCLK

.

3

–2+W

–2 ns

3

–4+W

HCLK
HCLK
HCLK

+W
+W

3
3

ns

ns
ns
ns
ns

MS3–0

IOMS

BMS

A21–0

RD

ACK

D15–0

WR

t

CSRS

t

t

RDA

t

ADA

t

t

SDA

RW

AKW

t

SD

t

ARS

t

DRSAK

t

CDA

Figure 12. External Port Read Cycle Timing

t

t

t

t

RSA

RWR

HRD

RSCS

–24– REV. 0

External Port Bus Request and Grant Cycle Timing

Table 14 and Figure 13 describe external port bus request and bus grant operations.

Table 14. External Port Bus Request and Grant Cycle Timing

Parameter

1, 2

Switching Characteristics

t

SD

t

SE

t

DBG

t

EBG

t

DBH

t

EBH

CLKOUT High to xMS, Address, and RD/WR Disable 0.5t
CLKOUT Low to xMS, Address, and RD/WR Enable04ns
CLKOUT High to BG Asserted Setup 0 4 ns
CLKOUT High to BG Deasserted Hold Time 0 4 ns
CLKOUT High to BGH Asserted Setup 0 4 ns
CLKOUT High to BGH Deasserted Hold Time04ns

Timing Requirements

t

BS

t

BH

1

t

is the peripheral clock period.

HCLK

2

These are timing parameters that are based on worst-case operating conditions.

BR Asserted to CLKOUT High Setup 4.6 ns
CLKOUT High to BR Deasserted Hold Time 0 ns

CLKOUT

ADSP-2191M

Min Max Unit

+1 ns

HCLK

BR

MS3–0

IOMS

BMS

A21–0

WR

RD

BG

BGH

t

BS

t

BH

t

t

t

t

t

SD

SD

SD

DBG

DBH

t

t

EBG

EBH

t

SE

t

SE

t

SE

Figure 13. External Port Bus Request and Grant Cycle Timing

–25–REV. 0

ADSP-2191M

Host Port ALE Mode Write Cycle Timing

Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 15. Host Port ALE Mode Write Cycle Timing

Parameter Min Max Unit

Switching Characteristics

t

WHKS1

HWR Asserted to HACK Asserted (Setup, ACK Mode) First
Byte

t

WHKS2

t

WHKH

t

WHS

t

WHH

HWR Asserted to HACK Asserted (Setup, ACK Mode)
HWR Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns

HWR Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
HWR Asserted to HACK Deasserted (Hold, Ready Mode)

10 5t

2

05t

HCLK+tNH

10 ns

HCLK+tNH

1

ns

1

ns

First Byte

Timing Requirements

t

CSAL

t

ALPW

t

ALCSW

t

WCSW

t

ALW

t

WCS

HCMS or HCIOMS Asserted to HALE Asserted 0ns
HALE Asserted Pulsewidth 4 ns
HALE Deasserted to HCMS or HCIOMS Deasserted 1 ns
HWR Deasserted to HCMS or HCIOMS Deasserted 0 ns
HALE Deasserted to HWR Asserted 1 ns
HWR Deasserted (After Last Byte) to HCMS or

0ns

HCIOMS Deasserted (Ready for Next Write)

t

HKWD

t

AALS

t

ALAH

t

DWS

t

WDH

1

tNH are peripheral bus latencies (n ⴛt

at the same time.

2

Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

HACK Asserted to HWR Deasserted (Hold, ACK Mode) 1.5 ns
Address Valid to HALE Deasserted (Setup) 2 ns
HALE Deasserted to Address Invalid (Hold) 4 ns
Data Valid to HWR Deasserted (Setup) 4 ns
HWR Deasserted to Data Invalid (Hold) 1 ns

); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

HCLK

–26– REV. 0

HCMS

HIOMS

t

HALE

HWR

H ACK

(ACK

MODE)

HACK

(READY

MODE)

HAD15–0

HA16

CSAL

t

AALS

t

t

ALPW

t

ALW

t

WHS

ALAH

A DDR ESS

VALID

START

FIRST W ORD

t

WHKS

t

ALCSW

t

HKWD

t

DWS

DA TA
VALID

FIR ST
BYTE

t

WHH

t

t

WHKH

WCSW

t

WDH

DATA

VALID

LAST
BYTE

ADSP-2191M

t

WCS

HA CK E ACH BYT E

HACK FIRST BYTE

AD DR ESS

VALID
START

NEXT WORD

Figure 14. Host Port ALE Mode Write Cycle Timing

–27–REV. 0

ADSP-2191M

Host Port ACC Mode Write Cycle Timing

Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 16. Host Port ACC Mode Write Cycle Timing

Parameter Min Max Unit

Switching Characteristics

t

WHKS1

t

WHKS2

t

WHKH

t

WHS

t

WHH

HWR Asserted to HACK Asserted (ACK Mode) First Byte 10 5t
HWR Asserted to HACK Asserted (Setup, ACK Mode)
HWR Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns
HWR Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
HWR Asserted to HACK Deasserted (Hold, Ready Mode)

2

05t

HCLK+tNH

12 ns

HCLK+tNH

1

ns

1

ns

First Byte

t

WSHKS

HWR Asserted to HACK Asserted (Setup) During Address

10 ns

Latch

t

WHHKH

HWR Deasserted to HACK Deasserted (Hold) During

10 ns

Address Latch

Timing Requirements

t

WAL

t

CSAL

t

ALCS

HWR Asserted to HALE Deasserted (Delay) 1.5 ns
HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0ns

HALE Deasserted to Optional HCMS or HCIOMS

1ns

Deasserted

t

WCSW

t

ALW

t

CSW

t

WCS

HWR Deasserted to HCMS or HCIOMS Deasserted 0 ns
HALE Asserted to HWR Asserted 0.5 ns

HCMS or HCIOMS Asserted to HWR Asserted 0ns
HWR Deasserted (After Last Byte) to HCMS or

0ns

HCIOMS Deasserted (Ready for Next Write)

t

ALEW

t

HKWD

t

ADW

t

WAD

t

DWS

t

WDH

t

HKWAL

1

tNH are peripheral bus latencies (nⴛ t

at the same time.

2

Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent

on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

HALE Deasserted to HWR Asserted 1 ns
HACK Asserted to HWR Deasserted (Hold, ACK Mode) 1.5 ns
Address Valid to HWR Asserted (Setup) 3 ns
HWR Deasserted to Address Invalid (Hold) 3 ns
Data Valid to HWR Deasserted (Setup) 2 ns
HWR Deasserted to Data Invalid (Hold) 2 ns

HACK Asserted to HWR Deasserted (Hold) During Address

2

Latch

); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

HCLK

2ns

–28– REV. 0

HCMS

HIOMS

t

CSA L

HALE

HWR

HACK

( ACK

MODE)

HACK

(R E A DY

MODE)

HAD15–0

HA16

t

t

WSHK S

t

ADW

t

WAL

HKWA L

t

WHHKH

t

WAD

A DDR ESS

FIR ST WORD

t

ALCS

t

ALW

VALID

START

t

HKWD

t

WHKS

t

WHS

ADSP-2191M

t

WCSW

t

CSW

t

t

ALE W

t

WHKH

t

WHH

t

DWS

DA TA

VALID

FIRST

BYTE

t

WDH

DATA
VALID

LAST
BYTE

WCS

HACK EACH BYTE

H ACK FIR ST B YTE

AD DR ES S

VALID

START

NEX T WO RD

Figure 15. Host Port ACC Mode Write Cycle Timing

–29–REV. 0

ADSP-2191M

Host Port ALE Mode Read Cycle Timing

Table 17 and Figure 16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 17. Host Port ALE Mode Read Cycle Timing

Parameter Min Max Unit

Switching Characteristics

t

RHKS1

t

RHKS2

t

RHKH

t

RHS

t

RHH

HRD Asserted to HACK Asserted (ACK Mode) First Byte 12t
HRD Asserted to HACK Asserted (Setup, ACK Mode)
HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns
HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
HRD Asserted to HACK Deasserted (Hold, Ready Mode)

15t

HCLK+tNH

12 ns

15t

HCLK+tNH

12t

HCLK

HCLK

2

1

ns

1

ns

First Byte

t

RDH

t

RDD

HRD Deasserted to Data Invalid (Hold) 1 ns
HRD Deasserted to Data Disable 10 ns

Timing Requirements

t

CSAL

t

ALCS

HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0ns
HALE Deasserted to Optional HCMS or HCIOMS

1ns

Deasserted

t

RCSW

t

ALR

t

RCS

HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns
HALE Deasserted to HRD Asserted 5 ns
HRD Deasserted (After Last Byte) to HCMS or

0ns

HCIOMS Deasserted (Ready for Next Read)

t

ALPW

t

HKRD

t

AALS

t

ALAH

1

tNH are peripheral bus latencies (nⴛt

the same time.

2

Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

HALE Asserted Pulsewidth 4 ns
HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns
Address Valid to HALE Deasserted (Setup) 2 ns
HALE Deasserted to Address Invalid (Hold) 4 ns

); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

HCLK

–30– REV. 0

HCMS

HIOMS

ADSP-2191M

t

CSA L

HALE

HRD

HACK

( ACK

MODE)

HAC K

(RE ADY

MODE)

HAD15–0

HA16

t

ALPW

t

AALS

t

ALA H

ADDRESS

VALID

START
FIRST
WORD

t

RHKS

t

RHS

t

ALCS

t

ALR

t

HKRD

DATA
VALID

FIRST
BYTE

t

RHH

t

RCSW

t

RHKH

t

RDH

DATA
VALID

LAST
BYTE

t

RCS

Figure 16. Host Port ALE Mode Read Cycle Timing

t

RDD

HA C K FOR EACH BY TE

HA CK FIRST BY T E

AD DR ESS

VALID

START

NEXT

WORD

–31–REV. 0

ADSP-2191M

Host Port ACC Mode Read Cycle Timing

Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 18. Host Port ACC Mode Read Cycle Timing

Parameter Min Max Unit

Switching Characteristics

t

RHKS1

t

RHKS2

t

RHKH

t

RHS

t

RHH

HRD Asserted to HACK Asserted (ACK Mode) First Byte 12t
HRD Asserted to HACK Asserted (Setup, ACK Mode)
HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns
HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
HRD Asserted to HACK Deasserted (Hold, Ready Mode)

15t

HCLK+tNH

10 ns

15t

HCLK+tNH

12t

HCLK

HCLK

2

1

ns

1

ns

First Byte

t

RDH

t

WSHKS

HRD Deasserted to Data Invalid (Hold) 1 ns
HWR Asserted to HACK Asserted (Setup) During Address

10 ns

Latch

t

WHHKH

HWR Deasserted to HACK Deasserted (Hold) During

10 ns

Address Latch

t

RDD

HRD Deasserted to Data Disable 10 ns

Timing Requirements

t

CSAL

t

ALCS

HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0ns
HALE Deasserted to Optional HCMS or HCIOMS

1ns

Deasserted

t

RCSW

t

ALW

t

ALER

t

CSR

t

RCS

HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns
HALE Asserted to HWR Asserted 0.5 ns
HALE Deasserted to HWR Asserted 1 ns

HCMS or HCIOMS Asserted to HRD Asserted 0ns
HRD Deasserted (After Last Byte) to HCMS or

0ns

HCIOMS Deasserted (Ready for Next Read)

t

WAL

t

HKRD

t

ADW

t

WAD

t

HKWAL

1

tNH are peripheral bus latencies (nⴛt

the same time.

2

Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

HWR Deasserted to HALE Deasserted (Delay) 2.5 ns
HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns
Address Valid to HWR Deasserted (Setup) 2 ns
HWR Deasserted to Address Invalid (Hold) 1 ns
HACK Asserted to HWR Deasserted (Hold) During Address

2

Latch

); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

HCLK

2ns

–32– REV. 0

HCMS

HIOMS

t

HALE

HW R

HRD

HACK

(ACK

MODE)

HACK

(READY

MODE)

CSAL

t

ALW

t

WSHKS

t

t

WHHKH

WAL

t

ALCS

t

ALER

t

CSR

t

t

RHKS

HKWAL

t

RHS

t

HKRD

t

RHH

t

RCSW

t

RHKH

t

ADSP-2191M

RCS

HA CK EAC H BYT E

HACK FIRST BYTE

HAD 15–0

HA16

t

ADW

FIR ST WORD

ADDRESS

VALID

START

t

WAD

DATA

VALID

FIRST

BYTE

t

RDH

DATA
VALID

LAST
BYTE

t

RDD

Figure 17. Host Port ACC Mode Read Cycle Timing

ADDRESS

VAL ID

START

NEX T WO RD

–33–REV. 0

ADSP-2191M

Serial Ports

Table 19 and Figure 18 describe SPORT transmit and receive operations, while Figure 19 and Figure 20 describe SPORT Frame

Sync operations.

Table 19. Serial Ports

1, 2

Parameter Min Max Unit

External Clock

Timing Requirements

t

SFSE

t

HFSE

t

SDRE

t

HDRE

t

SCLKW

t

SCLK

TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width 0.5t
TCLK/RCLK Period 2t

3

3

3

3

4ns
4ns

1.5 ns
4ns

–1 ns

HCLK

HCLK

ns

Internal Clock

Timing Requirements

t

SFSI

t

HFSI

t

SDRI

t

HDRI

TFS Setup Before TCLK4; RFS Setup Before RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK

3

3

3

3

4ns
3ns
2ns
5ns

External or Internal Clock

Switching Characteristics

t

DFSE

t

HOFSE

TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)

4

4

3ns

14 ns

External Clock

Switching Characteristics

t

DDTE

t

HDTE

Transmit Data Delay After TCLK
Transmit Data Hold After TCLK

4

4

4ns

13.4 ns

Internal Clock

Switching Characteristics

t

DDTI

t

HDTI

t

SCLKIW

Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width 0.5t

Enable and Three-State

Switching Characteristics

t

DTENE

t

DDTTE

t

DTENI

t

DDTTI

Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from External TCLK

5

4

4

4

4

4

4

4ns

–3.5 0.5t

HCLK

012.1ns

013ns

13.4 ns

+2.5 ns

HCLK

13 ns

12 ns

External Late Frame Sync

Switching Characteristics

t

DDTLFSE

t

DTENLFSE

1

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay

and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.

2

Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).

3

Referenced to sample edge.

4

Referenced to drive edge.

5

Only applies to SPORT0/1.

6

MCE=1, TFS enable, and TFS valid follow t

7

If external RFSD/TFS setup to RCLK/TCLK>0.5t

Data Delay from Late External TFS with MCE =1, MFD =0
Data Enable from Late FS or MCE=1, MFD=0

DDTENFS

LSCK

and t

, t

DDTLFSE

DDTLSCK

.

and t

6, 7

DTENLSCK

6, 7

3.5 ns

apply; otherwise t

DDTLFSE

and t

10.5 ns

apply.

DTENLFS

–34– REV. 0

ADSP-2191M

DATA RECEIVE-INTERNAL CLOCK

DRIVE
EDGE

RCLK

t

DFSE

t

HOFSE

RFS

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CANBE USED AS THEACTIVE SAMPLING EDGE.

DATA TRANSMIT-INTERNAL CLOCK

DRIVE
EDGE

TCLK

t

DFSE

t

HOFSE

TFS

t

DDTI

t

HDTI

DT

t

SCLKIW

t

SCLKIW

t

SFSI

t

SDRI

t

SFSI

SAMPLE

EDGE

SAMPLE

EDGE

t

HFSI

t

HDRI

t

HFSI

DATA RECEIVE-EXTERNAL CLOCK

DRIVE
EDGE

t

SCLKW

RCLK

t

DFSE

t

HOFSE

RFS

DR

DATA TRANSMIT-EXTERNAL CLOCK

DRIVE
EDGE

t

SCLKW

TCLK

t

DFSE

t

HOFSE

TFS

t

DDTE

t

HDTE

DT

t

SFSE

t

SDRE

t

SFSE

SAMPLE

EDGE

SAMPLE

EDGE

t

HFSE

t

HDRE

t

HFSE

TCLK (EXT)

TFS ("LATE," EXT.)

DT

TCLK (INT)

TFS ("LATE," INT.)

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CANBE USED AS THEACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE
EDGE

TCLK / RCLK

DRIVE
EDGE

t

DDTEN

DRIVE
EDGE

t

DDTTE

TCLK / RCLK

t

DDTIN

t

DDTTI

Figure 18. Serial Ports

–35–REV. 0

ADSP-2191M

EXTERNAL RFS WITH MCE = 1, MFD = 0

RCLK

RFS

DT

DRIVE

t

DDTLFSE

t

SFSE /I

t

DTENLFSE

SAMPLE

1ST BIT 2ND BIT

LATE EXTERNAL TFS

DRIVE

TCLK

TFS

DT

t

SFSE /I

t

DTENLFSE

SAMPLE

1ST BIT 2ND BIT

DRIVE

DRIVE

t

HOSFSE/ I

t

DDTE/I

t

HDTE/ I

t

HOSFSE/ I

t

DDTE/I

t

HDTE/ I

t

DDTLFSE

Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5t

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

RCLK

t

RFS

DT

t

DDTLFSE

LATE EXTERNAL TFS

DRIVE

TCLK

t

TFS

DT

SFSE/I

t

DTENLFSE

SFSE /I

t

DTENLFSE

SAMPLE

SAMPLE

DRIVE

t

HOFSE/I

t

DDTE/I

t

HDTE/ I

1ST BIT 2ND BIT

DRIVE

t

HOFSE/I

t

DDTE/I

t

HDTE/ I

1ST BIT 2ND BIT

SCLK

)

t

DDTLFSE

Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5t

–36– REV. 0

HCLK

)

ADSP-2191M

Serial Peripheral Interface (SPI) Port—Master Timing

Table 20 and Figure 21 describe SPI port master operations.

Table 20. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter Min Max Unit

Switching Characteristics

t

SDSCIM

t

SPICHM

t

SPICLM

t

SPICLK

t

HDSM

t

SPITDM

t

DDSPID

t

HDSPID

Timing Requirements

t

SSPID

t

HSPID

SPIxSEL Low to First SCLK edge (x=0 or 1) 2t
Serial Clock High Period 2t
Serial Clock Low Period 2t
Serial Clock Period 4t
Last SCLK Edge to SPIxSEL High (x= 0 or 1) 2t
Sequential Transfer Delay 2t

–3 ns

HCLK

–3 ns

HCLK

–3 ns

HCLK

–1 ns

HCLK

–3 ns

HCLK

–2 ns

HCLK

SCLK Edge to Data Output Valid (Data Out Delay) 0 6 ns
SCLK Edge to Data Output Invalid (Data Out Hold) 0 5 ns

Data Input Valid to SCLK Edge (Data Input Setup) 8 ns
SCLK Sampling Edge to Data Input Invalid (Data In Hold) 1 ns

t

SPIxSEL

(OUTPUT)

(x = 0 or 1 )

SCLK

(CPOL = 0)

(OUTP UT )

t

SDSCIM

SPICHM

t

SPICLM

t

SPICLK

t

HDSM

t

SPITDM

(CPOL = 1)

(OUTP UT )

(OUTPUT)

CPHA = 1

(INPUT)

(OUTPUT)

CPHA = 0

(INPUT )

SCLK

MOSI

MISO

MOSI

MISO

t

SSPID

t

SPICLM

t

SSPID

MSB

VALID

MSB

VALID

t

HSPID

t

DDSPID

t

HSPID

t

DDSPID

t

SPICHM

t

HDSPID

t

SSPID

LSB

VALID

t

HDSPID

LSBMSB

LSB

VALID

Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing

LSBMSB

t

HSPID

–37–REV. 0

ADSP-2191M

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 21 and Figure 22 describe SPI port slave operations.

Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter Min Max Unit

Switching Characteristics

t

DSOE

t

DSDHI

t

DDSPID

t

HDSPID

Timing Requirements

t

SPICHS

t

SPICLS

t

SPICLK

t

HDS

t

SPITDS

t

SDSCI

t

SSPID

t

HSPID

SPISS Assertion to Data Out Active 08ns
SPISS Deassertion to Data High Impedance 010ns

SCLK Edge to Data Out Valid (Data Out Delay) 0 10 ns
SCLK Edge to Data Out Invalid (Data Out Hold) 0 10 ns

Serial Clock High Period 2t
Serial Clock Low Period 2t
Serial Clock Period 4t
Last SPICLK Edge to SPISS Not Asserted 2t
Sequential Transfer Delay 2t
SPISS Assertion to First SPICLK Edge 2t

HCLK
HCLK
HCLK
HCLK

+4 ns

HCLK
HCLK

Data Input Valid to SCLK Edge (Data Input Setup) 1.6 ns
SCLK Sampling Edge to Data Input Invalid (Data In Hold) 2.4 ns

ns
ns
ns
ns

ns

(CPOL= 0)

(CPOL= 1)

CPHA = 1

CPHA = 0

SPISS

(INPUT)

SCLK

(INPUT)

SCLK

(INPUT)

t

MISO

(OUTPUT)

MOSI

(INPUT)

t

DSOE

MISO

(OUTPUT)

MOSI

(INPUT)

DSOE

t

t

t

SDSCI

SPICHS

SPICLS

t

DDSPIDtHDSPID

t

SSPID

MSB

VALID

t

DDSPID

MSB

MSB

VALID

t

HSPID

t

SPICLS

t

SPICHS

t

SSPID

t

DDSPID

VALID

t

SPICLK

t

LSB

SSPID

LSB

LSB

VALID

t

HSPID

t

HDS

t

DSDHI

LSBMSB

t

DSDHI

t

HSPID

t

SPITDS

Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing

–38– REV. 0

ADSP-2191M

Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure 23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 23 there

is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at
the data transmission rates for the UART.

HCLK

(SAMPLE

CLOCK)

RXD

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

TXD

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

AS DATA

WRITTEN TO

BUFFER

DATA(5–8)

START

DATA(5–8)

STOP

STOP (1–2)

Figure 23. UART Port—Receive and Transmit Timing

UART RECEIVEBITSET BY DATA STOP;

CLEAREDBY FIFOREAD

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

–39–REV. 0

ADSP-2191M

JTAG Test And Emulation Port Timing

Table 22 and Figure 24 describe JTAG port operations.

Table 22. JTAG Port Timing

Parameter Min Max Unit

Switching Characteristics

t

DTDO

t

DSYS

Timing Requirements

t

TCK

t

STAP

t

HTAP

t

SSYS

t

HSYS

t

TRSTW

1

System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, R CLK1,

TFS0, TFS1, RFS0, RFS1, BMS.

2

System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,

CLKIN, RESET.

3

50 MHz max.

TDO Delay from TCK Low 8 ns
System Outputs Delay After TCK Low

1

022ns

TCK Period 20 ns
TDI, TMS Setup Before TCK High 4 ns
TDI, TMS Hold After TCK High 4 ns
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth

3

2

2

4t

TCK

4ns
5ns

ns

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

t

DTDO

t

STAP

t

DSYS

t

TCK

t

HTAP

t

SSYS

Figure 24. JTAG Port Timing

t

HSYS

–40– REV. 0

ADSP-2191M

Output Drive Currents

Figure 25 shows typical I-V characteristics for the output drivers

of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.

60

40

A
m
–

20

T
N
E
R

0

R
U
C
)

–20

T
X
E
D
D

–40

V

(
E

C
R

–60

U
O
S

–80

–100

03.50.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRENT

INPUT CURRENT

SOURCE (

V

DDEXT

V

OL

VDDEXT

=3.65V@–40°C

V

=3.3V@+25°C

DDEXT

V

=3.0V@+ 85°C

DDEXT

V

=3.0V@+85°C

DDEXT

V

=3.3V@+25°C

DDEXT

V

=3.65V@– 40°C

DDEXT

)VOLTAGE–V

V

OH

4.0

Figure 25. Typical Drive Currents

Power Dissipation

Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

• Number of output pins that switch during each cycle (O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Their voltage swing (V

DD

)

and is calculated by the formula below.

P

EXT

OC× V

2

× f×=

DD

The load capacitance includes the processor’s package capaci­tance (C

). The switching frequency includes driving the load

IN

high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t
every cycle at a frequency of 1/t
but selects can switch on each cycle. For example, estimate P

). The write strobe can switch

CK

. Select pins switch at 1/(2tCK),

CK

EXT

with the following assumptions:

• A system with one bank of external data memory—asyn-

chronous RAM (16-bit)

• One 64Kⴛ16 RAM chip is used with a load of 10 pF

• Maximum peripheral speed CCLK = 80 MHz, HCLK =

80 MHz

• External data memory writes occur every other cycle, a

rate of 1/(4t

• The bus cycle time is 80 MHz (t
The P

equation is calculated for each class of pins that can

EXT

), with 50% of the pins switching

HCLK

HCLK

= 12.5 nsec)

drive as shown in Table 23.

Table 23. P

Pin Type # of Pins % Switching ⴛ C ⴛ f ⴛ V

Calculation Example

EXT

DD

2

= P

EXT

Address 15 50 10 pF ⴛ20 MHz ⴛ10.9 V = .01635 W

MSx 10 10pFⴛ20 MHz ⴛ10.9V = 0W
WR 1— 10pFⴛ40 MHz ⴛ10.9 V = .00436 W

Data 16 50 10 pF ⴛ20 MHz ⴛ10.9 V = .01744 W
CLKOUT 1 — 10 pF ⴛ 80 MHz ⴛ 10.9 V = .00872 W

P

=.04687 W

EXT

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.

Test Conditions

The DSP is tested for output enable, disable, and hold time.

Output Disable Time

Output pins are considered to be disabled when they stop driving,

Where:

• P

EXT

• P

INT

P

TOTAL

is from Table 23

is I

ⴛ 2.5 V, using the calculation I

DDINT

P=

EXT

P

+

INT

go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by – V is dependent on the capacitive load, C

. This decay time can be approximated by the

L

DDINT

load current, I
equation below.

listed in Power Dissipation on page 41.

Note that the conditions causing a worst-case P
from those causing a worst-case P

. Maximum P

INT

occur while 100% of the output pins are switching from all ones

are different

EXT

INT

cannot

t

DECAY

=

CLV∆

---------------

I

L

to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.

and the

L

–41–REV. 0

ADSP-2191M

The output disable time t
t

MEASURED

t

MEASURED

and t

DECAY

is the interval from when the reference signal

is the difference between

DIS

as shown in Figure 26. The time

switches to when the output voltage decays –V from the measured
o ut p ut h i gh o r ou t put l ow v ol t age . Th e t
test loads C

and IL, and with –V equal to 0.5 V.

L

REFERENCE

SIGNAL

t

MEASURED

V

OH (MEASURED)

V

OL (MEASURED )

t

DECAY

DRIVING

TEST CONDITIONS CAUSE THIS VOLTAGE

V

OH (MEASURED)

V

OL (MEASURED)

t

DIS

OUTPUTSTOPS

HIGH-IMPEDANCE STATE.

TO BE APPROXIMATELY 1.5V

is calculated with

DECAY

– ⌬V

+ ⌬V

OUTPUT STARTS

t

ENA

2.0V

1.0V

DRIVING

Figure 26. Output Enable/Disable

I

OL

TO

OUTPUT

PIN

50pF

I

OH

+1.5V

Figure 27. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

INPUT

OR

OUTPUT

1.5V 1.5V

Figure 28. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t

is the interval from when

ENA

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 26). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,
first calculate t

using the equation at Output Disable Time

DECAY

on page 41. Choose –V to be the difference between the

ADSP-2191M’s output voltage and the input threshold for the
device requiring the hold time. A typical –V will be 0.4 V. C
the total bus capacitance (per data line), and I

is the total leakage

L

is

L

or three-state current (per data line). The hold time will be
t

DECAY

plus the minimum disable time (i.e., t

DATRWH

for the

write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica­tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF. Figure 28 and Figure 29
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see Output Disable Time on page 41.) The
graphs in these figures may not be linear outside the ranges
shown.

40

)
%

0

9
–

%

30

0

1

(
s

n
–

S
E

20

M

I
T

L
L
A
F

D
N

10

A
E

S

I
R

0

025050 100 150 200

LOAD CAPACITANCE – pF

RISE TIME

Figure 29. Typical Output Rise Time (10%-90%,

V

= Minimum at Maximum Ambient

DDEXT

Operating Temperature) vs. Load Capacitance

Environmental Conditions

The thermal characteristics in which the DSP is operating
influence performance.

Thermal Characteristics

The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T

) as calculated using the

AMB

formula below.
To ensure that the T

data sheet specification is not exceeded,

AMB

a heatsink and/or an air flow source may be used. A heatsink
should be attached to the ground plane (as close as possible to
the thermal pathways) with a thermal adhesive.

T

= PD

AMBTCASE

θ

×–

CA

–42– REV. 0

ADSP-2191M

30

s
n

20

–
D

L
O
H

R
O

Y

10

A
L
E
D

T
U
P
T

0

U
O

–10

025050 100 150 200

LOAD CAPACITANCE – pF

Figure 30. Typical Output Delay or Hold vs. Load

Capacitance (at Maximum Case Temperature)

Where:

• T

= Ambient temperature (measured near top

AMB

surface of package)

• PD = Power dissipation in W (this value depends upon

the specific application; a method for calculating PD is
shown under Power Dissipation).

= Value from Table 24.

•θ

CA

• For the LQFP package: θ
For the mini-BGA package: θ

Table 24. θ

Valu es

CA

Airflow

= 0.96°C/W

JC

= 8.4°C/W

JC

0 100 200 400 600
(Linear Ft./Min.)
Airflow

00.5123
(Meters/Second)
LQFP:

(°C/W)

θ

CA

Mini-BGA:

(°C/W)

θ

CA

44.3 41.4 38.5 35.3 32.1

26 24 22 20.9 19.8

–43–REV. 0

ADSP-2191M

144-Lead LQFP Pinout

Table 25 lists the LQFP pinout by signal name. Table 26 lists

the LQFP pinout by pin.

Table 25. 144-Lead LQFP Pins (Alphabetically by Signal)

Signal

Pin
No. Signal

Pin
No. Signal

Pin
No. Signal

Pin
No. Signal

Pin
No.

A0 84 BYPASS 72 GND 33 HCMS 27 TCLK1 65
A1 85 CLKIN 132 GND 54 HCIOMS
A2 86 CLKOUT 130 GND 55 HRD
A3 87 D0 123 GND 77 HWR
A4 88 D1 124 GND 80 IOMS
A5 89 D2 125 GND 94 MS0
A6 91 D3 126 GND 105 MS1
A7 92 D4 128 GND 129 MS2
A8 93 D5 135 GND 134 MS3

28 TCLK2 47
31 TDI 75
32 TDO 74
114 TFS0 59
115 TFS1 66
116 TFS2 48
117 TMR0 43

119 TMR1 44
A9 95 D6 136 HA16 23 OPMODE 83 TMR2 45
A10 96 D7 137 HACK 26 PF0 34 TMS 76
A11 97 D8 138 HACK_P 24 PF1 35 TRST

79
A12 98 D9 139 HAD0 3 PF2 36 TXD 53
A13 99 D10 140 HAD1 4 PF3 37 V
A14 101 D11 141 HAD2 6 PF4 38 V
A15 102 D12 142 HAD3 7 PF5 39 V
A16 103 D13 144 HAD4 8 PF6 41 V
A17 104 D14 1 HAD5 9 PF7 42 V
A18 106 D15 2 HAD6 10 RCLK0 61 V
A19 107 DR0 60 HAD7 11 RCLK1 68 V
A20 108 DR1 67 HAD8 12 RCLK2 50 V
A21 109 DR2 49 HAD9 14 RD

122 V

ACK 120 DT0 56 HAD10 15 RESET 73 V

BG
BGH

111 DT1 64 HAD11 17 RFS0 62 V
110 DT2 46 HAD12 18 RFS1 69 V

BMODE0 70 EMU 81HAD13 20RFS2 51V

DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDINT
DDINT
DDINT
DDINT

BMODE1 71 GND 5 HAD14 21 RXD 52 WR

BMS
BR

113 GND 16 HAD15 22 TCK 78 XTAL 133
112 GND 29 HALE 30 TCLK0 57

13

25

40

63

90

100

118

131

143

19

58

82

127

121

–44– REV. 0

Table 26. 144-Lead LQFP Pins (Numerically by Pin Number)

ADSP-2191M

Pin
No. Signal

Pin
No. Signal

Pin
No. Signal

Pin
No. Signal

Pin
No. Signal

1 D14 30 HALE 59 TFS0 88 A4 117 MS2
2 D15 31 HRD 60 DR0 89 A5 118 V
3HAD0 32HWR 61 RCLK0 90 V

DDEXT

119 MS3

DDEXT

4 HAD1 33 GND 62 RFS0 91 A6 120 ACK
5GND 34PF0 63V

DDEXT

92 A7 121 WR
6 HAD2 35 PF1 64 DT1 93 A8 122 RD
7 HAD3 36 PF2 65 TCLK1 94 GND 123 D0
8 HAD4 37 PF3 66 TFS1 95 A9 124 D1
9 HAD5 38 PF4 67 DR1 96 A10 125 D2
10 HAD6 39 PF5 68 RCLK1 97 A11 126 D3
11 HAD7 40 V

DDEXT

69 RFS1 98 A12 127 V

DDINT

12 HAD8 41 PF6 70 BMODE0 99 A13 128 D4
13 V

DDEXT

42 PF7 71 BMODE1 100 V

DDEXT

129 GND
14 HAD9 43 TMR0 72 BYPASS 101 A14 130 CLKOUT
15 HAD10 44 TMR1 73 RESET 102 A15 131 V

DDEXT

16 GND 45 TMR2 74 TDO 103 A16 132 CLKIN
17 HAD11 46 DT2 75 TDI 104 A17 133 XTAL
18 HAD12 47 TCLK2 76 TMS 105 GND 134 GND
19 V

DDINT

48 TFS2 77 GND 106 A18 135 D5
20 HAD13 49 DR2 78 TCK 107 A19 136 D6
21 HAD14 50 RCLK2 79 TRST 108 A20 137 D7
22 HAD15 51 RFS2 80 GND 109 A21 138 D8
23 HA16 52 RXD 81 EMU 110 BGH 139 D9
24 HACK_P 53 TXD 82 V
25 V

DDEXT

54 GND 83 OPMODE 112 BR 141 D11

DDINT

111 BG 140 D10

26 HACK 55 GND 84 A0 113 BMS 142 D12
27 HCMS 56 DT0 85 A1 114 IOMS 143 V

DDEXT

28 HCIOMS 57 TCLK0 86 A2 115 MS0 144 D13
29 GND 58 V

DDINT

87 A3 116 MS1

–45–REV. 0

ADSP-2191M

144-Lead Mini-BGA Pinout

Table 27 lists the mini-BGA pinout by signal name. Table 28

lists the mini-BGA pinout by ball number.

Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal)

Signal

Ball
No. Signal

Ball
No. Signal

Ball
No. Signal

Ball
No. Signal

Ball
No.

A0 J11 BYPASS M11 GND F7 HALE J1 TCLK0 J6
A1 H9 CLKIN A5 GND F8 HCIOMS
A2 H10 CLKOUT C6 GND F9 HCMS
A3 G12 D0 D7 GND G4 HRD
A4 H11 D1 A7 GND G5 HWR
A5 G10 D2 C7 GND G6 IOMS
A6 F12 D3 A6 GND H5 MS0
A7 G11 D4 B7 GND L6 MS1
A8 F10 D5 A4 GND M1 MS2
A9 F11 D6 C5 GND M12 MS3

J3 TCLK1 M9
H1 TCLK2 K5
J2 TDI K12
K2 TDO L11
E8 TFS0 M8
D9 TFS1 J8
A9 TFS2 M5
C9 TMR0 K4

D8 TMR1 L4
A10 E12 D7 B5 HACK H3 OPMODE H12 TMR2 J4
A11 E11 D8 D5 HACK_P G1 PF0 K1 TMS K10
A12 E10 D9 A3 HAD0 C1 PF1 L1 TRST

J12
A13 E9 D10 C4 HAD1 B3 PF2 M2 TXD M7
A14 D11 D11 B4 HAD2 C2 PF3 L2 V
A15 D10 D12 C3 HAD3 D1 PF4 M3 V
A16 D12 D13 A2 HAD4 D4 PF5 L3 V
A17 C11 D14 B1 HAD5 D3 PF6 K3 V
A18 C12 D15 B2 HAD6 D2 PF7 M4 V
A19 B12 DR0 L7 HAD7 E1 RCLK0 K7 V
A20 B11 DR1 K9 HAD8 E4 RCLK1 J9 V
A21 A11 DR2 L5 HAD9 E2 RCLK2 J5 V
ACK A8 DT0 H6 HAD10 F1 RD B8 V

BG
BGH

C10 DT1 L8 HAD11 E3 RESET L12 V
B10 DT2 H4 HAD12 F2 RFS0 K8 V

BMODE0 L10 EMU J10 HAD13 G2 RFS1 M10 V

DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDEXT
DDINT
DDINT
DDINT
DDINT

BMODE1 L9 GND A1 HAD14 F3 RFS2 M6 WR

BMS
BR

A10 GND A12 HAD15 G3 RXD K6 XTAL B6
B9 GND E7 HA16 H2 TCK K11

E5

E6

F5

F6

G7

G8

H7

H8

D6

F4

G9

J7

C8

–46– REV. 0

Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number)

ADSP-2191M

Ball
No. Signal

Ball
No. Signal

Ball
No. Signal

Ball
No. Signal

Ball
No. Signal

A1 GND C6 CLKOUT E11 A11 H4 DT2 K9 DR1
A2 D13 C7 D2 E12 A10 H5 GND K10 TMS
A3 D9 C8 WR F1 HAD10 H6 DT0 K11 TCK
A4 D5 C9 MS2 F2 HAD12 H7 V
A5 CLKIN C10 BG F3 HAD14 H8 V
A6 D3 C11 A17 F4 V
A7 D1 C12 A18 F5 V
A8 ACK D1 HAD3 F6 V

DDINT
DDEXT
DDEXT

H9 A1 L2 PF3
H10 A2 L3 PF5
H11 A4 L4 TMR1

DDEXT
DDEXT

K12 TDI
L1 PF1

A9 MS1 D2 HAD6 F7 GND H12 OPMODE L5 DR2
A10 BMS D3 HAD5 F8 GND J1 HALE L6 GND
A11 A21 D4 HAD4 F9 GND J2 HRD L7 DR0
A12 GND D5 D8 F10 A8 J3 HCIOMS L8 DT1
B1 D14 D6 V

DDINT

F11 A9 J4 TMR2 L9 BMODE1
B2 D15 D7 D0 F12 A6 J5 RCLK2 L10 BMODE0
B3 HAD1 D8 MS3 G1 HACK_P J6 TCLK0 L11 TDO
B4 D11 D9 MS0 G2 HAD13 J7 V

DDINT

L12 RESET
B5 D7 D10 A15 G3 HAD15 J8 TFS1 M1 GND
B6 XTAL D11 A14 G4 GND J9 RCLK1 M2 PF2
B7 D4 D12 A16 G5 GND J10 EMU M3 PF4
B8 RD E1 HAD7 G6 GND J11 A0 M4 PF7
B9 BR E2 HAD9 G7 V
B10 BGH E3 HAD11 G8 V
B11 A20 E4 HAD8 G9 V
B12 A19 E5 V
C1 HAD0 E6 V

DDEXT
DDEXT

G10 A5 K3 PF6 M8 TFS0
G11 A7 K4 TMR0 M9 TCLK1

DDEXT
DDEXT
DDINT

J12 TRST M5 TFS2
K1 PF0 M6 RFS2
K2 HWR M7 TXD

C2 HAD2 E7 GND G12 A3 K5 TCLK2 M10 RFS1
C3 D12 E8 IOMS H1 HCMS K6 RXD M11 BYPASS
C4 D10 E9 A13 H2 HA16 K7 RCLK0 M12 GND
C5 D6 E10 A12 H3 HACK K8 RFS0

–47–REV. 0

ADSP-2191M

OUTLINE DIMENSIONS

144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)

22.00 BSC SQ

20.00 BSC SQ

109

108

0.27

0.22

0.17

SEATING

PLANE

0.08 MAX LEAD
COPLANARITY

0.75

0.60

0.45

144

1

TYP

0.15

0.05

1.45

1.40

1.35

1.60 MAX

36

DETAIL A

NOTES:

1.

DIMENSIONS IN MILLIMETERS.

2.

ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERALDIRECTION.

3.

CENTER DIMENSIONS ARE NOMINAL.

144-BALL MINI-BGA (CA-144A)

10.10

10.00 SQ

9.90

8.80
BSC

SQ

TOP VIEW

1.70

MAX

DETAIL A

0.25
MIN

37

DETAIL A

TOP VIEW (PINS DOWN)

12 11 10 9 8 7 6 5 4 3 2 1

0.80
BSC

BALL

PITCH

0.50 BSC
LEAD PITCH

A1 CORNER INDEX

TRIANGLE

BOTTOM VIEW

A
B
C
D
E
F
G
H
J
K
L
M

0.85
MIN

73

72

NOTES:

1.

DIMENSIONS IN MILLIMETERS.

2.

ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE TO
THE PACKAGE EDGES.

3.

ACTUAL POSITION OF EACH BALL IS WITHIN 0.08
OF ITS IDEAL POSITION, RELATIVE TO THE BALL
GRID.

4.

CENTER DIMENSIONS ARE NOMINAL.

0.55

0.50

0.45

BALL

DIAMETER

SEATING
PLANE

0.10 MAX BALL
COPLANARITY

DETAIL A

–48– REV. 0

ORDERING GUIDE

ADSP-2191M

Part Number

1, 2

Ambient Temperature Range

Instruction
Rate (MHz)

Package
Description Operating Voltage

ADSP-2191MKST-160 0ºC to 70ºC 160 144-Lead LQFP 2.5 Int./3.3 Ext. V
ADSP-2191MBST-140 – 40ºC to +85ºC 140 144-Lead LQFP 2.5 Int./3.3 Ext. V
ADSP-2191MKCA-160 0ºC to 70ºC 160 144-Ball Mini-BGA 2.5 Int./3.3 Ext. V
ADSP-2191MBCA-140 –40ºC to +85ºC 140 144-Ball Mini-BGA 2.5 Int./3.3 Ext. V

1

ST = Plastic Thin Quad Flatpack (LQFP).

2

CA = Mini Ball Grid Array

–49–REV. 0

ADSP-2191M

–50– REV. 0

ADSP-2191M

–51–REV. 0

–52– REV. 0

ADSP-2191M

PRINTED IN U.S.A. C02936-0-4/02(0)