ANALOG DEVICES ADSP-218x Service Manual

ADSP-218x DSP

Instruction Set Reference

Revision 2.0, November 2004

Part Number

82-002000-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, EZ-ICE, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

INTRODUCTION

Audience ...................................................................................... 1-1

Contents Overview ....................................................................... 1-2

Development Tools ....................................................................... 1-4

Additional Product Information .................................................... 1-7

For Technical or Customer Support ............................................... 1-7

What’s New in This Manual .......................................................... 1-8

Related Documents ....................................................................... 1-8

Conventions ................................................................................. 1-8

PROGRAMMING MODEL

Overview ...................................................................................... 2-1

Data Address Generators .......................................................... 2-2

Always Initialize L Registers ................................................ 2-4

Program Sequencer .................................................................. 2-4

Interrupts ........................................................................... 2-5

Loop Counts ....................................................................... 2-5

Status and Mode Bits .......................................................... 2-6

Stacks ................................................................................. 2-6

ADSP-218x DSP Instruction Set Reference iii

CONTENTS

Computational Units .............................................................. 2-7

Bus Exchange .......................................................................... 2-8

Timer ..................................................................................... 2-8

Serial Ports .............................................................................. 2-8

Memory Interface and SPORT Enables ................................... 2-9

Program Example ....................................................................... 2-10

Example Program: Setup Routine Discussion ......................... 2-13

Example Program: Interrupt Routine Discussion .................... 2-15

Hardware Overlays and Software Issues ....................................... 2-16

Libraries and Overlays ........................................................... 2-17

Interrupts and Overlays ......................................................... 2-17

Loop Hardware and Overlays ................................................ 2-19

SOFTWARE EXAMPLES

Overview ...................................................................................... 3-1

System Development Process ....................................................... 3-3

Single-Precision Fir Transversal Filter ............................................ 3-5

Cascaded Biquad IIR Filter ........................................................... 3-7

Sine Approximation ...................................................................... 3-9

Single-Precision Matrix Multiply ................................................. 3-11

Radix-2 Decimation-in-Time FFT .............................................. 3-13

Main Module ........................................................................ 3-14

DIT FFT Subroutine ............................................................ 3-16

Bit-Reverse Subroutine .......................................................... 3-21

Block Floating-Point Scaling Subroutine ................................ 3-22

iv ADSP-218x DSP Instruction Set Reference

CONTENTS

INSTRUCTION SET

Quick List Of Instructions ............................................................ 4-2

Instruction Set Overview ............................................................... 4-5

Multifunction Instructions ............................................................ 4-7

ALU/MAC With Data and Program Memory Read .................. 4-7

Data and Program Memory Read ............................................. 4-9

Computation With Memory Read ........................................... 4-9

Computation With Memory Write ........................................ 4-10

Computation With Data Register Move ................................. 4-10

ALU, MAC and Shifter Instructions ............................................ 4-14

ALU Group ........................................................................... 4-14

MAC Group .......................................................................... 4-16

Shifter Group ........................................................................ 4-18

MOVE: Read and Write Instructions ........................................... 4-20

Program Flow Control ................................................................ 4-22

Miscellaneous Instructions .......................................................... 4-25

Extra Cycle Conditions ............................................................... 4-27

Multiple Off-Chip Memory Accesses ...................................... 4-27

Wait States ............................................................................ 4-27

SPORT Autobuffering and DMA ........................................... 4-28

Instruction Set Syntax ................................................................. 4-28

Punctuation and Multifunction Instructions ........................... 4-28

Syntax Notation Example ...................................................... 4-29

Status Register Notation ........................................................ 4-30

ADSP-218x DSP Instruction Set Reference v

CONTENTS

ALU Instructions ........................................................................ 4-31

Add/Add With Carry ............................................................ 4-32

Subtract X-Y/Subtract X-Y With Borrow ............................... 4-35

Subtract Y-X/Subtract Y-X With Borrow ................................ 4-39

Bitwise Logic: AND, OR, XOR ............................................. 4-42

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT ....... 4-45

Clear: PASS .......................................................................... 4-48

Negate .................................................................................. 4-52

NOT .................................................................................... 4-54

Absolute Value: ABS ............................................................. 4-56

Increment ............................................................................. 4-59

Decrement ............................................................................ 4-61

Divide Primitives: DIVS and DIVQ ...................................... 4-63

Generate ALU Status Only: NONE ....................................... 4-71

MAC Instructions ...................................................................... 4-73

Multiply ............................................................................... 4-74

Multiply With Cumulative Add ............................................. 4-78

Multiply With Cumulative Subtract ...................................... 4-82

Squaring ............................................................................... 4-86

MAC Clear ........................................................................... 4-90

MAC Transfer MR ................................................................ 4-92

Conditional MR Saturation ................................................... 4-94

vi ADSP-218x DSP Instruction Set Reference

CONTENTS

Shifter Instructions ..................................................................... 4-96

Arithmetic Shift .................................................................... 4-97

Logical Shift ........................................................................ 4-100

Normalize ........................................................................... 4-103

Derive Exponent ................................................................. 4-106

Block Exponent Adjust ........................................................ 4-110

Arithmetic Shift Immediate ................................................. 4-112

Logical Shift Immediate ....................................................... 4-114

Move Instructions ..................................................................... 4-116

Load Register Immediate ..................................................... 4-119

Data Memory Read (Direct Address) .................................... 4-122

Data Memory Read (Indirect Address) ................................. 4-124

Program Memory Read (Indirect Address) ............................ 4-126

Data Memory Write (Direct Address) ................................... 4-128

Data Memory Write (Indirect Address) ................................ 4-130

Program Memory Write (Indirect Address) ........................... 4-133

IO Space Read/Write ........................................................... 4-135

Program Flow Instructions ........................................................ 4-137

JUMP ................................................................................. 4-138

CALL .................................................................................. 4-140

JUMP or CALL on Flag In Pin ............................................ 4-142

Modify Flag Out Pin ........................................................... 4-144

RTS (Return from Subroutine) ............................................ 4-146

ADSP-218x DSP Instruction Set Reference vii

CONTENTS

RTI (Return from Interrupt) ............................................... 4-148

Do Until ............................................................................. 4-150

Idle ..................................................................................... 4-153

MISC Instructions .................................................................... 4-155

Stack Control ...................................................................... 4-156

TOPPCSTACK .................................................................. 4-159

Mode Control ..................................................................... 4-162

Interrupt Enable and Disable ............................................... 4-165

Program Memory Overlay Register Update .......................... 4-166

Data Memory Overlay Register Update ................................ 4-169

Modify Address Register ...................................................... 4-172

No Operation ..................................................................... 4-174

Multifunction Instructions ........................................................ 4-175

Computation With Memory Read ....................................... 4-176

Computation With Register-to-Register Move ..................... 4-182

Computation With Memory Write ...................................... 4-187

Data and Program Memory Read ......................................... 4-192

ALU/MAC With Data and Program Memory Read .............. 4-194

viii ADSP-218x DSP Instruction Set Reference

CONTENTS

INSTRUCTION CODING

Opcode Definitions ..................................................................... A-2

Opcode Mnemonics ..................................................................... A-9

AMF ALU / MAC Function Codes ......................................... A-9

BO ....................................................................................... A-10

CC ....................................................................................... A-10

COND Status Condition Codes ........................................... A-11

CP Counter Stack Pop Codes ................................................ A-11

D Direction Codes ............................................................... A-12

DD Double Data Fetch Data Memory

Destination Codes ............................................................. A-12

DREG Data Register Codes .................................................. A-12

DV Divisor Codes for Slow Idle Instruction (IDLE (n)) ........ A-14

FIC FI Condition Codes ...................................................... A-14

FO Control Codes for Flag Output Pins

(FO, FL0, FL1, FL2) ......................................................... A-14

G Data Address Generator Codes .......................................... A-15

I Index Register Codes .......................................................... A-15

LP Loop Stack Pop Codes .................................................... A-15

M Modify Register Codes ..................................................... A-16

PD Dual Data Fetch Program Memory

Destination Codes ............................................................. A-16

PP PC Stack Pop Codes ........................................................ A-16

REG Register Codes ............................................................. A-17

S Jump/Call Codes ............................................................... A-18

ADSP-218x DSP Instruction Set Reference ix

CONTENTS

SF Shifter Function Codes .................................................... A-18

SPP Status Stack Push/Pop Codes .......................................... A-19

T Return Type Codes ............................................................ A-19

TERM Termination Codes for DO UNTIL ........................... A-20

X X Operand Codes .............................................................. A-21

Y Y Operand Codes .............................................................. A-21

YY ........................................................................................ A-21

Z ALU/MAC Result Register Codes ...................................... A-22

YY, CC, BO ALU / MAC Constant Codes (Type 9) ............... A-22

INDEX

x ADSP-218x DSP Instruction Set Reference

1 INTRODUCTION

The ADSP-218x DSP Instruction Set Reference provides assembly syntax information for the ADSP-218x Digital Signal Processor (DSP). The syntax descriptions for instructions that execute within the DSP’s processor core include processing elements, program sequencer, and data address generators. For architecture and design information on the DSP, see the ADSP-218x DSP Hardware Reference.

Audience

DSP system designers and programmers who are familiar with signal processing concepts are the primary audience for this manual. This manual assumes that the audience has a working knowledge of microcomputer technology and DSP-related mathematics.

DSP system designers and programmers who are unfamiliar with signal processing can use this manual, but should supplement this manual with other texts, describing DSP techniques.

All readers, particularly programmers, should refer to the DSP’s development tools documentation for software development information. For additional suggested reading, see the section “Additional Product Infor-

mation” on page 1-7.

ADSP-218x DSP Instruction Set Reference 1-1

Contents Overview

The Instruction Set Reference is a four-chapter book that describes the instructions syntax for the ADSP-218x DSPs.

Chapter 1, “Introduction”, provides introductory information including contacts at Analog Devices, an overview of the development tools, related documentation and conventions.

Chapter 2, “Programming Model”, describes the computational units of the ADSP-218x DSPs and provides a programming example with discussion.

Chapter 3, “Software Examples”, describes the process to create executable programs for the ADSP-218x DSPs. It provides several software examples that can be used to create programs.

Chapter 4, “Instruction Set”, presents information organized by the type of instruction. Instruction types relate to the machine language opcode for the instruction. On this DSP, the opcodes categorize the instructions by the portions of the DSP architecture that execute the instructions.

Appendix A, “Instruction Coding”, provides a summary of the complete instruction set of the ADSP-218x DSPs with opcode descriptions.

Each reference page for an instruction shows the syntax of the instruction, describes its function, gives one or two assembly-language examples, and identifies fields of its opcode. The instructions are also referred to by type, ranging from 1 to 31. These types correspond to the opcodes that ADSP-218x DSPs recognize, but are for reference only and have no bearing on programming.

Some instructions have more than one syntactical form; for example, instruction “Multiply” on page 4-73 has many distinct forms.

1-2 ADSP-218x DSP Instruction Set Reference

Introduction

Many instructions can be conditional. These instructions are prefaced by

IF cond; for example:

IF EQ MR = MX0 * MY0 (SS);

In a conditional instruction, the execution of the entire instruction is based on the condition.

The following instructions groups are available for ADSP-218x DSPs:

• “Quick List Of Instructions” on page 4-2—This section provides a a quick reference to all instructions.

• “ALU Instructions” on page 4-31—These instruction specify operations that occur in the DSP’s ALU.

• “MAC Instructions” on page 4-72—These instructions specify operations that occur in the DSP’s Multiply–Accumulator.

• “Shifter Instructions” on page 4-94—These instructions specify operations that occur in the DSP’s Shifter.

• “Move Instructions” on page 4-113—These instructions specify memory and register access operations.

• “Program Flow Instructions” on page 4-133—These instructions specify program sequencer operations.

• “MISC Instructions” on page 4-151—These instructions specify memory access operations.

• “Multifunction Instructions” on page 4-171—These instructions specify parallel, single-cycle operations.

Appendix A, “Instruction Coding”, lists the instruction encoding fields by type number and defines opcode mnemonics as listed alphabetically.

ADSP-218x DSP Instruction Set Reference 1-3

Development Tools

The ADSP-218x DSPs are supported by VisualDSP++®, an easy-to-use programming environment, comprised of a VisualDSP++ Integrated Development and Debugging Environment (IDDE). VisualDSP++ lets you manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities.

Flexible Project Management. VisualDSP++ IDDE provides flexible project management for the development of DSP applications. VisualDSP++ includes access to all the activities necessary to create and debug DSP projects. You can create or modify source files or view listing or map files with the IDDE Editor. This powerful Editor is part of VisualDSP++ and includes multiple language syntax highlighting, OLE drag and drop, bookmarks, and standard editing operations such as undo/redo, find/replace, copy/paste/cut, and goto.

Also, VisualDSP++ includes access to the C Compiler, C Runtime Library, Assembler, Linker, Loader, Simulator, and Splitter tools You specify options for these tools through property dialog boxes. Tool dialog boxes are easy to use, and make configuring, changing, and managing your projects simple. These options control how the tools process inputs and generate outputs, and have a one-to-one correspondence to the tools’ command line switches. You can define these options once, or modify them to meet changing development needs. You can also access the tools from the operating system command line if you choose.

Greatly Reduced Debugging Time. The Debugger has an easy-to-use, common interface for all processor simulators and emulators available through Analog Devices and third parties or custom developments. The Debugger has many features that greatly reduce debugging time. You can view C source interspersed with the resulting Assembly code. You can profile execution of a range of instructions in a program; set simulated watch

1-4 ADSP-218x DSP Instruction Set Reference

Introduction

points on hardware and software registers, program and data memory; and trace instruction execution and memory accesses. These features enable you to correct coding errors, identify bottlenecks, and examine DSP performance. You can use the custom register option to select any combination of registers to view in a single window. The Debugger can also generate inputs, outputs, and interrupts so you can simulate real world application conditions.

Software Development Tools. The Software Development Tools, which support the ADSP-218x DSPs, allow you to develop applications that take full advantage of the DSP architecture, including shared memory and memory overlays. Software Development tools include C Compiler, C Runtime Library, DSP and Math Libraries, Assembler, Linker, Loader, Simulator, and Splitter.

C Compiler and Assembler. The C Compiler generates efficient code that is optimized for both code density and execution time. The C Compiler allows you to include Assembly language statements inline. Because of this, you can program in C and still use Assembly for time-critical loops. You can also use pretested Math, DSP, and C Runtime Library routines to help shorten your time to market. The ADSP-218x Assembly language is based on an algebraic syntax that is easy to learn, program, and debug. The add instruction, for example, is written in the same manner as the actual equation using registers for variables (for example, AR = AX0 +

AY0;).

Linker and Loader. The Linker provides flexible system definition through Linker Description Files (

.LDF). In a single .LDF file, you can

define different types of executables for a single or multiprocessor system. The Linker resolves symbols over multiple executables, maximizes memory use, and easily shares common code among multiple processors. The Loader supports creation of a 16-bit host port and 8-bit PROM boot images. Along with the Linker, the Loader allows a variety of system configurations with smaller code and faster boot time.

ADSP-218x DSP Instruction Set Reference 1-5

Development Tools

Simulator. The Simulator is a cycle-accurate, instruction-level simulator that allows you to simulate your application in real time.

Emulator. The EZ-ICE® serial emulator system provides state-of-the-art emulation for the ADSP-218x DSPs using a controlled environment for observing, debugging, and testing activities in a target system. The key features of the ADSP-218x EZ-ICE include a shielded enclosure with the reset switch, a high speed RS-232 serial port interface, and support for

2.5, 3.3 and 5.0V DSPs. The EZ-ICE connects directly to the target processor via the emulation interface port. It’s ease of use, full speed emulation, and shield board ensures that your design process runs smoothly.

3rd Party Extensible. The VisualDSP++ environment enables third party companies to add value using Analog Devices’ published set of Application Programming Interfaces (API). Third party products including runtime operating systems, emulators, high-level language compilers, multiprocessor hardware can interface seamlessly with VisualDSP++ thereby simplifying the tools integration task. VisualDSP++ follows the COM API format. Two API tools, Target Wizard and API Tester, are also available for use with the API set. These tools help speed the time-to-market for vendor products. Target Wizard builds the programming shell based on API features the vendor requires. The API tester exercises the individual features independently of VisualDSP++. Third parties can use a subset of these APIs that meets their application needs. The interfaces are fully supported and backward compatible.

Further details and ordering information are available in the VisualDSP++ Development Tools data sheet. This data sheet can be requested from any Analog Devices sales office or distributor.

1-6 ADSP-218x DSP Instruction Set Reference

Introduction

Additional Product Information

Analog Devices can be found on the internet at http://www.analog.com. Our Web pages provide information about the company and products, including access to technical information and documentation, product overviews, and product announcements.

You may obtain additional information about Analog Devices and its products in any of the following ways:

Visit our World Wide Web site at www.analog.com

• FAX questions or requests for information to 1(781)461-3010.

• Access the division’s File Transfer Protocol (FTP) site at ftp

ftp.analog.com or ftp 137.71.23.21 or ftp://ftp.analog.com.

For Technical or Customer Support

You can reach our Customer Support group in the following ways:

• E-mail questions to:

dsp.support@analog.com, dsptools.support@analog.com or dsp.europe@analog.com (European customer support)

• Contact your local ADI sales office or an authorized ADI distributor

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

ADSP-218x DSP Instruction Set Reference 1-7

What’s New in This Manual

This edition of the ADSP-218x DSP Instruction Set Reference is formatted for easy reading and conversion to online help. Some technical information is also updated or corrected.

Conventions

Throughout this manual there are tables summarizing the syntax of the instruction groups. Table 1-1 identifies the notation conventions that apply to all chapters. Note that additional conventions, which apply only to specific chapters, may appear throughout this manual.

1-8 ADSP-218x DSP Instruction Set Reference

Introduction

Table 1-1. Instruction Set Notation

Notation Meaning

UPPERCASE Explicit syntax—assembler keyword. The assembler is case-

insensitive.

; A semicolon terminates an instruction line.

, A comma separates multiple, parallel instructions in the same

instruction line.

// single line comment /* multi line comment */

operands Some instruction operands are shown in lowercase letters. These

<exp> Denotes exponent (shift value) in Shift Immediate instructions;

<data> Denotes an immediate data value.

<addr> Denotes an immediate address value to be encoded in the instruc-

<reg> Refers to any accessible register; see Table 4-7 “Processor Registers:

[brackets] Refers to optional instruction extensions

<dreg> Refers to any data register; see Table 4-7 “Processor Registers: reg

0x Denotes number in hexadecimal format (

h# Denotes number in hexadecimal format (h#FFFF).

b# Denotes number in binary format (b#0001000100010001).

// or /* */ indicate comments or remarks that explain program code, but that the assembler ignores. For more details, see the Visu- alDSP++ Assembler Manual for ADSP-218x DSPs.

operands may take different values in assembly code. For example, the operand

must be an 8-bit signed integer constant.

tion. The <addr> may be either an immediate value (a constant) or a program label.

reg and dreg” on page 4-22.

and dreg” on page 4-22.

yop may be one of several registers: AY0, AY1, or AF.

0xFFFF).

ADSP-218x DSP Instruction Set Reference 1-9

Conventions

Table 1-1. Instruction Set Notation (Cont’d)

Notation Meaning

L [

Immediate values such as <exp>, <data>, or <addr> may be a constant in decimal, hexadecimal, octal or binary format. The default format is decimal.

A note, providing information of special interest or identifying a related topic. In the online version of this book, the word Note appears instead of this symbol.

A caution, providing information about critical design or programming issues that influence operation of a product. In the online version of this book, the word Caution appears instead of this symbol.

1-10 ADSP-218x DSP Instruction Set Reference

2 PROGRAMMING MODEL

This chapter provides an overview of ADSP-218x registers and their operations used in processor programming.

This chapter contains:

• “Overview” on page 2-1

• “Program Example” on page 2-10

• “Hardware Overlays and Software Issues” on page 2-16

Overview

From a programming standpoint, the ADSP-218x DSPs consist of three computational units (ALU, MAC and Shifter), two data address generators, and a program sequencer, plus on-chip peripherals and memory that vary with each processor. Almost all operations using these architectural components require one or more registers to store data, to keep track of values such as pointers, or to specify operating modes.

Internal registers hold data, addresses, control information or status information. For example, DAG2 pointer (address); ASTAT contains status flags from arithmetic operations; fields in the wait state register control the number of wait states for different zones of external memory.

AX0 stores an ALU operand (data); I4 stores a

ADSP-218x DSP Instruction Set Reference 2-1

Overview

There are two types of accesses for registers. The first type of access is made to dedicated registers such as MX0 and IMASK. These registers can be read and written explicitly in assembly language. For example,

MX0=1234; IMASK=0xF;

The second type of access is made to memory-mapped registers such as the system control register, wait state control register, timer registers and SPORT registers. These registers are accessed by reading and writing the corresponding data memory locations.

For example, the following code clears the Wait State Control Register, which is mapped to data memory location 0x3FFE:

AX0=0; DM(0x3FFE)=AX0;

In this example, AX0 is used to hold the constant 0 because there is no instruction to write an immediate data value to memory using an immediate address.

The ADSP-218x registers are shown in Figure 2-1. The registers are grouped by function: data address generators (DAGs), program sequencer, computational units (ALU, MAC, and shifter), bus exchange (PX), memory interface, timer, SPORTs, host interface, and DMA interface.

Data Address Generators

DAG1 and DAG2 each have twelve 14-bit registers: four index (I) registers for storing pointers, four modify ( and four length (

L) registers for implementing circular buffers. DAG1

addresses data memory only and has the capability of bit-reversing its outputs. DAG2 addresses both program and data memory and can provide addresses for indirect branching (jumps and calls) as well as for accessing data.

M) registers for updating pointers

2-2 ADSP-218x DSP Instruction Set Reference

Processor Core

DATA ADDRESS GENERATORS

DAG1 DAG2 (DM addressing only) (DM and PM addressing)

Bit-reverse capability Indirect branch capability

PC STACK 16 X 14

710

MSTAT*IMASK*

MX0 MX 1 MY1MY

81616

BUS EXCHANGE

I4 I5I6L5

SSTA T

ASTAT

L6 L7

1414

MR0MR1MR2 MF

I1 I2 I3

14 1414

LOOP

STACK

4X18

OWRCNTR

CNT R

COUNT STACK 4X

14 * Status Stack Depth = 12 mem ory locations, Width = 25 bits

AX0 AX1 AY1AY0

SHIFTER

SI SE SB

PROGRAM SEQUENCER

ICNTL

IFC*

STATUS STACK*

ALU MAC

AFAR

SR0SR1

Programming Model

TIMER

0x3FFD

M4L4 M5 M6 M7I7

TPERIOD

0x3FFC

TCOUNT

TSCALE

0x3FFB

SPORT 0

RX0 TX0

Multichannel enables

0x3FFA

RX 3116

RX 15-0

0x3FF9

TX 31-16

0x3FF8

TX 15-

0x3FF7

0 SPORT0 Control

0x3FF

Control

0x3FF

SCLKDIV

RFSDIV

0x3FF 4

0x3FF

Autobuffer

SPORT 1

RX1 TX1

SPORT1Control

0x3FF2

Control

0x3FF1

SCLKDIV

RFSDIV

0x3FF0

Autobuffer

0x3FEF

MEMORY INTERFACE

System Control

0x3FFF

0x3FFE

States

DMOVLAY

PROGRAMMABLE FLAGS

IDMA Registers IDMA Control

0x3FE0

Programmable Flag Registers

PFTYPE

0x3FE6 0x3FE5 PFDATA

PMOVLAY

IDMA PORT

BDMA PORT

0x3FE 4

0x3FE3

0x3FE2

0x3FE1

BDMA Registers

BWCOUNT

BDMA C ontrol

BEAD

BIAD

Figure 2-1. ADSP-218x DSP Registers

ADSP-218x DSP Instruction Set Reference 2-3

Overview

The following example is an indirect data memory read from the location pointed to by I0. Once the read is complete, I0 is updated by M0.

AX0=DM(I0,M0);

The following example is an indirect program memory data write to the address pointed to by I4 with a post modify by M5:

PM(I4,M5)=MR1;

The following example is an example of an indirect jump:

JUMP (I4);

Always Initialize L Registers

The ADSP-218x processors allow two addressing modes for data memory accesses: direct and register indirect. Indirect addressing is accomplished by loading an address into an I (index) register and specifying one of the available M (modify) registers.

The L registers are provided to facilitate wraparound addressing of circular data buffers. A circular buffer is only implemented when an L register is set to a non-zero value.

[

For linear(that is, non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. Do not assume that the ignored; the I, M, and L registers contain random values following processor reset. Your program must initialize the L registers corresponding to any

L registers are automatically initialized or may be

I registers it uses.

Program Sequencer

Registers associated with the program sequencer control subroutines, loops, and interrupts. They also indicate status and select modes of operation.

2-4 ADSP-218x DSP Instruction Set Reference

Programming Model

Interrupts

The ICNTL register controls interrupt nesting and external interrupt sensitivity. The IFC register which is 16 bits wide lets you force and clear interrupts in software. The IMASK register which is 10 bits wide masks (disables) individual interrupts. ADSP-218x processors support twelve interrupts, two of which (reset, powerdown) are non-maskable.

The ADSP-2181 DSP supports a global interrupt enable instruction (ENA

INTS) and interrupt disable instruction (DIS INTS). Executing the disable

interrupt instruction causes all interrupts to be masked without changing the contents of the IMASK register. Disabling interrupts does not affect serial port autobuffering, which operate normally whether or not interrupts are enabled. The disable interrupt instruction masks all user interrupts including the powerdown interrupt. The interrupt enable instruction allows all unmasked interrupts to be serviced again.

Loop Counts

The CNTR register stores the count value for the currently executing loop. The count stack allows the nesting of count-based loops to four levels. A write to CNTR pushes the current value onto the count stack before writing the new value. The following example pushes the current value of CNTR on the count stack and then loads CNTR with 10.

CNTR=10;

OWRCNTR

for the current loop without pushing CNTR on the count stack.

is a special syntax with which you can overwrite the count value

OWRCNTR cannot be read (for example, used as a source register), and

must not be written in the last instruction of a

DO UNTIL loop.

ADSP-218x DSP Instruction Set Reference 2-5

Overview

Status and Mode Bits

The stack status (SSTAT) register contains full and empty flags for stacks. The arithmetic status (ASTAT) register contains status flags for the computational units. The mode status (MSTAT) register contains control bits for various options. MSTAT contains 4 bits that control alternate register selection for the computational units, bit-reverse mode for DAG1, and overflow latch and saturation modes for the ALU. MSTAT also has 3 bits to control the MAC result placement, timer enable, and Go mode enable.

Use the Mode Control instruction (ENA or DIS) to conveniently enable or disable processor modes.

Stacks

The program sequencer contains four stacks that allow loop, subroutine and interrupt nesting.

The PC stack is 14 bits wide and 16 locations deep. It stores return addresses for subroutines and interrupt service routines, and top-of-loop addresses for loops. PC stack handling is automatic for subroutine calls and interrupt handling. In addition, the PC stack can be manually pushed or popped using the PC Stack Control instructions TOPPCSTACK=reg and

reg=TOPPCSTACK.

The loop stack is 18 bits wide, 14 bits for the end-of-loop address and 4 bits for the termination condition code. The loop stack is four locations deep. It is automatically pushed during the execution of a

DO UNTIL

instruction. It is popped automatically during a loop exit if the loop was nested. The loop stack may be manually popped with the POP LOOP instruction.

The status stack, which is automatically pushed when the processor services an interrupt, accommodates the interrupt mask (IMASK), mode status (

MSTAT) and arithmetic status (ASTAT) registers. The depth and width of

the status stack varies with each processor, since each of the processors has

2-6 ADSP-218x DSP Instruction Set Reference

Programming Model

a different numbers of interrupts. The status stack is automatically popped when the return from interrupt (RTI) instruction is executed. The status stack can be pushed and popped manually with the PUSH STS and POP STS instructions.

The count stack is 14 bits wide and holds counter (CNTR) values for nested counter-based loops. This stack is pushed automatically with the current

CNTR value when there is a write to CNTR. The counter stack may be manu-

ally popped with the POP CNTR instruction.

Computational Units

The registers in the computational units store data. The ALU and MAC require two inputs for most operations. The AX0, AX1, MX0, and MX1 registers store X inputs, and the AY0, AY1, MY0, and MY1 registers store Y inputs.

The AR and AF registers store ALU results; AF can be fed back to the ALU Y input, whereas AR can provide the X input of any computational unit. Likewise, the MR0, MR1, MR2, and MF register store MAC results and can be fed back for other computations. The 16-bit MR0 and MR1 registers together with the 8-bit MR2 register can store a 40-bit multiply/accumulate result.

The shifter can receive input from the ALU or MAC, from its own result registers, or from a dedicated shifter input (SI) register. It can store a 32-bit result in the

SR0 and SR1 registers. The SB register stores the block

exponent for block floating-point operations. The SE register holds the shift value for normalize and denormalize operations.

Registers in the computational units have secondary registers, shown in

Figure 2-1 on page 2-3 as second set of registers behind the first set. Sec-

ondary registers are useful for single-cycle context switches. The selection of these secondary registers is controlled by a bit in the

MSTAT register; the

bit is set and cleared by these instructions:

ENA SEC_REG; /*select secondary registers*/ DIS SEC_REG; /*select primary registers*/

ADSP-218x DSP Instruction Set Reference 2-7

Overview

Bus Exchange

The PX register is an 8-bit register that allows data transfers between the 16-bit DMD bus and the 24-bit PMD bus. In a transfer between program memory and a 16-bit register, PX provides or receives the lower eight bits implicitly.

Timer

The TPERIOD, TCOUNT, and TSCALE hold the timer period, count, and scale factor values, respectively. These registers are memory-mapped at locations 0x3FFD, 0x3FFC, and 0x3FFB respectively.

Serial Ports

SPORT0 and SPORT1 each have receive (RX), transmit (TX) and control registers. The control registers are memory-mapped registers at locations

0x3FEF through 0x3FFA in data memory. SPORT0 also has registers for

controlling its multichannel functions. Each SPORT control register contains bits that control frame synchronization, companding, word length and, in SPORT0, multichannel options. The SCLKDIV register for each SPORT determines the frequency of the internally generated serial clock, and the RFSDIV register determines the frequency of the internally generated receive frame sync signal for each SPORT. The autobuffer registers control autobuffering in each SPORT.

Programming a SPORT consists of writing to its control register and, depending on the modes selected, writing to its

SCLKDIV and/or RFSDIV

registers as well. The following example code may be used to program SPORT0 for 8-bit µ-law companding with normal framing and an internally generated serial clock. RFSDIV is set to 255 for 256 SCLK cycles between RFS assertions. SCLKDIV is set to 2, resulting in an SCLK frequency that is 1/6 of the

CLKIN frequency.

2-8 ADSP-218x DSP Instruction Set Reference

Programming Model

SI=0xB27; DM(0X3FF6)=SI; /*SPORT0 control register*/ SI=2; DM(0x3FF5)=SI; /*SCLKDIV = 2*/ SI=255; DM(0x3FF4)=SI; /*RFSDIV = 255*/

Memory Interface and SPORT Enables

The system control register, memory-mapped at DM(0x3fff), contains SPORT0 and SPORT1 enable bits (bits 12 and 11 respectively) as well as the SPORT1 configuration selection bit (bit 10). On all ADSP-218x processors, the system control register also contains fields for external program memory wait states. For the following processors, the system control register contains the disable BMS bit, which allows the external signal BMS to be disabled during byte memory accesses.

This feature can be used, for example, to allow the DSP to boot from an EPROM and then access a Flash memory, or other byte-wide device, at runtime via the CMS signal.

ADSP-2184 ADSP-2184L ADSP-2185M ADSP-2184N

ADSP-2186 ADSP-2185L ADSP-2186M ADSP-2185N

ADSP-2186L ADSP-2188M ADSP-2186N

ADSP-2187L ADSP-2189 M ADSP-2187N

ADSP-2188N

ADSP-2189 N

The wait state control register, memory-mapped at DM(

0x3ffe), contains

fields that specify the number of wait states for external data memory, and four banks of external I/O memory space.

ADSP-218x DSP Instruction Set Reference 2-9

Program Example

On the following processors, bit 15 of the register, the wait state mode select bit, determines whether the assigned wait state value operates in a “1x” or “2x+1” mode:

ADSP-2185M ADSP-2185N

ADSP-2186M ADSP-2186N

ADSP-2188M ADSP-2187N

ADSP-2189M ADSP-2188N

ADSP-2189N

Other memory-mapped registers control the IDMA port and byte memory DMA (BDMA) port for booting and runtime operations. These registers can be used in many ways that includes selecting the byte memory page, operating in data packing mode, or forcing the boot from software.

Program Example

Listing 2-1 presents an example of an FIR filter program written for the

ADSP-2181 DSP followed by a discussion of each part of the program. The program can also be executed on any other ADSP-218x processor, with minor modifications. This FIR filter program demonstrates much of the conceptual power of the ADSP-218x architecture and instruction set.

Listing 2-1. Include File, Constants Initialization

/*ADSP-2181 FIR Filter Routine

-serial port 0 used for I/O

-internally generated serial clock

-40.000 MHz processor clock rate is divided to generate a

1.5385 MHz serial clock

-serial clock divided to 8 kHz frame sampling rate*/

2-10 ADSP-218x DSP Instruction Set Reference

+ 258 hidden pages

ANALOG DEVICES ADSP-218x Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

INTRODUCTION

PROGRAMMING MODEL

SOFTWARE EXAMPLES

INSTRUCTION SET

INSTRUCTION CODING

INDEX

1 INTRODUCTION

Audience

Contents Overview

Development Tools

Additional Product Information

For Technical or Customer Support

What’s New in This Manual

Related Documents

Conventions

2 PROGRAMMING MODEL

Overview

Data Address Generators

Always Initialize L Registers

Program Sequencer

Interrupts

Loop Counts

Status and Mode Bits

Stacks

Computational Units

Bus Exchange

Timer

Serial Ports

Memory Interface and SPORT Enables

Program Example