Datasheet ADSP-218x Datasheet (ANALOG DEVICES)

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ADSP-218x DSP

Instruction Set Reference

Revision 2.0, November 2004

Part Number

82-002000-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

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Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

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The Analog Devices logo, EZ-ICE, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

INTRODUCTION

Audience ...................................................................................... 1-1

Contents Overview ....................................................................... 1-2

Development Tools ....................................................................... 1-4

Additional Product Information .................................................... 1-7

For Technical or Customer Support ............................................... 1-7

What’s New in This Manual .......................................................... 1-8

Related Documents ....................................................................... 1-8

Conventions ................................................................................. 1-8

PROGRAMMING MODEL

Overview ...................................................................................... 2-1

Data Address Generators .......................................................... 2-2

Always Initialize L Registers ................................................ 2-4

Program Sequencer .................................................................. 2-4

Interrupts ........................................................................... 2-5

Loop Counts ....................................................................... 2-5

Status and Mode Bits .......................................................... 2-6

Stacks ................................................................................. 2-6

ADSP-218x DSP Instruction Set Reference iii

CONTENTS

Computational Units .............................................................. 2-7

Bus Exchange .......................................................................... 2-8

Timer ..................................................................................... 2-8

Serial Ports .............................................................................. 2-8

Memory Interface and SPORT Enables ................................... 2-9

Program Example ....................................................................... 2-10

Example Program: Setup Routine Discussion ......................... 2-13

Example Program: Interrupt Routine Discussion .................... 2-15

Hardware Overlays and Software Issues ....................................... 2-16

Libraries and Overlays ........................................................... 2-17

Interrupts and Overlays ......................................................... 2-17

Loop Hardware and Overlays ................................................ 2-19

SOFTWARE EXAMPLES

Overview ...................................................................................... 3-1

System Development Process ....................................................... 3-3

Single-Precision Fir Transversal Filter ............................................ 3-5

Cascaded Biquad IIR Filter ........................................................... 3-7

Sine Approximation ...................................................................... 3-9

Single-Precision Matrix Multiply ................................................. 3-11

Radix-2 Decimation-in-Time FFT .............................................. 3-13

Main Module ........................................................................ 3-14

DIT FFT Subroutine ............................................................ 3-16

Bit-Reverse Subroutine .......................................................... 3-21

Block Floating-Point Scaling Subroutine ................................ 3-22

iv ADSP-218x DSP Instruction Set Reference

CONTENTS

INSTRUCTION SET

Quick List Of Instructions ............................................................ 4-2

Instruction Set Overview ............................................................... 4-5

Multifunction Instructions ............................................................ 4-7

ALU/MAC With Data and Program Memory Read .................. 4-7

Data and Program Memory Read ............................................. 4-9

Computation With Memory Read ........................................... 4-9

Computation With Memory Write ........................................ 4-10

Computation With Data Register Move ................................. 4-10

ALU, MAC and Shifter Instructions ............................................ 4-14

ALU Group ........................................................................... 4-14

MAC Group .......................................................................... 4-16

Shifter Group ........................................................................ 4-18

MOVE: Read and Write Instructions ........................................... 4-20

Program Flow Control ................................................................ 4-22

Miscellaneous Instructions .......................................................... 4-25

Extra Cycle Conditions ............................................................... 4-27

Multiple Off-Chip Memory Accesses ...................................... 4-27

Wait States ............................................................................ 4-27

SPORT Autobuffering and DMA ........................................... 4-28

Instruction Set Syntax ................................................................. 4-28

Punctuation and Multifunction Instructions ........................... 4-28

Syntax Notation Example ...................................................... 4-29

Status Register Notation ........................................................ 4-30

ADSP-218x DSP Instruction Set Reference v

CONTENTS

ALU Instructions ........................................................................ 4-31

Add/Add With Carry ............................................................ 4-32

Subtract X-Y/Subtract X-Y With Borrow ............................... 4-35

Subtract Y-X/Subtract Y-X With Borrow ................................ 4-39

Bitwise Logic: AND, OR, XOR ............................................. 4-42

Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT ....... 4-45

Clear: PASS .......................................................................... 4-48

Negate .................................................................................. 4-52

NOT .................................................................................... 4-54

Absolute Value: ABS ............................................................. 4-56

Increment ............................................................................. 4-59

Decrement ............................................................................ 4-61

Divide Primitives: DIVS and DIVQ ...................................... 4-63

Generate ALU Status Only: NONE ....................................... 4-71

MAC Instructions ...................................................................... 4-73

Multiply ............................................................................... 4-74

Multiply With Cumulative Add ............................................. 4-78

Multiply With Cumulative Subtract ...................................... 4-82

Squaring ............................................................................... 4-86

MAC Clear ........................................................................... 4-90

MAC Transfer MR ................................................................ 4-92

Conditional MR Saturation ................................................... 4-94

vi ADSP-218x DSP Instruction Set Reference

CONTENTS

Shifter Instructions ..................................................................... 4-96

Arithmetic Shift .................................................................... 4-97

Logical Shift ........................................................................ 4-100

Normalize ........................................................................... 4-103

Derive Exponent ................................................................. 4-106

Block Exponent Adjust ........................................................ 4-110

Arithmetic Shift Immediate ................................................. 4-112

Logical Shift Immediate ....................................................... 4-114

Move Instructions ..................................................................... 4-116

Load Register Immediate ..................................................... 4-119

Data Memory Read (Direct Address) .................................... 4-122

Data Memory Read (Indirect Address) ................................. 4-124

Program Memory Read (Indirect Address) ............................ 4-126

Data Memory Write (Direct Address) ................................... 4-128

Data Memory Write (Indirect Address) ................................ 4-130

Program Memory Write (Indirect Address) ........................... 4-133

IO Space Read/Write ........................................................... 4-135

Program Flow Instructions ........................................................ 4-137

JUMP ................................................................................. 4-138

CALL .................................................................................. 4-140

JUMP or CALL on Flag In Pin ............................................ 4-142

Modify Flag Out Pin ........................................................... 4-144

RTS (Return from Subroutine) ............................................ 4-146

ADSP-218x DSP Instruction Set Reference vii

CONTENTS

RTI (Return from Interrupt) ............................................... 4-148

Do Until ............................................................................. 4-150

Idle ..................................................................................... 4-153

MISC Instructions .................................................................... 4-155

Stack Control ...................................................................... 4-156

TOPPCSTACK .................................................................. 4-159

Mode Control ..................................................................... 4-162

Interrupt Enable and Disable ............................................... 4-165

Program Memory Overlay Register Update .......................... 4-166

Data Memory Overlay Register Update ................................ 4-169

Modify Address Register ...................................................... 4-172

No Operation ..................................................................... 4-174

Multifunction Instructions ........................................................ 4-175

Computation With Memory Read ....................................... 4-176

Computation With Register-to-Register Move ..................... 4-182

Computation With Memory Write ...................................... 4-187

Data and Program Memory Read ......................................... 4-192

ALU/MAC With Data and Program Memory Read .............. 4-194

viii ADSP-218x DSP Instruction Set Reference

CONTENTS

INSTRUCTION CODING

Opcode Definitions ..................................................................... A-2

Opcode Mnemonics ..................................................................... A-9

AMF ALU / MAC Function Codes ......................................... A-9

BO ....................................................................................... A-10

CC ....................................................................................... A-10

COND Status Condition Codes ........................................... A-11

CP Counter Stack Pop Codes ................................................ A-11

D Direction Codes ............................................................... A-12

DD Double Data Fetch Data Memory

Destination Codes ............................................................. A-12

DREG Data Register Codes .................................................. A-12

DV Divisor Codes for Slow Idle Instruction (IDLE (n)) ........ A-14

FIC FI Condition Codes ...................................................... A-14

FO Control Codes for Flag Output Pins

(FO, FL0, FL1, FL2) ......................................................... A-14

G Data Address Generator Codes .......................................... A-15

I Index Register Codes .......................................................... A-15

LP Loop Stack Pop Codes .................................................... A-15

M Modify Register Codes ..................................................... A-16

PD Dual Data Fetch Program Memory

Destination Codes ............................................................. A-16

PP PC Stack Pop Codes ........................................................ A-16

REG Register Codes ............................................................. A-17

S Jump/Call Codes ............................................................... A-18

ADSP-218x DSP Instruction Set Reference ix

CONTENTS

SF Shifter Function Codes .................................................... A-18

SPP Status Stack Push/Pop Codes .......................................... A-19

T Return Type Codes ............................................................ A-19

TERM Termination Codes for DO UNTIL ........................... A-20

X X Operand Codes .............................................................. A-21

Y Y Operand Codes .............................................................. A-21

YY ........................................................................................ A-21

Z ALU/MAC Result Register Codes ...................................... A-22

YY, CC, BO ALU / MAC Constant Codes (Type 9) ............... A-22

INDEX

x ADSP-218x DSP Instruction Set Reference

1 INTRODUCTION

The ADSP-218x DSP Instruction Set Reference provides assembly syntax information for the ADSP-218x Digital Signal Processor (DSP). The syntax descriptions for instructions that execute within the DSP’s processor core include processing elements, program sequencer, and data address generators. For architecture and design information on the DSP, see the ADSP-218x DSP Hardware Reference.

Audience

DSP system designers and programmers who are familiar with signal processing concepts are the primary audience for this manual. This manual assumes that the audience has a working knowledge of microcomputer technology and DSP-related mathematics.

DSP system designers and programmers who are unfamiliar with signal processing can use this manual, but should supplement this manual with other texts, describing DSP techniques.

All readers, particularly programmers, should refer to the DSP’s development tools documentation for software development information. For additional suggested reading, see the section “Additional Product Infor-

mation” on page 1-7.

ADSP-218x DSP Instruction Set Reference 1-1

Contents Overview

The Instruction Set Reference is a four-chapter book that describes the instructions syntax for the ADSP-218x DSPs.

Chapter 1, “Introduction”, provides introductory information including contacts at Analog Devices, an overview of the development tools, related documentation and conventions.

Chapter 2, “Programming Model”, describes the computational units of the ADSP-218x DSPs and provides a programming example with discussion.

Chapter 3, “Software Examples”, describes the process to create executable programs for the ADSP-218x DSPs. It provides several software examples that can be used to create programs.

Chapter 4, “Instruction Set”, presents information organized by the type of instruction. Instruction types relate to the machine language opcode for the instruction. On this DSP, the opcodes categorize the instructions by the portions of the DSP architecture that execute the instructions.

Appendix A, “Instruction Coding”, provides a summary of the complete instruction set of the ADSP-218x DSPs with opcode descriptions.

Each reference page for an instruction shows the syntax of the instruction, describes its function, gives one or two assembly-language examples, and identifies fields of its opcode. The instructions are also referred to by type, ranging from 1 to 31. These types correspond to the opcodes that ADSP-218x DSPs recognize, but are for reference only and have no bearing on programming.

Some instructions have more than one syntactical form; for example, instruction “Multiply” on page 4-73 has many distinct forms.

1-2 ADSP-218x DSP Instruction Set Reference

Introduction

Many instructions can be conditional. These instructions are prefaced by

IF cond; for example:

IF EQ MR = MX0 * MY0 (SS);

In a conditional instruction, the execution of the entire instruction is based on the condition.

The following instructions groups are available for ADSP-218x DSPs:

• “Quick List Of Instructions” on page 4-2—This section provides a a quick reference to all instructions.

• “ALU Instructions” on page 4-31—These instruction specify operations that occur in the DSP’s ALU.

• “MAC Instructions” on page 4-72—These instructions specify operations that occur in the DSP’s Multiply–Accumulator.

• “Shifter Instructions” on page 4-94—These instructions specify operations that occur in the DSP’s Shifter.

• “Move Instructions” on page 4-113—These instructions specify memory and register access operations.

• “Program Flow Instructions” on page 4-133—These instructions specify program sequencer operations.

• “MISC Instructions” on page 4-151—These instructions specify memory access operations.

• “Multifunction Instructions” on page 4-171—These instructions specify parallel, single-cycle operations.

Appendix A, “Instruction Coding”, lists the instruction encoding fields by type number and defines opcode mnemonics as listed alphabetically.

ADSP-218x DSP Instruction Set Reference 1-3

Development Tools

The ADSP-218x DSPs are supported by VisualDSP++®, an easy-to-use programming environment, comprised of a VisualDSP++ Integrated Development and Debugging Environment (IDDE). VisualDSP++ lets you manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities.

Flexible Project Management. VisualDSP++ IDDE provides flexible project management for the development of DSP applications. VisualDSP++ includes access to all the activities necessary to create and debug DSP projects. You can create or modify source files or view listing or map files with the IDDE Editor. This powerful Editor is part of VisualDSP++ and includes multiple language syntax highlighting, OLE drag and drop, bookmarks, and standard editing operations such as undo/redo, find/replace, copy/paste/cut, and goto.

Also, VisualDSP++ includes access to the C Compiler, C Runtime Library, Assembler, Linker, Loader, Simulator, and Splitter tools You specify options for these tools through property dialog boxes. Tool dialog boxes are easy to use, and make configuring, changing, and managing your projects simple. These options control how the tools process inputs and generate outputs, and have a one-to-one correspondence to the tools’ command line switches. You can define these options once, or modify them to meet changing development needs. You can also access the tools from the operating system command line if you choose.

Greatly Reduced Debugging Time. The Debugger has an easy-to-use, common interface for all processor simulators and emulators available through Analog Devices and third parties or custom developments. The Debugger has many features that greatly reduce debugging time. You can view C source interspersed with the resulting Assembly code. You can profile execution of a range of instructions in a program; set simulated watch

1-4 ADSP-218x DSP Instruction Set Reference

Introduction

points on hardware and software registers, program and data memory; and trace instruction execution and memory accesses. These features enable you to correct coding errors, identify bottlenecks, and examine DSP performance. You can use the custom register option to select any combination of registers to view in a single window. The Debugger can also generate inputs, outputs, and interrupts so you can simulate real world application conditions.

Software Development Tools. The Software Development Tools, which support the ADSP-218x DSPs, allow you to develop applications that take full advantage of the DSP architecture, including shared memory and memory overlays. Software Development tools include C Compiler, C Runtime Library, DSP and Math Libraries, Assembler, Linker, Loader, Simulator, and Splitter.

C Compiler and Assembler. The C Compiler generates efficient code that is optimized for both code density and execution time. The C Compiler allows you to include Assembly language statements inline. Because of this, you can program in C and still use Assembly for time-critical loops. You can also use pretested Math, DSP, and C Runtime Library routines to help shorten your time to market. The ADSP-218x Assembly language is based on an algebraic syntax that is easy to learn, program, and debug. The add instruction, for example, is written in the same manner as the actual equation using registers for variables (for example, AR = AX0 +

AY0;).

Linker and Loader. The Linker provides flexible system definition through Linker Description Files (

.LDF). In a single .LDF file, you can

define different types of executables for a single or multiprocessor system. The Linker resolves symbols over multiple executables, maximizes memory use, and easily shares common code among multiple processors. The Loader supports creation of a 16-bit host port and 8-bit PROM boot images. Along with the Linker, the Loader allows a variety of system configurations with smaller code and faster boot time.

ADSP-218x DSP Instruction Set Reference 1-5

Development Tools

Simulator. The Simulator is a cycle-accurate, instruction-level simulator that allows you to simulate your application in real time.

Emulator. The EZ-ICE® serial emulator system provides state-of-the-art emulation for the ADSP-218x DSPs using a controlled environment for observing, debugging, and testing activities in a target system. The key features of the ADSP-218x EZ-ICE include a shielded enclosure with the reset switch, a high speed RS-232 serial port interface, and support for

2.5, 3.3 and 5.0V DSPs. The EZ-ICE connects directly to the target processor via the emulation interface port. It’s ease of use, full speed emulation, and shield board ensures that your design process runs smoothly.

3rd Party Extensible. The VisualDSP++ environment enables third party companies to add value using Analog Devices’ published set of Application Programming Interfaces (API). Third party products including runtime operating systems, emulators, high-level language compilers, multiprocessor hardware can interface seamlessly with VisualDSP++ thereby simplifying the tools integration task. VisualDSP++ follows the COM API format. Two API tools, Target Wizard and API Tester, are also available for use with the API set. These tools help speed the time-to-market for vendor products. Target Wizard builds the programming shell based on API features the vendor requires. The API tester exercises the individual features independently of VisualDSP++. Third parties can use a subset of these APIs that meets their application needs. The interfaces are fully supported and backward compatible.

Further details and ordering information are available in the VisualDSP++ Development Tools data sheet. This data sheet can be requested from any Analog Devices sales office or distributor.

1-6 ADSP-218x DSP Instruction Set Reference

Introduction

Additional Product Information

Analog Devices can be found on the internet at http://www.analog.com. Our Web pages provide information about the company and products, including access to technical information and documentation, product overviews, and product announcements.

You may obtain additional information about Analog Devices and its products in any of the following ways:

Visit our World Wide Web site at www.analog.com

• FAX questions or requests for information to 1(781)461-3010.

• Access the division’s File Transfer Protocol (FTP) site at ftp

ftp.analog.com or ftp 137.71.23.21 or ftp://ftp.analog.com.

For Technical or Customer Support

You can reach our Customer Support group in the following ways:

• E-mail questions to:

dsp.support@analog.com, dsptools.support@analog.com or dsp.europe@analog.com (European customer support)

• Contact your local ADI sales office or an authorized ADI distributor

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

ADSP-218x DSP Instruction Set Reference 1-7

What’s New in This Manual

This edition of the ADSP-218x DSP Instruction Set Reference is formatted for easy reading and conversion to online help. Some technical information is also updated or corrected.

Conventions

Throughout this manual there are tables summarizing the syntax of the instruction groups. Table 1-1 identifies the notation conventions that apply to all chapters. Note that additional conventions, which apply only to specific chapters, may appear throughout this manual.

1-8 ADSP-218x DSP Instruction Set Reference

Introduction

Table 1-1. Instruction Set Notation

Notation Meaning

UPPERCASE Explicit syntax—assembler keyword. The assembler is case-

insensitive.

; A semicolon terminates an instruction line.

, A comma separates multiple, parallel instructions in the same

instruction line.

// single line comment /* multi line comment */

operands Some instruction operands are shown in lowercase letters. These

<exp> Denotes exponent (shift value) in Shift Immediate instructions;

<data> Denotes an immediate data value.

<addr> Denotes an immediate address value to be encoded in the instruc-

<reg> Refers to any accessible register; see Table 4-7 “Processor Registers:

[brackets] Refers to optional instruction extensions

<dreg> Refers to any data register; see Table 4-7 “Processor Registers: reg

0x Denotes number in hexadecimal format (

h# Denotes number in hexadecimal format (h#FFFF).

b# Denotes number in binary format (b#0001000100010001).

// or /* */ indicate comments or remarks that explain program code, but that the assembler ignores. For more details, see the Visu- alDSP++ Assembler Manual for ADSP-218x DSPs.

operands may take different values in assembly code. For example, the operand

must be an 8-bit signed integer constant.

tion. The <addr> may be either an immediate value (a constant) or a program label.

reg and dreg” on page 4-22.

and dreg” on page 4-22.

yop may be one of several registers: AY0, AY1, or AF.

0xFFFF).

ADSP-218x DSP Instruction Set Reference 1-9

Conventions

Table 1-1. Instruction Set Notation (Cont’d)

Notation Meaning

L [

Immediate values such as <exp>, <data>, or <addr> may be a constant in decimal, hexadecimal, octal or binary format. The default format is decimal.

A note, providing information of special interest or identifying a related topic. In the online version of this book, the word Note appears instead of this symbol.

A caution, providing information about critical design or programming issues that influence operation of a product. In the online version of this book, the word Caution appears instead of this symbol.

1-10 ADSP-218x DSP Instruction Set Reference

2 PROGRAMMING MODEL

This chapter provides an overview of ADSP-218x registers and their operations used in processor programming.

This chapter contains:

• “Overview” on page 2-1

• “Program Example” on page 2-10

• “Hardware Overlays and Software Issues” on page 2-16

Overview

From a programming standpoint, the ADSP-218x DSPs consist of three computational units (ALU, MAC and Shifter), two data address generators, and a program sequencer, plus on-chip peripherals and memory that vary with each processor. Almost all operations using these architectural components require one or more registers to store data, to keep track of values such as pointers, or to specify operating modes.

Internal registers hold data, addresses, control information or status information. For example, DAG2 pointer (address); ASTAT contains status flags from arithmetic operations; fields in the wait state register control the number of wait states for different zones of external memory.

AX0 stores an ALU operand (data); I4 stores a

ADSP-218x DSP Instruction Set Reference 2-1

Overview

There are two types of accesses for registers. The first type of access is made to dedicated registers such as MX0 and IMASK. These registers can be read and written explicitly in assembly language. For example,

MX0=1234; IMASK=0xF;

The second type of access is made to memory-mapped registers such as the system control register, wait state control register, timer registers and SPORT registers. These registers are accessed by reading and writing the corresponding data memory locations.

For example, the following code clears the Wait State Control Register, which is mapped to data memory location 0x3FFE:

AX0=0; DM(0x3FFE)=AX0;

In this example, AX0 is used to hold the constant 0 because there is no instruction to write an immediate data value to memory using an immediate address.

The ADSP-218x registers are shown in Figure 2-1. The registers are grouped by function: data address generators (DAGs), program sequencer, computational units (ALU, MAC, and shifter), bus exchange (PX), memory interface, timer, SPORTs, host interface, and DMA interface.

Data Address Generators

DAG1 and DAG2 each have twelve 14-bit registers: four index (I) registers for storing pointers, four modify ( and four length (

L) registers for implementing circular buffers. DAG1

addresses data memory only and has the capability of bit-reversing its outputs. DAG2 addresses both program and data memory and can provide addresses for indirect branching (jumps and calls) as well as for accessing data.

M) registers for updating pointers

2-2 ADSP-218x DSP Instruction Set Reference

Processor Core

DATA ADDRESS GENERATORS

DAG1 DAG2 (DM addressing only) (DM and PM addressing)

Bit-reverse capability Indirect branch capability

PC STACK 16 X 14

710

MSTAT*IMASK*

MX0 MX 1 MY1MY

81616

BUS EXCHANGE

I4 I5I6L5

SSTA T

ASTAT

L6 L7

1414

MR0MR1MR2 MF

I1 I2 I3

14 1414

LOOP

STACK

4X18

OWRCNTR

CNT R

COUNT STACK 4X

14 * Status Stack Depth = 12 mem ory locations, Width = 25 bits

AX0 AX1 AY1AY0

SHIFTER

SI SE SB

PROGRAM SEQUENCER

ICNTL

IFC*

STATUS STACK*

ALU MAC

AFAR

SR0SR1

Programming Model

TIMER

0x3FFD

M4L4 M5 M6 M7I7

TPERIOD

0x3FFC

TCOUNT

TSCALE

0x3FFB

SPORT 0

RX0 TX0

Multichannel enables

0x3FFA

RX 3116

RX 15-0

0x3FF9

TX 31-16

0x3FF8

TX 15-

0x3FF7

0 SPORT0 Control

0x3FF

Control

0x3FF

SCLKDIV

RFSDIV

0x3FF 4

0x3FF

Autobuffer

SPORT 1

RX1 TX1

SPORT1Control

0x3FF2

Control

0x3FF1

SCLKDIV

RFSDIV

0x3FF0

Autobuffer

0x3FEF

MEMORY INTERFACE

System Control

0x3FFF

0x3FFE

States

DMOVLAY

PROGRAMMABLE FLAGS

IDMA Registers IDMA Control

0x3FE0

Programmable Flag Registers

PFTYPE

0x3FE6 0x3FE5 PFDATA

PMOVLAY

IDMA PORT

BDMA PORT

0x3FE 4

0x3FE3

0x3FE2

0x3FE1

BDMA Registers

BWCOUNT

BDMA C ontrol

BEAD

BIAD

Figure 2-1. ADSP-218x DSP Registers

ADSP-218x DSP Instruction Set Reference 2-3

Overview

The following example is an indirect data memory read from the location pointed to by I0. Once the read is complete, I0 is updated by M0.

AX0=DM(I0,M0);

The following example is an indirect program memory data write to the address pointed to by I4 with a post modify by M5:

PM(I4,M5)=MR1;

The following example is an example of an indirect jump:

JUMP (I4);

Always Initialize L Registers

The ADSP-218x processors allow two addressing modes for data memory accesses: direct and register indirect. Indirect addressing is accomplished by loading an address into an I (index) register and specifying one of the available M (modify) registers.

The L registers are provided to facilitate wraparound addressing of circular data buffers. A circular buffer is only implemented when an L register is set to a non-zero value.

[

For linear(that is, non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero. Do not assume that the ignored; the I, M, and L registers contain random values following processor reset. Your program must initialize the L registers corresponding to any

L registers are automatically initialized or may be

I registers it uses.

Program Sequencer

Registers associated with the program sequencer control subroutines, loops, and interrupts. They also indicate status and select modes of operation.

2-4 ADSP-218x DSP Instruction Set Reference

Programming Model

Interrupts

The ICNTL register controls interrupt nesting and external interrupt sensitivity. The IFC register which is 16 bits wide lets you force and clear interrupts in software. The IMASK register which is 10 bits wide masks (disables) individual interrupts. ADSP-218x processors support twelve interrupts, two of which (reset, powerdown) are non-maskable.

The ADSP-2181 DSP supports a global interrupt enable instruction (ENA

INTS) and interrupt disable instruction (DIS INTS). Executing the disable

interrupt instruction causes all interrupts to be masked without changing the contents of the IMASK register. Disabling interrupts does not affect serial port autobuffering, which operate normally whether or not interrupts are enabled. The disable interrupt instruction masks all user interrupts including the powerdown interrupt. The interrupt enable instruction allows all unmasked interrupts to be serviced again.

Loop Counts

The CNTR register stores the count value for the currently executing loop. The count stack allows the nesting of count-based loops to four levels. A write to CNTR pushes the current value onto the count stack before writing the new value. The following example pushes the current value of CNTR on the count stack and then loads CNTR with 10.

CNTR=10;

OWRCNTR

for the current loop without pushing CNTR on the count stack.

is a special syntax with which you can overwrite the count value

OWRCNTR cannot be read (for example, used as a source register), and

must not be written in the last instruction of a

DO UNTIL loop.

ADSP-218x DSP Instruction Set Reference 2-5

Overview

Status and Mode Bits

The stack status (SSTAT) register contains full and empty flags for stacks. The arithmetic status (ASTAT) register contains status flags for the computational units. The mode status (MSTAT) register contains control bits for various options. MSTAT contains 4 bits that control alternate register selection for the computational units, bit-reverse mode for DAG1, and overflow latch and saturation modes for the ALU. MSTAT also has 3 bits to control the MAC result placement, timer enable, and Go mode enable.

Use the Mode Control instruction (ENA or DIS) to conveniently enable or disable processor modes.

Stacks

The program sequencer contains four stacks that allow loop, subroutine and interrupt nesting.

The PC stack is 14 bits wide and 16 locations deep. It stores return addresses for subroutines and interrupt service routines, and top-of-loop addresses for loops. PC stack handling is automatic for subroutine calls and interrupt handling. In addition, the PC stack can be manually pushed or popped using the PC Stack Control instructions TOPPCSTACK=reg and

reg=TOPPCSTACK.

The loop stack is 18 bits wide, 14 bits for the end-of-loop address and 4 bits for the termination condition code. The loop stack is four locations deep. It is automatically pushed during the execution of a

DO UNTIL

instruction. It is popped automatically during a loop exit if the loop was nested. The loop stack may be manually popped with the POP LOOP instruction.

The status stack, which is automatically pushed when the processor services an interrupt, accommodates the interrupt mask (IMASK), mode status (

MSTAT) and arithmetic status (ASTAT) registers. The depth and width of

the status stack varies with each processor, since each of the processors has

2-6 ADSP-218x DSP Instruction Set Reference

Programming Model

a different numbers of interrupts. The status stack is automatically popped when the return from interrupt (RTI) instruction is executed. The status stack can be pushed and popped manually with the PUSH STS and POP STS instructions.

The count stack is 14 bits wide and holds counter (CNTR) values for nested counter-based loops. This stack is pushed automatically with the current

CNTR value when there is a write to CNTR. The counter stack may be manu-

ally popped with the POP CNTR instruction.

Computational Units

The registers in the computational units store data. The ALU and MAC require two inputs for most operations. The AX0, AX1, MX0, and MX1 registers store X inputs, and the AY0, AY1, MY0, and MY1 registers store Y inputs.

The AR and AF registers store ALU results; AF can be fed back to the ALU Y input, whereas AR can provide the X input of any computational unit. Likewise, the MR0, MR1, MR2, and MF register store MAC results and can be fed back for other computations. The 16-bit MR0 and MR1 registers together with the 8-bit MR2 register can store a 40-bit multiply/accumulate result.

The shifter can receive input from the ALU or MAC, from its own result registers, or from a dedicated shifter input (SI) register. It can store a 32-bit result in the

SR0 and SR1 registers. The SB register stores the block

exponent for block floating-point operations. The SE register holds the shift value for normalize and denormalize operations.

Registers in the computational units have secondary registers, shown in

Figure 2-1 on page 2-3 as second set of registers behind the first set. Sec-

ondary registers are useful for single-cycle context switches. The selection of these secondary registers is controlled by a bit in the

MSTAT register; the

bit is set and cleared by these instructions:

ENA SEC_REG; /*select secondary registers*/ DIS SEC_REG; /*select primary registers*/

ADSP-218x DSP Instruction Set Reference 2-7

Overview

Bus Exchange

The PX register is an 8-bit register that allows data transfers between the 16-bit DMD bus and the 24-bit PMD bus. In a transfer between program memory and a 16-bit register, PX provides or receives the lower eight bits implicitly.

Timer

The TPERIOD, TCOUNT, and TSCALE hold the timer period, count, and scale factor values, respectively. These registers are memory-mapped at locations 0x3FFD, 0x3FFC, and 0x3FFB respectively.

Serial Ports

SPORT0 and SPORT1 each have receive (RX), transmit (TX) and control registers. The control registers are memory-mapped registers at locations

0x3FEF through 0x3FFA in data memory. SPORT0 also has registers for

controlling its multichannel functions. Each SPORT control register contains bits that control frame synchronization, companding, word length and, in SPORT0, multichannel options. The SCLKDIV register for each SPORT determines the frequency of the internally generated serial clock, and the RFSDIV register determines the frequency of the internally generated receive frame sync signal for each SPORT. The autobuffer registers control autobuffering in each SPORT.

Programming a SPORT consists of writing to its control register and, depending on the modes selected, writing to its

SCLKDIV and/or RFSDIV

registers as well. The following example code may be used to program SPORT0 for 8-bit µ-law companding with normal framing and an internally generated serial clock. RFSDIV is set to 255 for 256 SCLK cycles between RFS assertions. SCLKDIV is set to 2, resulting in an SCLK frequency that is 1/6 of the

CLKIN frequency.

2-8 ADSP-218x DSP Instruction Set Reference

Programming Model

SI=0xB27; DM(0X3FF6)=SI; /*SPORT0 control register*/ SI=2; DM(0x3FF5)=SI; /*SCLKDIV = 2*/ SI=255; DM(0x3FF4)=SI; /*RFSDIV = 255*/

Memory Interface and SPORT Enables

The system control register, memory-mapped at DM(0x3fff), contains SPORT0 and SPORT1 enable bits (bits 12 and 11 respectively) as well as the SPORT1 configuration selection bit (bit 10). On all ADSP-218x processors, the system control register also contains fields for external program memory wait states. For the following processors, the system control register contains the disable BMS bit, which allows the external signal BMS to be disabled during byte memory accesses.

This feature can be used, for example, to allow the DSP to boot from an EPROM and then access a Flash memory, or other byte-wide device, at runtime via the CMS signal.

ADSP-2184 ADSP-2184L ADSP-2185M ADSP-2184N

ADSP-2186 ADSP-2185L ADSP-2186M ADSP-2185N

ADSP-2186L ADSP-2188M ADSP-2186N

ADSP-2187L ADSP-2189 M ADSP-2187N

ADSP-2188N

ADSP-2189 N

The wait state control register, memory-mapped at DM(

0x3ffe), contains

fields that specify the number of wait states for external data memory, and four banks of external I/O memory space.

ADSP-218x DSP Instruction Set Reference 2-9

Program Example

On the following processors, bit 15 of the register, the wait state mode select bit, determines whether the assigned wait state value operates in a “1x” or “2x+1” mode:

ADSP-2185M ADSP-2185N

ADSP-2186M ADSP-2186N

ADSP-2188M ADSP-2187N

ADSP-2189M ADSP-2188N

ADSP-2189N

Other memory-mapped registers control the IDMA port and byte memory DMA (BDMA) port for booting and runtime operations. These registers can be used in many ways that includes selecting the byte memory page, operating in data packing mode, or forcing the boot from software.

Program Example

Listing 2-1 presents an example of an FIR filter program written for the

ADSP-2181 DSP followed by a discussion of each part of the program. The program can also be executed on any other ADSP-218x processor, with minor modifications. This FIR filter program demonstrates much of the conceptual power of the ADSP-218x architecture and instruction set.

Listing 2-1. Include File, Constants Initialization

/*ADSP-2181 FIR Filter Routine

-serial port 0 used for I/O

-internally generated serial clock

-40.000 MHz processor clock rate is divided to generate a

1.5385 MHz serial clock

-serial clock divided to 8 kHz frame sampling rate*/

2-10 ADSP-218x DSP Instruction Set Reference

Programming Model

#include <def2181.h> See Notes: Section A #define taps 15 #define taps_less_one 14

.section/dmdm_data; .var/circdata_buffer[taps]; /* dm data buffer */

.section/pmpm_data; .var/circ/init24coefficient[taps] = "coeff.dat";

.section/pm Interrupts; start:

jump main; rti; rti; rti; /* 0x0000: ~Reset vector */ rti; rti; rti; rti; /* 0x0004: ~IRQ2 */ rti; rti; rti; rti; /* 0x0008: ~IRQL1 */ rti; rti; rti; rti; /* 0x000c: ~IRQL0 */ rti; rti; rti; rti; /* 0x0010: SPORT0 Transmit */ jump fir_start; rti; rti; rti; /* 0x0014: SPORT0 Receive */ rti; rti; rti; rti; /* 0x0018: ~IRQE */ rti; rti; rti; rti; /* 0x001c: BDMA */ rti; rti; rti; rti; /* 0x0020: SPORT1 Transmit or ~IRQ1 */ rti; rti; rti; rti; /* 0x0024: SPORT1 Receive or ~IRQ0 */ rti; rti; rti; rti; /* 0x0028: Timer */ rti; rti; rti; rti; /* 0x002c: Power Down (non-maskable */

.section/pm pm_code;

main:

l0 = length (data_buffer);

l4 = length (coefficient); /*setup circular buffer */

See Notes: Section B

See Notes: Section C

See Notes: Section D

/* setup circular buffer length */

m0 = 1; /* modify =1 for increment */ m4 = 1; /* through buffers */

ADSP-218x DSP Instruction Set Reference 2-11

Program Example

i0 = data_buffer; /* point to start of buffer */ i4 = coefficient; /* point to start of buffer */

ax0 = 0;

cntr = length(data_buffer);

/* initialize loop counter */

do clear until ce;

clear: dm(i0,m0) = ax0; /* clear data buffer */

/* setup divide value for 8KHz RFS */ ax0 = 0x00c0; dm(Sport0_Rfsdiv) = ax0;

ax0 = 0x000c; dm(Sport0_Sclkdiv) = ax0;

/* multichannel disabled, internally generated sclk, receive frame sync required, receive width = 0, transmit frame sync required, transmit width = 0, external transmit frame sync, internal receive frame sync,u-law companding, 8-bit words */

See Notes: Section E

/* 1.5385 MHz internal serial clock */

ax0 = 0x69b7; dm(Sport0_Ctrl_Reg) = ax0;

ax0 = 0x1000; /* enable sport0 */ dm(Sys_Ctrl_Reg) = ax0;

icntl = 0x00; /* disable interrupt nesting */ imask = 0x0060;

/* enable sport0 rx and tx interrupts only */

2-12 ADSP-218x DSP Instruction Set Reference

Programming Model

mainloop:

idle; /* wait here for interrupt */ jump mainloop; /* jump back to idle after rti */

Example Program: Setup Routine Discussion

The setup and main loop routine performs initialization and then loops on the occurs. The filter is interrupt-driven. When the interrupt occurs, control shifts to the interrupt service routine shown in Listing 2-2.

NOTES:

Section A of the program declares two constants and includes a header file

of definitions named

Section B of the program includes the assembler directives defining two circular buffers in on-chip memory: one in data memory RAM that is used to hold a delay line of samples and one in program memory RAM that is used to store coefficients for the filter. The coefficients are actually loaded from an external file by the linker. These values can be changed without reassembling; only another linking is required.

IDLE instruction to wait until the receive interrupt from SPORT0

def2181.h.

Section C shows the setup of interrupts. The first instruction is placed at the reset vector: address PM (0x0000). The first location is the reset vector instruction, which jumps to

main. Interrupt vectors that are not used are

filled with a return from interrupt instruction. This is a preferred programming practice rather than a necessity. The SPORT0 receive interrupt vector jumps to the interrupt service routine.

Section D, main, sets up the index (I), length (L), and modify (M) registers used to address the two circular buffers. A non-zero value for length activates the processor’s modulus logic. Each time the interrupt occurs, the register pointers advance one position through the buffers. The

clear loop

sets all values in the data memory buffer to zero.

ADSP-218x DSP Instruction Set Reference 2-13

Program Example

Section E sets up the processor’s memory-mapped control registers used in this system. See Appendix B in the ADSP-218x Hardware Reference Man- ual for control register initialization information.

SPORT0 is set up to generate the serial clock internally at 1.5385 MHz, based on a processor clock rate of 40 MHz. The receive and transmit signals are both required. The receive signal is generated internally at 8 KHz, while the transmit signal comes from the external device communicating with the processor.

Finally, SPORT0 is enabled and the interrupts are enabled. Now the IDLE instruction causes the processor to wait for interrupts. After the return from interrupt instruction, execution resumes at the instruction following the IDLE instruction. Once these setup instructions have been executed, all further activity takes place in the interrupt service routine shown in

Listing 2-2.

Listing 2-2. Interrupt Routine

fir_start:

si = rx0; /* read from sport0 */ dm(i0,m0) = si; /* transfer data to buffer */ mr = 0, my0 = pm(i4,m4), mx0 = dm(i0,m0);

cntr = taps_less_one; /* perform loop taps-1 times */ do convolution until ce;

convolution:

mr = mr + mx0 * my0 (ss), my0 = pm(i4,m4), mx0 = dm(i0,m0);

mr = mr + mx0 * my0 (rnd);

/* Nth pass of loop with rounding of result */ if mv sat mr; tx0 = mr1; /* write result to sport0 tx */ rti; /* return from interrupt */

/* setup multiplier for loop */

/* perform MAC and fetch next values */

2-14 ADSP-218x DSP Instruction Set Reference

Programming Model

Example Program: Interrupt Routine Discussion

This subroutine transfers the received data to the next location in the circular buffer overwriting the oldest sample. All samples and coefficients are then multiplied and the products are accumulated to produce the next output value. The subroutine checks for overflow and saturates the output value to the appropriate full scale. It then writes the result to the transmit section of SPORT0 and returns.

The subroutine begins by reading a new sample from SPORT0’s receive data register, RX0, into the SI register. The choice of SI is of no particular significance. Then, the data is written into the data buffer. Because of the automatic circular buffer addressing, the new data overwrites the oldest sample. The N-most recent samples are always in the buffer.

The third instruction of the routine, MR=0, MY0=PM(I4,M4),

MX0=DM(I0,M0), clears the multiplier result register (MR) and fetches the

first two operands. This instruction accesses both program and data memory but still executes in a single cycle because of the processor’s architecture. The counter register (CNTR) directs the loop to be performed

taps-1 times.

The convolution label identifies the loop itself, consisting of only two instructions, one instruction setting up the loop (DO UNTIL) and one instruction nested in the loop. The MAC instruction multiplies and accumulates the previous set of operands while fetching the next ones from each memory. This instruction also accesses both memories.

The final result is written back to the SPORT0 transmit data register TX0 to be sent to the communicating device.

ADSP-218x DSP Instruction Set Reference 2-15

Hardware Overlays and Software Issues

Hardware overlay pages can be used for both program execution and data storage. Switching between hardware overlay memory pages can be done in a single processor cycle with no effect latencies. The following examples show the assembly instructions for managing different program memory hardware overlay regions:

pmovlay = ax0; pmovlay = 5;

Since the program memory hardware overlay regions reside in address locations PM 0x2000 through 0x3fff, programs are restricted to execute the pmovlay= instruction from within the fixed program memory region, located at addresses PM 0x0000 through 0x1FFF.

If a pmovlay = instruction were to be executed from a program memory hardware overlay page, the next instruction would be fetched and executed from the subsequent address of the new hardware overlay page. In this scenario, there is no possibility to specify a well-defined address of the target program memory overlay region. Therefore, the portion of your program that controls the management of the program memory overlay pages must reside within the fixed/non-overlay program memory region.

If the program flow requires execution from a module that resides in an overlay region, it is good programming practice to have the calling function access the overlay module using a

CALL instruction versus a JUMP

instruction. Executing a call instruction pushes the address of the subsequent address after the call instruction onto the program counter stack, which is the return address after the overlay module is completed. Upon return from the overlay subroutine via the rts instruction, program execution resumse with the instruction following the subroutine call.

2-16 ADSP-218x DSP Instruction Set Reference

Programming Model

The example below shows one application of switching between program memory overlay regions at runtime:

main: . . . pmovlay = 4; /* switch to PM overlay #4 */ call Ovl4Function; /* call overlay function */ pmovlay = 5; /* return from overlay #4 & goto overlay #5 */ call Ovl5Function; /* call overlay function */ . . .

Libraries and Overlays

Because the program sequencer works independently from the program memory overlay register (PMOVLAY), program modules that run within an overlay page have no direct access to any program modules resident in other overlay pages. This means that all the required libraries and sub-functions must be placed either in the same page as the calling function or in the fixed memory/non-overlay area. Place libraries that are used by multiple modules located in different pages in the fixed program memory region as well. Unfortunately, for some applications there is a limited amount of fixed program memory. In this case, the linker places parts of the library in different overlay pages to help balance the memory usage in the system.

Interrupts and Overlays

The interrupt vector table occupies program memory addresses 0x0000 through 0x002f. When an unmasked interrupt is raised, ASTAT, MSTAT and

IMASK are pushed onto the status stack in this specific order. The current

value of the program counter which contains the address of the next instruction is placed onto the PC stack. This allows the program execution to continue with the next instruction of the main program after the interrupt is serviced.

ADSP-218x DSP Instruction Set Reference 2-17

Hardware Overlays and Software Issues

The ADSP-218x interrupt controller has no knowledge of the PMOVLAY and DMOVLAY registers. Therefore, the values of these registers must be saved or restored by the programmer in the interrupt service routine.

Whenever the interrupt service routine is located within the fixed program memory region, no special context saving of the overlay registers is required. However, if you would like to place the ISR within an overlay page, some additional instructions are needed to facilitate the saving or restoring of the PMOVLAY and DMOVLAY registers. The interrupt vector table features only four instruction locations per interrupt. Listing 2-3 is an example of a four instruction implementation that restores the PMOVLAY register after an interrupt.

Listing 2-3. PMOVLAY Register Restoration

Interrupt Vector: ax0 = PMOVLAY; /* save PMOVLAY value into ax0 */ Toppcstack = ax0; /* push PMOVLAY value onto PC stack */ Jump My_ISR; /* jump to interrupt subroutine */ Rti; /* placeholder in vector table (4 locations total */

My_ISR:

/* ISR code goes here */

jump I_Handler; /* use instead of rti to restore PMOVLAY

reg */

I_Handler: /* this subroutine should reside in fixed PM */ ax0 = Toppcstack; /* pop PMOVLAY value into ax0 */ nop; /* one cycle effect latency */ rti; /* return from interrupt */

If the interrupt service routine also accesses alternate data memory overlay pages, the DMOVLAY register must be saved and restored like the PMOVLAY register. Listing 2-4 is an example of a

DMOVLAY register restoration.

2-18 ADSP-218x DSP Instruction Set Reference

Programming Model

Listing 2-4. DMOVLAY Register Restoration

Interrupt Vector:

jump I_Handler; /* jump to interrupt handler */ rti; /* unreachable instructions */ rti; /* used as placeholders to */ rti; /* occupy all 4 locations of the vector */

I_Handler: /* this subroutine should reside in fixed PM */

ax0 = PMOVLAY; /* save PMOVLAY value into ax0 */ dm(save_PMOVLY)= ax0;/* save PMOVLAY value to DM variable*/ ax0 = DMOVLAY; /* save DMOVLAY value into ax0 */ dm(save_DMOVLY)= ax0;/*save DMOVLAY value to DM variable */ PMOVLAY = 5; /* isr is in PM page 5 */ DMOVLAY = 4; /* isr accesses DM page 4 */ call My_ISR; ax0 = dm(save_DMOVLY);

/* return from isr and restore DMOVLAY */ DMOVLAY = ax0; /* restore DMOVLAY value */ ax0 = dm(save_PMOVLY);

/* restore “saved” PMOVLAY from memory */ PMOVLAY = ax0; /* restore PMOVLAY value */ rti; /* return from interrupt */

My_ISR:

/* isr code goes here */ rts; /* return to I_Handler instead of rti */

Loop Hardware and Overlays

The loop hardware of the ADSP-218x DSPs operates independent of the

PMOVLAY register. Once a DO UNTIL instruction has been executed, the loop

comparator compares the next address generated by the program sequencer to the address of the last instruction of the loop. The loop com-

ADSP-218x DSP Instruction Set Reference 2-19

Hardware Overlays and Software Issues

pares the address value only. This comparison is performed independently from the value of the PMOVLAY register. Whenever the PMOVLAY register is updated to point to another overlay page while a loop in another overlay page is still active, the loop comparator may detect an end-of-loop address and force the PC to branch to an undesired memory location. In a real system design, this scenario may happen when a loop within an overlay page is exited temporarily by an interrupt service routine that runs in a different overlay page.

To avoid the improper execution of a loop:

The fixed memory region for program memory occupies addresses

0x0000 through 0x1fff; the program memory overlay region occu-

pies addresses 0x2000 through 0x3fff.

• Place hardware loops either in the fixed program memory or in overlay pages. Do not place loops whose loop bodies cross the boundary between program memory and an overlay page.

• Always place interrupt service routines in fixed program memory or in non-overlay program memory.

• Avoid end-of-loop addresses in ISRs.

2-20 ADSP-218x DSP Instruction Set Reference

3 SOFTWARE EXAMPLES

This chapter provides a brief summary of the development process that you use to create executable programs for the ADSP-218x DSPs. The overview is followed by software examples that you can use as a guide when writing your own applications.

The chapter contains:

• “Overview” on page 3-1

• “System Development Process” on page 3-3

• “Single-Precision Fir Transversal Filter” on page 3-5

• “Cascaded Biquad IIR Filter” on page 3-7

• “Sine Approximation” on page 3-9

• “Single-Precision Matrix Multiply” on page 3-11

• “Radix-2 Decimation-in-Time FFT” on page 3-13

Refer to the VisualDSP++ 3.5 Compiler amd Library Manual for ADSP-218x DSPs for information on appropriate library functions.

Overview

The software examples presented in this chapter are used for a variety of DSP operations. The FIR filter and cascaded biquad IIR filter are general filter algorithms that can be tailored to many applications. Matrix multiplication is used in image processing and other areas requiring vector

ADSP-218x DSP Instruction Set Reference 3-1

Overview

operations. The sine function is required for many scientific calculations. The FFT (fast Fourier transform) has wide application in signal analysis. Each of these examples is described in greater detail in Digital Signal Pro- cessing Applications Using The ADSP-2100 Family, Volume1, available from our website at www.analog.com. They are presented here to show some aspects of typical programs.

The FFT example is a complete program, including a subroutine that performs the FFT, a main calling program that initializes registers and calls the FFT subroutine, and an auxiliary routine.

Each of the other examples is shown as a subroutine in its own module. The module starts with a .SECTION assignment for data or code, using the section name defined in the .LDF file. The subroutine can be called from a program in another module that declares the starting label of the subroutine as an external symbol .EXTERN. This is the same label that is declared with the .GLOBAL directive in the subroutine module. This makes the subroutine callable from routines defined in other .ASM files. The last instruction in each subroutine is the RTS instruction, which returns control to the calling program.

Each module is prefaced by a comment block that provides the information shown in Table 3-1.

Table 3-1. Subroutine Modules and Comment Information

Module Comment Information

Calling Parameters Register values that the calling program must set before

calling the subroutine

Return Values Registers that hold the results of the subroutine

Altered Registers Register used by the subroutine. The calling program

must save them before calling the subroutine and restore them afterward in order to preserve their values

Computation Time The number of instruction cycles needed to perform the

subroutine

3-2 ADSP-218x DSP Instruction Set Reference

Software Examples

System Development Process

The ADSP-218x DSPs are supported by a complete set of development tools. Programming aids and processor simulators facilitate software design and debug. In-circuit emulators and demonstration boards help in hardware prototyping.

Figure 3-1 shows a flow chart of the system development process.

Linker

Step 1: ArchitectureDescription

Description File

(. LDF )

Step 2: Code Generation

Step 3: System V erification

Step 4: Software Verification

Generate Assem bly

S ource

(.DSP, .ASM)

and/or

GenerateC

Sour ce

(.C)

Assembler

EASM218x

C Compiler

cc218x

(. DOJ )

Linker

linker.exe

(. DX E)

VisualD SP

Debugg er

debu gapp

Worki ng

Cod e?

YES

Ha rdwa re E val uat ion

EZ-Kit Lit e

Tar get V erification

EZ-ICE

ROM Production

E LFS PL21

Figure 3-1. ADSP-218x DSP System Development Process

Software development tools include a C Compiler, C Runtime Library, DSP and Math Libraries, Assembler, Linker, Loader, Simulator, and Splitter. These tools are described in detail in the following documents:

• VisualDSP++ Assembler and Preprocessor Manual for ADSP-218x

DSPs

• VisualDSP++ C Compiler & Library Manual for ADSP-218x DSPs

ADSP-218x DSP Instruction Set Reference 3-3

System Development Process

• Product Bulletin for VisualDSP++ and ADSP-218x DSPs

• VisualDSP++ User’s Manual for ADSP-218x DSPs

• VisualDSP++ Linker & Utilities Manual for ADSP-218 DSPs

These documents are included in the software distribution CD-ROM and can be downloaded from our website at www.analog.com.

The development process begins with the task of describing the system and generating source code. You describe the system in the Linker Description File (.LDF) and you generate source code in C and/or assembly language.

Describing the system in the .LDF file includes providing information about the hardware environment and memory layout. Refer to the VisualDSP++ Linker & Utilities Manual for ADSP-218x DSPs for details.

Generating source code requires creating code modules, which can be written in either assembly language or C language. These modules include a main program, subroutines, or data variable declarations. The C modules are compiled by the C compiler cc218x.exe. Each code module is assembled separately by the assembler, which produces an object file (.DOJ).

The .DOJ file is input to the Linker linker.exe, along with the .LDF file. The linker links several object modules together to form an executable program

.LDF file to determine appropriate addresses for code and data. You specify

.DXE. The linker reads the target hardware information from the

the segment your code or data belongs to in the assembly file. You specify the location of the segment in the

.LDF file.

The linker places non-relocatable code or data modules at the specified memory addresses, provided the memory area has the correct attributes. The linker selects addresses for relocatable object. The linker generates a

3-4 ADSP-218x DSP Instruction Set Reference

Software Examples

memory image file .DXE containing a single executable program, which may be loaded into a VisualDSP debugger session (simulator or emulator) for testing.

The simulator provides windows that display different portions of the hardware environment. To replicate the target hardware, the simulator configures memory according to the memory specification in the .LDF file. The resulting simulation allows you to debug the system and analyze performance before committing to a hardware prototype.

After fully simulating your system and software, you can use an EZ-ICE in-circuit emulator in the prototype hardware to test circuitry, timing, and real-time software execution.

The PROM splitter software tool elfpsl21.exe translates the .DXE file into an industry-standard file format for a PROM programmer. Once you program the code in PROM devices and install an ADSP-218x processor into your prototype, it is ready to run.

Single-Precision Fir Transversal Filter

An FIR transversal filter structure can be obtained directly from the equation for discrete-time convolution:

N 1–

yn() hkn()xn k–()

≡

∑

k 0=

In this equation, the filter at time n. The output y(n) is formed as a weighted linear combination of the current and past input values of x, x(n–k). The weights,

(n), are the transversal filter coefficients at time n.

x(n) and y(n) represent the input to and output from

ADSP-218x DSP Instruction Set Reference 3-5

Single-Precision Fir Transversal Filter

In the equation, x(n–k) represents the past value of the input signal “contained” in the (k+1)th tap of the transversal filter. For example, x(n), the present value of the input signal, would correspond to the first tap, while

x(n–42) would correspond to the forty-third filter tap.

The subroutine that realizes the sum-of-products operation used in computing the transversal filter is shown in Listing 3-1.

Listing 3-1. Single-Precision FIR Transversal Filter

.SECTION/CODE program;

/* * FIR Transversal Filter Subroutine * Calling Parameters * I0 -> Oldest input data value in delay line * L0 = Filter length (N) * I4 -> Beginning of filter coefficient table * L4 = Filter length (N) * M1,M5 = 1 * CNTR = Filter length - 1 (N-1)

* Return Values * MR1 = Sum of products (rounded and saturated) * I0 -> Oldest input data value in delay line * I4 -> Beginning of filter coefficient table * * Altered Registers * MX0,MY0,MR * * Computation Time * N - 1 + 5 + 2 cycles * * All coefficients and data values are assumed to be * in 1.15 format. * */

3-6 ADSP-218x DSP Instruction Set Reference

Software Examples

.GLOBAL fir;

fir: MR=0, MX0=DM(I0,M1), MY0=PM(I4,M5);

DO sop UNTIL CE;

sop: MR=MR+MX0*MY0(SS), MX0=DM(I0,M1), MY0=PM(I4,M5);

MR=MR+MX0*MY0(RND); IF MV SAT MR; RTS;

Cascaded Biquad IIR Filter

A second-order biquad IIR filter section is represented by the transfer function (in the z-domain):

H(z) = Y(z)/X(z) = ( B0+ B

z–1+ B

–2

)/( 1 + A

–1

+ A2z

–2

)

where A1, A2, B0, B1 and B2 are coefficients that determine the desired impulse response of the system H(z). The corresponding difference equation for a biquad section is:

Y(n) = B0X(n) + B1X(n–1) + B

X(n–2) – A

Y(n–1) – A

Y(n–2)

Higher-order filters can be obtained by cascading several biquad sections with appropriate coefficients. The biquad sections can be scaled separately and then cascaded in order to minimize the coefficient quantization and the recursive accumulation errors.

A subroutine that implements a high-order filter is shown in Listing 3-2. A circular buffer in program memory contains the scaled biquad coeffi-

cients. These coefficients are stored in the order:

, B1. B0, A2 and A1 for

each biquad. The individual biquad coefficient groups must be stored in the order that the biquads are cascaded.

ADSP-218x DSP Instruction Set Reference 3-7

Cascaded Biquad IIR Filter

Listing 3-2. Cascaded Biquad IIR Filter

.SECTION/DATA data1; .var number_of_biquads;

.SECTION/CODE program;

/* Nth order cascaded biquad filter subroutine * * Calling Parameters: * * SR1=input X(n) * I0 -> delay line buffer for X(n-2), X(n-1), * Y(n-2), Y(n-1) * L0 = 0 * I1 -> scaling factors for each biquad section * L1 = 0 (in the case of a single biquad) * L1 = number of biquad sections * for multiple biquads) * I4 -> scaled biquad coefficients * L4 = 5 x [number of biquads] * M0, M4 = 1 * M1 = -3 * M2 = 1 (in the case of multiple biquads) * M2 = 0 (in the case of a single biquad) * M3 = (1 - length of delay line buffer) * * Return Value: * SR1 = output sample Y(n) * * Altered Registers: * SE, MX0, MX1, MY0, MR, SR * * Computation Time (with N even): * ADSP-218X: (8 x N/2) + 5 cycles * ADSP-218X: (8 x N/2) + 5 + 5 cycles * * All coefficients and data values are assumed to * be in 1.15 format *

3-8 ADSP-218x DSP Instruction Set Reference

.GLOBAL biquad;

biquad: CNTR = number_of_biquads;

DO sections UNTIL CE; /* Loop once for each biquad */

SE=DM(I1,M2); /* Scale factor for biquad */ MX0=DM(I0,M0), MY0=PM(I4,M4); MR=MX0*MY0(SS), MX1=DM(I0,M0), MY0=PM(I4,M4); MR=MR+MX1*MY0(SS), MY0=PM(I4,M4); MR=MR+SR1*MY0(SS), MX0=DM(I0,M0), MY0=PM(I4,M4); MR=MR+MX0*MY0(SS), MX0=DM(I0,M1), MY0=PM(I4,M4); DM(I0,M0)=MX1, MR=MR+MX0*MY0(RND);

sections: DM(I0,M0)=SR1, SR=ASHIFT MR1 (HI);

DM(I0,M0)=MX0; DM(I0,M3)=SR1; RTS;

Software Examples

Sine Approximation

The following formula approximates the sine of the input variable x (in radians):

y(x) = sin(x)

= 3.140625(x/

+ 0.5446778(x/

π) + 0.02026367(x/π)

π)

+ 1.800293(x/π)

where:

0 < X < (π/2)

The approximation is a 5th order polynomial fit, accurate for any value of x from 0° to 90° (the first quadrant). However, because sin(–x) =

-sin(x)

and sin(x) = sin(180° – x), you can infer the sine of any angle

from the sine of an angle in the first quadrant.

– 5.325196(x/π)3

ADSP-218x DSP Instruction Set Reference 3-9

Sine Approximation

The routine that implements this sine approximation, accurate to within two LSBs, is shown in Listing 3-3. This routine accepts input values in

1.15 format. The coefficients, which are initialized in data memory in

4.12 format, have been adjusted to reflect an input value scaled to the maximum range allowed by this format. On this scale, 180° ( π radians) equals the maximum positive value, 0x7FFF, while –180° ( π radians) equals the maximum negative value, 0x8000.

The routine shown in Listing 3-3 first adjusts the input angle to its equiv- alent in the first quadrant. The sine of the modified angle is calculated by multiplying increasing powers of the angle by the appropriate coefficients. The result is adjusted if necessary to compensate for the modifications made to the original input value.

Listing 3-3. Sine Approximation

/* * Sine Approximation * Y = Sin(x) * * Calling Parameters * AX0 = x in scaled 1.15 format * M3 = 1 * L3 = 0 * * Return Values * AR = y in 1.15 format * * Altered Registers * AY0,AF,AR,MY1,MX1,MF,MR,SR,I3 * * Computation Time * 25 cycles */

.SECTION/DATA data1; .VAR sin_coeff[5] = 0x3240, 0x0053, 0xAACC, 0x08B7, 0x1CCE;

3-10 ADSP-218x DSP Instruction Set Reference

Software Examples

.SECTION/CODE program; .GLOBAL sin;

sin: I3=sin_coeff; /* Pointer to coeff. buffer */

AY0=0x4000; AR=AX0; /* Copy x */ AF=AX0 AND AY0; /* Check 2nd or 4th Quad */ IF NE AR = -AX0; /* If yes, negate */ AY0=0x7FFF; AR=AR AND AY0; /* Remove sign bit */ MY1=AR; /* Copy x */ MF=AR*MY1 (RND); MX1=DM(I3,M3);

/* MF = x

MR=MX1*MY1 (SS); MX1=DM(I3,M3);

/* MR = x * 1st coeff, Get 2nd coeff */ CNTR=3; DO approx UNTIL CE;

MR=MR+MX1*MF (SS); MF=AR*MF (RND); /* MF = x

approx: MX1=DM(I3,M3); /* Get coeff. C,D,E */

MR=MR+MX1*MF (SS);

, Get 1st coeff */

, x4, x

SR=ASHIFT MR1 BY 3 (HI); /* Convert to 1.15 fmt */ SR=SR OR LSHIFT MR0 BY 3 (LO);

AR=PASS SR1; IF LT AR=PASS AY0; /* Saturate if needed */ AF=PASS AX0; IF LT AR=-AR; /* Negate output if needed */ RTS;

Single-Precision Matrix Multiply

The routine presented in this section multiplies two input matrices: X and Y. X is an

SxT (S rows, T columns) matrix stored in program memory. The output,

Z, is an

RxS (R rows, S columns) matrix stored in data memory. Y is an

RxT (R rows, T columns) matrix written to data memory.

ADSP-218x DSP Instruction Set Reference 3-11

Single-Precision Matrix Multiply

The matrix multiply routine is shown in Listing 3-4. It requires that you initialize a number of registers as listed in the Calling Parameters section of the initial comment. SE must contain the value necessary to shift the result of each multiplication into the desired format. For example, SE would be set to zero to obtain a matrix of 1.31 values from the multiplication of two matrices of 1.15 values.

Listing 3-4. Single-Precision Matrix Multiply

/* Single-Precision Matrix Multiplication *S * Z(i,j) = * k=0 * * X is an RxS matrix, Y is an SxT matrix, Z is an RxT matrix * * Calling Parameters * I1 -> Z buffer in data memory L1 = 0 * I2 -> X, stored by rows in data memory L2 = 0 * I6 -> Y, stored by rows in program memory L6 = 0 * M0 = 1M1 = S * M4 = 1M5 = T * L0,L4,L5 = 0 * SE = Appropriate scale value * CNTR = R * * Return Values * Z Buffer filled by rows * * Altered Registers * I0,I1,I2,I4,I5,MR,MX0,MY0,SR *

∑[X(i,k) × Y(k,j)] i=0 to R; j=0 to T

3-12 ADSP-218x DSP Instruction Set Reference

Software Examples

* Computation Time * ((S + 8) × T + 4) × R + 2 + 2 cycles */

.SECTION/CODE program;

.GLOBALspmm;

spmm: DO row_loop UNTIL CE;

I5=I6;/* I5 = start of Y */ CNTR=M5; DO column_loop UNTIL CE;

I0=I2; /* Set I0 to current X row */ I4=I5; /* Set I4 to current Y col */ CNTR=M1; MR=0, MX0=DM(I0,M0), MY0=PM(I4,M5)

/* Get 1st data */

DO element_loop UNTIL CE;

element_loop: MR=MR+MX0*MY0 (SS), MX0=DM(I0,M0),

MY0=PM(I4,M5); SR=ASHIFT MR1 (HI), MY0=DM(I5,M4); /* Update I5 */ SR=SR OR LSHIFT MR0 (LO); /* Finish Shift */

column_loop: DM(I1,M0)=SR1; /* Save Output */ row_loop: MODIFY(I2,M1); /* Update I2 to next X row */

RTS;

Radix-2 Decimation-in-Time FFT

The FFT program includes three subroutines. The first subroutine scrambles the input data placing the data in bit-reversed address order, so that the FFT output is in the normal, sequential order. The next subroutine computes the FFT. The third subroutine scales the output data to maintain the block floating-point data format.

ADSP-218x DSP Instruction Set Reference 3-13

Radix-2 Decimation-in-Time FFT

The program is contained in four modules. The main module declares and initializes data buffers and calls subroutines. The other three modules contain the FFT, bit reversal, and block floating-point scaling subroutines. The main module calls the FFT and bit reversal subroutines. The FFT module calls the data scaling subroutine.

The FFT is performed in place; that is, the outputs are written to the same buffer that the inputs are read from.

Main Module

The dit_fft_main module is shown in Listing 3-5. N is the number of points in the FFT (in this example, N=1024) and N_div_2 is used for specifying the lengths of buffers. To change the number of points in the FFT, you change the value of these constants and the twiddle factors.

The data buffers twid_real and twid_imag in program memory hold the twiddle factor cosine and sine values. The inplacereal, inplaceimag,

inputreal and inputimag buffers in data memory store real and imaginary

data values. Sequentially ordered input data is stored in inputreal and

inputimag. This data is scrambled and written to inplacereal and inplaceimag. A four-location buffer called “padding” is placed at the end of inplaceimag to allow data accesses to exceed the buffer length. This buffer

assists in debugging but is not necessary in a real system. Variables (one-location buffers) named

blk_exponent are declared last.

groups, bflys_per_group, node_space and

The real parts (cosine values) of the twiddle factors are stored in the buffer

twid_real. This buffer is initialized from the file twid_real.dat. Like-

wise, twid_imag.dat values initialize the twid_imag buffer that stores the sine values of the twiddle factors. In an actual system, the hardware would be set up to initialize these memory locations.

3-14 ADSP-218x DSP Instruction Set Reference

Software Examples

The variable called groups is initialized to N_div_2. The variables

bflys_per_group and node_space are each initialized to 2 because there

are two butterflies per group in the second stage of the FFT. The

blk_exponent

variable is initialized to zero. This exponent value is

updated when the output data is scaled.

After the initializations are complete, two subroutines are called. The first subroutine places the input sequence in bit-reversed order. The second performs the FFT and calls the block floating-point scaling routine.

Listing 3-5. Main Module, Radix-2 DIT FFT

.SECTION/CODE program; #define N 1024 #define N_div_2 512 /* For 2048 points */

.SECTION/DATA data1;

.VAR padding [4]=0,0,0,0;

.VAR inputreal [N] = "inputreal.dat"; .VAR inputimag [N] = "inputimag.dat"; .GLOBAL inputreal, inputimag;

.VAR inplacereal[N]; .VAR inplaceimag[N] = "inputimag.dat"; .GLOBAL inplacereal, inplaceimag;

.VAR groups = N_div_2; .VAR bflys_per_group = 2; .VAR node_space = 2; .VAR blk_exponent = 0; .GLOBAL

.SECTION/DATA data2;

.VAR twid_real [N_div_2] = "twid_real.dat"; .VAR twid_imag [N_div_2] = "twid_imag.dat";

groups, bflys_per_group, node_space, blk_exponent;

ADSP-218x DSP Instruction Set Reference 3-15

Radix-2 Decimation-in-Time FFT

.GLOBAL twid_real, twid_imag;

.SECTION/CODE program;

.EXTERN scramble, fft_strt;

CALL scramble; /* subroutine calls */ CALL fft_strt; IDLE; /* halt program */

DIT FFT Subroutine

The radix-2 DIT FFT routine is shown in Listing 3-6. The constants N and log2N are the number of points and the number of stages in the FFT, respectively. To change the number of points in the FFT, you modify these constants.

The first and last stages of the FFT are performed outside of the loop that executes all the other stages. Treating the first and last stages individually allows them to execute faster. In the first stage, there is only one butterfly per group, so the butterfly loop is unnecessary. The twiddle factors are all either 1 or 0 making multiplications unnecessary. In the last stage, there is only one group. Therefore, the group loop is unnecessary and the setup operations for the next stage.

Listing 3-6. Radix-2 DIT FFT Routine, Conditional Block Floating-Point

/* 1024 point DIT radix 2 FFT * Block Floating Point Scaling */

.SECTION/CODE program;

/* Calling Parameters * inplacereal=real input data in scrambled order * inplaceimag=all zeroes (real input assumed) * twid_real=twiddle factor cosine values * twid_imag=twiddle factor sine values * groups=N/2

3-16 ADSP-218x DSP Instruction Set Reference

Software Examples

* bflys_per_group=1 * node_space=1 * * Return Values * inplacereal=real FFT results, sequential order * inplaceimag=imag. FFT results, sequential order * * Altered Registers * I0,I1,I2,I3,I4,I5,L0,L1,L2,L3,L4,L5 * M0,M1,M2,M3,M4,M5 * AX0,AX1,AY0,AY1,AR,AF * MX0,MX1,MY0,MY1,MR,SB,SE,SR,SI * * Altered Memory * inplacereal, inplaceimag, groups, node_space, * bflys_per_group, blk_exponent */

#define log2N 10 #define N 1024 #define nover2 512 #define nover4 256

.EXTERN twid_real, twid_imag; .EXTERN inplacereal, inplaceimag; .EXTERN groups, bflys_per_group, node_space; .EXTERN bfp_adj; .GLOBAL fft_strt;

fft_strt: CNTR=log2N - 2;

/* Initialize stage counter */ M0=0; M1=1; L1=0; L2=0; L3=0; L4=LENGTH(twid_real); L5=LENGTH(twid_imag); L6=0; SB=-2;

ADSP-218x DSP Instruction Set Reference 3-17

Radix-2 Decimation-in-Time FFT

/* ---- STAGE 1 ---- */

I0=inplacereal; I1=inplacereal + 1; I2=inplaceimag; I3=inplaceimag + 1; M2=2;

CNTR=nover2; AX0=DM(I0,M0); AY0=DM(I1,M0); AY1=DM(I3,M0);

DO group_lp UNTIL CE;

AR=AX0+AY0, AX1=DM(I2,M0); SB=EXPADJ AR, DM(I0,M2)=AR; AR=AX0-AY0; SB=EXPADJ AR; DM(I1,M2)=AR, AR=AX1+AY1; SB=EXPADJ AR, DM(I2,M2)=AR; AR=AX1-AY1, AX0=DM(I0,M0); SB=EXPADJ AR, DM(I3,M2)=AR; AY0=DM(I1,M0);

group_lp: AY1=DM(I3,M0);

CALL bfp_adj;

/* ----- STAGES 2 TO N-1----- */

DO stage_loop UNTIL CE; /* Compute all stages in FFT */

I0=inplacereal; /* I0 ->x0 in 1st grp of stage */ I2=inplaceimag; /* I2 ->y0 in 1st grp of stage */ SI=DM(groups); SR=ASHIFT SI BY -1(LO); /* groups / 2 */ DM(groups)=SR0; /* groups=groups / 2 */ CNTR=SR0; /* CNTR=group counter */ M4=SR0; /* M4=twiddle factor modifier */ M2=DM(node_space); /* M2=node space modifier */ I1=I0; MODIFY(I1,M2); /* I1 ->y0 of 1st grp in stage */

3-18 ADSP-218x DSP Instruction Set Reference

MODIFY(I3,M2); /* I3 ->y1 of 1st grp in stage */

DO group_loop UNTIL CE;

I4=twid_real; /* I4 -> C of W0 */ I5=twid_imag; /* I5 -> (-S) of W0 */ CNTR=DM(bflys_per_group); /* CNTR=bfly count */ MY0=PM(I4,M4),MX0=DM(I1,M0); /* MY0=C,MX0=x1 */ MY1=PM(I5,M4),MX1=DM(I3,M0); /* MY1=-S,MX1=y1 */ DO bfly_loop UNTIL CE;

MR=MX0*MY1(SS),AX0=DM(I0,M0);

MR=MR+MX1*MY0(RND),AX1=DM(I2,M0);

/* MR=(y1(C)+x1(-S)),AX1=y0 */

AY1=MR1,MR=MX0*MY0(SS);

/* AY1=y1(C)+x1(-S),MR=x1(C) */ MR=MR-MX1*MY1(RND); /* MR=x1(C)-y1(-S) */ AY0=MR1,AR=AX1-AY1; /* AY0=x1(C)-y1(-S), */

SB=EXPADJ AR,DM(I3,M1)=AR;

AR=AX0-AY0,MX1=DM(I3,M0),MY1=PM(I5,M4);

/* AR=x0-[x1(C)-y1(-S)], */ /* MX1=next y1,MY1=next (-S) */

SB=EXPADJ AR,DM(I1,M1)=AR;

/* x1=x0-[x1(C)-y1(-S)] */

AR=AX0+AY0,MX0=DM(I1,M0),MY0=PM(I4,M4);

SB=EXPADJ AR,DM(I0,M1)=AR;

AR=AX1+AY1; /* AR=y0+[y1(C)+x1(-S)] */

bfly_loop: SB=EXPADJ AR,DM(I2,M1)=AR;

MODIFY(I0,M2); /* I0 ->1st x0 in next group */ MODIFY(I1,M2); /* I1 ->1st x1 in next group */ MODIFY(I2,M2); /* I2 ->1st y0 in next group */

Software Examples

/* MR=x1(-S),AX0=x0 */

/* AR=y0-[y1(C)+x1(-S)] */

/* Check for bit growth, */ /* y1=y0-[y1(C)+x1(-S)] */

/* Check for bit growth, */

/* AR=x0+[x1(C)-y1(-S)], */ /* MX0=next x1,MY0=next C */

/* Check for bit growth, */ /* x0=x0+[x1(C)-y1(-S)] */

/* Check for bit growth, */ /* y0=y0+[y1(C)+x1(-S)] */

ADSP-218x DSP Instruction Set Reference 3-19

Radix-2 Decimation-in-Time FFT

group_loop: MODIFY(I3,M2); /* I3 ->1st y1 in next group */

CALL bfp_adj; /* Compensate for bit growth */ SI=DM(bflys_per_group); SR=ASHIFT SI BY 1(LO); DM(node_space)=SR0; /* node_space=node_space / 2 */

stage_loop: DM(bflys_per_group)=SR0;

/* bflys_per_group=bflys_per_group / 2 */

/* ---- LAST STAGE ---- */

I0=inplacereal; I1=inplacereal+nover2; I2=inplaceimag; I3=inplaceimag+nover2;

CNTR=nover2; M2=DM(node_space); M4=1; I4=twid_real; I5=twid_imag;

MY0=PM(I4,M4),MX0=DM(I1,M0); /* MY0=C,MX0=x1 */ MY1=PM(I5,M4),MX1=DM(I3,M0); /* MY1=-S,MX1=y1 */ DO bfly_lp UNTIL CE;

MR=MX0*MY1(SS),AX0=DM(I0,M0);

MR=MR+MX1*MY0(RND),AX1=DM(I2,M0);

/* MR=(y1(C)+x1(-S)),AX1=y0 */

AY1=MR1,MR=MX0*MY0(SS);

/* AY1=y1(C)+x1(-S),MR=x1(C) */ MR=MR-MX1*MY1(RND); /* MR=x1(C)-y1(-S) */ AY0=MR1,AR=AX1-AY1;

/* AY0=x1(C)-y1(-S), */

/* AR=y0-[y1(C)+x1(-S)] */

SB=EXPADJ AR,DM(I3,M1)=AR;

/* Check for bit growth, */ /* y1=y0-[y1(C)+x1(-S)] */

AR=AX0-AY0,MX1=DM(I3,M0),MY1=PM(I5,M4);

/* AR=x0-[x1(C)-y1(-S)], */

3-20 ADSP-218x DSP Instruction Set Reference

/* MR=x1(-S),AX0=x0 */

SB=EXPADJ AR,DM(I1,M1)=AR;

AR=AX0+AY0,MX0=DM(I1,M0),MY0=PM(I4,M4);

SB=EXPADJ AR,DM(I0,M1)=AR;

AR=AX1+AY1; /* AR=y0+[y1(C)+x1(-S)] */

bfly_lp: SB=EXPADJ AR,DM(I2,M1)=AR;

CALL bfp_adj;

RTS;

Bit-Reverse Subroutine

Software Examples

/* MX1=next y1,MY1=next (-S) */

/* Check for bit growth, */ /* x1=x0-[x1(C)-y1(-S)] */

/* AR=x0+[x1(C)-y1(-S)], */ /* MX0=next x1,MY0=next C */

/* Check for bit growth, */ /* x0=x0+[x1(C)-y1(-S)] */

/* Check for bit growth */

The bit-reversal routine, called scramble, puts the input data in bit-reversed order so that the results are in sequential order. This routine (Listing 3-7) uses the bit-reverse capability of the ADSP-218x processors.

Listing 3-7. Bit-Reverse Routine (Scramble)

.SECTION/CODE program;

/* Calling Parameters * Sequentially ordered input data in inputreal * * Return Values * Scrambled input data in inplacereal * * Altered Registers * I0,I4,M0,M4,AY1 *

ADSP-218x DSP Instruction Set Reference 3-21

Radix-2 Decimation-in-Time FFT

* Altered Memory * inplacereal

#define N 1024 #define mod_value 0x0010; /* Initialize constants */

.EXTERN inputreal, inplacereal;

.GLOBAL scramble;

scramble: I4=inputreal; /* I4->sequentially ordered data */

I0=inplacereal; /* I0->scrambled data */ M4=1; M0=mod_value; /* M0=modifier for reversing N Bits */ L4=0; L0=0; CNTR = N;

ENA BIT_REV; /* Enable bit-reversed outputs on DAG1 */ DO brev UNTIL CE;

AY1=DM(I4,M4); /* Read sequentially ordered data */

brev: DM(I0,M0)=AY1;

/* Write data in bit-reversed location */ DIS BIT_REV; /* Disable bit-reverse */ RTS; /* Return to calling program */

Block Floating-Point Scaling Subroutine

The bfp_adj routine checks the FFT output data for bit growth and scales the entire set of data if necessary. This check prevents data overflow for each stage in the FFT. The routine, shown in Listing 3-8, uses the exponent detection capability of the shifter.

3-22 ADSP-218x DSP Instruction Set Reference

Software Examples

Listing 3-8. Radix-2 Block Floating-Point Scaling Routine

.SECTION/CODE program;

/* Calling Parameters * Radix-2 DIT FFT stage results in inplacereal and inplaceimag * * Return Parameters * inplacereal and inplaceimag adjusted for bit growth * * Altered Registers * I0,I1,AX0,AY0,AR,MX0,MY0,MR,CNTR * * Altered Memory * inplacereal, inplaceimag, blk_exponent */

#define Ntimes 2048 .EXTERN inplacereal, blk_exponent; /* Begin declaration */

.GLOBAL bfp_adj;

bfp_adj: AY0=CNTR; /* Check for last stage */

AR=AY0-1; IF EQ RTS; /* If last stage, return */ AY0=-2; AX0=SB; AR=AX0-AY0; /* Check for SB=-2 */ IF EQ RTS; /* IF SB=-2, no bit */

/* growth, return */ I0=inplacereal; /* I0=read pointer */ I1=inplacereal; /* I1=write pointer */ AY0=-1; MY0=0x4000; /* Set MY0 to shift 1 */

/* bit right */

AR=AX0-AY0,MX0=DM(I0,M1);

/* Check if SB=-1 */

ADSP-218x DSP Instruction Set Reference 3-23

Radix-2 Decimation-in-Time FFT

/* Get 1st sample */

IF EQ JUMP strt_shift;

/* If SB=-1, shift block */ /* data 1 bit */

AX0=-2; /* Set AX0 for block */

/* exponent update */

MY0=0x2000; /* Set MY0 to shift 2 */

/* bits right */

strt_shift: CNTR=Ntimes2 - 1; /* initialize loop counter */

DO shift_loop UNTIL CE; /* Shift block of data*/

MR=MX0*MY0(RND),MX0=DM(I0,M1);

/* MR=shifted data */ /* MX0=next value */

shift_loop: DM(I1,M1)=MR1; /* Unshifted data */

/* shifted data */ MR=MX0*MY0(RND); /* Shift last data word */ AY0=DM(blk_exponent); /* Update block exponent */

/*and store last shifted sample */

DM(I1,M1)=MR1,AR=AY0-AX0;

DM(blk_exponent)=AR; RTS;

3-24 ADSP-218x DSP Instruction Set Reference

4 INSTRUCTION SET

This chapter is a complete reference for the instruction set of the ADSP-218x DSPs.

The chapter contains:

• “Quick List Of Instructions” on page 4-2

• “Instruction Set Overview” on page 4-5

• “Multifunction Instructions” on page 4-7

• “ALU, MAC and Shifter Instructions” on page 4-14

• “MOVE: Read and Write Instructions” on page 4-20

• “Program Flow Control” on page 4-22

• “Miscellaneous Instructions” on page 4-25

• “Extra Cycle Conditions” on page 4-27

• “Instruction Set Syntax” on page 4-28

• “ALU Instructions” on page 4-31

• “MAC Instructions” on page 4-72

• “Shifter Instructions” on page 4-94

• “Move Instructions” on page 4-113

• “Program Flow Instructions” on page 4-133

• “MISC Instructions” on page 4-151

• “Multifunction Instructions” on page 4-171

ADSP-218x DSP Instruction Set Reference 4-1

Quick List Of Instructions

The instruction set is organized by instruction group and, within each group, by individual instruction. The list below shows all of the instructions and the reference page for each instruction.

ALU Instructions

• “Add/Add With Carry” on page 4-32

• “Subtract X-Y/Subtract X-Y With Borrow” on page 4-35

• “Subtract Y-X/Subtract Y-X With Borrow” on page 4-39

• “Bitwise Logic: AND, OR, XOR” on page 4-42

• “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on

page 4-45

• “Clear: PASS” on page 4-48

• “Syntax” on page 4-32

• “NOT” on page 4-54

• “Absolute Value: ABS” on page 4-56

• “Increment” on page 4-58

• “Decrement” on page 4-60

• “Divide Primitives: DIVS and DIVQ” on page 4-62

• “Generate ALU Status Only: NONE” on page 4-70

MAC Instructions

• “Multiply” on page 4-73

• “Multiply With Cumulative Add” on page 4-77

• “Multiply With Cumulative Subtract” on page 4-81

4-2 ADSP-218x DSP Instruction Set Reference

• “Squaring” on page 4-85

• “MAC Clear” on page 4-88

• “MAC Transfer MR” on page 4-90

• “Conditional MR Saturation” on page 4-92

Shifter Instructions

• “Arithmetic Shift” on page 4-95

• “Logical Shift” on page 4-98

• “Normalize” on page 4-101

• “Derive Exponent” on page 4-104

• “Block Exponent Adjust” on page 4-107

• “Arithmetic Shift Immediate” on page 4-109

Instruction Set

• “Logical Shift Immediate” on page 4-111

Move Instructions

• “Register Move” on page 4-114

• “Load Register Immediate” on page 4-116

• “Data Memory Read (Direct Address)” on page 4-118

• “Data Memory Read (Indirect Address)” on page 4-120

• “Program Memory Read (Indirect Address)” on page 4-122

• “Data Memory Write (Direct Address)” on page 4-124

• “Data Memory Read (Indirect Address)” on page 4-120

• “Program Memory Write (Indirect Address)” on page 4-129

• “IO Space Read/Write” on page 4-131

ADSP-218x DSP Instruction Set Reference 4-3

Quick List Of Instructions

Program Flow Instructions

• “JUMP” on page 4-134

• “CALL” on page 4-136

• “JUMP or CALL on Flag In Pin” on page 4-138

• “Modify Flag Out Pin” on page 4-140

• “RTS (Return from Subroutine)” on page 4-142

• “RTI (Return from Interrupt)” on page 4-144

• “Do Until” on page 4-146

• “Idle” on page 4-149

MISC Instructions

• “Stack Control” on page 4-152

• “Program Memory Overlay Register Update” on page 4-162

• “Data Memory Overlay Register Update” on page 4-165

• “Modify Address Register” on page 4-168

• “No Operation” on page 4-170

Multifunction Instructions

• “Computation With Memory Read” on page 4-172

• “Computation With Register-to-Register Move” on page 4-178

• “Computation With Memory Write” on page 4-183

• “Data and Program Memory Read” on page 4-188

• “ALU/MAC With Data and Program Memory Read” on

page 4-190

4-4 ADSP-218x DSP Instruction Set Reference

Instruction Set

Instruction Set Overview

This chapter provides an overview and detailed reference for the instruction set of the ADSP-218x DSPs. The instruction set is grouped into the following categories:

• Computational: ALU, MAC, Shifter

•Move

• Program Flow

• Multifunction

• Miscellaneous

The instruction set is tailored to the computation-intensive algorithms common in DSP applications. For example, sustained single-cycle multiplication/accumulation operations are possible. The instruction set provides full control of the processors’ three computational units: the ALU, MAC and Shifter. Arithmetic instructions can process single-precision 16-bit operands directly; provisions for multiprecision operations are available.

The high-level syntax of ADSP-218x source code is both readable and efficient. Unlike many assembly languages, the ADSP-218x instruction set uses an algebraic notation for arithmetic operations and for data moves, resulting in highly readable source code. There is no performance penalty for this; each program statement assembles into one 24-bit instruction which executes in a single cycle. There are no multicycle instructions in the instruction set. (If memory access times require, or contention for off-chip memory occurs, overhead cycles are required, but all instructions can otherwise execute in a single cycle.)

ADSP-218x DSP Instruction Set Reference 4-5

Instruction Set Overview

In addition to JUMP and CALL, the instruction set’s control instructions support conditional execution of most calculations and a DO UNTIL looping instruction. Return from interrupt (RTI) and return from subroutine (RTS) are also provided.

The IDLE instruction is provided for idling the processor until an interrupt occurs. IDLE puts the processor into a low-power state while waiting for interrupts.

Two addressing modes are supported for memory fetches. Direct addressing uses immediate address values; indirect addressing uses the I registers of the two data address generators (DAGs).

The 24-bit instruction word allows a high degree of parallelism in performing operations. The instruction set allows for single-cycle execution of any of the following combinations:

• Any ALU, MAC or Shifter operation (conditional or non-conditional)

• Any register-to-register move

• Any data memory read or write

• A computation with any data register to data register move

• A computation with any memory read or write

• A computation with a read from two memories

The instruction set allows maximum flexibility. It provides moves from any register to any other register, and from most registers to/from memory. In addition, almost any ALU, MAC or Shifter operation may be combined with any register-to-register move or with a register move to or from internal or external memory.

4-6 ADSP-218x DSP Instruction Set Reference

Instruction Set

Because the multifunction instructions best illustrate the power of the processors’ architecture, in the next section we begin with a discussion of this group of instructions.

Multifunction Instructions

Multifunction operations take advantage of the inherent parallelism of the ADSP-218x architecture by providing combinations of data moves, memory reads/memory writes, and computation, all in a single cycle.

ALU/MAC With Data and Program Memory Read

Perhaps the single most common operation in DSP algorithms is the sum of products, performed as follows:

• Fetch two operands (such as a coefficient and data point)

• Multiply the operands and sum the result with previous products

The ADSP-218x processors can execute both data fetches and the multiplication/accumulation in a single-cycle. Typically, a loop of multiply/accumulates can be expressed in ADSP-218x source code in just two program lines. Since the on-chip program memory of the ADSP-218x processors is fast enough to provide an operand and the next instruction in a single cycle, loops of this type can execute with sustained single-cycle throughput. An example of such an instruction is:

MR=MR+MX0*MY0(SS), MX0=DM(I0,M0), MY0=PM(I4,M5);

The first clause of this instruction (up to the first comma) says that MR, the MAC result register, gets the sum of its previous value plus the product of the (current) X and Y input registers of the MAC (MX0 and MY0) both treated as signed (

SS).

ADSP-218x DSP Instruction Set Reference 4-7

Multifunction Instructions

In the second and third clauses of this multifunction instruction, two new operands are fetched. One is fetched from the data memory (DM) pointed to by index register zero (I0, post modified by the value in M0) and the other is fetched from the program memory location (PM) pointed to by I4 (post-modified by M5 in this instance). Note that indirect memory addressing uses a syntax similar to array indexing, with DAG registers providing the index values. Any I register may be paired with any M register within the same DAG.

As discussed in the ADSP-218x DSP Hardware Reference Manual, Chapter 2, “Computational Units”, registers are read at the beginning of the cycle and written at the end of the cycle. The operands present in the MX0 and

MY0 registers at the beginning of the instruction cycle are multiplied and

added to the MAC result register, MR. The new operands fetched at the end of this same instruction overwrite the old operands after the multiplication has taken place and are available for computation on the following cycle. You may, of course, load any data registers in conjunction with the computation, not just MAC registers with a MAC operation as in our example.

The computational part of this multifunction instruction may be any unconditional ALU instruction except division or any MAC instruction except saturation. Certain other restrictions apply: the next X operand must be loaded into MX0 from data memory and the new Y operand must be loaded into MY0 from program memory (internal and external memory are identical at the level of the instruction set). The result of the computation must go to the result register (

MR or AR) not to the feedback register

(MF or AF).

4-8 ADSP-218x DSP Instruction Set Reference

Instruction Set

Data and Program Memory Read

This variation of a multifunction instruction is a special case of the multifunction instruction described above in which the computation is omitted. It executes only the dual operand fetch, as shown below:

AX0=DM(I2,M0), AY0=PM(I4,M6);

In this example we have used the ALU input registers as the destination. As with the previous multifunction instruction, X operands must come from data memory and Y operands from program memory (internal or external memory in either case, for the processors with on-chip memory).

Computation With Memory Read

If a single memory read is performed instead of the dual memory read of the previous two multifunction instructions, a wider range of computations can be executed. The legal computations include all ALU operations except division, all MAC operations and all Shifter operations except

SHIFT IMMEDIATE. Computation must be unconditional. An example of

this kind of multifunction instruction is:

AR=AX0+AY0, DM(I0,M0)=AX0;

Here, an addition is performed in the ALU while a single operand is fetched from data memory. The restrictions are similar to those for previous multifunction instructions. The value of AX0, used as a source for the computation, is the value at the beginning of the cycle. The data read operation loads a new value into reason, the destination register (

AX0 by the end of the cycle. For this same

AR in the example above) cannot be the

destination for the memory read.

ADSP-218x DSP Instruction Set Reference 4-9

Multifunction Instructions

Computation With Memory Write

The computation with memory write instruction is similar in structure to the computation with memory read: the order of the clauses in the instruction line, however, is reversed. First the memory write is performed, then the computation, as shown below:

DM(I0,M0)=AR, AR=AX0+AY0;

Again the value of the source register for the memory write (AR in this example) is the value at the beginning of the instruction. The computation loads a new value into the same register; this is the value in AR at the end of this instruction. Reversing the order of the clauses would imply that the result of the computation is written to memory when, in fact, the previous value of the register is what is written. There is no requirement that the same register be used in this way although this usually is the case in order to pipeline operands to the computation.

The restrictions on computation operations are identical to those given above. All ALU operations except division, all MAC operations, and all Shifter operations except SHIFT IMMEDIATE are legal. Computations must be unconditional.

Computation With Data Register Move

This final type of multifunction instruction performs a data register to data register move in parallel with a computation. Most of the restrictions applying to the previous two instructions also apply to this instruction.

AR=AX0+AY0, AX0=MR2;

Here, an ALU addition operation occurs while a new value is loaded into

AX0 from MR2. As before, the value of AX0 at the beginning of the instruc-

tion is the value used in the computation. The move may be from or to all ALU, MAC and Shifter input and output registers except the feedback registers (AF and MF) and SB.

4-10 ADSP-218x DSP Instruction Set Reference

Instruction Set

In the example, the data register move loads the AX0 register with the new value at the end of the cycle. All ALU operations except division, all MAC operations and all Shifter operations except SHIFT IMMEDIATE are legal. Computation must be unconditional.

A complete list of data registers is given in “Processor Registers: reg and

dreg” on page 4-22. A complete list of the permissible xops and yops for

computational operations is given in the reference page for each instruction. Table 4-1 shows the legal combinations for multifunction instructions (described in Table 4-2). You may combine operations on the same row with each other.

Table 4-1. Summary of Valid Combinations for Multifunction Instructions

Unconditional Computations Data Move

(DM=DAG1)

None or any ALU (except Division) or MAC DM read PM read

Any MAC Any ALU except Division Any Shift except Immediate

DM read — DM write — Register-to-Register

Data Move (PM=DAG2)

— PM read — PM write

ADSP-218x DSP Instruction Set Reference 4-11

Multifunction Instructions

Table 4-2. Multifunction Instructions

<ALU>*† , AX0 = DM ( I0 , M0 ), AY0 = PM ( I4 , M4

<MAC>*† AX1 I1 , M1 AY1 I5 , M5

MX0 I2 , M2 MY0 I6 , M6

MX1 I3 , M3 MY1 I7 , M7

AX0 = DM ( I0 , M0 ) , AY0 = PM ( I4 , M4 ); AX1 I1 , M1 AY1 I5 , M5 MX0 I2 , M2 MY0 I6 , M6 MX1 I3 , M3 MY1 I7 , M7

<ALU>* , dreg = DM ( I0 , M0 ) ; <MAC>* I1 , M1

<SHIFT>* I2 , M2

I3 , M3

I4 , M4 I5 , M5 I6 , M6 I7 , M7

PM ( I4 , M4 )

I5 , M5 I6 , M6 I7 , M7

* May not be conditional instruction

4-12 ADSP-218x DSP Instruction Set Reference

DM ( I0 , M0 ) = dreg, <ALU>* ;

I1 , M1 <MAC>* I2 , M2 <SHIFT>* I3 , M3

I4 , M4 I5 , M5 I6 , M6 I7 , M7

PM ( I4 , M4 )

I5 , M5 I6 , M6 I7 , M7

<ALU>* , dreg = dreg; <MAC>*

<SHIFT>*

Instruction Set

<ALU> Any ALU instructions (except DIVS, DIVQ) <MAC> Any multiply/accumulate instruction <SHIFT> Any shifter instruction (except Shift Immediate) * May not be conditional instruction † AR, MR result registers must be used-- not AF, MF feedback registers

or NONE.

ALU, MAC and Shifter Instructions

This group of instructions performs computations. All of these instructions can be executed conditionally except the ALU division instructions and the Shifter SHIFT IMMEDIATE instructions.

ALU Group

The following is an example of one ALU instruction, Add/Add with Carry:

IF AC AR=AX0+AY0+C;

The (optional) conditional expression, IF AC, tests the ALU Carry bit (AC); if there is a carry from the previous instruction, this instruction executes, otherwise a NOP occurs and execution continues with the next instruction. The algebraic expression AR=AX0+AY0+C means that the ALU result register (AR) gets the value of the ALU X input and Y input registers plus the value of the carry-in bit.

Table 4-3 gives a summary list of all ALU instructions. In this list, condi-

tion stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the ALU. The

conditional clause is optional and is enclosed in square brackets to show this. A complete list of the permissible xops and yops is given in the reference page for each instruction.

A complete list of conditions is given in Table 4-9 on page 4-24.

4-14 ADSP-218x DSP Instruction Set Reference

Table 4-3. ALU Instructions

[IF cond] AR = xop + yop ;

AF + C

+ yop + C

+ constant

+ constant + C

[IF cond] AR = xop – yop ;

AF – yop + C – 1

+ C – 1

– constant

–1 constant + C – 1

Instruction Set

[IF cond] AR = – xop ;

AF yop

[IF cond] AR = NOT xop ;

AF yop

[IF cond] AR = ABS xop;

[IF cond] AR = yop + 1;

[IF cond] AR = yop – 1;

DIVS yop, xop ; DIVQ xop ;

NONE = <ALU> ;

ADSP-218x DSP Instruction Set Reference 4-15

ALU, MAC and Shifter Instructions

[IF cond] AR = yop – xop ;

AF – xop + C – 1

– xop + constant + C –1

[IF cond] AR = xop AND yop ;

AF OR constant

[IF cond] AR = TSTBIT n OF xop ;

AF SETBIT n OF xop

CLRBIT n OF xop TGLBIT n OF xop

– xop + C – 1

– xop + constant

XOR

[IF cond] AR = PASS xop ;

AF yop

constant

MAC Group

Here is an example of one of the MAC instructions, Multiply/Accumulate:

IF NOT MV MR=MR+MX0*MY0(UU);

The conditional expression, IF NOT MV, tests the MAC overflow bit. If the condition is not true, a the multiply/accumulate operation: the multiplier result register ( the value of itself plus the product of the X and Y input registers selected. The modifier in parentheses (

4-16 ADSP-218x DSP Instruction Set Reference

NOP is executed. The expression MR=MR+MX0*MY0 is

UU) treats the operands as unsigned. There

MR) gets

Instruction Set

can be only one such modifier selected from the available set. The modifier (SS) means both are signed, while (US) and (SU) mean that either the first or second operand is signed; (RND) means to round the (implicitly signed) result.

Table 4-4 gives a summary list of all MAC instructions. In this list,

condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the MAC. A complete list of the permissible xops and yops is given in the reference page for each instructions.

Table 4-4. MAC Instructions

[IF cond] MR = xop * yop ( SS );

MF xop SU

RND

[IF cond] MR = MR + xop * yop ( SS );

MF xop SU

RND

[IF cond] MR = MR – xop * yop ( SS );

MF xop SU

RND

ADSP-218x DSP Instruction Set Reference 4-17

ALU, MAC and Shifter Instructions

Table 4-4. MAC Instructions (Cont’d)

[IF cond] MR = 0;

[IF cond] MR = MR [(RND)];

IF MV SAT MR ;

Shifter Group

Here is an example of one of the Shifter instruction, Normalize:

IF NOT CE SR= SR OR NORM SI (HI);

The conditional expression, IF NOT CE, tests the “not counter expired” condition. If the condition is false, a NOP is executed. The destination of all shifting operations is the Shifter Result register, SR. The destination of exponent detection instructions is SE or SB, as shown in Table 4-5. In this example, SI, the Shifter Input register, is the operand. The amount and direction of the shift is controlled by the signed value in the

SE register in

all shift operations except an immediate shift. Positive values cause left shifts; negative values cause right shifts.

The optional SR OR modifier logically ORs the result with the current contents of the from two 16-bit pieces.

SR register; this allows you to construct a 32-bit value in SR

NORM is the operator and HI is the modifier that

determines whether the shift is relative to the HI or LO (16-bit) half of SR. If

SR OR is omitted, the result is passed directly into SR.

Table 4-5 gives a summary list of all Shifter instructions. In this list, con-

dition stands for all the possible conditions that can be tested.

4-18 ADSP-218x DSP Instruction Set Reference

Table 4-5. Shifter Instructions

[IF cond] SR = [SR OR] ASHIFT xop ( HI );

[IF cond] SR = [SR OR] LSHIFT xop ( HI );

[IF cond] SR = [SR OR] NORM xop ( HI );

[IF cond] SE = EXP xop ( HI );

Instruction Set

HIX

[IF cond] SB = EXPADJ xop;

SR = [SR OR] ASHIFT xop BY <exp> ( HI );

SR = [SR OR] LSHIFT xop BY <exp> ( HI );

ADSP-218x DSP Instruction Set Reference 4-19

MOVE: Read and Write Instructions

Move instructions, shown in Table 4-6, move data to and from data registers and external memory. Registers are divided into two groups, referred to as reg which includes almost all registers and dreg, or data registers, which is a subset. Only the program counter (PC) and the ALU and MAC feedback registers (AF and MF) are not accessible.

Table 4-6. Move Instructions

reg = reg ;

reg = DM (<address>) ;

dreg = DM ( I0 , M0 );

I1 , M1

I2 , M2

I3 , M3

I4 , M4

I5 , M5

I6 , M6

I7 , M7

DM ( I0 , M0 ) = dreg ;

I1 , M1 <data>

I2 , M2

I3 , M3

4-20 ADSP-218x DSP Instruction Set Reference

Table 4-6. Move Instructions (Cont’d)

I4 , M4

I5 , M5

I6 , M6

I7 , M7

DM (<address>) = reg ;

reg = <data> ;

dreg = PM ( I4 ’ M4 );

I5 ’ M5

I6 ’ M6

I7 ’ M7

Instruction Set

PM ( I4 ’ M4 ) = dreg;

I5 ’ M5

I6 ’ M6

I7 ’ M7

Table 4-7 shows how registers are grouped. These registers are read and

written via their register names.

ADSP-218x DSP Instruction Set Reference 4-21

Program Flow Control

Table 4-7. Processor Registers: reg and dreg

reg (registers) dreg (Data Registers)

I0 – 17, M0 – M7, L0 – L7 AX0, AX1, AY0, AY1, AR

CNTR MX0, MX1, MY0, MY1, MR0,

MR1, MR2

ASTAT, MSTAT, SSTAT SI, SE, SR0, SR1

IMASK, ICNTL, IFC

TX0, TX1, RX0, RX1

Program Flow Control

Program flow control on the ADSP-218x processors is simple but powerful. Here is an example of one instruction:

IF EQ JUMP my_label;

JUMP, of course, is a familiar construct from many other languages. My_label is any identifier you wish to use as a label for the destination

jumped to. Instead of the label, an index register in DAG2 may be explicitly used. The default scope for any label is the source code module in which it is declared. The assembler directive .

ENTRY makes a label visible as

an entry point for routines outside the module. Conversely, the .EXTERNAL directive makes it possible to use a label declared in another module.

If the counter condition ( ment to

CALL permit the additional conditionals FLAG_IN and NOT FLAG_IN to be

CNTR must be executed to initialize the counter value. JUMP and

used for branching on the state of the

DO UNTIL CE, IF NOT CE) is to be used, an assign-

FI pin, but only with direct address-

ing, not with DAG2 as the address source.

4-22 ADSP-218x DSP Instruction Set Reference

Instruction Set

RTS and RTI provide for conditional return from CALL or interrupt vectors

respectively.

The IDLE instruction provides a way to wait for interrupts. IDLE causes the processor to wait in a low-power state until an interrupt occurs. When an interrupt is serviced, control returns to the instruction following the IDLE statement. IDLE uses less power than loops created with NOPs.

Table 4-8 gives a summary of all program flow control instructions. The

condition codes are described in Table 4-9.

Table 4-8. Program Flow Control Instructions

[IF cond] JUMP (I4) ;

(I5)

(I6)

(I7)

IF FLAG_IN JUMP <address>;

NOT FLAG_IN

[IF cond] CALL (I4) ;

(I5)

(I6)

(I7)

IF FLAG_IN CALL <address>;

NOT FLAG_IN

[IF cond] RTS;

ADSP-218x DSP Instruction Set Reference 4-23

Program Flow Control

Table 4-8. Program Flow Control Instructions (Cont’d)

[IF cond] RTI;

DO <address> [UNTIL termination];

IDLE [(n)];

Table 4-9. IF Status Condition Codes

Syntax Status Condition True If:

EQ Equal Zero AZ = 1

NE Not Equal Zero AZ = 0

LT Less Than Zero AN .XOR. AV = 1

GE Greater Than or Equal Zero AN .XOR. AV = 0

LE Less Than or Equal Zero (AN .XOR. AV) .OR. AZ = 1

GT Greater Than Zero (AN .XOR. AV) .OR. AZ = 0

AC ALU Carry AC = 1

NOT AC Not ALU Carry AC = 0

AV ALU Overflow AV = 1

NOT AV Not ALU Overflow AV = 0

MV MAC Overflow MV = 1

NOT MV Not MAC Overflow MV = 0

NEG X Input Sign Negative AS = 1

POS X Input Sign Positive AS = 0

NOT CE Not Counter Expired

FLAG_IN

NOT FLAG_IN1 Not FI pin Last sample of FI pin = 0

FI pin Last sample of FI pin = 1

1 Only available on JUMP and CALL instructions

4-24 ADSP-218x DSP Instruction Set Reference

Instruction Set

Miscellaneous Instructions

There are several miscellaneous instructions. NOP is a no operation instruction. The PUSH/POP instructions allow you to explicitly control the status, counter, PC and loop stacks; interrupt servicing automatically pushes and pops these stacks.

The Mode Control instruction enables and disables processor modes of operation: bit-reversal on DAG1, latching ALU overflow, saturating the ALU result register, choosing the primary or secondary register set, GO mode for continued operation during bus grant, multiplier shift mode for fractional or integer arithmetic, and timer enabling.

A single ENA or DIS can be followed by any number of mode identifiers, separated by commas; ENA and DIS can also be repeated. All seven modes can be enabled, disabled, or changed in a single instruction.

The MODIFY instruction modifies the address pointer in the I register selected with the value in the selected M register, without performing any actual memory access. As always, the I and M registers must be from the same DAG; any of I0-I3 may be used only with one from M0-M3 and the same for I4-I7 and M4-M7. If circular buffering is in use, modulus logic applies. See the ADSP-218x DSP Hardware Reference Manual, Chapter 4, “Data Address Generators” for more information.

FO (Flag Out), FL0, FL1, and FL2 pins can each be set, cleared, or tog-

The gled. This instruction provides a control structure for multiprocessor communication.

ADSP-218x DSP Instruction Set Reference 4-25

Miscellaneous Instructions

Table 4-10. Miscellaneous Instructions

NOP;

[ PUSH STS] [, POP CNTR] [, POP PC] [,POP LOOP];

POP

ENA BIT_REV [,] ;

DIS AV_LATCH

AR_SAT

SEC_REG

G_MODE

M_MODE

TIMER

MODIFY ( I0 , M0 );

I1 , M1 I2 , M2 I3 , M3

I4 , M4 I5 , M5 I6 , M6 I7 , M7

[IF cond] SET FLAG_OUT [,];

RESET FL0

TOGGLE FL1

FL2

ENA INTS;

DIS

4-26 ADSP-218x DSP Instruction Set Reference

Instruction Set

Extra Cycle Conditions

All instructions execute in a single cycle except under certain conditions, as explained below.

Multiple Off-Chip Memory Accesses

The data and address buses of the ADSP-218x processors are multiplexed off-chip. Because of this occurrence, the processors can perform only one off-chip access per instruction in a single cycle. If two off-chip accesses are required such as the instruction fetch and one data fetch, or data fetches from both program and data memory, then one overhead cycle occurs. In this case the program memory access occurs first, followed by the data memory access. If three off-chip accesses are required—the instruction fetch as well as data fetches from both program and data memory—then two overhead cycles occur.

A multifunction instruction requires three items to be fetched from memory: the instruction itself and two data words. No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory. This excludes external wait states or bus request holdoffs. Two fetches must be from on-chip memory, either PM or DM.

Wait States

All family processors allow the programming of wait states for external memory chips. Up to 15 extra wait state cycles for the ADSP-2185M, ADSP-2186M, ADSP-2188M, ADSP-2189M, ADSP-2188N, ADSP-2185N, ADSP-2186N, ADSP-2187N and ADSP-2189N DSPs and up to seven extra wait state cycles for all other ADSP-218x models may be added to the processor’s access time for external memory. Extra cycles inserted due to wait states are in addition to any cycles caused by multiple off-chip accesses. Wait state programming is described in the ADSP-218x DSP Hardware Reference, Chapter 8, “Memory Interface”.

ADSP-218x DSP Instruction Set Reference 4-27

Instruction Set Syntax

Wait states and multiple off-chip memory accesses are the two cases when an extra cycle is generated during instruction execution. The following case, SPORT autobuffering and DMA, causes the insertion of extra cycles between instructions.

SPORT Autobuffering and DMA

If serial port autobuffering or DMA is being used to transfer data words to or from internal memory, then one memory access is “stolen” for each transfer. The stolen memory access occurs only between complete instructions. If extra cycles are required to execute any instruction (for one of the two reasons above), the processor waits until it is completed before “stealing” the access cycle.

Instruction Set Syntax

The following sections describe instruction set syntax and other notation conventions used in the reference page of each instruction.

Punctuation and Multifunction Instructions

All instructions terminate with a semicolon. A comma separates the clauses of a multifunction instruction but does not terminate it. For example, the statements below in Example A comprise one multifunction instruction (which can execute in a single cycle). Example B shows two separate instructions, requiring two instruction cycles.

Example A: One multifunction instruction

/* a comma is used in multifunction instructions */

AX0 = DM(I0, M0), or AX0 = DM(I0, M0),AY0 = PM(I4, M4); AY0 = PM(I4, M4);

4-28 ADSP-218x DSP Instruction Set Reference

Instruction Set

Example B: Two separate instructions

/* a semicolon terminates an instruction */

AX0 = DM(I0, M0); AY0 = PM(I4, M4);

Syntax Notation Example

Here is an example of one instruction, the ALU Add/Add with Carry instruction:

[ IF cond ] AR = xop + yop ;

AF C

yop + C

The permissible conds, xops, and yops are given in a list. The conditional IF clause is enclosed in square brackets, indicating that it is optional.

The destination register for the add operation must be either AR or AF. These are listed within parallel bars, indicating that one of the two must be chosen.

Similarly, the yop term may consist of a Y operand, the carry bit, or the sum of both. One of these three terms must be used.

ADSP-218x DSP Instruction Set Reference 4-29

Instruction Set Syntax

Status Register Notation

The following notation is used in the discussion of the effect each instruction has on the processors’ status registers:

Table 4-11. Status Register Notation

Notation Meaning

* An asterisk indicates a bit in the status word that is changed by the execution

of the instruction.

– A dash indicates that a bit is not affected by the instruction.

0 or 1 Indicates that a bit is unconditionally cleared or set.

For example, the status word ASTAT is shown below:

ASTAT:76543210

SS MV AQ AS AC AV AN AZ

–*–––0––

Here the MV bit is updated and the AV bit is cleared.

4-30 ADSP-218x DSP Instruction Set Reference

ALU Instructions

ALU instructions are:

• “Add/Add With Carry” on page 4-32

• “Subtract X-Y/Subtract X-Y With Borrow” on page 4-35

• “Subtract Y-X/Subtract Y-X With Borrow” on page 4-39

• “Bitwise Logic: AND, OR, XOR” on page 4-42

• “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on

page 4-45

• “Clear: PASS” on page 4-48

Instruction Set

• “Syntax” on page 4-32

• “NOT” on page 4-54

• “Absolute Value: ABS” on page 4-56

• “Increment” on page 4-58

• “Decrement” on page 4-60

• “Divide Primitives: DIVS and DIVQ” on page 4-62

• “Generate ALU Status Only: NONE” on page 4-70

ADSP-218x DSP Instruction Set Reference 4-31

ALU Instructions

Add/Add With Carry

Syntax

[ IF cond ] AR = xop + yop ;

AF + C

+ yop + C

+ [constant]

+ [constant] + C

Permissible xops Permissible yops Permissible conds

AX0 AX1 AR

Permissible constants

1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767, -2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097,

-8193, -16385, -32768

MR2 MR1 MR0 SR1 SR0

AY0 AY1 AF

EQ NE GT GE LT

LE NEG POS AV NOT AV

AC NOT AC MV NOT MV NOT CE

Example

/* Conditional ADD with carry */ IF EQ AR = AX0 + AY0 + C;

/* Unconditional ADD */ AR = AR + 512;

/* ADD a negative constant */ AR = AX0 - 129; /* AR = AX0 + (- 129) */

/* 32 Bit Addition: AX1:AX0 = AX1:AX0 + AY1:AY0 */ DIS AR_SAT; /* If not already disabled */ AR = AX0 + AY0; /* Add low words */ AR = AX1 + AY1 + C, AX0 = AR; /* Add high words + carry */ AX1 = AR; /* Copy result if required */

4-32 ADSP-218x DSP Instruction Set Reference

Instruction Set

Description

Test the optional condition and, if true, perform the specified addition. If false then perform a no-operation. Omitting the condition performs the addition unconditionally. The addition operation adds the first source operand to the second source operand along with the ALU carry bit, AC, (if designated by the +C notation), using binary addition. The result is stored in the destination register. The operands are contained in the data registers or constant specified in the instruction.

Status Generated

(See Table 4-11 on page 4-30 for register notation)

ASTAT: 76543210

SS MV AQ AS AC AV AN AZ –––*** * *

AZ Set if the result equals zero. Cleared otherwise. AN Set if the result is negative. Cleared otherwise. AV Set if an arithmetic overflow occurs. Cleared otherwise. AC Set if a carry is generated. Cleared otherwise.

Instruction Format

Conditional ALU/MAC operation, Instruction Type 9:

23222120 191817161514131211109876543210 00100ZAMF Yop Xop 0000COND

AMF specifies the ALU or MAC operation, in this case:

AMF = 10010 for + yop + C AMF = 10011 for xop + yop

Note that xop + C is a special case of xop + yop + C with yop=0.

Z: Destination register Yop: Y operand

ADSP-218x DSP Instruction Set Reference 4-33

ALU Instructions

Xop: X operand COND: Condition

(xop + constant) Conditional ALU/MAC operation, Instruction Type 9:

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00100ZAMF YY Xop CC BO COND

AMF specifies the ALU or MAC operation, in this case:

AMF = 10010 for xop + constant + C AMF = 10011 for xop + constant

: Destination register COND: Condition

Xop: X operand

BO, CC, and YY specify the constant.

Subtract X-Y/Subtract X-Y With Borrow

Syntax

[ IF cond ] AR = xop – yop ;

AF – yop + C–1

+ C–1

– [constant]

– [constant] + C–1

Permissible xops Permissible yops Permissible status conditions

AX0 AX1 AR

Permissible constants

0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767, -2, -3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097,

-8193, -16385, -32768

MR2 MR1 MR0 SR1 SR0

AY0 AY1 AF

EQ NE GT GE LT

LE NEG POS AV NOT AV

Instruction Set

AC NOT AC MV NOT MV NOT CE

Example

/* Conditional subtraction */ IF GE AR = AX0 - AY0;

/* Subtraction of the negative value -17 */ AR = AX0 + 17; /* AR = AX0 -(-17) */

/* 32 Bit Subtraction: AX1:AX0 = AX1:AX0 - AY1:AY0 */ DIS AR_SAT; /* If not already disabled */ AR = AX0 - AY0; /* Subtract low words */ AR = AX1 - AY1 + C -1, AX0 = AR; /* Sub high words - borrow */ AX1 = AR; /* Copy result if required */

/* Negate MR Register MR = -MR */ DIS AR_SAT; /* If not already disabled */

ADSP-218x DSP Instruction Set Reference 4-35

ALU Instructions

AR = -MR0;/* Negate low word */ AR = -MR1 + C -1, MR0 = AR; /* Negate middle word - borrow */ AR = -MR2 + C -1, MR1 = AR; /* Negate high word minus borrow */ MR2 = AR;

Description

Test the optional condition and, if true, then perform the specified subtraction. If the condition is not true then perform a no-operation. Omitting the condition performs the subtraction unconditionally. The subtraction operation subtracts the second source operand from the first source operand, and optionally adds the ALU Carry bit (AC) minus 1 (0x0001), and stores the result in the destination register. The (C–1) quantity effectively implements a borrow capability for multiprecision subtractions. The operands are contained in the data registers or constant specified in the instruction.

Status Generated

(See Table 4-11 on page 4-30 for register notation)

ASTAT: 76543210

SS MV AQ AS AC AV AN AZ –––*** * *

Instruction Format

Conditional ALU/MAC operation, Instruction Type 9:

23222120 191817161514131211109876543210 00100ZAMF Yop Xop 0000COND

4-36 ADSP-218x DSP Instruction Set Reference

Datasheet ADSP-218x Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

INTRODUCTION

PROGRAMMING MODEL

SOFTWARE EXAMPLES

INSTRUCTION SET

INSTRUCTION CODING

INDEX

1 INTRODUCTION

Audience

Contents Overview

Development Tools

Additional Product Information

For Technical or Customer Support

What’s New in This Manual

Related Documents

Conventions

2 PROGRAMMING MODEL

Overview

Data Address Generators

Always Initialize L Registers

Program Sequencer

Interrupts

Loop Counts

Status and Mode Bits

Stacks

Computational Units

Bus Exchange

Timer

Serial Ports

Memory Interface and SPORT Enables

Program Example

Example Program: Setup Routine Discussion

Example Program: Interrupt Routine Discussion

Hardware Overlays and Software Issues

Libraries and Overlays

Interrupts and Overlays

Loop Hardware and Overlays

3 SOFTWARE EXAMPLES

Overview

System Development Process

Single-Precision Fir Transversal Filter

Cascaded Biquad IIR Filter

Sine Approximation

Single-Precision Matrix Multiply

Radix-2 Decimation-in-Time FFT

Main Module

DIT FFT Subroutine

Bit-Reverse Subroutine

Block Floating-Point Scaling Subroutine

4 INSTRUCTION SET

Quick List Of Instructions

Instruction Set Overview

Multifunction Instructions

ALU/MAC With Data and Program Memory Read

Data and Program Memory Read

Computation With Memory Read

Computation With Memory Write

Computation With Data Register Move

ALU, MAC and Shifter Instructions

ALU Group

MAC Group

Shifter Group

MOVE: Read and Write Instructions

Program Flow Control

Miscellaneous Instructions

Extra Cycle Conditions

Multiple Off-Chip Memory Accesses

Wait States

Instruction Set Syntax

SPORT Autobuffering and DMA

Punctuation and Multifunction Instructions

Syntax Notation Example

Status Register Notation

ALU Instructions

Add/Add With Carry

Subtract X-Y/Subtract X-Y With Borrow