Analog Devices ADSP-2186L Datasheet

a

DSP Microcomputer

ADSP-2186L

FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained

Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition
Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction

Set Extensions
40K Bytes of On-Chip RAM, Configured as

8K Words On-Chip Program Memory RAM and

8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction

and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction

Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
144-Ball Mini-BGA

SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data

Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design

(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port
Six External Interrupts

ICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTERMACALU

CONTROL

MEMORY

8K ⴛ 24

PROGRAM

MEMORY

SERIAL PORTS

8K ⴛ 16

DATA

MEMORY

SPORT 1SPORT 0

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

13 Programmable Flag Pins Provide Flexible System

Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

GENERAL NOTE

This data sheet represents production grade specifications for
the ADSP-2186L (3.3 V) processor.

GENERAL DESCRIPTION

The ADSP-2186L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.

The ADSP-2186L combines the ADSP-2100 family base archi­tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.

The ADSP-2186L integrates 40K bytes of on-chip memory
configured as 8K words (24-bit) of program RAM and 8K
words (16-bit) of data RAM. Power-down circuitry is also pro­vided to meet the low power needs of battery operated portable
equipment. The ADSP-2186L is available in a 100-lead LQFP
and 144-ball mini-BGA packages.

In addition, the ADSP-2186L supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans­fers and global interrupt masking for increased flexibility.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADSP-2186L

Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186L operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.

The ADSP-21xx family DSPs contain a shadow bank register
that is useful for single cycle context switching of the processor.

The ADSP-2186L’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera­tions in parallel. In one processor cycle the ADSP-2186L can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup­ports the ADSP-2186L. The System Builder provides a high
level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction­level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186L assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft­ware design. The EZ-KIT Lite includes the following features:

• 33 MHz ADSP-2181

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort

• RS-232 Interface to PC with Windows

• EZ-ICE

®

Connector for Emulator Control

®

3.1 Control Software

• DSP Demo Programs

• Code compatible with all 218x products

The ADSP-218x EZ-ICE

Emulator aids in the hardware debug­ging of an ADSP-2186L system. The emulator consists of hard­ware, host computer resident software, and the target board
connector. The ADSP-2186L integrates on-chip emulation
support with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-ICEs.
The ADSP-2186L device need not be removed from the target
system when using the EZ-ICE, nor are any adapters needed. Due
to the small footprint of the EZ-ICE connector, emulation can
be supported in final board designs.

SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.

®

Codec

–2–

The EZ-ICE

performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE

Probe section
of this data sheet, for the exact specifications of the EZ-ICE
target board connector.

Additional Information

This data sheet provides a general overview of ADSP-2186L
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2186L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro­cessor cycle. The ADSP-2186L assembly language uses an alge­braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTERMACALU

CONTROL

MEMORY

8K ⴛ 24

PROGRAM

MEMORY

SERIAL PORTS

8K ⴛ 16

DATA

MEMORY

SPORT 1SPORT 0

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

Figure 1. Block Diagram

Figure 1 is an overall block diagram of the ADSP-2186L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi­sions to support multiprecision computations. The ALU per­forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith­metic shifts, normalization, denormalization and derive expo­nent operations.

The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.

REV. A

ADSP-2186L

The internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps, sub­routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2186L executes looped
code with zero overhead; no explicit jump instructions are re­quired to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro­gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos­sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit­ting the ADSP-2186L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2186L can fetch an operand from program memory and
the next instruction in the same cycle.

When configured in host mode, the ADSP-2186L has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. The IDMA port is made up of 16 data/address pins
and five control pins. The IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH and BG). One execution mode (Go Mode) allows
the ADSP-2186L to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.

The ADSP-2186L can respond to 11 interrupts. There are up to
six external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORTs), the Byte DMA port and
the power-down circuitry. There is also a master RESET inter­rupt. The two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide

REV. A

–3–

variety of framed or frameless data transmit and receive modes
of operation.

Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2186L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycles, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2186L incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2186L SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual, Third Edition.

• SPORTs are bidirectional and have a separate, double-buff­ered transmit and receive section.

• SPORTs can use an external serial clock or generate their own
serial clock internally.

• SPORTs have independent framing for the receive and trans­mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.

• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.

PIN DESCRIPTIONS

The ADSP-2186L is available in a 100-lead LQFP and a 144-ball
Mini-BGA package. In order to maintain maximum functionality
and reduce package size and pin count, some serial port, pro­grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config­ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown in
italics.

ADSP-2186L

Common-Mode Pins

# Input/
Pin of Out­Name(s) Pins put Function

RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2/ 1 I Edge- or Level-Sensitive

Interrupt Request

1

PF7 I/O Programmable I/O Pin
IRQL0/ 1 I Level-Sensitive Interrupt Requests

1

PF5 I/O Programmable I/O Pin
IRQL1/ 1 I Level-Sensitive Interrupt Requests

1

PF6 I/O Programmable I/O Pin
IRQE/ 1 I Edge-Sensitive Interrupt Requests

1

PF4 I/O Programmable I/O Pin
PF3 1 I/O Programmable I/O Pin

Mode C/ 1 I Mode Select Input—Checked

only During RESET

PF2 I/O Programmable I/O Pin During

Normal Operation

Mode B/ 1 I Mode Select Input—Checked

only During RESET

PF1 I/O Programmable I/O Pin During

Normal Operation

Mode A/ 1 I Mode Select Input—Checked

only During RESET

PF0 I/O Programmable I/O Pin During

Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins

IRQ1:0 Edge- or Level-Sensitive Interrupts,
FI, FO Flag In, Flag Out

2

PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
V

and GND 16 I Power and Ground

DD

EZ-Port 9 I/O For Emulation Use

NOTES

1

Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.

2

SPORT configuration determined by the DSP System Control Register. Soft­ware configurable.

3

See Designing an EZ-ICE-Compatible System in this data sheet for complete
information.

3

Memory Interface Pins

The ADSP-2186L processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capabili­ties. The operating mode is determined by the state of the Mode C
pin during reset and cannot be changed while the processor is
running. (See Table VI for complete mode operation descriptions.)

Full Memory Mode Pins (Mode C = 0)

#
of Input/

Pin Name Pins Output Function

A13:0 14 O Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

D23:0 24 I/O Data I/O Pins for Program,

Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)

Host Mode Pins (Mode C = 1)

#
of Input/

Pin Name Pins Output Function

IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O,

Program, Data or Byte Access

D23:8 16 I/O Data I/O Pins for Program,

Data Byte and I/O Spaces

IWR 1 I IDMA Write Enable
IRD 1 I IDMA Read Enable

IAL 1 I IDMA Address Latch Pin

IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge

In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.

Setting Memory Mode

Memory Mode selection for the ADSP-2186L is made during
chip reset through the use of the Mode C pin. This pin is multi­plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.

Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.

Active configuration involves the use of a three-stateable exter­nal driver connected to the Mode C pin. A driver’s output en­able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow­ing full use of the PF2 pin as either an input or output.

–4–

REV. A

ADSP-2186L

To minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three­stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.

Interrupts

The interrupt controller allows the processor to respond to the
thirteen possible interrupts (eleven of which can be enabled
at any one time), and RESET with minimum overhead. The
ADSP-2186L provides four dedicated external interrupt input
pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4
pins). In addition, SPORT1 may be reconfigured for IRQ0,
IRQ1, FLAG_IN and FLAG_OUT, for a total of six external
interrupts. The ADSP-2186L also supports internal interrupts
from the timer, the byte DMA port, the two serial ports, soft­ware and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
power-down and RESET). The IRQ2, IRQ0 and IRQ1 input
pins can be programmed to be either level- or edge-sensitive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
The priorities and vector addresses of all interrupts are shown in
Table I.

Table I. Interrupt Priority and Interrupt Vector Addresses

Source Of Interrupt Interrupt Vector Address (Hex)

RESET (or Power-Up with

PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable) 002C

IRQ2 0004
IRQL1 0008
IRQL0 000C

SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter­rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.

The ADSP-2186L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest­ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts.

On-chip stacks preserve the processor status and are automati­cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servic­ing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2186L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

• Power-Down

•Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

Power-Down

The ADSP-2186L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Following is a brief list of power­down features. Refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter, for detailed informa­tion about the power-down feature.

• Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.

• Support for an externally generated TTL or CMOS proces­sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
400 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi­mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 400 CLKIN
cycle start-up.

• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit.

• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The power­down interrupt also can be used as a nonmaskable, edge­sensitive interrupt.

• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge (PWDACK) pin indicates when
the processor has entered power-down.

REV. A

–5–

ADSP-2186L

Idle

When the ADSP-2186L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2186L to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program­mable fraction of the normal clock rate, is specified by a select­able divisor given in the IDLE instruction. The format of the
instruction is:

IDLE (n)

where n = 16, 32, 64 or 128. This instruction keeps the proces­sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals such
as SCLK, CLKOUT and timer clock, are reduced by the same
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in­coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2186L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the
ADSP-2186L, two serial devices, a byte-wide EPROM and op­tional external program and data overlay memories (mode select­able). Programmable wait state generation allows the processor
to connect easily to slow peripheral devices. The ADSP-2186L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

SYSTEM

INTERFACE

OR

␮CONTROLLER

FULL MEMORY MODE

ADSP-2186L

CLKIN

XTAL

FL0–2
PF3

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

MODE C/PF2
MODE B/PF1
MODE A/PF0

SPORT1

SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

HOST MEMORY MODE

ADSP-2186L

CLKIN

XTAL

FL0–2
PF3

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

MODE C/PF2
MODE B/PF1
MODE A/PF0

SPORT1

SCLK1

RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OOR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

IDMA PORT

IRD/D6
IWR/D7
IS/D4

IAL/D5
IACK/D3

16

IAD15–0

ADDR13–0

DATA23–0

BMS

WR

IOMS

PMS
DMS
CMS

BGH

PWD

PWDACK

DATA23–8

BMS

IOMS

PMS
DMS
CMS

BGH

PWD

PWDACK

WR

RD

BR
BG

A0

RD

BR
BG

A

14

24

1

16

13–0

D

A0–A21

23–16

D

15–8

DATA

CS

A

10–0

ADDR

D

23–8

DATA

CS

A

13–0

ADDR

D

23–0

DATA

Figure 2. Basic System Configuration

BYTE

MEMORY

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

–6–

REV. A

ADSP-2186L

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MODE B = 0)

0x3FFF

0x2000

0x1FFF

8K INTERNAL

0x0000

PROGRAM MEMORY ADDRESS

Clock Signals

The ADSP-2186L can be clocked by either a crystal or a
TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera­tion. The only exception is while the processor is in the power­down state. For additional information on the power-down
feature, refer to the ADSP-2100 Family User’s Manual, Third
Edition.

If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con­nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.

The ADSP-2186L uses an input clock with a frequency equal to
half the instruction rate; a 0.20 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.

Because the ADSP-2186L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors con­nected as shown in Figure 3. Capacitor values are dependent on
crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor­grade crystal should be used.

A clock output (CLKOUT) signal is generated by the proces­sor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.

Reset

The RESET signal initiates a master reset of the ADSP-2186L.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini­mum pulsewidth specification, t

The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, an external Schmidt
trigger is recommended.

REV. A

CLKIN CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

.

RSP

DD

The master RESET sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes. In an EZ-ICE-compatible system RESET and
ERESET have the same functionality. For complete information,
see Designing an EZ-ICE-Compatible System section.

MEMORY ARCHITECTURE

The ADSP-2186L provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O.

Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The ADSP-2186L
has 8K words of Program Memory RAM on chip, and the capabil­ity of accessing up to two 8K external memory overlay spaces using
the external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.

Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2186L has 8K words on Data
Memory RAM on chip, consisting of 8160 user-accessible
locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus.

Byte Memory (Full Memory Mode) provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port.
The Byte Memory interface provides access to 4 MBytes of
memory by utilizing eight data lines as additional address lines.
This gives the BDMA Port an effective 22-bit address range. On
power-up, the DSP can automatically load bootstrap code from
byte memory.

I/O Space (Full Memory Mode) allows access to 2048 loca­tions of 16-bit-wide data. It is intended to be used to communi­cate with parallel peripheral devices such as data converters and
external registers or latches.

Program Memory

The ADSP-2186L contains an 8K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2186L allows the use of 8K
external memory overlays.

The program memory space organization is controlled by the
Mode B pin and the PMOVLAY register. Normally, the ADSP­2186L is configured with Mode B = 0 and program memory
organized as shown in Figure 4.

is

Figure 4. Program Memory (Mode B = 0)

–7–

ADSP-2186L

There are 8K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to some­thing other than 0, external accesses occur at addresses 0x2000
through 0x3FFF. The external address is generated as shown
in Table II.

Table II. PMOVLAY Addressing

PMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable
1 External 13 LSBs of Address

Overlay 1 0 Between 0x2000

and 0x3FFF

2 External 13 LSBs of Address

Overlay 2 1 Between 0x2000

and 0x3FFF

NOTE: Addresses 0x2000 through 0x3FFF should not be accessed when
PMOVLAY = 0.

This organization provides for two external 8K overlay segments
using only the normal 14 address bits, which allows for simple
program overlays using one of the two external segments in place
of the on-chip memory. Care must be taken in using this overlay
space in that the processor core (i.e., the sequencer) does not take
into account the PMOVLAY register value. For example, if a loop
operation is occurring on one of the external overlays and the
program changes to another external overlay or internal memory,
an incorrect loop operation could occur. In addition, care must
be taken in interrupt service routines as the overlay registers are
not automatically saved and restored on the processor mode stack.

When Mode B = 1, booting is disabled and overlay memory is
disabled (PMOVLAY must be 0). Figure 5 shows the memory
map in this configuration.

PROGRAM MEMORY

RESERVED

8K EXTERNAL

ADDRESS

0x3FFF

0x2000
0x1FFF

0x0000

Figure 5. Program Memory (Mode B = 1)

Data Memory

The ADSP-2186L has 8160 16-bit words of internal data memory.
In addition, the ADSP-2186L allows the use of 8K external
memory overlays. Figure 6 shows the organization of the data
memory.

DATA MEMORY

32 MEMORY–

MAPPED REGISTERS

INTERNAL

8160 WORDS

EXTERNAL 8K

(DMOVLAY = 1, 2)

ADDRESS

0x3FFF

0x3FEO

0x3FDF

0x2000

0x1FFF

0x0000

Figure 6. Data Memory

–8–

There are 8160 words of memory accessible internally when the
DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.

Table III. DMOVLAY Addressing

DMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable
1 External 13 LSBs of Address

Overlay 1 0 Between 0x0000

and 0x1FFF

2 External 13 LSBs of Address

Overlay 2 1 Between 0x0000

and 0x1FFF

This organization allows for two external 8K overlays using only
the normal 14 address bits. All internal accesses complete in one
cycle. Accesses to external memory are timed using the wait
states specified by the DWAIT register.

I/O Space (Full Memory Mode)

The ADSP-2186L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals or to bus interface ASIC data regis­ters. I/O space supports 2048 locations. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP­2100 Family instruction set to read from and write to I/O
memory space. The I/O space also has four dedicated three-bit
wait state registers, IOWAIT0-3, that specify up to seven wait
states to be automatically generated for each of four regions.
The wait states act on address ranges as shown in Table IV.

Table IV.

Address Range Wait State Register

0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3

Composite Memory Select (CMS)

The ADSP-2186L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS), but can combine their
functionality.

Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as­serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory and use either DMS or PMS as the additional
address bit.

The CMS pin functions as the other memory select signal, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.

REV. A

ADSP-2186L

Boot Memory Select (BMS) Disable

The ADSP-2186L also lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for BDMA
transfers and BMS to select the second external memory space
for booting. The BMS signal can be disabled by setting Bit 3 of
the System Control Register to 1. The System Control Register
is illustrated in Figure 7.

15 14 13 12 11 10

00 00 01 00 00 0 00 11 1

SPORT0 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

SYSTEM CONTROL REGISTER

9876543210

DM (0ⴛ3FFF)

PWAIT
PROGRAM MEMORY
WAIT STATES

BMS ENABLE
0 = ENABLED, 1 = DISABLED

Figure 7. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 8. The byte memory space consists of 256 pages,
each of which is 16K × 8.

1514131211109876543210

00000000000 01000

BMPAGE

BDMA CONTROL

DM (0ⴛ3FE3)

BTYPE

BDIR
0 = LOAD FROM BM
1 = STORE TO BM

BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA

Figure 8. BDMA Control Register

The byte memory space on the ADSP-2186L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats, that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses is determined from the byte memory space to
build the word size selected. Table V shows the data formats sup­ported by the BDMA circuit.

Table V. BDMA Data Formats

Internal

BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. Finally the 14-bit BWCOUNT
register specifies the number of DSP words to transfer and
initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener­ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.

When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera­tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write directly to the DSP’s
memory-mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com­pletely asynchronous and can be written to while the ADSP­2186L is operating at full speed.

REV. A

–9–

ADSP-2186L

The DSP memory address is latched and then automatically incre­mented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.

Once the address is stored, data can then either be read from or
written to the ADSP-2186L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2186L that a particular
transaction is required. In either case, there is a one-processor­cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati­cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2186L has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits as shown in Table VI. These four states can be compressed
into two-state bits by allowing an IDMA boot with Mode C = 1.
However, three bits are used to ensure future compatibility with
parts containing internal program memory ROM.

BDMA Booting

When the MODE pins specify BDMA booting, the ADSP-2186L
initiates a BDMA boot sequence when RESET is released.

The BDMA interface is set up during reset to the following de­faults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0; the BTYPE register is
set to 0 to specify program memory 24-bit words; and the
BWCOUNT register is set to 32. This causes 32 words of on­chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program
execution to be held off until all 32 words are loaded into on-chip
program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad­dresses to boot memory must be constructed externally to the
ADSP-2186L. The only memory address bit provided by the
processor is A0.

Table VI. Boot Summary Table

MODE C MODE B MODE A Booting Method

0 0 0 BDMA feature is used to load

the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Full Memory
Mode.

010No Automatic boot opera-

tions occur. Program execu­tion starts at external memory
location 0. Chip is config­ured in Full Memory Mode.
BDMA can still be used but
the processor does not auto­matically use or wait for these
operations.

1 0 0 BDMA feature is used to load

the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Host Mode.
Additional interface hardware
is required.

101IDMA feature is used to load

any internal memory as de­sired. Program execution is
held off until internal pro­gram memory location 0 is
written to. Chip is configured
in Host Mode.

IDMA Booting

The ADSP-2186L can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186L boots from the IDMA port. The IDMA feature
can load as much on-chip memory as desired. Program execu­tion is held off until on-chip program memory location 0 is
written to.

Bus Request and Bus Grant

The ADSP-2186L can relinquish control of the data and ad­dress buses to an external device. When the external device
requires access to memory, it asserts the bus request (BR) sig­nal. If the ADSP-2186L is not performing an external memory
access, it responds to the active BR input in the following pro­cessor cycle by:

• Three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

–10–

REV. A

ADSP-2186L

If Go Mode is enabled, the ADSP-2186L will not halt program
execution until it encounters an instruction that requires an
external memory access.

If the ADSP-2186L is performing an external memory access
when the external device asserts the BR signal, it will not three­state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.

When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2186L is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2186L deasserts BG and BGH and executes the external
memory access.

Flag I/O Pins

The ADSP-2186L has eight general purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-2186L’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2186L has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.

Note: Pins PF0, PF1 and PF2 are also used for device configu­ration during reset.

BIASED ROUNDING

A mode is available on the ADSP-2186 or ADSP-2186L to allow
biased rounding in addition to the normal unbiased rounding.
When the BIASRND bit is set to 0, the normal unbiased round­ing operations occur. When the BIASRND bit is set to 1, biased
rounding occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.

For example:

Table VII. Biased Rounding Example

MR Value Biased Unbiased
Before RND RND Result RND Result

00-0000-8000 00-0001-8000 00-0000-8000
00-0001-8000 00-0002-8000 00-0002-8000
00-0000-8001 00-0001-8001 00-0001-8001
00-0001-8001 00-0002-8001 00-0002-8001
00-0000-7FFF 00-0000-7FFF 00-0000-7FFF
00-0001-7FFF 00-0001-7FFF 00-0001-7FFF

This mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. This
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.

Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.

INSTRUCTION SET DESCRIPTION

The ADSP-2186L assembly language instruction set has an
algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.

• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan­guage and is completely source and object code compatible
with other family members. Programs may need to be relo­cated to utilize on-chip memory and conform to the ADSP­2186L’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2186L has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface.

If using a passive method of maintaining mode information (as
discussed in Setting Memory Modes), it does not matter that
the mode information is latched by an emulator reset. However,
if using the RESET pin as a method of setting the value of the
mode pins, the effects of an emulator reset must be taken into
consideration.

One method of ensuring that the values located on the mode
pins are the desired values is to construct a circuit like the one
shown in Figure 9. This circuit forces the value located on the
Mode A pin to logic low, regardless if it latched via the RESET
or ERESET pin.

REV. A

–11–

ADSP-2186L

ERESET

RESET

1k⍀

ADSP-2186L

MODE A/PF0

PROGRAMMABLE I/O

Figure 9. Boot Mode Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.

The ICE-Port interface consists of the following ADSP-2186L
pins:

EBR EBG ERESET
EMS EINT ECLK

ELIN ELOUT EE

These ADSP-2186L pins are usually connected only to the
EZ-ICE

connector in the target system. These pins have no
function except during emulation, and do not require pull-up
or pull-down resistors. The traces for these signals between
the ADSP-2186L and the connector must be kept as short as
possible, no longer than three inches.

The following pins are also used by the EZ-ICE:

BR BG
RESET GND

The EZ-ICE

uses the EE (emulator enable) signal to take con-

trol of the ADSP-2186L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow
enough room in your system to fit the EZ-ICE probe onto the
14-pin connector.

GND

EBG

EBR

KEY (NO PIN)

ELOUT

EE

RESET

12

34

56

7

910

11 12

13 14

TOP VIEW

BG

BR

EINT

8

ELIN

ECLK

EMS

ERESET

Figure 10. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca­tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac­ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emu­lator, it must comply with the memory interface guidelines listed
below.

PM, DM, BM, IOM, and CM

Design Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim­ing requirements and switching characteristics as specified in
this DSP’s data sheet. The performance of the EZ-ICE may ap­proach published worst case specification for some memory
access timing requirements and switching characteristics.

Note: If your target does not meet the worst case chip specifica­tions for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend­ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti­cally vary in switching characteristics and timing requirements
within published limits.

Restriction: All memory strobe signals on the ADSP-2186L
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE

is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance of some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE

• EZ-ICE

board:

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the RESET signal.

• EZ-ICE

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the BR signal.

• EZ-ICE

emulation ignores RESET and BR when single-

stepping.

• EZ-ICE

emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE

emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE

board’s DSP.

–12–

REV. A

ADSP-2186L

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade B Grade

Parameter Min Max Min Max Unit

V

DD

T

AMB

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typ Max Unit

V
V
V
V

V

I

IH

I

IL

I

OZH

I

OZL

I

DD

I

DD

C

C

IH

IH

IL

OH

OL

I

O

Hi-Level Input Voltage
Hi-Level CLKIN Voltage @ VDD = max 2.2 V
Lo-Level Input Voltage
Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Three-State Leakage Current

Three-State Leakage Current

Supply Current (Idle)
Supply Current (Dynamic)

Input Pin Capacitance

Output Pin Capacitance

3.0 3.6 3.0 3.6 V
0 +70 –40 +85 °C

K/B Grades

1, 2

1, 3

1, 4, 5

1, 4, 5

3

3

7

7

9

10

3, 6, 12

6, 7, 12, 13

@ VDD = max 2.0 V

@ VDD = min 0.8 V
@ VDD = min
I

= –0.5 mA 2.4 V

OH

= min

@ V

DD

I

= –100 µA

OH

6

VDD – 0.3 V

@ VDD = min

= 2 mA 0.4 V

I

OL

@ VDD = max
V

= VDDmax 10 µA

IN

@ VDD = max
V

= 0 V 10 µA

IN

@ VDD = max

= VDDmax

V

IN

@ VDD = max
V

= 0 V

IN

8

8

10 µA

10 µA
@ VDD = 3.3 8.6 mA
@ VDD = 3.3
T

= +25°C

AMB

= 25 ns

t

CK

11

42 mA
@ VIN = 2.5 V,
f

= 1.0 MHz,

IN

= +25°C8pF

T

AMB

@ VIN = 2.5 V,
f

= 1.0 MHz,

IN

T

= +25°C8pF

AMB

NOTES

1

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

2

Input only pins: RESET, BR, DR0, DR1, PWD.

3

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

5

Although specified for TTL outputs, all ADSP-2186L outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

6

Guaranteed but not tested.

7

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

8

0 V on BR, CLKIN Inactive.

9

Idle refers to ADSP-2186L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

10

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.

11

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

12

Applies to LQFP package type.

13

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. A

–13–

or GND.

DD

ADSP-2186L

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V

Operating Temperature Range (Ambient) . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2186L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

+ 0.5 V

DD

+ 0.5 V

DD

TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.

Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements must be met to guarantee
that the processor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2186L timing parameters, for
your convenience.

Memory ADSP-2186L Timing
Device Timing Parameter
Specification Parameter Definition

Address Setup to t

ASW

A0–A13, xMS Setup

Write Start before WR Low

Address Setup to t

AW

A0–A13, xMS Setup

Write End before WR Deasserted

Address Hold Time t

WRA

A0–A13, xMS Hold
before WR Low

Data Setup Time t

DW

Data Setup before WR
High

Data Hold Time t

DH

Data Hold after WR
High

OE to Data Valid t

Address Access Time t

RDD

AA

RD Low to Data Valid
A0–A13, xMS to Data

Valid

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS

tCK is defined as 0.5 t

. The ADSP-2186L uses an input clock

CKI

with a frequency equal to half the instruction rate: a 20 MHz
input clock (which is equivalent to 50 ns) yields a 25 ns proces­sor cycle (equivalent to 40 MHz). t

0.5 t

period should be substituted for all relevant timing para-

CKI

values within the range of

CK

meters to obtain the specification value.

Example: t

= 0.5 tCK – 7 ns = 0.5 (25 ns) – 7 ns = 5.5 ns

CKH

–14–

REV. A

ADSP-2186L

TIMING PARAMETERS

Parameter Min Max Unit

Clock Signals and Reset

Timing Requirements:
t

CKI

t

CKIL

t

CKIH

Switching Characteristics:

t

CKL

t

CKH

t

CKOH

Control Signals

CLKIN Period 50 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns

CLKOUT Width Low 0.5 t
CLKOUT Width High 0.5 t

– 7 ns

CK

– 7 ns

CK

CLKIN High to CLKOUT High 0 20 ns

Timing Requirements:
t

RSP

t

MS

t

MH

NOTE

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

RESET Width Low
Mode Setup Before RESET High 2 ns
Mode Setup After RESET High 5 ns

CLKOUT

PF(2:0)

CLKIN

RESET

1

t

CKI

t

CKIL

t

CKL

*

t

MS

5 t

CK

t

CKIH

t

CKOH

t

CKH

t

MH

ns

REV. A

*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 11. Clock Signals

–15–

t

RSP

ADSP-2186L

TIMING PARAMETERS

Parameter Min Max Unit

Interrupts and Flag

Timing Requirements:
t
t

IFS

IFH

IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High

Switching Characteristics:
t

FOH

t

FOD

NOTES

1

If IRQx and FI inputs meet t
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further
information on interrupt servicing.)

2

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5

Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low

and t

IFS

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

IFH

CLKOUT

FLAG

OUTPUTS

IRQx

FI

PFx

1, 2, 3, 4

1, 2, 3, 4

5

5

t

FOD

t

FOH

t

IFH

0.25 tCK + 15 ns

0.25 t

CK

0.25 tCK – 7 ns

0.5 t

+ 6 ns

CK

t

IFS

ns

Figure 12. Interrupts and Flags

–16–

REV. A

ADSP-2186L

Parameter Min Max Unit

Bus Request–Bus Grant

Timing Requirements:
t

BH

t

BS

BR Hold after CLKOUT High
BR Setup before CLKOUT Low

1

1

0.25 tCK + 2 ns

0.25 tCK + 17 ns

Switching Characteristics:
t

SD

t

SDB

t

SE

t

SEC

t

SDBH

t

SEH

NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.

1

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.

2

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT High to xMS, RD, WR Disable 0.25 tCK + 10 ns

xMS, RD, WR Disable to BG Low 0 ns
BG High to xMS, RD, WR Enable 0 ns
xMS, RD, WR Enable to CLKOUT High 0.25 tCK – 7 ns
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable

CLKOUT

BR

2

2

t

BH

t

BS

0ns
0ns

CLKOUT

PMS, DMS

BMS, RD

WR

BG

BGH

t

SD

t

SDB

t

SDBH

Figure 13. Bus Request–Bus Grant

t

t

SE

SEH

t

SEC

REV. A

–17–

ADSP-2186L
TIMING PARAMETERS

Parameter Min Max Unit

Memory Read

Timing Requirements:
t

RDD

t

AA

t

RDH

Switching Characteristics:
t

RP

t

CRD

t

ASR

t

RDA

t

RWR

w = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

RD Low to Data Valid 0.5 tCK – 9 + w ns

A0–A13, xMS to Data Valid 0.75 tCK – 12.5 + w ns
Data Hold from RD High 1 ns

RD Pulsewidth 0.5 tCK – 5 + w ns
CLKOUT High to RD Low 0.25 tCK – 5 0.25 tCK + 7 ns
A0–A13, xMS Setup before RD Low 0.25 tCK – 6 ns
A0–A13, xMS Hold after RD Deasserted 0.25 tCK – 3 ns
RD High to RD or WR Low 0.5 t

CLKOUT

A0–A13

– 5 ns

CK

DMS, PMS,

BMS, IOMS,

CMS

RD

D0–D23

WR

t

t

CRD

ASR

t

AA

t

RDD

t

RP

Figure 14. Memory Read

t

RDA

t

RDH

t

RWR

–18–

REV. A

ADSP-2186L

Parameter Min Max Unit

Memory Write

Switching Characteristics:
t

DW

t

DH

t

WP

t

WDE

t

ASW

t

DDR

t

CWR

t

AW

t

WRA

t

WWR

w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.

Data Setup before WR High 0.5 t
Data Hold after WR High 0.25 t

WR Pulsewidth 0.5 tCK – 5 + w ns
WR Low to Data Enabled 0 ns

A0–A13, xMS Setup before WR Low 0.25 t
Data Disable before WR or RD Low 0.25 tCK – 7 ns
CLKOUT High to WR Low 0.25 t
A0–A13, xMS, Setup before WR Deasserted 0.75 t
A0–A13, xMS Hold after WR Deasserted 0.25 t
WR High to RD or WR Low 0.5 tCK – 5 ns

CLKOUT

– 7+ w ns

CK

– 2 ns

CK

– 6 ns

CK

– 5 0.25 tCK + 7 ns

CK

– 9 + w ns

CK

– 3 ns

CK

A0–A13

DMS, PMS,
BMS, CMS,

IOMS

WR

D0–D23

RD

t

CWR

t

ASW

t

WDE

t

WP

t

AW

t

DW

Figure 15. Memory Write

t

WRA

t

WWR

t

DH

t

DDR

REV. A

–19–

ADSP-2186L

TIMING PARAMETERS

Parameter Min Max Unit

Serial Ports

Timing Requirements:
t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics:
t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

TDE

t

TDV

t

SCDD

t

RDV

SCLK Period 50 ns
DR/TFS/RFS Setup before SCLK Low 4 ns
DR/TFS/RFS Hold after SCLK Low 8 ns
SCLK

CLKOUT High to SCLK

Width 20 ns

IN

OUT

0.25 t

CK

0.25 t

+ 10 ns

CK

SCLK High to DT Enable 0 ns
SCLK High to DT Valid 15 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 15 ns

OUT

DT Hold after SCLK High 0 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 14 ns
SCLK High to DT Disable 15 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns

CLKOUT

SCLK

DR
TFS
RFS

RFS

OUT

TFS

OUT

DT

TFS

OUT

ALTERNATE

FRAME MODE

RFS

MULTICHANNEL MODE,

MULTICHANNEL MODE,

OUT

FRAME DELAY 0

(MFD = 0)

TFS

ALTERNATE

FRAME MODE

RFS

FRAME DELAY 0

(MFD = 0)

t

CC

IN
IN

IN

IN

t

SCDE

t

t

RH

t

t

TDE

t

TDE

RD

SCDV

t

TDV

t

RDV

t

TDV

t

RDV

t

CC

t

t

SCS

SCH

t

t

SCDH

SCDD

t

SCK

t

SCP

t

SCP

Figure 16. Serial Ports

–20–

REV. A

ADSP-2186L

Parameter Min Max Unit

IDMA Address Latch

Timing Requirements:
t

IALP

t

IASU

t

IAH

t

IKA

t

IALS

NOTES

1

Start of Address Latch = IS Low and IAL High.

2

Start of Write or Read = IS Low and IWR Low or IRD Low.

3

End of Address Latch = IS High or IAL Low.

Duration of Address Latch
IAD15–0 Address Setup before Address Latch End
IAD15–0 Address Hold after Address Latch End
IACK Low before Start of Address Latch
Start of Write or Read after Address Latch End

IACK

IAL

IS

IAD15–0

IRD

OR

IWR

1, 3

3

3

2, 3

2, 3

t

IKA

t

IALP

t

IASU

t

t

IALS

10 ns
5ns
3ns
0ns
3ns

IAH

Figure 17. IDMA Address Latch

REV. A

–21–

ADSP-2186L

TIMING PARAMETERS

Parameter Min Max Unit

IDMA Write, Short Write Cycle

Timing Requirements:
t

IKW

t

IWP

t

IDSU

t

IDH

IACK Low before Start of Write
Duration of Write

1, 2

IAD15–0 Data Setup before End of Write
IAD15–0 Data Hold after End of Write

Switching Characteristics:
t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

End of Write = IS High or IWR High.

3

If Write Pulse ends before IACK Low, use specifications t

4

If Write Pulse ends after IACK Low, use specifications t

Start of Write to IACK High 17 ns

IACK

IS

IWR

1

IKSU

IDSU

0ns

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

t

IWP

t

IDSU

15 ns
5ns
2ns

t

IDH

IAD15–0

DATA

Figure 18. IDMA Write, Short Write Cycle

–22–

REV. A

ADSP-2186L

Parameter Min Max Unit

IDMA Write, Long Write Cycle

Timing Requirements:
t

IKW

t

IKSU

t

IKH

IACK Low before Start of Write
IAD15–0 Data Setup before IACK Low
IAD15–0 Data Hold after IACK Low

Switching Characteristics:
t

IKLW

t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

If Write Pulse ends before IACK Low, use specifications t

3

If Write Pulse ends after IACK Low, use specifications t

4

This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.

Start of Write to IACK Low
Start of Write to IACK High 17 ns

IACK

IS

4

IKSU

IDSU

1

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

0ns

0.5 tCK + 10 ns
2ns

t

IKLW

1.5 t

CK

ns

IWR

IAD15–0

t

IKSU

DATA

t

IKH

Figure 19. IDMA Write, Long Write Cycle

REV. A

–23–

ADSP-2186L

TIMING PARAMETERS

Parameter Min Max Unit

IDMA Read, Long Read Cycle

Timing Requirements:
t
t

IKR

IRK

IACK Low before Start of Read
End of Read after IACK Low 2 ns

Switching Characteristics:
t

IKHR

t

IKDS

t

IKDH

t

IKDD

t

IRDE

t

IRDV

t

IRDH1

t

IRDH2

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

3

DM read or first half of PM read.

4

Second half of PM read.

IACK High after Start of Read
IAD15–0 Data Setup before IACK Low 0.5 tCK – 10 ns
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)
IAD15–0 Previous Data Hold after Start of Read (PM2)

IACK

1

1

2

2

3

4

t

t

IKR

IS

IKHR

0ns

17 ns

0ns

10 ns

2 tCK – 5 ns
tCK – 5 ns

IRD

IAD15–0

t

IRK

t

t

IRDE

t

IRDV

PREVIOUS

DATA

t

IRDH

IKDS

READ
DATA

Figure 20. IDMA Read, Long Read Cycle

t

IKDD

t

IKDH

–24–

REV. A

ADSP-2186L

Parameter Min Max Unit

IDMA Read, Short Read Cycle

Timing Requirements:
t
t

IKR

IRP

IACK Low before Start of Read
Duration of Read 15 ns

Switching Characteristics:
t

IKHR

t

IKDH

t

IKDD

t

IRDE

t

IRDV

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

IACK High after Start of Read
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns

IACK

IRD

IAD15–0

1

1

2

2

t

IKR

t

IS

t

IRDE

IKHR

t

IRDV

t

IRP

PREVIOUS

DATA

0ns

15 ns

0ns

10 ns

t

IKDH

t

IKDD

Figure 21. IDMA Read, Short Read Cycle

REV. A

–25–

ADSP-2186L

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

DD

2

× f

C × V

C = load capacitance, f = output switching frequency.

Example

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:

Assumptions

• External data memory is accessed every cycle with 50% of the
address pins switching.

• External data memory writes occur every other cycle with
50% of the data pins switching.

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V

Total Power Dissipation = P

P

= internal power dissipation from Power vs. Frequency

INT

= 3.3 V and tCK = 30 ns.

DD

+ (C × V

INT

DD

2

× f)

graph (Figure 23).

(C × V

Address, DMS 8 × 10 pF × 3.32 V × 33.3 MHz = 29.0 mW
Data Output, WR 9 × 10 pF × 3.32 V × 16.67 MHz = 16.3 mW
RD 1 × 10 pF × 3.32 V × 16.67 MHz = 1.8 mW
CLKOUT 1 × 10 pF × 3.32 V × 33.3 MHz = 3.6 mW

2

× f ) is calculated for each output:

DD

# of
Pins × C × V

DD

2

× f

50.7 mW

Total power dissipation for this example is PINT + 50.7 mW.

Output Drive Currents

Figure 22 shows typical I-V characteristics for the output drivers
of the ADSP-2186L. The curves represent the current drive
capability of the output drivers as a function of output voltage.

80

VDD = 3.3V @ +25ⴗC

60

40

20

VDD = 3.0V @ +85ⴗC

0

–20

SOURCE CURRENT – mA

–40

–60

VDD = 3.6V @ –40ⴗC

–80

0

VDD = 3.0V @ +85ⴗC

SOURCE VOLTAGE – V

V

OH

V

OL

VDD = 3.6V @ –40ⴗC

VDD = 3.3V @ +25ⴗC

3.50.5 1 1.5 2 2.5 3

Figure 22. Typical Output Driver Characteristics

1, 2, 4

1, 2, 3

2

169mW

139mW

113mW

35mW

28mW

22mW

28mW

13mW

12mW

4230 32 34 36 38 40

4230 32 34 36 38 40

IDLE

IDLE (16)

IDLE (128)

OR GND.

DD

180

170

160

150

) – mW

140

INT

130

120

POWER (P

110

100

90

80

36

34

32

30

) – mW

28

IDLE

26

24

22

POWER (P

20

18

16

32

30

28

26

24

n) – mW

22

20

IDLE

18

16

14

POWER (P

12

10

8

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

TYPICAL POWER DISSIPATION AT 3.3V VDD AND TA = 25°C EXCEPT WHERE SPECIFIED.

3

IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14)
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

4

IDLE REFERS TO ADSP-2186L STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

2186L POWER, INTERNAL

VDD = 3.6V

VDD = 3.3V

126mW

102mW

83mW

VDD = 3.0V

1/tCK – MHz

POWER, IDLE

VDD = 3.6V

27mW

22mW

19mW

VDD = 3.3V

VDD = 3.0V

1/tCK – MHz

POWER, IDLE n MODES

22mW

10mW

9mW

30 32 34 36 38 40 42

1/tCK – MHz

Figure 23. Power vs. Frequency

–26–

REV. A

ADSP-2186L

CAPACITIVE LOADING

Figures 24 and 25 show the capacitive loading characteristics of
the ADSP-2186L.

25

0 20020

VDD = 3.0V
T = ⴙ85ⴗC

40 60 80 100 120 140 160 180

CL – pF

RISE TIME (0.4V – 2.4V) – ns

20

15

10

5

0

Figure 24. Typical Output Rise Time vs. Load Capacitance,

(at Maximum Ambient Operating Temperature)

C

L

18

NOMINAL

VALID OUTPUT DELAY OR HOLD – ns

16

14

12

10

8

6

4

2

–2
–3
–4

–6

VDD = 3.0V
T = +85ⴗC

0

50 100 150 250200

CL – pF

Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

L

Temperature)

the current load, i

, on the output pin. It can be approximated

L

by the following equation:

C

× 0.5V

t

DECAY

L

=

i

L

from which

t

DIS

= t

MEASURED

– t

DECAY

is calculated. If multiple pins (such as the data bus) are
disabled, the measurement value is that of the last pin to
stop driving.

INPUT

OR

OUTPUT

1.5V 1.5V

Figure 26. Voltage Reference Levels for AC Measure­ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

) is the interval from when

ENA

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.

REFERENCE

SIGNAL

(MEASURED)

OUTPUT

(MEASURED)

t

MEASURED

t

V

DIS

OH

V

OL

OUTPUT STOPS

DRIVING

t

ENA

V

OH

(MEASURED)

(MEASURED) – 0.5V

V

OH

(MEASURED) +0.5V

V

OL

t

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

2.0V

1.0V

OUTPUT STARTS

DRIVING

V

OL

(MEASURED)

Figure 27. Output Enable/Disable

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out­put disable time (t
t

, as shown in the Output Enable/Disable diagram. The

DECAY

) is the difference between t

DIS

MEASURED

and

time is the interval from when a reference signal reaches a high
or low voltage level to when the output voltages have changed
by 0.5 V from the measured output high or low voltage. The
decay time, t

REV. A

, is dependent on the capacitive load, CL, and

DECAY

–27–

I

OL

OUTPUT

PIN

TO

50pF

I

OH

+1.5V

Figure 28. Equivalent Device Loading for AC Measure­ments (Including All Fixtures)

ADSP-2186L

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

T
T

=T

AMB

= Case Temperature in °C

CASE

– (PD × θCA)

CASE

PD = Power Dissipation in W

θ
θ
θ

Package ␪

= Thermal Resistance (Case-to-Ambient)

CA

= Thermal Resistance (Junction-to-Ambient)

JA

= Thermal Resistance (Junction-to-Case)

JC

JA

␪

JC

␪

CA

LQFP 50°C/W 2°C/W 48°C/W
Mini-BGA 70.7°C/W 7.4°C/W 63.3°C/W

10k

1k

VDD = 3.6V

100

CURRENT – ␮A

10

1

0

25 55 85

TEMPERATURE – ⴗC

VDD = 3.3V

Figure 29. Power-Down Graph

–28–

REV. A

100-Lead LQFP Package Pinout

ADSP-2186L

A4/IAD3

A5/IAD4

GND

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

VDD

CLKOUT

GND

VDD

WR

RD
BMS
DMS

PMS

IOMS

CMS

A2/IAD1

A3/IAD2

A1/IAD0

9998979695949392919089888786858483828180797877

100

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

27

28

26

GND

IRQE+PF4

IRQL0+PF5

PWDACK

A0

29

30

IRQL1+PF6

BGH

31

DT0

IRQ2+PF7

PF0 [MODE A]

GND

PF1 [MODE B]

32

33

34

DR0

TFS0

RFS0

PF3

VDD

PWD

PF2 [MODE C]

ADSP-2186L

TOP VIEW

(Not to Scale)

35

36

37

38

DT1

VDD

TFS1

SCLK0

FL0

39

RFS1

FL1

40

DR1

FL2

41

GND

D23

D22

42

43

SCLK1

ERESET

D20

D21

44

45

EMS

RESET

GND

46

EE

D19

47

ECLK

D18

48

ELOUT

D17

49

ELIN

D16

76

50

EINT

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

D15

D14

D13

D12

GND

D11

D10

D9

VDD

GND

D8
D7/IWR

D6/IRD

D5/IAL
D4/IS

GND

VDD
D3/IACK

D2/IAD15

D1/IAD14

D0/IAD13

BG
EBG
BR
EBR

REV. A

–29–

ADSP-2186L

The ADSP-2186L package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

LQFP Pin Configurations

LQFP Pin LQFP Pin LQFP Pin LQFP Pin
Number Name Number Name Number Name Number Name

1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17
3GND28GND53EBG 78 D18
4 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19
5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDD 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDD 61 D4/IS 86 FL1
12 GND 37 DT1 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1 63 D6/IRD 88 PF3
14 XTAL 39 RFS1 64 D7/IWR 89 PF2 [Mode C]
15 VDD 40 DR1 65 D8 90 VDD
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDD 92 GND
18 VDD 43 ERESET 68 D9 93 PF1 [Mode B]
19 WR 44 RESET 69 D10 94 PF0 [Mode A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2

–30–

REV. A

ADSP-2186L

ADSP-2186L Mini-BGA (CAP) Package Pinout

Bottom View

121110987654321

GND GND D22 NC NC NC GND NC A0 GND A1/IAD0 A2/ IAD1

D16 D17 D18 D20 D23 VDD GND NC NC GND A3/IAD2 A4/ IAD3

D14 NC D15 D19 D21 VDD

GND NC D12 D13 NC

D10 GND VDD GND GND PF3 FL2

D9 NC D8 D11

D4/ IS

GND NC GND

VDD VDD D1/ IAD14

EBG BR EBR ERESET

EINT

ECLK EE

NC NC D5 /IAL

D3/ IACK

ELOUT ELIN

EMS

RESET

D7/IWR

D6/ IRD

D2/ IAD15 TFS0 DT0 VDD GND GND GND CLKIN

RFS1 D0/IAD13 SCLK0 VDD VDD NC VDD CLKOUT

BG

SCLK1 TFS1 RFS0

GND DR0

NC GND DR1 DT1 GND

PF2

[MODE C]

[MODE B]

NC NC FL1

NC NC NC A10/ IAD9 GND NC XTAL

PWD

PF1

PMS

A7/IAD6 A5/IAD4

A9/ IAD8

PF0

[MODE A]

DMS BMS

GND

BGH

FL0 A8/ IAD7 VDD VDD

A11/

IAD10

IOMS

CMS

A6/IAD5 PWDACK

RD

NC

A12/

IAD11

NC NC NC

IRQL1

+

PF6

NC

WR

NC

NC

IRQ2

+

PF7

NC

A13/

IAD12

IRQE

+

PF4

IRQL0

+

PF5

A

B

C

D

E

F

G

H

J

K

L

M

REV. A

–31–

ADSP-2186L

The ADSP-2186L Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named func-
tions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals
enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

Mini-BGA Package Pinout

Ball # Name Ball # Name Ball # Name Ball # Name

A01 A2/IAD1 D01 N/C G01 XTAL K01 N/C
A02 A1/IAD0 D02 WR G02 N/C K02 N/C

A03 GND D03 N/C G03 GND K03 N/C
A04 A0 D04 BGH G04 A10/IAD9 K04 BMS
A05 N/C D05 A9/IAD8 G05 N/C K05 DMS

A06 GND D06 PF1[MODE B] G06 N/C K06 RFS0

A07 N/C D07 PF2[MODE C] G07 N/C K07 TFS1
A08 N/C D08 N/C G08 D6/IRD K08 SCLK1
A09 N/C D09 D13 G09 D5/IAL K09 ERESET
A10 D22 D10 D12 G10 N/C K10 EBR
A11 GND D11 N/C G11 N/C K11 BR
A12 GND D12 GND G12 D4/IS K12 EBG

B01 A4/IAD3 E01 VDD H01 CLKIN L01 IRQE+PF4

B02 A3/IAD2 E02 VDD H02 GND L02 N/C
B03 GND E03 A8/IAD7 H03 GND L03 IRQL1+PF6
B04 N/C E04 FL0 H04 GND L04 IOMS

B05 N/C E05 PF0[MODE A] H05 VDD L05 GND
B06 GND E06 FL2 H06 DT0 L06 PMS

B07 VDD E07 PF3 H07 TFS0 L07 DR0

B08 D23 E08 GND H08 D2/IAD15 L08 GND
B09 D20 E09 GND H09 D3/IACK L09 RESET

B10 D18 E10 VDD H10 GND L10 ELIN

B11 D17 E11 GND H11 N/C L11 ELOUT
B12 D16 E12 D10 H12 GND L12 EINT

C01 PWDACK F01 A13/IAD12 J01 CLKOUT M01 IRQL0+PF5
C02 A6/IAD5 F02 N/C J02 VDD M02 IRQ2+PF7
C03 RD F03 A12/IAD11 J03 N/C M03 N/C
C04 A5/IAD4 F04 A11/IAD10 J04 VDD M04 CMS

C05 A7/IAD6 F05 FL1 J05 VDD M05 GND
C06 PWD F06 N/C J06 SCLK0 M06 DT1

C07 VDD F07 N/C J07 D0/IAD13 M07 DR1
C08 D21 F08 D7/IWR J08 RFS1 M08 GND
C09 D19 F09 D11 J09 BG M09 N/C
C10 D15 F10 D8 J10 D1/IAD14 M10 EMS

C11 N/C F11 N/C J11 VDD M11 EE

C12 D14 F12 D9 J12 VDD M12 ECLK

–32–

REV. A

ADSP-2186L

ORDERING GUIDE

Ambient Instruction
Temperature Rate Package Package

Part Number Range (MHz) Description Option*

ADSP-2186LKST-115 0°C to +70°C 28.8 100-Lead LQFP ST-100
ADSP-2186LBST-115 –40°C to +85°C 28.8 100-Lead LQFP ST-100
ADSP-2186LKST-133 0°C to +70°C 33.3 100-Lead LQFP ST-100
ADSP-2186LBST-133 –40°C to +85°C 33.3 100-Lead LQFP ST-100
ADSP-2186LKST-160 0°C to +70°C 40.0 100-Lead LQFP ST-100
ADSP-2186LBST-160 –40°C to +85°C 40.0 100-Lead LQFP ST-100
ADSP-2186LBCA-160 –40°C to +85°C 40.0 144-Ball Mini-BGA CA-144

*ST = Plastic Thin Quad Flatpack (LQFP); CA = Mini-BGA.

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters).

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

0.638 (16.20)

0.630 (16.00)

0.622 (15.80)

0.553 (14.05)

0.551 (14.00)

0.063 (1.60) MAX

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

SEATING

PLANE

0.003

(0.08)

MAX LEAD

COPLANARITY

0° – 7°

NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

12°
TYP

6° ± 4°

0.006 (0.15)

0.002 (0.05)

25

0.549 (13.95)

0.472 (12.00) TYP SQ

100 76
1

TOP VIEW

(PINS DOWN)

26

0.020 (0.50)
BSC

LEAD PITCH

TYP SQ

TYP SQ

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

LEAD WIDTH

75

51

50

REV. A

–33–

ADSP-2186L

Dimensions shown in inches and (millimeters).

0.398 (10.10)

0.394 (10.00) SQ

0.390 (9.90)

TOP VIEW

0.053 (1.35)

0.049 (1.25)

0.045 (1.15)

NOTES

1

THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.006 (0.150) OF ITS IDEAL POSITION
RELATIVE TO THE PACKAGE EDGES.

2

THE ACTUAL POSITION OF EACH BALL IS
WITHIN 0.002 (0.05) OF ITS IDEAL POSITION
RELATIVE TO THE BALL GRID.

OUTLINE DIMENSIONS

144-Ball Mini-BGA

(CA-144)

0.346

0.398 (10.10)

0.394 (10.00) SQ

0.390 (9.90)

DETAIL A

(8.80)

BSC

0.014 (0.35)

0.012 (0.30)

0.010 (0.25)

0.031
(0.80)

BSC

0.010
(0.25)

MAX

12 11 10 9 8 7 6 5 4 3 2 1

0.031 (0.80) BSC

0.346 (8.80) BSC

DETAIL A

0.018 (0.45)

0.016 (0.40)

0.014 (0.35)

BALL DIAMETER

0.006

(0.15)

MAX

A
B
C
D
E
F
G
H
J
K
L
M

0.030 (0.75)

0.028 (0.70)

0.026 (0.65)

SEATING
PLANE

C00191a–2.5–8/00 (rev. A)

–34–

PRINTED IN U.S.A.

REV. A