Analog Devices ADSP-2186 User Manual

a

DSP Microcomputer

ADSP-2186

FEATURES
PERFORMANCE
30 ns Instruction Cycle Time 33 MIPS Sustained

Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 100 Cycle Recovery from

Power-Down Condition
Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction

Set Extensions
40K Bytes of On-Chip RAM, Configured as

8K Words On-Chip Program Memory RAM and

8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction

and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction

Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP

SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data

Tables & Program Overlays
8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design

(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

*ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2DAG 1

ARITHMETIC UNITS

ALU

MAC

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

CONTROL

MEMORY

8K

24

PROGRAM

MEMORY

SERIAL PORTS

8K 16

DATA

MEMORY

SPORT 1SPORT 0

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

Six External Interrupts
13 Programmable Flag Pins Provide Flexible System

Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™* Emulator Interface Supports Debugging

in Final Systems

GENERAL NOTE

This data sheet represents production grade specifications for
the ADSP-2186 (5 V) processor. This data sheet also contains
preliminary (x-grade) specifications for the new ADSP-2186
40 MHz processor.

GENERAL DESCRIPTION

The ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.

The ADSP-2186 combines the ADSP-2100 family base archi­tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.

The ADSP-2186 integrates 40K bytes of on-chip memory con­figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip­ment. The ADSP-2186 is available in 100-pin TQFP package.

In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

ADSP-2186

biased rounding, result free ALU operations, I/O memory trans­fers and global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.

The ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera­tions in parallel. In one processor cycle the ADSP-2186 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation
This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup­ports the ADSP-2186. The System Builder provides a high level
method for defining the architecture of systems under develop­ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction­level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft­ware design. The EZ-KIT Lite includes the following features:

• 33 MHz ADSP-2181

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort
Codec

• RS-232 Interface to PC with Microsoft
Control Software

• EZ-ICE

®

* Connector for Emulator Control

®

Windows 3.1

®

*

• DSP Demo Programs

The ADSP-218x EZ-ICE

®

* Emulator aids in the hardware
debugging of an ADSP-2186 system. The emulator consists of
hardware, host computer resident software, and the target board
connector. The ADSP-2186 integrates on-chip emulation sup­port with a 14-pin ICE-Port™* interface. This interface pro­vides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICE
moved from the target system when using the EZ-ICE

®

*s. The ADSP-2186 device need not be re-

®

*, nor

are any adapters needed. Due to the small footprint of the

*SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.

EZ-ICE

®

* connector, emulation can be supported in final board

designs.
The EZ-ICE

®

* performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging
See Designing An EZ-ICE

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE
tion of this data sheet, for the exact specifications of the EZ-

®

ICE

* target board connector.

®

*-Compatible Target System in the

®

* Probe sec-

Additional Information

This data sheet provides a general overview of ADSP-2186
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools Data
Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2186 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro­cessor cycle. The ADSP-2186 assembly language uses an alge­braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.

POWER-DOWN

DATA ADDRESS

GENERATORS

DAG 2DAG 1

ARITHMETIC UNITS

ALU

MAC

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

CONTROL

MEMORY

8K 24

PROGRAM

MEMORY

SERIAL PORTS

8K 16

MEMORY

SPORT 1SPORT 0

DATA

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

Figure 1. Block Diagram

Figure 1 is an overall block diagram of the ADSP-2186. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi­sions to support multiprecision computations. The ALU per­forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith­metic shifts, normalization, denormalization and derive expo­nent operations.

–2–

REV. 0

ADSP-2186

The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.

The internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps, sub­routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2186 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro­gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos­sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus
The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit­ting the ADSP-2186 to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP­2186 can fetch an operand from program memory and the next
instruction in the same cycle.

When configured in host mode, the ADSP-2186 has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. The IDMA port is made up of 16 data/address pins
and five control pins. The IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH and BG). One execution mode (Go Mode) allows
the ADSP-2186 to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.

The ADSP-2186 can respond to eleven interrupts. There are up
to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port

REV. 0

–3–

and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.

Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2186 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2186 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2186 SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual.

• SPORTs are bidirectional and have a separate, double-buff­ered transmit and receive section.

• SPORTs can use an external serial clock or generate their own
serial clock internally.

• SPORTs have independent framing for the receive and trans­mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.

• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.

PIN DESCRIPTIONS

The ADSP-2186 will be available in a 100-lead TQFP package.
In order to maintain maximum functionality and reduce pack­age size and pin count, some serial port, programmable flag,
interrupt and external bus pins have dual, multiplexed function­ality. The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained

ADSP-2186

concurrently on multiplexed pins. In cases where pin func­tionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.

Common-Mode Pins

# Input/
Pin of Out­Name(s) Pins put Function

RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2/ 1 I Edge- or Level-Sensitive

Interrupt Request

1

PF7 I/O Programmable I/O Pin
IRQL0/ 1 I Level-Sensitive Interrupt Requests

1

PF5 I/O Programmable I/O Pin
IRQL1/ 1 I Level-Sensitive Interrupt Requests

1

PF6 I/O Programmable I/O Pin
IRQE/ 1 I Edge-Sensitive Interrupt Requests

1

PF4 I/O Programmable I/O Pin
PF3 1 I/O Programmable I/O Pin
Mode C/ 1 I Mode Select Input—Checked

only During RESET

PF2 I/O Programmable I/O Pin During

Normal Operation

Mode B/ 1 I Mode Select Input—Checked

only During RESET

PF1 I/O Programmable I/O Pin During

Normal Operation

Mode A/ 1 I Mode Select Input—Checked

only During RESET

PF0 I/O Programmable I/O Pin During

Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins

IRQ1:0 Edge- or Level-Sensitive Interrupts,
FI, FO Flag In, Flag Out

2

PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags

and GND 16 I Power and Ground

V

DD

EZ-Port 9 I/O For Emulation Use

NOTES

1

Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.

2

SPORT configuration determined by the DSP System Control Register. Soft­ware configurable.

Memory Interface Pins

The ADSP-2186 processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.

Full Memory Mode Pins (Mode C = 0)

#
of Input/

Pin Name Pins Output Function

A13:0 14 O Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

D23:0 24 I/O Data I/O Pins for Program,

Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)

Host Mode Pins (Mode C = 1)

#
of Input/

Pin Name Pins Output Function

IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O,

Program, Data, or Byte Access

D23:8 16 I/O Data I/O Pins for Program,

Data Byte and I/O Spaces

IWR 1 I IDMA Write Enable
IRD 1 I IDMA Read Enable

IAL 1 I IDMA Address Latch Pin

IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge

In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.

Setting Memory Mode

Memory Mode selection for the ADSP-2186 is made during
chip reset through the use of the Mode C pin. This pin is multi­plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.

Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.

Active configuration involves the use of a three-stateable exter­nal driver connected to the Mode C pin. A driver’s output en­able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow­ing full use of the PF2 pin as either an input or output.

–4–

REV. 0

ADSP-2186

To minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three­stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.

Interrupts

The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2186 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2186 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter­rupt levels are internally prioritized and individually maskable
(except power-down and reset). The IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-sensitive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
The priorities and vector addresses of all interrupts are shown in
Table I.

Table I. Interrupt Priority & Interrupt Vector Addresses

Source Of Interrupt Interrupt Vector Address (Hex)

Reset (or Power-Up with

PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable) 002C

IRQ2 0004
IRQL1 0008
IRQL0 000C

SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter­rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.

The ADSP-2186 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest­ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts.

On-chip stacks preserve the processor status and are automati­cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servic­ing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.

ENA INTS;
DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2186 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle
The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

The ADSP-2186 processor has a low power feature that lets the
processor enter a very low power dormant state through hard­ware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, “System
Interface” chapter, for detailed information about the power­down feature.

• Quick recovery from power-down. The processor begins
executing instructions in as few as 100 CLKIN cycles.

• Support for an externally generated TTL or CMOS proces­sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
100 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi­mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 100CLKIN
cycle start-up.

• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit.

• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The power­down interrupt also can be used as a nonmaskable, edge­sensitive interrupt.

• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor
has entered power-down.

REV. 0

–5–

ADSP-2186

Idle

When the ADSP-2186 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2186 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program­mable fraction of the normal clock rate, is specified by a select­able divisor given in the IDLE instruction. The format of the
instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the proces­sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in­coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2186 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

1/2x CLOCK

OR

CRYSTAL

SERIAL
DEVICE

SERIAL
DEVICE

SYSTEM

INTERFACE

OR

µCONTROLLER

FULL MEMORY MODE

ADSP-2186

A

CLKIN
XTAL
FL0-2

PF3

MODE C/PF2
MODE B/PF1
MODE A/PF0

SPORT1

SCLK1
RFS1 OR
TFS1 OR
DT1 OR FO
DR1 OR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

HOST MEMORY MODE

/PF7
/PF4

/PF5
/PF6

ADDR13-0

DATA23-0

14

13-0

A0-A21

D

23-16

24

D

15-8

DATA

A

10-0

ADDR

D

23-8

DATA

A

13-0

ADDR

D

23-0

DATA

ADSP-2186

16

CLKIN
XTAL

FL0-2
PF3

/PF7
/PF4

/PF5
/PF6

MODE C/PF2
MODE B/PF1
MODE A/PF0

SPORT1

SCLK1
RFS1 OR
TFS1 OR
DT1 OR FO
DR1 OR FI

SPORT0

SCLK0
RFS0
TFS0
DT0
DR0

IDMA PORT

/D6

/D7

/D4

IAL/D5

/D3

IAD15-0

ADDR0

DATA23-8

1

16

Figure 2. Basic System Configuration

BYTE

MEMORY

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

–6–

REV. 0

ADSP-2186

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MODE B = 0)

0x3FFF

0x2000
0x1FFF

8K INTERNAL

0x0000

PROGRAM MEMORY

ADDRESS

Clock Signals

The ADSP-2186 can be clocked by either a crystal or a TTL­compatible clock signal.

The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera­tion. The only exception is while the processor is in the power­down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, for detailed information on
this power-down feature.

If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con­nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.

The ADSP-2186 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.

Because the ADSP-2186 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be con­nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufac­turer. A parallel-resonant, fundamental frequency, microproces­sor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the proces­sor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.

Reset

The RESET signal initiates a master reset of the ADSP-2186.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini­mum pulse width specification, t

The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.

REV. 0

CLKIN CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

.

RSP

DD

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.

MEMORY ARCHITECTURE

The ADSP-2186 provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O.

Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The ADSP-2186
has 8K words of Program Memory RAM on chip, and the capabil­ity of accessing up to two 8K external memory overlay spaces using
the external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.

Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2186 has 8K words on Data
Memory RAM on chip, consisting of 8160 user-accessible
locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus.

Byte Memory (Full Memory Mode) provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port.
The Byte Memory interface provides access to 4 MBytes of
memory by utilizing eight data lines as additional address lines.
This gives the BDMA Port an effective 22-bit address range. On
power-up, the DSP can automatically load bootstrap code from
byte memory.

I/O Space (Full Memory Mode) allows access to 2048 loca­tions of 16-bit-wide data. It is intended to be used to communi­cate with parallel peripheral devices such as data converters and
external registers or latches.

Program Memory

The ADSP-2186 contains an 8K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2186 allows the use of 8K
external memory overlays.

The program memory space organization is controlled by the
Mode B pin and the PMOVLAY register. Normally, the ADSP­2186 is configured with Mode B = 0 and program memory
organized as shown in Figure 4.

is

Figure 4. Program Memory (Mode B = 0)

–7–

ADSP-2186

There are 8K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to some­thing other than 0, external accesses occur at addresses 0x2000
through 0x3FFF. The external address is generated as shown in
Table II.

Table II.

PMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable
1 External 13 LSBs of Address

Overlay 1 0 Between 0x2000

and 0x3FFF

2 External 13 LSBs of Address

Overlay 2 1 Between 0x2000

and 0x3FFF

NOTE: Addresses 0x2000 through 0x3FFF should not be accessed when
PMOVLAY = 0.

This organization provides for two external 8K overlay segments
using only the normal 14 address bits, which allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space in that the processor core (i.e., the sequencer)
does not take into account the PMOVLAY register value. For
example, if a loop operation was occurring on one of the exter­nal overlays and the program changes to another external over­lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.

When Mode B = 1, booting is disabled and overlay memory is
disabled (PMOVLAY must be 0). Figure 5 shows the memory
map in this configuration.

PROGRAM MEMORY ADDRESS

0x3FFF

RESERVED

There are 8160 words of memory accessible internally when the
DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.

Table III.

DMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable
1 External 13 LSBs of Address

Overlay 1 0 Between 0x2000

and 0x3FFF

2 External 13 LSBs of Address

Overlay 2 1 Between 0x2000

and 0x3FFF

This organization allows for two external 8K overlays using only
the normal 14 address bits. All internal accesses complete in one
cycle. Accesses to external memory are timed using the wait
states specified by the DWAIT register.

I/O Space (Full Memory Mode)

The ADSP-2186 supports an additional external memory space
called I/O space. This space is designed to support simple con­nections to peripherals or t o bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper three bits are unde­fined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0-3, which specify up to seven wait states to
be automatically generated for each of four regions. The wait
states act on address ranges as shown in Table IV.

Table IV.

Address Range Wait State Register

0x2000
0x1FFF

8K EXTERNAL

0x0000

Figure 5. Program Memory (Mode B = 1)

Data Memory

The ADSP-2186 has 8160 16-bit words of internal data memory.
In addition, the ADSP-2186 allows the use of 8K external memory
overlays. Figure 6 shows the organization of the data memory.

DATA MEMORY ADDRESS

32 MEMORY–

MAPPED REGISTERS

INTERNAL

8160 WORDS

EXTERNAL 8K

(DMOVLAY = 1, 2)

0x3FFF

0x3FEO

0x3FDF

0x2000
0x1FFF

0x0000

Figure 6. Data Memory

–8–

0x000–0x1FF IOWAIT0
0x200–0x3FF IOWAIT1
0x400–0x5FF IOWAIT2
0x600–0x7FF IOWAIT3

Composite Memory Select (CMS)

The ADSP-2186 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS), but can combine their
functionality.

Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as­serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory and use either DMS or PMS as the additional
address bit.

The CMS pin functions as the other memory select signals, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.

REV. 0

ADSP-2186

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2186 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats, which
are selected by the BTYPE register field. The appropriate num­ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.

Table V.

Internal

BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. Finally the 14-bit BWCOUNT
register specifies the number of DSP words to transfer and
initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener­ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.

When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.

The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera­tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory­mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com­pletely asynchronous and can be written to while the ADSP­2186 is operating at full speed.

The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in­creases throughput as the address does not have to be sent for
each memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.

Once the address is stored, data can then either be read from or
written to the ADSP-2186’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2186 that a particular
transaction is required. In either case, there is a one-processor­cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati­cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.

REV. 0

–9–

ADSP-2186

Bootstrap Loading (Booting)

The ADSP-2186 has two mechanisms to allow automatic load­ing of the internal program memory after reset. The method for
booting is controlled by the Mode A, B and C configuration bits
as shown in Table VI. These four states can be compressed into
two-state bits by allowing an IDMA boot with Mode C = 1.
However, three bits are used to ensure future compatibility with
parts containing internal program memory ROM.

BDMA Booting

When the MODE pins specify BDMA booting, the ADSP-2186
initiates a BDMA boot sequence when RESET is released.

Table VI. Boot Summary Table

MODE C MODE B MODE A Booting Method

0 0 0 BDMA feature is used to load

the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Full Memory
Mode.

0 1 0 No Automatic boot opera-

tions occur. Program execu­tion starts at external memory
location 0. Chip is config­ured in Full Memory Mode.
BDMA can still be used but
the processor does not auto­matically use or wait for these
operations.

1 0 0 BDMA feature is used to load

the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Host Mode.
Additional interface hardware
is required.

1 0 1 IDMA feature is used to load

any internal memory as de­sired. Program execution is
held off until internal pro­gram memory location 0 is
written to. Chip is configured
in Host Mode.

The BDMA interface is set up during reset to the following de­faults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0; the BTYPE register is
set to 0 to specify program memory 24 bit words; and the
BWCOUNT register is set to 32. This causes 32 words of on­chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad­dresses to boot memory must be constructed externally to the
ADSP-2186. The only memory address bit provided by the
processor is A0.

IDMA Port Booting

The ADSP-2186 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.

Bus Request & Bus Grant

The ADSP-2186 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2186 is not performing an external memory access, it
responds to the active BR input in the following processor cycle
by:

• Three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2186 will not halt program
execution until it encounters an instruction that requires an
external memory access.

If the ADSP-2186 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.

When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2186 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2186 deasserts BG and BGH and executes the external
memory access.

Flag I/O Pins

The ADSP-2186 has eight general purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin

–10–

REV. 0

ADSP-2186

configured as an input is synchronized to the ADSP-2186’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2186 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.

Note: Pins PF0, PF1 and PF2 are also used for device configu­ration during reset.

BIASED ROUNDING

A mode is available on the ADSP-2186 to allow biased round­ing in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding opera­tions occur. When the BIASRND bit is set to 1, biased round­ing occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.

For example:

Table VII.

MR Value Biased Unbiased
Before RND RND Result RND Result

00-0000-8000 00-0001-8000 00-0000-8000
00-0001-8000 00-0002-8000 00-0002-8000
00-0000-8001 00-0001-8001 00-0001-8001
00-0001-8001 00-0002-8001 00-0002-8001
00-0000-7FFF 00-0000-7FFF 00-0000-7FFF
00-0001-7FFF 00-0001-7FFF 00-0001-7FFF

This mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. This
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.

Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer Con­trol register.

Instruction Set Description

The ADSP-2186 assembly language instruction set has an alge­braic syntax that was designed for ease of coding and readabil­ity. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.

• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan­guage and is completely source and object code compatible
with other family members. Programs may need to be relo­cated to utilize on-chip memory and conform to the ADSP­2186’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

I/O Space Instructions

The instructions used to access the ADSP-2186’s I/O memory
space are as follows:

Syntax: IO(addr) = dreg

dreg = IO(addr);

where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.

Examples: IO(23) = AR0;

AR1 = IO(17);

Description: The I/O space read and write instructions move

data between the data registers and the I/O
memory space.

DESIGNING AN EZ-ICE®*-COMPATIBLE SYSTEM

The ADSP-2186 has on-chip emulation support and an
ICE-Port™*, a special set of pins that interface to the EZ-ICE

®

*.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE
14-pin connector to accept the EZ-ICE

®

*. Target systems must have a

®

*’s in-circuit probe, a
14-pin plug. See the ADSP-2100 Family EZ-Tools data sheet for
complete information on ICE products.

The ICE-Port™* interface consists of the following ADSP-2186
pins:

EBR
EBG
ERESET
EMS
EINT

ECLK
ELIN
ELOUT
EE

These ADSP-2186 pins must be connected only to the EZ-ICE

®

*
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or
pull-down resistors. The traces for these signals between the
ADSP-2186 and the connector must be kept as short as pos­sible, no longer than three inches.

The following pins are also used by the EZ-ICE

®

*:

BR
BG
RESET

GND
The EZ-ICE

®

* uses the EE (emulator enable) signal to take
control of the ADSP-2186 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.

REV. 0

–11–

ADSP-2186

The EZ-ICE®* connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE®* Probe

The EZ-ICE®* connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE
enough room in your system to fit the EZ-ICE

®

*. Be sure to allow

®

* probe onto the

14-pin connector.

GND

EBG

EBR

KEY (NO PIN)

ELOUT

EE

RESET

12

34

56

78

×

910

11 12

13 14

TOP VIEW

BG

BR

EINT

ELIN

ECLK

EMS

ERESET

Figure 7. Target Board Connector for EZ-ICE®*

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca­tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac­ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE

®

*
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE®*
emulator, it must comply with the memory interface guidelines
listed below.

PM, DM, BM, IOM, & CM

Design your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim­ing requirements and switching characteristics as specified in
this DSP’s data sheet. The performance of the EZ-ICE

®

* may
approach published worst case specification for some memory
access timing requirements and switching characteristics.

Note: If your target does not meet the worst case chip specifica­tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend­ing on the severity of the specification violation, you may have

trouble manufacturing your system as DSP components statisti­cally vary in switching characteristic and timing requirements
within published limits.

Restriction: All memory strobe signals on the ADSP-2186 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE

®

* is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE
at your option when the EZ-ICE

®

* debugging sessions. These resistors may be removed

®

* is not being used.

Target System Interface Signals

When the EZ-ICE®* board is installed, the performance on
some system signals change. Design your system to be compat­ible with the following system interface signal changes intro­duced by the EZ-ICE

®

• EZ-ICE

* emulation introduces an 8 ns propagation delay

®

* board:

between your target circuitry and the DSP on the RESET
signal.

• EZ-ICE

®

* emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR signal.

• EZ-ICE

®

* emulation ignores RESET and BR when single-

stepping.

• EZ-ICE

®

* emulation ignores RESET and BR when in Emu-

lator Space (DSP halted).

• EZ-ICE

®

* emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE

®

* board’s DSP.

–12–

REV. 0

ADSP-2186

ADSP-2186 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade B Grade

Parameter Min Max Min Max Unit

V
T

DD
AMB

4.5 5.5 4.5 5.5 V
0 +70 –40 +85 °C

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter Test Conditions Min Typ Max Unit

V

IH

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OZH

I

OZL

I

DD

I

DD

C

I

C

O

Parameters displayed inside brackets, [ ], represent preliminary 40 MHz specifications.
NOTES

1

Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7.

2

Input only pins: RESET, BR, DR0, DR1, PWD.

3

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

5

Although specified for TTL outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

6

Guaranteed but not tested.

7

Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7.

8

0 V on BR, CLKIN Inactive.

9

Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

10

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.

11

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

12

Applies to TQFP package type.

13

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

Hi-Level Input Voltage
Hi-Level CLKIN Voltage @ VDD = max 2.2 V
Lo-Level Input Voltage
Hi-Level Output Voltage

Lo-Level Output Voltage
Hi-Level Input Current
Lo-Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Supply Current (Idle)

Supply Current (Dynamic)

Input Pin Capacitance

Output Pin Capacitance

1, 2

1, 3

1, 4, 5

1, 4, 5

3

3

9

3, 6, 12

6, 7, 12, 13

@ VDD = max 2.0 V
@ VDD = min 0.8 V

@ VDD = min
I

= –0.5 mA 2.4 V

OH

@ V

= min

DD

I

= –100 µA

OH

6

VDD – 0.3 V
@ VDD = min
I

= 2 mA 0.4 V

OL

@ VDD = max
V

= VDDmax 10 µA

IN

@ VDD = max
V

= 0 V 10 µA

7

7

10

IN

@ VDD = max
V

= VDDmax

IN

@ VDD = max
V

= 0 V

IN

8

8

10 µA

10 µA
@ VDD = 5.0 12.4 mA
@ VDD = 5.0
T

= +25°C

AMB

t

= 30 ns

CK

t

= 25 ns

CK

11
11

55 mA

[65] mA
@ VIN = 2.5 V,
f

= 1.0 MHz, 8 pF

IN

T

= +25°C

AMB

@ VIN = 2.5 V,
f

= 1.0 MHz,

IN

T

= +25°C8pF

AMB

or GND.

DD

REV. 0

–13–

ADSP-2186

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V

Operating Temperature Range (Ambient) . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The ADSP-2186 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.

The ADSP-2186 features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are recom­mended to avoid performance degradation or loss of functionality. Unused devices must be stored in
conductive foam or shunts, and the foam should be discharged to the destination before devices are
removed.

+ 0.3 V

DD

+ 0.3 V

DD

WARNING!

ESD SENSITIVE DEVICE

ADSP-2186 TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.

Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces­sor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2186 timing parameters, for your
convenience.

Memory ADSP-2186 Timing
Device Timing Parameter
Specification Parameter Definition

Address Setup to t

ASW

A0–A13, xMS Setup

Write Start before WR Low

Address Setup to t

AW

A0–A13, xMS Setup

Write End before WR Deasserted

Address Hold Time t

WRA

A0–A13, xMS Hold before
WR Low

Data Setup Time t

DW

Data Setup before WR

High
Data Hold Time t
OE to Data Valid t
Address Access Time t

DH
RDD
AA

Data Hold after WR High

RD Low to Data Valid

A0–A13, xMS to Data

Valid

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS

tCK is defined as 0.5 t

. The ADSP-2186 uses an input clock

CKI

with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces­sor cycle (equivalent to 33 MHz). t

0.5 t

period should be substituted for all relevant timing para-

CKI

values within the range of

CK

meters to obtain the specification value.
Example: t

= 0.5 tCK – 7 ns = 0.5 (30 ns) – 7 ns = 8 ns

CKH

–14–

REV. 0

ADSP-2186

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

T
T

=T

AMB

= Case Temperature in °C

CASE

– (PD x θCA)

CASE

PD = Power Dissipation in W

θ
θ
θ

Package u

= Thermal Resistance (Case-to-Ambient)

CA

= Thermal Resistance (Junction-to-Ambient)

JA

= Thermal Resistance (Junction-to-Case)

JC

JA

u

JC

u

CA

TQFP 50°C/W 2°C/W 48°C/W

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

DD

2

× f

C × V

C = load capacitance, f = output switching frequency.

Example

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:

Assumptions

• External data memory is accessed every cycle with 50% of the
address pins switching.

• External data memory writes occur every other cycle with
50% of the data pins switching.

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V

Total Power Dissipation = P

= internal power dissipation from Power vs. Frequency

P

INT

= 5.0 V and tCK = 30 ns.

DD

+ (C × V

INT

DD

2

× f)

graph (Figure 8).
(C × V

Address, DMS 8 × 10 pF × 5
Data Output, WR 9 × 10 pF × 5
RD 1 × 10 pF × 5
CLKOUT 1 × 10 pF × 5

2

× f) is calculated for each output:

DD

# of
Pins 3 C 3 V

DD

2

V × 33.3 MHz = 66.6 mW

2

V × 16.67 MHz = 37.5 mW

2

V × 16.67 MHz = 4.2 mW

2

V × 33.3 MHz = 8.3 mW

2

3f

116.6 mW

Total power dissipation for this example is PINT + 116.6 mW.

VDD = 5.5V

VDD = 5.0V

VDD = 4.5V

1, 2, 3, 5

VDD = 5.5V

VDD = 5.0V

VDD = 4.5V

30mW

1, 3, 4, 5

430mW

325mW

235mW

3, 5

84mW

67mW

54mW

67mW

34mW

32mW

4230 32 34 36 38 40

4230 32 34 36 38 40

IDLE (16)

OR GND.

DD

IDLE

IDLE (128)

450
425
400
375
350

) – mW

325

INT

300
275
250

POWER (P

225
200
175
150

85
80
75
70
65

) – mW

60

IDLE

55
50
45

POWER (P

40
35
30

70
65
60
55

) – mW

50

n

IDLE

45
40
35

POWER (P

30
25
20

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

3

TYPICAL POWER DISSIPATION AT 5.0V VDD AND TA = 25°C EXCEPT WHERE SPECIFIED.

4

IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

5

SPECIFICATIONS AT 40MHz ARE PRELIMINARY AT THIS PRINTING.

2186 POWER, INTERNAL

370mW

330mW

275mW

245mW

195mW

175mW

1/fCK – MHz

POWER, IDLE

76mW

69mW

61mW

56mW

49mW

45mW

1/fCK – MHz

POWER, IDLE n MODES

61mW

56mW

30mW

28mW

28 4230 32 34 36 38 40

32mW

1/fCK – MHz

REV. 0

Figure 8. Power vs. Frequency

–15–

ADSP-2186

CAPACITIVE LOADING

Figures 9 and 10 show the capacitive loading characteristics of
the ADSP-2186.

t

, is dependent on the capacitive load, CL, and the current

DECAY

load, i

, on the output pin. It can be approximated by the fol-

L

lowing equation:

30

T = +85°C

= 4.5V

V

DD

25

20

15

10

RISE TIME (0.4V–2.4V) – ns

5

0

100 150 200 250

50

CL – pF

3000

Figure 9. Typical Output Rise Time vs. Load Capacitance,
C

(at Maximum Ambient Operating Temperature)

L

18
16
14
12
10

8
6

4
2

NOMINAL

–2

VALID OUTPUT DELAY OR HOLD – ns

–4
–6

0

50

100 150 250200

CL – pF

Figure 10. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

L

Temperature)

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out­put disable time (t

) is the difference of t

DIS

MEASURED

and t

DECAY

,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,

×0.5V

C

t

DECAY

L

=

i

L

from which

t

DIS

= t

MEASURED

– t

DECAY

is calculated. If multiple pins (such as the data bus) are dis­abled, the measurement value is that of the last pin to stop
driving.

INPUT

OUTPUT

1.5V

1.5V

0.8V

2.0V

Figure 11. Voltage Reference Levels for AC Measure­ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

) is the interval from when

ENA

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.

REFERENCE

SIGNAL

t

(MEASURED)

OUTPUT

(MEASURED)

MEASURED

t

V

DIS

OH

V

OL

OUTPUT STOPS

DRIVING

V

(MEASURED) – 0.5V

OH

VOL (MEASURED) +0.5V

t

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

t

ENA

V

2.0V

1.0V

OUTPUT STARTS

(MEASURED)

V
(MEASURED)

DRIVING

OH

OL

Figure 12. Output Enable/Disable

I

OL

TO

OUTPUT

PIN

50pF

+1.5V

I

OH

Figure 13. Equivalent Device Loading for AC Measure­ments (Including All Fixtures)

–16–

REV. 0

ADSP-2186

TIMING PARAMETERS

Parameter Min Max Unit
Clock Signals and Reset

Timing Requirements:
t

CKI

t

CKIL

t

CKIH

Switching Characteristics:

t

CKL

t

CKH

t

CKOH

Control Signals

CLKIN Period 60 [50] 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns

CLKOUT Width Low 0.5 t
CLKOUT Width High 0.5 t

– 7 ns

CK

– 7 ns

CK

CLKIN High to CLKOUT High 0 20 ns

Timing Requirements:
t

RSP

t

MS

t

MH

NOTES
Parameters displayed inside brackets [ ] represent preliminary 40 MHz specifications.

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

RESET Width Low
Mode Setup Before RESET High 2 ns
Mode Setup After RESET High 5 ns

CLKOUT

PF(2:0)

CLKIN

1

t

CKI

t

CKIL

t

CKL

*

5 t

t

CKOH

t

CK

CKH

t

ns

CKIH

REV. 0

RESET

t

MS

*

PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

t

MH

Figure 14. Clock Signals

–17–

ADSP-2186
TIMING PARAMETERS

Parameter Min Max Unit
Interrupts and Flag

Timing Requirements:
t
t

IFS
IFH

IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High

Switching Characteristics:
t

FOH

t

FOD

NOTES

1

If IRQx and FI inputs meet t
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)

2

Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5

Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.

Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low

and t

IFS

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

IFH

CLKOUT

FLAG

OUTPUTS

IRQ

x

FI

PFx

1, 2, 3, 4

1, 2, 3, 4

5

5

t

FOD

t

FOH

t

IFH

0.25 tCK + 15 ns

0.25 t

CK

0.25 tCK – 7 ns

0.5 t

+ 5 ns

CK

t

IFS

ns

Figure 15. Interrupts and Flags

–18–

REV. 0

ADSP-2186

Parameter Min Max Unit
Bus Request/Grant

Timing Requirements:
t
t

BH
BS

BR Hold after CLKOUT High
BR Setup before CLKOUT Low

1

1

0.25 tCK + 2 ns

0.25 tCK + 17 ns

Switching Characteristics:
t

SD

t

SDB

t

SE

t

SEC

t

SDBH

t

SEH

NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.

1

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

2

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT High to xMS, RD, WR Disable 0.25 tCK + 10 ns

xMS, RD, WR Disable to BG Low 0 ns
BG High to xMS, RD, WR Enable 0 ns
xMS, RD, WR Enable to CLKOUT High 0.25 tCK – 7 ns
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable

CLKOUT

BR

2
2

t

BH

t

BS

0ns
0ns

CLKOUT

PMS, DMS

BMS, RD

WR

BG

BGH

t

SD

t

SDB

t

SDBH

Figure 16. Bus Request–Bus Grant

t

SEC

t

SE

t

SEH

REV. 0

–19–

ADSP-2186
TIMING PARAMETERS

Parameter Min Max Unit
Memory Read

Timing Requirements:
t

RDD

t

AA

t

RDH

Switching Characteristics:
t

RP

t

CRD

t

ASR

t

RDA

t

RWR

w = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

RD Low to Data Valid 0.5 tCK – 9 + w ns

A0–A13, xMS to Data Valid 0.75 tCK – 10.5 + w ns
Data Hold from RD High 0 ns

RD Pulse Width 0.5 tCK – 5 + w ns
CLKOUT High to RD Low 0.25 tCK – 5 0.25 tCK + 7 ns
A0–A13, xMS Setup before RD Low 0.25 tCK – 6 ns
A0–A13, xMS Hold after RD Deasserted 0.25 tCK – 3 ns
RD High to RD or WR Low 0.5 t

CLKOUT

– 5 ns

CK

A0 – A13

DMS, PMS,

BMS, IOMS,

CMS

RD

WR

t

RDA

t

ASR

t

CRD

D

t

AA

t

RP

t

RDD

t

RDH

t

RWR

Figure 17. Memory Read

–20–

REV. 0

ADSP-2186

Parameter Min Max Unit
Memory Write

Switching Characteristics:
t

DW

t

DH

t

WP

t

WDE

t

ASW

t

DDR

t

CWR

t

AW

t

WRA

t

WWR

w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.

Data Setup before WR High 0.5 t
Data Hold after WR High 0.25 t

– 7+ w ns

CK

– 2 ns

CK

WR Pulse Width 0.5 tCK – 5 + w ns
WR Low to Data Enabled 0 ns

A0-A13, xMS Setup before WR Low 0.25 t

– 6 ns

CK

Data Disable before WR or RD Low 0.25 tCK – 7 ns
CLKOUT High to WR Low 0.25 t
A0-A13, xMS, Setup before WR Deasserted 0.75 t
A0-A13, xMS Hold after WR Deasserted 0.25 t

– 5 0.25 tCK + 7 ns

CK

– 9 + w ns

CK

– 3 ns

CK

WR High to RD or WR Low 0.5 tCK – 5 ns

CLKOUT

A0–A13

DMS, PMS,
BMS, CMS,

IOMS

WR

RD

t

WRA

t

ASW

t

D

CWR

t

WDE

t

WP

t

AW

t

DW

t

WWR

t

DH

t

DDR

Figure 18. Memory Write

REV. 0

–21–

ADSP-2186
TIMING PARAMETERS

Parameter Min Max Unit
Serial Ports

Timing Requirements:
t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics:
t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

TDE

t

TDV

t

SCDD

t

RDV

SCLK Period 50 ns
DR/TFS/RFS Setup before SCLK Low 4 ns
DR/TFS/RFS Hold after SCLK Low 7 ns
SCLK

CLKOUT High to SCLK

Width 20 ns

IN

OUT

0.25 t

CK

0.25 t

+ 10 ns

CK

SCLK High to DT Enable 0 ns
SCLK High to DT Valid 15 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 15 ns

OUT

DT Hold after SCLK High 0 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 14 ns
SCLK High to DT Disable 15 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns

CLKOUT

SCLK

DR
TFS
RFS

RFS

OUT

TFS

OUT

DT

TFS

OUT

ALTERNATE

FRAME MODE

RFS

MULTICHANNEL MODE,

MULTICHANNEL MODE,

OUT

FRAME DELAY 0

(MFD = 0)

TFS

ALTERNATE

FRAME MODE

RFS

FRAME DELAY 0

(MFD = 0)

t

CC

IN
IN

IN

IN

t

SCDE

t

t

RH

t

t

TDE

t

TDE

RD

SCDV

t

TDV

t

RDV

t

TDV

t

RDV

t

CC

t

t

SCS

SCH

t

t

SCDH

SCDD

t

SCK

t

SCP

t

SCP

Figure 19. Serial Ports

–22–

REV. 0

ADSP-2186

Parameter Min Max Unit
IDMA Address Latch

Timing Requirements:
t

IALP

t

IASU

t

IAH

t

IKA

t

IALS

NOTES

1

Start of Address Latch = IS Low and IAL High.

2

Start of Write or Read = IS Low and IWR Low or IRD Low.

3

End of Address Latch = IS High or IAL Low.

Duration of Address Latch
IAD15–0 Address Setup before Address Latch End
IAD15–0 Address Hold after Address Latch End
IACK Low before Start of Address Latch
Start of Write or Read after Address Latch End

IACK

IAL

IS

IAD 15–0

IRD

OR

IWR

1, 3

3

3

2, 3

2, 3

t

IKA

t

IALP

t

IASU

t

IALS

t

10 ns
5ns
2ns
0ns
3ns

IAH

Figure 20. IDMA Address Latch

REV. 0

–23–

ADSP-2186
TIMING PARAMETERS

Parameter Min Max Unit
IDMA Write, Short Write Cycle

Timing Requirements:
t

IKW

t

IWP

t

IDSU

t

IDH

IACK Low before Start of Write
Duration of Write

1, 2

IAD15–0 Data Setup before End of Write
IAD15–0 Data Hold after End of Write

1

2, 3, 4

Switching Characteristics:
t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

End of Write = IS High or IWR High.

3

If Write Pulse ends before IACK Low, use specifications t

4

If Write Pulse ends after IACK Low, use specifications t

Start of Write to IACK High 15 ns

, t

IDSU

IDH

, t

.

IKSU

IKH

t

IKW

IACK

IS

IWR

2, 3, 4

.

0ns
15 ns
5ns
2ns

t

IKHW

t

IWP

t

t

IDSU

IDH

IAD 15–0

DATA

Figure 21. IDMA Write, Short Write Cycle

–24–

REV. 0

ADSP-2186

Parameter Min Max Unit
IDMA Write, Long Write Cycle

Timing Requirements:
t

IKW

t

IKSU

t

IKH

IACK Low before Start of Write
IAD15–0 Data Setup before IACK Low
IAD15–0 Data Hold after IACK Low

Switching Characteristics:
t

IKLW

t

IKHW

NOTES

1

Start of Write = IS Low and IWR Low.

2

If Write Pulse ends before IACK Low, use specifications t

3

If Write Pulse ends after IACK Low, use specifications t

4

This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

Start of Write to IACK Low
Start of Write to IACK High 15 ns

IACK

IS

4

IKSU

IDSU

1

2, 3, 4

2, 3, 4

, t

.

IDH

, t

.

IKH

t

IKW

t

IKHW

0ns

0.5 tCK + 10 ns
2ns

t

IKLW

1.5 t

CK

ns

IWR

IAD 15–0

t

IKSU

DATA

t

IKH

Figure 22. IDMA Write, Long Write Cycle

REV. 0

–25–

ADSP-2186
TIMING PARAMETERS

Parameter Min Max Unit
IDMA Read, Long Read Cycle

Timing Requirements:
t

IKR

t

IRP

IACK Low before Start of Read
Duration of Read

1

Switching Characteristics:
t

IKHR

t

IKDS

t

IKDH

t

IKDD

t

IRDE

t

IRDV

t

IRDH1

t

IRDH2

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

3

DM read or first half of PM read.

4

Second half of PM read.

IACK High after Start of Read
IAD15–0 Data Setup before IACK Low 0.5 tCK – 10 ns
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)
IAD15–0 Previous Data Hold after Start of Read (PM2)

IACK

IS

IRD

1

0ns
15 ns

1

2

2

3

4

t

t

IKR

IKHR

t

IRP

0ns

2 tCK – 5 ns
tCK – 5 ns

15 ns

10 ns

IAD 15–0

t

IRDE

t

IRDV

PREVIOUS

DATA

t

IRDH

t

IKDS

READ
DATA

Figure 23. IDMA Read, Long Read Cycle

t

IKDD

t

IKDH

–26–

REV. 0

ADSP-2186

Parameter Min Max Unit
IDMA Read, Short Read Cycle

Timing Requirements:
t

IKR

t

IRP

IACK Low before Start of Read
Duration of Read 15 ns

Switching Characteristics:
t

IKHR

t

IKDH

t

IKDD

t

IRDE

t

IRDV

NOTES

1

Start of Read = IS Low and IRD Low.

2

End of Read = IS High or IRD High.

IACK High after Start of Read
IAD15–0 Data Hold after End of Read
IAD15–0 Data Disabled after End of Read
IAD15–0 Previous Data Enabled after Start of Read 0 ns
IAD15–0 Previous Data Valid after Start of Read 15 ns

IACK

IRD

IAD 15–0

1

1

2

2

t

IKR

t

IS

t

IRDE

IKHR

t

IRDV

t

IRP

PREVIOUS

DATA

0ns

15 ns

0ns

10 ns

t

IKDH

t

IKDD

REV. 0

Figure 24. IDMA Read, Short Read Cycle

–27–

ADSP-2186

A4/IAD3
A5/IAD4

GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8

A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12

GND

CLKIN

XTAL

VDD

CLKOUT

GND

VDD

WR

RD
BMS
DMS
PMS

IOMS

CMS

100-Lead TQFP Package Pinout

A2/IAD1

A3/IAD2
100

1

PIN 1

2

IDENTIFIER

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

PWDACK

A0

A1/IAD0

9998979695949392919089888786858483828180797877

PF0 [MODE A]

BGH

PF1 [MODE B]

GND

PWD

VDD

PF2 [MODE C]

PF3

FL0

FL1

FL2

D23

D22

D21

D20

GND

D19

D18

ADSP-2186

TOP VIEW

(Not to Scale)

D17

D16
76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

D15
D14
D13
D12
GND
D11

D10
D9
VDD
GND
D8
D7/IWR
D6/IRD

D5/IAL
D4/IS

GND
VDD
D3/IACK
D2/IAD15
D1/IAD14
D0/IAD13

BG
EBG
BR
EBR

26

IRQE+PF4

27

IRQL0+PF5

28

GND

29

IRQL1+PF6

30

IRQ2+PF7

31

DT0

32

TFS0

33

RFS0

34

DR0

35

36

VDD

SCLK0

37

DT1

38

TFS1

39

RFS1

40

DR1

41

GND

42

SCLK1

43

44

RESET

ERESET

45

EMS

47

ECLK

48

49

ELIN

ELOUT

50

EINT

46
EE

–28–

REV. 0

ADSP-2186

The ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

TQFP Pin Configurations

TQFP Pin TQFP Pin TQFP Pin TQFP Pin
Number Name Number Name Number Name Number Name

1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17
3 GND 28 GND 53 EBG 78 D18
4 A6/IAD5 29 IRQL1 + PF6 54
5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDD 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDD 61 D4/IS 86 FL1
12 GND 37 DT1 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1 63 D6/IRD 88 PF3
14 XTAL 39 RFS1 64 D7/IWR 89 PF2 [Mode C]
15 VDD 40 DR1 65 D8 90 VDD
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDD 92 GND
18 VDD 43 ERESET 68 D9 93 PF1 [Mode B]
19 WR 44 RESET 69 D10 94 PF0 [Mode A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2

BG 79 D19

REV. 0

–29–

ADSP-2186

ORDERING GUIDE

Ambient Instruction
Temperature Rate Package Package

Part Number Range (MHz) Description Option*

ADSP-2186KST-115 0°C to +70°C 28.8 100-Lead TQFP ST-100
ADSP-2186BST-115 –40°C to +85°C 28.8 100-Lead TQFP ST-100
ADSP-2186KST-133 0°C to +70°C 33.3 100-Lead TQFP ST-100
ADSP-2186BST-133 –40°C to +85°C 33.3 100-Lead TQFP ST-100
ADSP-2186KST-160x 0°C to +70°C 40.0 100-Lead TQFP ST-100
ADSP-2186BST-160x –40°C to +85°C 40.0 100-Lead TQFP ST-100

*ST = Plastic Thin Quad Flatpack (TQFP).

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

100-Lead Metric Thin Plastic Quad Flatpack (TQFP)

(ST-100)

0.640 (16.25)

0.024 (0.75)

0.022 (0.60) TYP

0.020 (0.50)

SEATING

PLANE

0.063 (1.60) MAX

0.630 (16.00)

0.620 (15.75)

0.555 (14.05)

0.551 (14.00)

0.547 (13.90)

0.476 (12.10)

0.474 (12.05)

0.472 (12.00)

100 76

12°

1

TYP

TYP SQ

TYP SQ

TYP SQ

75

0.004

(0.102)

MAX LEAD

COPLANARITY

0° – 10°

25

26

6° ± 4°

0.007 (0.177)

0.005 (0.127) TYP

0.003 (0.077)

–30–

TOP VIEW

(PINS DOWN)

0.020 (0.50)
BSC

LEAD PITCH

50

0.010 (0.27)

0.009 (0.22) TYP

0.006 (0.17)

LEAD WIDTH

51

REV. 0

–31–

C2999–6–3/97

–32–

PRINTED IN U.S.A.