ANALOG DEVICES ADSP-2185 MKSTZ Datasheet

Download

Page 1

DSP

FEATURES

Performance

13.3 ns Instruction Cycle Time @ 2.5 V (Internal), 75 MIPS Sustained Performance

Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power

Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition

Low Power Dissipation in Idle Mode

Integration

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words Program Memory RAM 16K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA

Microcomputer ADSP-2185M

System Interface

Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to

On-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System

Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

MEMORY

DATA ADDRESS

GENERATORS

DAG1

DAG2

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

ICE-Port is a trademark of Analog Devices, Inc.

PROGRAM

SEQUENCER

SHIFTERMACALU

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

PROGRAM

MEMORY

16K

ⴛ

24 BIT

SPORT0

SERIAL PORTS

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FULL MEMORY MODE

DATA

MEMORY

16K ⴛ 16 BIT

SPORT1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

Page 2

ADSP-2185M* Product Page Quick Links

Comparable Parts

View a parametric search of comparable parts

Last Content Update: 08/30/2016

Documentation

Application Notes

• AN-227: Digital Control System Design with the ADSP-2100 Family

• AN-334: Digital Signal Processing Techniques

• AN-524: ADV601/ADV611 Bin Width Calculation in ADSP-21xx DSP

• EE-06: ADSP-21xx Serial Port Startup Issues

• EE-100: ADSP-218x External Overlay Memory

• EE-102: Mode D and ADSP-218x Pin Compatibility - the FAQs

• EE-11: ADSP-2181 Priority Chain & IDMA Holdoffs

• EE-115: ADSP-2189 IDMA Interface to Motorola MC68300 Family of Microprocessors

• EE-12: Interrupts and Programmable Flags on the ADSP-2185/2186

• EE-121: Porting Code from ADSP-21xx to ADSP-219x

• EE-122: Coding for Performance on the ADSP-219x

• EE-123: An Overview of the ADSP-219x Pipeline

• EE-124: Booting up the ADSP-2192

• EE-125: ADSP-218x Embedded System Software Management and In-System-Programming (ISP)

• EE-129: ADSP-2192 Interprocessor Communication

• EE-130: Making Fast Transition from ADSP-21xx to ADSP-219x

• EE-131: Booting the ADSP-2191/95/96 DSPs

• EE-133: Converting From Legacy Architecture Files To Linker Description Files for the ADSP-218x

• EE-139: Interfacing the ADSP-2191 to an AD7476 via the SPI Port

• EE-142: Autobuffering, C and FFTs on the ADSP-218x

• EE-144: Creating a Master-Slave SPI Interface Between Two ADSP-2191 DSPs

• EE-145: SPI Booting of the ADSP-2191 using the Atmel AD25020N on an EZ-KIT Lite Evaluation Board

• EE-146: Implementing a Boot Manager for ADSP-218x Family DSPs

• EE-152: Using Software Overlays with the ADSP-219x and VisualDSP 2.0++

• EE-153: ADSP-2191 Programmable PLL

• EE-154: ADSP-2191 Host Port Interface

• EE-156: Support for the H.100 protocol on the ADSP-2191

• EE-158: ADSP-2181 EZ-Kit Lite IDMA to PC Printer Port Interface

Page 3

• EE-164: Advanced EPROM Boot and No-boot Scenarios with ADSP-219x DSPs

• EE-168: Using Third Overtone Crystals with the ADSP-218x DSP

• EE-17: ADSP-2187L Memory Organization

• EE-18: Choosing and Using FFTs for ADSP-21xx

• EE-188: Using C To Implement Interrupt-Driven Systems On ADSP-219x DSPs

• EE-2: Using ADSP-218x I/O Space

• EE-226: ADSP-2191 DSP Host Port Booting

• EE-227: CAN Configuration Procedure for ADSP-21992 DSPs

• EE-249: Implementing Software Overlays on ADSP-218x DSPs with VisualDSP++®

• EE-32: Language Extensions: Memory Storage Types, ASM & Inline Constructs

• EE-33: Programming The ADSP-21xx Timer In C

• EE-35: Troubleshooting your ADSP-218x EZ-ICE

• EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users

• EE-36: ADSP-21xx Interface to the IOM-2 bus

• EE-38: ADSP-2181 IDMA Port - Cycle Steal Timing

• EE-39: Interfacing 5V Flash Memory to an ADSP-218x (Byte Programming Algorithm)

• EE-48: Converting Legacy 21xx Systems To A 218x System Design

• EE-5: ADSP-218x Full Memory Mode vs. Host Memory Mode

• EE-60: Simulating an RS-232 UART Using the Synchronous Serial Ports on the ADSP-21xx Family DSPs

• EE-64: Setting Mode Pins on Reset

• EE-68: Analog Devices JTAG Emulation Technical Reference

• EE-71: Minimum Rise Time Specs for Critical Interrupt and Clock Signals on the ADSP-21x1/21x5

• EE-78: BDMA Usage on 100 pin ADSP-218x DSPs Configured for IDMA Use

• EE-79: EPROM Booting In Host Mode with 100 Pin 218x Processors

• EE-82: Using an ADSP-2181 DSP's IO Space to IDMA Boot Another ADSP-2181

• EE-89: Implementing A Software UART on the ADSP-2181 EZ-Kit-Lite

• EE-90: Using the 21xx C-FFT Library

• EE-96: Interfacing Two AD73311 Codecs to the ADSP-218x

Data Sheet

• ADSP-2185M: 16-bit, 75 MIPS, 2.5v, 2 serial ports, host port, 80 KB RAM Data Sheet

Integrated Circuit Anomalies

• ADSP-2185M Anomaly List for Revision 2.1

Processor Manuals

• ADSP 21xx Processors: Manuals

• ADSP-218x DSP Hardware Reference

• ADSP-218x DSP Instruction Set Reference

• Using the ADSP-2100 Family Volume 2

Software Manuals

• VisualDSP++ 3.5 Assembler and Preprocessor Manual for ADSP-218x and ADSP-219x DSPs

• VisualDSP++ 3.5 C Compiler and Library Manual for ADSP-218x DSPs

• VisualDSP++ 3.5 C/C++ Compiler and Library Manual for ADSP-219x Processors

• VisualDSP++ 3.5 Linker and Utilities Manual for 16-Bit Processors

• VisualDSP++ 3.5 Loader Manual for 16-Bit Processors

Software and Systems Requirements

• Software and Tools Anomalies Search

Tools and Simulations

• ADSP-218xM IBIS Datafile (LQFP Package)

Reference Materials

Analog Dialogue

• For Efficient Signal Processing in Embedded Systems, Take a DSP, not a RISC

Product Selection Guide

• ADI Complementary Parts Guide - Supervisory Devices and DSP Processors

Design Resources

• ADSP-2185M Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Discussions

View all ADSP-2185M EngineerZone Discussions

Sample and Buy

Visit the product page to see pricing options

Technical Support

Submit a technical question or find your regional support number

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

Page 4

ADSP-2185M

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7

Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7

Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11

Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Mapped Registers (New to the

ADSP-2185M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13

Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14

Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14

Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14

Internal Memory DMA Port

(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15

Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15

IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16

Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16

Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17

Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17

PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17

Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17

RECOMMENDED OPERATING CONDITIONS . . . . . 18

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19

GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19

FREQUENCY DEPENDENCY FOR

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20

POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30

IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31

IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32

IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33

IDMA Read, Short Read Cycle in Short Read

Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35

LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37

Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38

OUTLINE DIMENSIONS

100-Lead Metric Thin Plastic Quad Flatpack

(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

OUTLINE DIMENSIONS

144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Tables

Table I. Interrupt Priority and Interrupt

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11

Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12

Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13

Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14

–2–

REV. 0

Page 5

ADSP-2185M

GENERAL DESCRIPTION

The ADSP-2185M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications.

The ADSP-2185M combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.

The ADSP-2185M integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2185M is available in a 100-lead LQFP package and 144 Ball Mini-BGA.

In addition, the ADSP-2185M supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (× squared), biased rounding, result-free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility.

Fabricated in a high-speed, low-power, CMOS process, the ADSP-2185M operates with a 13.3 ns instruction cycle time. Every instruction can execute in a single processor cycle.

The ADSP-2185M’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2185M can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2185M. The System Builder provides a high-level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display different portions of the hardware environment.

The EZ-KIT Lite is a hardware/software kit offering a complete evaluation environment for the ADSP-218x family: an ADSP2189M-based evaluation board with PC monitor software plus assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features:

• 75 MHz ADSP-2189M

• Full 16-Bit Stereo Audio I/O with AD73322 Codec

• RS-232 Interface

• EZ-ICE Connector for Emulator Control

• DSP Demo Programs

• Evaluation Suite of VisualDSP

The ADSP-218x EZ-ICE debugging of an ADSP-2185M system. The ADSP-2185M integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2185M device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE-Compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector.

Additional Information

This data sheet provides a general overview of ADSP-2185M functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools data sheet.

Emulator aids in the hardware

EZ-ICE is a registered trademark of Analog Devices, Inc.

REV. 0

–3–

Page 6

ADSP-2185M

DATA ADDRESS

GENERATORS

DAG1

DAG2

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

SHIFTERMACALU

POWER-DOWN

CONTROL

MEMORY

PROGRAM

MEMORY

16K

ⴛ

24 BIT

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SPORT0

MEMORY

16K ⴛ 16 BIT

SERIAL PORTS

SPORT1

DATA

PROGRAMMABLE

TIMER

Figure 1. Functional Block Diagram

I/O

AND

FLAGS

FULL MEMORY MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

ARCHITECTURE OVERVIEW

The ADSP-2185M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2185M assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2185M. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations.

The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations.

The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2185M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers.

Efficient data transfer is achieved with the use of five internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses.

Program memory can store both instructions and data, permitting the ADSP-2185M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2185M can fetch an operand from program memory and the next instruction in the same cycle.

In lieu of the address and data bus for external memory connection, the ADSP-2185M may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM.

An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of

–4–

REV. 0

Page 7

ADSP-2185M

external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-2185M to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.

The ADSP-2185M can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two levelsensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.

Each port can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-2185M provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs.

A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2185M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2185M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual.

• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.

• SPORTs can use an external serial clock or generate their own serial clock internally.

• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time- division multiplexed, serial bitstream.

• SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration.

PIN DESCRIPTIONS

The ADSP-2185M is available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.

REV. 0

–5–

Page 8

ADSP-2185M

Common-Mode Pins

Pin Name # of Pins I/O Function

RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output IOMS 1 O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output

IRQ2 1 I Edge- or Level-Sensitive Interrupt Request

PF7 I/O Programmable I/O Pin

IRQL1 1 I Level-Sensitive Interrupt Requests

PF6 I/O Programmable I/O Pin IRQL0 1 I Level-Sensitive Interrupt Requests

PF5 I/O Programmable I/O Pin IRQE 1 I Edge-Sensitive Interrupt Requests

PF4 I/O Programmable I/O Pin Mode D 1 I Mode Select Input—Checked Only During RESET

PF3 I/O Programmable I/O Pin During Normal Operation Mode C 1 I Mode Select Input—Checked Only During RESET

PF2 I/O Programmable I/O Pin During Normal Operation Mode B 1 I Mode Select Input—Checked Only During RESET

PF1 I/O Programmable I/O Pin During Normal Operation Mode A 1 I Mode Select Input—Checked Only During RESET

PF0 I/O Programmable I/O Pin During Normal Operation

CLKIN, XTAL 2 I Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output SPORT0 5 I/O Serial Port I/O Pins SPORT1 5 I/O Serial Port I/O Pins

IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO PWD 1 I Power-Down Control Input PWDACK 1 O Power-Down Control Output FL0, FL1, FL2 3 O Output Flags V

DDINT

DDEXT

2 I Internal VDD (2.5 V) Power (LQFP)

4 I External VDD (2.5 V or 3.3 V) Power (LQFP) GND 10 I Ground (LQFP) V

DDINT

DDEXT

4 I Internal VDD (2.5 V) Power (Mini-BGA)

7 I External VDD (2.5 V or 3.3 V) Power (Mini-BGA) GND 20 I Ground (Mini-BGA)

EZ-Port 9 I/O For Emulation Use

NOTES

Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.

SPORT configuration determined by the DSP System Control Register. Software configurable.

–6–

REV. 0

Page 9

ADSP-2185M

Memory Interface Pins

The ADSP-2185M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.

The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.

Full Memory Mode Pins (Mode C = 0)

Pin Name # of Pins I/O Function

A13:0 14 O Address Output Pins for Program, Data, Byte, and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also

used as Byte Memory Addresses.)

Host Mode Pins (Mode C = 1)

Pin Name # of Pins I/O Function

IAD15:0 16 I/O IDMA Port Address/Data Bus A0 1 O Address Pin for External I/O, Program, Data, or Byte Access D23:8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces

IWR 1 I IDMA Write Enable

IRD

1 I IDMA Read Enable

IAL 1 I IDMA Address Latch Pin

IS 1 I IDMA Select IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain

NOTE

In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

REV. 0

–7–

Page 10

ADSP-2185M

Terminating Unused Pins

The following table shows the recommendations for terminating unused pins.

Pin Terminations

I/O 3-State Reset Hi-Z*

Pin Name (Z) State Caused By Unused Configuration

XTAL I I Float CLKOUT O O Float A13:1 or O (Z) Hi-Z BR, EBR Float IAD 12:0 I/O (Z) Hi-Z IS Float A0 O (Z) Hi-Z BR, EBR Float D23:8 I/O (Z) Hi-Z BR, EBR Float D7 or I/O (Z) Hi-Z BR, EBR Float IWR I I High (Inactive) D6 or I/O (Z) Hi-Z BR, EBR Float IRD IIBR, EBR High (Inactive) D5 or I/O (Z) Hi-Z Float IAL I I Low (Inactive) D4 or I/O (Z) Hi-Z BR, EBR Float IS I I High (Inactive) D3 or I/O (Z) Hi-Z BR, EBR Float IACK Float D2:0 or I/O (Z) Hi-Z BR, EBR Float IAD15:13 I/O (Z) Hi-Z IS Float

PMS O (Z) O BR, EBR Float DMS O (Z) O BR, EBR Float BMS O (Z) O BR, EBR Float IOMS O (Z) O BR, EBR Float CMS O (Z) O BR, EBR Float RD O (Z) O BR, EBR Float WR O (Z) O BR, EBR Float BR I I High (Inactive) BG O (Z) O EE Float BGH O O Float IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float

SCLK0 I/O I Input = High or Low, Output = Float RFS0 I/O I High or Low DR0 I I High or Low TFS0 I/O I High or Low DT0 O O Float SCLK1 I/O I Input = High or Low, Output = Float RFS1/IRQ0 I/O I High or Low DR1/FI I I High or Low TFS1/IRQ1 I/O I High or Low DT1/FO O O Float EE I I Float

EBR I I Float EBG O O Float ERESET I I Float EMS O O Float EINT I I Float

ECLK I I Float ELIN I I Float ELOUT O O Float

NOTES *Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.

2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as inter-

rupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float.

3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used.

–8–

REV. 0

Page 11

ADSP-2185M

Interrupts

The interrupt controller allows the processor to respond to the 11 possible interrupts and reset with minimum overhead. The ADSP-2185M provides four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-2185M also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except power- down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table I.

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source Of Interrupt Address (Hex)

Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power-Down (Nonmaskable) 002C

IRQ2 0004 IRQL1 0008 IRQL0 000C

SPORT0 Transmit 0010 SPORT0 Receive 0014 IRQE 0018 BDMA Interrupt 001C SPORT1 Transmit or IRQ1 0020 SPORT1 Receive or IRQ0 0024 Timer 0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.

The ADSP-2185M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts.

The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless

of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA.

ENA INTS; DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2185M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are:

• Power-Down

•Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external power dissipation.

Power-Down

The ADSP-2185M processor has a low power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual, “System Interface” chapter, for detailed information about the power-down feature.

• Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles.

• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during powerdown without affecting the lowest power rating and 200 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up.

• Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt.

• Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor has entered power-down.

Idle

When the ADSP-2185M is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur.

REV. 0

–9–

Page 12

ADSP-2185M

Slow Idle

The IDLE instruction is enhanced on the ADSP-2185M to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.

The format of the instruction is:

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2185M will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or

128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the ADSP-2185M, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (modeselectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The

ADSP-2185M also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals.

Clock Signals

The ADSP-2185M can be clocked by either a crystal or a TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, for detailed information on this power-down feature.

If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected.

The ADSP-2185M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields a 13 ns processor cycle (which is equivalent to 75 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled.

Because the ADSP-2185M includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.

1/2x CLOCK

CRYSTAL

SERIAL DEVICE

FULL MEMORY MODE

CLKIN

XTAL

FL0–2

IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6

MODE D/PF3 MODE C/PF2 MODE A/PF0 MODE B/PF1

SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR F

SCLK0 RFS0 TFS0 DT0 DR0

SPORT1

SPORT0

ADDR13–0

DATA23–0

PWDACK

BMS

IOMS

PMS DMS CMS

BGH PWD

BR BG

13–0

23–16

ADSP-2185M

15–8

10–0

23–8

13–0

23–0

A0–A21

DATA

ADDR

(PERIPHERALS)

DATA

ADDR

DATA

PM SEGMENTS

DM SEGMENTS

BYTE

MEMORY

I/O SPACE

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

Figure 2. Basic System Interface

–10–

1/2x CLOCK

CRYSTAL

SERIAL DEVICE

SYSTEM

INTERFACE

␮CONTROLLER

HOST MEMORY MODE

ADSP-2185M

CLKIN

XTAL

FL0–2

IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6

MODE D/PF3 MODE C/PF2 MODE A/PF0 MODE B/PF1

SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI

SCLK0 RFS0 TFS0 DT0 DR0

IDMA PORT

IRD/D6 IWR/D7 IS/D4

IAL/D5 IACK/D3

IAD15–0

SPORT1

SPORT0

DATA23–8

BMS

IOMS

PMS DMS CMS

BGH PWD

PWDACK

BR BG

REV. 0

Page 13

CLKIN XTAL CLKOUT

DSP

Figure 3. External Crystal Connections

RESET

The RESET signal initiates a master reset of the ADSP-2185M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid V

is applied to

the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, t

RSP

The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is

ADSP-2185M

performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.

Power Supplies

The ADSP-2185M has separate power supply connections for the internal (V

) and external (V

DDINT

The internal supply must meet the 2.5 V requirement. The external supply can be connected to either a 2.5 V or 3.3 V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, regardless of the external supply voltage. This feature provides maximum flexibility in mixing 2.5 V and 3.3 V components.

MODES OF OPERATION Setting Memory Mode

Memory Mode selection for the ADSP-2185M is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive.

Passive Configuration

Passive Configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 10 kΩ, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch.

) power supplies.

DDEXT

Table II. Modes of Operation

MODE D MODE C MODE B MODE A Booting Method

X 0 0 0 BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.

X010No automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations.

0100BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (REQUIRES ADDITIONAL HARDWARE).

0101IDMA feature is used to load any internal memory as desired. Program

execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK has active pull-down.

1100BDMA feature is used to load the first 32 program memory words from

the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pull down. (REQUIRES ADDITIONAL HARDWARE)

1101IDMA feature is used to load any internal memory as desired. Program

execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK requires external pull-down.

NOTE

Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

REV. 0

–11–

Page 14

ADSP-2185M

Active Configuration

Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver’s level hover around the logic switching point.

IACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be “wire OR’d.”

Mode D = 1 and in host mode: IACK is an open drain and requires an external pull-down, but multiple IACK pins can be “wire OR’d” together.

PM (MODE B = 0)

ALWAYS ACCESSIBLE AT ADDRESS 0x0000 – 0x1FFF

ACCESSIBLE WHEN PMOVLAY = 0

ACCESSIBLE WHEN PMOVLAY = 1

EXTERNAL MEMORY

ACCESSIBLE WHEN PMOVLAY = 2

0x2000 – 0x3FFF

0x2000 – 0

3FFF

0x2000 – 0

3FFF

PM (MODE B = 1)

MEMORY ARCHITECTURE

The ADSP-2185M provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-2185M.

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The ADSP2185M has 16K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus.

Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is 16 bits wide only.

RESERVED

ACCESSIBLE WHEN PMOVLAY = 0

EXTERNAL MEMORY

NOTES:

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

SEE TABLE III FOR PMOVLAY BITS

0x2000 – 0x3FFF

RESERVED

0000 – 1FFF

0x0000 –

1FFF

PROGRAM MEMORY

MODE B = 0

8K INTERNAL PMOVLAY = 0

8K EXTERNAL

PMOVLAY = 1, 2

INTERNAL

ADDRESS

0x3FFF

0x2000

0x1FFF

0x0000

PROGRAM MEMORY

MODE B = 1

8K INTERNAL PMOVLAY = 0

EXTERNAL

ADDRESS

0x3FFF

0x2000

0x1FFF

0x0000

Figure 4. Program Memory

Table III. PMOVLAY Bits

PMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable 1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF

–12–

REV. 0

Page 15

ADSP-2185M

(

)

RESERVED, ALWAYS

SET TO 0

SPORT0 ENABLE 0 = DISABLE 1 = ENABLE

DM(0x3FFF)

SYSTEM CONTROL

SPORT1 ENABLE 0 = DISABLE 1 = ENABLE

SPORT1 CONFIGURE 0 = FI, FO, IRQ0, IRQ1, SCLK 1 = SPORT1

DISABLE BMS 0 = ENABLE BMS 1 = DISABLE BMS, EXCEPT WHEN MEMORY STROBES ARE THREE-STATED

PWAIT PROGRAM MEMORY WAIT STATES

00000100000 00111

1514131211109876543210

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD

ALWAYS BE WRITTEN WITH ZEROS.

RESERVED

SET TO 0

Data Memory

Data Memory (Full Memory Mode) is a 16-bit-wide space used

for the storage of data variables and for memory-mapped control registers. The ADSP-2185M has 16K words on Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses

DATA MEMORY

ALWAYS ACCESSIBLE AT ADDRESS

x2000 – 0x3FFF

0x0000 – 0x1FFF

ACCESSIBLE WHEN DM OVLAY = 0

EXTERNAL MEMORY

ACCESSIBLE WHEN DMOVLAY = 1

ACCESSIBLE WHEN DMOVLAY = 2

0x0000 – 0x1FFF

complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register and the wait state mode bit.

Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0).

0x0000 – 0x1FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

INTERNAL

8160 WORDS

8K INTERNAL DMOVLAY = 0

EXTERNAL 8K

DMOVLAY = 1, 2

NOTE:

SEE TABLE IV FOR DMOVAY BITS

ADDR

0x3FFF

0x3FE0

0x3FDF

0x2000

0x1FFF

0x0000

Figure 5. Data Memory Map

Table IV. DMOVLAY Bits

DMOVLAY Memory A13 A12:0

0 Internal Not Applicable Not Applicable 1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF

Memory Mapped Registers (New to the ADSP-2185M)

The ADSP-2185M has three memory mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control, and System Control) provide the ADSP-2185M’s wait state and BMS control features. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a grey field. These bits should always be written with zeros.

1514131211109876543210

11111111111 11111

DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0

WAIT STATE MODE SELECT 0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING

FROM 0 TO 7)

1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING

FROM 0 TO 15)

Figure 6. Wait State Control Register

PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL

1514131211109876543210

11111011000 00000

BMWAIT CMSSEL

Figure 7. Programmable Flag and Composite Control Register

REV. 0

WAITSTATE CONTROL

0 = DISABLE CMS 1 = ENABLE CMS

WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM

PFTYPE 0 = INPUT 1 = OUTPUT

DM(0ⴛ3FFE)

DM(0x3FE6)

Figure 8. System Control Register

I/O Space (Full Memory Mode)

The ADSP-2185M supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0–3, which in combination with the wait state mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table V.

–13–

Page 16

ADSP-2185M

Table V. Wait States

Address Range Wait State Register

0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit 0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit 0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit 0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit

Composite Memory Select (CMS)

The ADSP-2185M has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality.

Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit.

The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.

Byte Memory Select (BMS)

The ADSP-2185M’s BMS disable feature combined with the CMS pin allows use of multiple memories in the byte memory

space. For example, an EPROM could be attached to the BMS select, and an SRAM could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the SRAM.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2185M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register and the wait state mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred.

1514131211109876543210

00000000000 01000

BMPAGE

BDMA CONTROL

BDMA

OVERLAY

BITS

DM (0ⴛ3FE3)

BTYPE

BDIR 0 = LOAD FROM BM

1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA

Figure 9. BDMA Control Register

The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table VI shows the data formats supported by the BDMA circuit.

Table VI. Data Formats

BTYPE Internal Memory Space Word Size Alignment

00 Program Memory 24 Full Word 01 Data Memory 16 Full Word 10 Data Memory 8 MSBs 11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed.

–14–

REV. 0

Page 17

ADSP-2185M

IDMA OVERLAY

DM (0x3FE7)

RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY

0000000 00000000

1514131211109876543210

SHORT READ ONLY 0 = ENABLE 1 = DISABLE

IDMA CONTROL (U = UNDEFINED AT RESET)

DM (0x3FE0)

IDMAA ADDRESS

UUU UUUUUUUUUUUU

1514131211109876543210

IDMAD DESTINATION MEMORY TYPE 0 = PM 1 = DM

NOTES: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS

SHOULD ALWAYS BE WRITTEN WITH ZEROS.

RESERVED SET TO 0

The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory. For ADSP-2185M, set to zero BDMA overlay bits in BDMA control register.

The BMWAIT field, which has 4 bits on ADSP-2185M, allows selection up to 15 wait states for BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication between a host system and the ADSP-2185M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’s memorymapped control registers. A typical IDMA transfer process is described as follows:

1. Host starts IDMA transfer

2. Host checks IACK control line to see if the DSP is busy

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1, the value of bits 7:0 represent the IDMA overlay: bits 14:8 must be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the starting address of internal memory to be accessed and Bit 14 reflects PM or DM for access. For ADSP-2185M, IDDMOVLAY and IDPMOVLAY bits in IDMA overlay register should be set to zero.

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

nal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed the

previous IDMA operation.

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-2185M is operating at full speed.

The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access.

IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register.

Once the address is stored, data can be read from, or written to, the ADSP-2185M’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2185M that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle.

Once an access has occurred, the latched address is automatically incremented, and another access can occur.

REV. 0

Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2185M to write the address onto the IAD0–14 bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register. This register, shown below, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 31 applies for short reads. When Bit 14 in 0x3FE7 is set to zero, short reads use the timing shown in Figure 32. For ADSP-2185M, IDDMOVLAY and IDPMOVLAY bits in IDMA overlay register should be set to zero.

Refer to the following figures for more information on IDMA and DMA memory maps.

Figure 10. IDMA Control/OVLAY Registers

DMA

PROGRAM MEMORY

OVLAY

ALWAYS ACCESSIBLE AT ADDRESS

0000 – 0x1FFF

2000 –

ACCESSIBLE WHEN PMOVLAY = 0

NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS.

3FFF

DMA

DATA MEMORY

OVLAY

ALWAYS ACCESSIBLE AT ADDRESS

2000 – 0x3FFF

ACCESSIBLE WHEN DMOVLAY = 0

0x0000 – 0

1FFF

Figure 11. Direct Memory Access—PM and DM Memory Maps

Bootstrap Loading (Booting)

The ADSP-2185M has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B, and C configuration bits.

When the MODE pins specify BDMA booting, the ADSP-2185M initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory.

–15–

Page 18

ADSP-2185M

These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2185M. The only memory address bit provided by the processor is A0.

IDMA Port Booting

The ADSP-2185M can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2185M boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to.

Bus Request and Bus Grant

The ADSP-2185M can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2185M is not performing an external memory access, it responds to the active BR input in the following processor cycle by:

• Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2185M will not halt program execution until it encounters an instruction that requires an external memory access.

If the ADSP-2185M is performing an external memory access when the external device asserts the BR signal, it will not threestate the memory interfaces nor assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.

When the BR signal is released, the processor releases the BG signal, re-enables the output drivers, and continues program execution from the point at which it stopped.

The bus request feature operates at all times, including when the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2185M requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2185M deasserts BG and BGH and executes the external memory access.

Flag I/O Pins

The ADSP-2185M has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to

read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2185M’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2185M has five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are dedicated output flags. FI and FO are available as an alternate configuration of SPORT1.

Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset.

Instruction Set Description

The ADSP-2185M assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation.

• Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-2185M’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle.

• Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2185M has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If a passive method of maintaining mode information is being used (as discussed in Setting Memory Modes), it does not matter that the mode information is latched by an emulator reset. However, if the RESET pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration.

One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 12. This circuit forces the value located on the Mode A pin to logic high; regardless of whether it is latched via the RESET or ERESET pin.

–16–

REV. 0

Page 19

ADSP-2185M

ERESET

RESET

ADSP-2185M

1k⍀

MODE A/PFO

PROGRAMMABLE I/O

Figure 12. Mode A Pin/EZ-ICE Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.

The ICE-Port interface consists of the following ADSP-2185M pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT

These ADSP-2185M pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2185M and the connector must be kept as short as possible, no longer than 3 inches.

The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND.

The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2185M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in Figure 13. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector.

GND

EBG

EBR

KEY (NO PIN)

ELOUT

RESET

ⴛ

11 12

13 14

TOP VIEW

EINT

ELIN

ECLK

EMS

ERESET

Figure 13. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—Pin 7 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug.

Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below.

PM, DM, BM, IOM, AND CM

Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZ- ICE may approach published worst-case specification for some memory access timing requirements and switching characteristics.

Note: If your target does not meet the worst-case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits.

Restriction: All memory strobe signals on the ADSP-2185M (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 kΩ pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the RESET signal.

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR signal.

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ- ICE board’s DSP.

REV. 0

–17–

Page 20

ADSP-2185M–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade B Grade

Parameter Min Max Min Max Unit

DDINT

DDEXT

INPUT

AMB

NOTES

The ADSP-2185M is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input V ≈ V

(max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,

DDEXT

BR, DR0, DR1, PWD).

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typ Max Unit

Hi-Level Input Voltage

Hi-Level CLKIN Voltage @ V

Lo-Level Input Voltage

Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Three-State Leakage Current7@ V

OZH

Three-State Leakage Current7@ V

OZL

Supply Current (Idle)

Supply Current (Dynamic)

Supply Current (Power-Down)12@ V

Input Pin Capacitance

Output Pin Capacitance

NOTES

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

Input only pins: RESET, BR, DR0, DR1, PWD.

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

Although specified for TTL outputs, all ADSP-2185M outputs are CMOS-compatible and will drive to V

Guaranteed but not tested.

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

0 V on BR.

Idle refers to ADSP-2185M state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions.

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

See Chapter 9 of the ADSP-2100 Family User’s Manual for details.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

2.37 2.63 2.25 2.75 V

2.37 3.6 2.25 3.6 V VIL = –0.3 VIH = +3.6 VIL = –0.3 VIH = +3.6 V 0 +70 –40 +85 °C

DDEXT

K/B Grades

1, 2

1, 3

1, 4, 5

3, 6

6, 7, 12, 13

@ V

@ V @ V @ V @ V @ V @ V @ V

@ V @ V @ V @ V

= max 1.5 V

DDINT

= max 2.0 V

DDINT

= min 0.7 V

DDINT

= min, IOH = –0.5 mA 2.0 V

DDEXT

= 3.0 V, IOH = –0.5 mA 2.4 V

DDEXT

= min, IOH = –100 µA

DDEXT

= min, IOL = 2 mA 0.4 V

DDEXT

= max, VIN = 3.6 V 10 µA

DDINT

= max, VIN = 0 V 10 µA

DDINT

= max, VIN = 3.6 V

DDEXT

= max, VIN = 0 V

DDEXT

= 2.5, tCK = 15 ns 9 mA

DDINT

= 2.5, tCK = 13.3 ns 10 mA

DDINT

= 2.5, tCK = 15 ns11, T

DDINT

= 2.5, tCK = 13.3 ns11, T

DDINT

= 2.5, T

= 25°C in Lowest 100 µA

AMB

Power Mode @ VIN = 2.5 V, fIN = 1.0 MHz, T @ VIN = 2.5 V, fIN = 1.0 MHz, T

= 25°C35mA

AMB

= 25°C38mA

AMB

= 25°C8pF

AMB

= 25°C8pF

AMB

DDEXT

– 0.3 V

DDEXT

and GND, assuming no dc loads.

; because VOH (max)

10 µA 10 µA

–18–

REV. 0

Page 21

ADSP-2185M

ABSOLUTE MAXIMUM RATINGS

Value

Parameter Min Max

Internal Supply Voltage (V External Supply Voltage (V Input Voltage Output Voltage Swing

) –0.3 V +3.0 V

DDINT

) –0.3 V +4.0 V

DDEXT

–0.5 V +4.0 V –0.5 V V

DDEXT

Operating Temperature Range –40°C +85°C Storage Temperature Range –65°C +150°C

+ 0.5 V

NOTES

Stresses greater than those listed may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).

Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH).

Lead Temperature (5 sec) LQFP 280°C

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2185M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

GENERAL NOTES

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications and the corresponding ADSP-2185M timing parameters, for your convenience.

Memory Timing Device Parameter Specification Parameter Definition

Address Setup to t

ASW

Write Start WR Low

Address Setup to t

Write End WR Deasserted

Address Hold Time t

Data Setup Time t

Data Hold Time t OE to Data Valid t Address Access Time t

NOTE

xMS = PMS, DMS, BMS, CMS or IOMS.

WRA

RDD

WARNING!

ESD SENSITIVE DEVICE

A0–A13, xMS Setup before

A0–A13, xMS Hold before WR Low

Data Setup before WR High

Data Hold after WR High RD Low to Data Valid A0–A13, xMS to Data Valid

REV. 0

–19–

Page 22

ADSP-2185M

FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS

tCK is defined as 0.5 t

. The ADSP-2185M uses an input clock

CKI

with a frequency equal to half the instruction rate. For example, a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields a 13.3 ns processor cycle (equivalent to 75 MHz). t within the range of 0.5 t

period should be substituted for all

CKI

values

relevant timing parameters to obtain the specification value.

Example: t

ENVIRONMENTAL CONDITIONS

= 0.5 tCK – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns

CKH

Rating Description Symbol LQFP Mini-BGA

Thermal Resistance θ

48°C/W 63.3°C/W

(Case-to-Ambient)

Thermal Resistance θ

50°C/W 70.7°C/W

(Junction-to-Ambient)

Thermal Resistance θ

2°C/W 7.4°C/W

(Junction-to-Case)

NOTE

Where the Ambient Temperature Rating (T T

= T

AMB

CASE

PD = Power Dissipation in W

– (PD × θCA)

CASE

= Case Temperature in °C

AMB

) is:

POWER DISSIPATION

To determine total power dissipation in a specific application, the following equation should be applied for each output:

C × V

2 × f

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows:

Assumptions:

• External data memory is accessed every cycle with 50% of the address pins switching.

• External data memory writes occur every other cycle with 50% of the data pins switching.

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V

Total Power Dissipation = P

= internal power dissipation from Power vs. Frequency

INT

+ (C × V

INT

= 3.3 V and tCK = 30 ns.

DDEXT

× f )

DDEXT

graph (Figure 15).

(C × V

× f ) is calculated for each output:

DDEXT

# of ⴛ C ⴛ V

DDEXT

ⴛ fPD

Parameters Pins pF V MHz mW

Address 7 10 3.3 Data Output, WR 9 10 3.3 RD 1 10 3.3 CLKOUT, DMS 2 10 3.3

16.67 12.7

16.67 16.3

16.67 1.8

33.3 7.2

38.0

Total power dissipation for this example is P

+ 38.0 mW.

INT

Output Drive Currents

Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2185M. The curves represent the current drive capability of the output drivers as a function of output voltage.

–20

SOURCE CURRENT – mA

–40

–60

–80

= 3.6V @ –40ⴗC

DDEXT

= 3.3V @ +2 5ⴗC

DDEXT

= 2.5V @ +8 5ⴗC

DDEXT

0.5 1.0

1.5 2.0 2.5 3.0 3.5 4.0

SOURCE VOLTAGE – V

DDEXT

= 3.6V @ –40ⴗC

= 2.5V @ +8 5ⴗC

DDEXT

= 3.3V @ +2 5ⴗC

DDEXT

Figure 14. Typical Output Driver Characteristics

–20–

REV. 0

Page 23

ADSP-2185M

– MHz

1, 2, 4

DDINT

1, 2, 3

110mW

95mW

82mW

28mW

24mW

20mW

24mW

16.4mW

15.7mW

AND 25ⴗC, EXCEPT

115

110

105

100

) – mW

INT

82mW

POWER (P

70mW

61mW

60 55

50 80

24mW

) – mW

IDLE

20mW

POWER (P

16.5mW

20mW

n) – mW

IDLE

15mW

POWER (P

14.25mW

50 75

NOTES:

VALID FOR ALL TEMPERATURE GRADES.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

TYPICAL POWER DISSIPATION AT 2.5V V WHERE SPECIFIED.

IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

POWER, INTERNAL

VDD = 2.65V

VDD = 2.5V

VDD = 2.35V

55 60 65 70 75

1/t

POWER, IDLE

VDD = 2.65V

VDD = 2.5V

VDD = 2.35V

55 60 65 70 75 80

1/t

POWER, IDLE n MODES

55 60 70 8065

1/t

IDLE

IDLE (16)

IDLE (128)

Capacitive Loading

Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2185M.

T = 85ⴗC

= 0V TO 2.0V

RISE TIME (0.4V–2.4V) – ns

100 150 200 250

CL – pF

3000

Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature)

NOMINAL

VALID OUTPUT DELAY OR HOLD – ns

–2

–4

–6

50 100 150 250200

CL – pF

Figure 17. Typical Output Valid Delay or Hold vs. Load Capacitance, C

(at Maximum Ambient Operating

Temperature)

REV. 0

Figure 15. Power vs. Frequency

–21–

Page 24

ADSP-2185M

TEST CONDITIONS Output Disable Time

Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (t

) is the difference of t

DIS

MEASURED

and t

DECAY

, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage.

The decay time, t C

, and the current load, iL, on the output pin. It can be

, is dependent on the capacitive load,

DECAY

approximated by the following equation:

× 05. V

MEASURED

– t

DECAY

from which

DIS

DECAY

= t

is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.

INPUT

OUTPUT

1.5V

0.8V

2.0V

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (t

) is the interval from when a refer-

ENA

ence signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown Figure

19. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

REFERENCE

SIGNAL

(MEASURED)

OUTPUT

(MEASURED)

MEASURED

DIS

OUTPUT STOPS

DRIVING

ENA

OUTPUT STARTS DRIVING

(MEASURED)

(MEASURED) – 0.5V

(MEASURED) +0.5V

DECAY

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

2.0V

1.0V

Figure 19. Output Enable/Disable

Figure 18. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

OUTPUT

50pF

1.5V

Figure 20. Equivalent Loading for AC Measurements (Including All Fixtures)

–22–

REV. 0

Page 25

ADSP-2185M

Parameter Min Max Unit

Clock Signals and Reset

Timing Requirements:

CKI

CKIL

CKIH

Switching Characteristics:

CKL

CKH

CKOH

Control Signals Timing Requirements: t

RSP

NOTE

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time).

CLKIN Period 26.6 80 ns CLKIN Width Low 8 ns CLKIN Width High 8 ns

CLKOUT Width Low 0.5tCK – 2ns CLKOUT Width High 0.5tCK – 2ns CLKIN High to CLKOUT High 0 13 ns

RESET Width Low 5t

Mode Setup before RESET High 2 ns Mode Hold after RESET High 5 ns

CKI

CKIH

CLKIN

CKIL

CKOH

CKH

CLKOUT

PF(3:0)

RESET

CKL

RSP

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 21. Clock Signals

REV. 0

–23–

Page 26

ADSP-2185M

Parameter Min Max Unit

Interrupts and Flags

Timing Requirements:

t t

IFS

IFH

IRQx, FI, or PFx Setup before CLKOUT Low IRQx, FI, or PFx Hold after CLKOUT High

Switching Characteristics:

FOH

FOD

NOTES

If IRQx and FI inputs meet t

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.)

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

Flag Outputs = PFx, FL0, FL1, FL2, FO.

Flag Output Hold after CLKOUT Low Flag Output Delay from CLKOUT Low

and t

IFS

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

IFH

CLKOUT

FLAG

OUTPUTS

IRQx

PFx

Figure 22. Interrupts and Flags

1, 2, 3, 4

FOD

FOH

IFH

0.25tCK + 10 ns

0.25t

0.5tCK – 5ns

0.5tCK + 4 ns

IFS

–24–

REV. 0

Page 27

ADSP-2185M

Parameter Min Max Unit

Bus Request–Bus Grant

Timing Requirements:

BR Hold after CLKOUT High BR Setup before CLKOUT Low

Switching Characteristics:

SDB

SEC

SDBH

SEH

NOTES xMS = PMS, DMS, CMS, IOMS, BMS.

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

CLKOUT High to xMS, RD, WR Disable 0.25tCK + 8 ns

xMS, RD, WR Disable to BG Low 0 ns BG High to xMS, RD, WR Enable 0 ns xMS, RD, WR Enable to CLKOUT High 0.25tCK – 3ns xMS, RD, WR Disable to BGH Low BGH High to xMS, RD, WR Enable

CLKOUT

0.25tCK + 2 ns

0.25tCK + 10 ns

0ns 0ns

CLKOUT

PMS, DMS

BMS, RD

BGH

SDB

SDBH

Figure 23. Bus Request–Bus Grant

SEH

SEC

REV. 0

–25–

Page 28

ADSP-2185M

Parameter Min Max Unit

Memory Read

Timing Requirements:

RDD

RDH

Switching Characteristics:

CRD

ASR

RDA

RWR

NOTES w = wait states x tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

RD Low to Data Valid 0.5tCK – 5 + w ns

A0–A13, xMS to Data Valid 0.75tCK – 6 + w ns Data Hold from RD High 0 ns

RD Pulsewidth 0.5tCK – 3 + w ns CLKOUT High to RD Low 0.25tCK – 2 0.25tCK + 4 ns A0–A13, xMS Setup before RD Low 0.25tCK – 3ns A0–A13, xMS Hold after RD Deasserted 0.25tCK – 3ns RD High to RD or WR Low 0.5tCK – 3ns

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

D0–D23

CRD

ASR

RDD

RDA

RDH

RWR

Figure 24. Memory Read

–26–

REV. 0

Page 29

ADSP-2185M

Parameter Min Max Unit

Memory Write

Switching Characteristics:

WDE

ASW

DDR

CWR

WRA

WWR

NOTES w = wait states x t xMS = PMS, DMS, CMS, IOMS, BMS.

Data Setup before WR High 0.5tCK – 4 + w ns Data Hold after WR High 0.25tCK – 1ns

WR Pulsewidth 0.5tCK – 3 + w ns WR Low to Data Enabled 0 ns

A0–A13, xMS Setup before WR Low 0.25tCK – 3ns Data Disable before WR or RD Low 0.25tCK – 3ns CLKOUT High to WR Low 0.25tCK – 2 0.25 tCK + 4 ns A0–A13, xMS, Setup before WR Deasserted 0.75tCK – 5 + w ns A0–A13, xMS Hold after WR Deasserted 0.25tCK – 1ns WR High to RD or WR Low 0.5tCK – 3ns

CK.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

D0–D23

IOMS

CWR

ASW

WDE

Figure 25. Memory Write

WRA

WWR

DDR

REV. 0

–27–

Page 30

ADSP-2185M

Serial Ports

Parameter Min Max Unit

Serial Ports

Timing Requirements:

SCK

SCS

SCH

SCP

Switching Characteristics: t

SCDE

SCDV

SCDH

TDE

TDV

SCDD

RDV

SCLK Period 26.6 ns DR/TFS/RFS Setup before SCLK Low 4 ns DR/TFS/RFS Hold after SCLK Low 7 ns SCLKIN Width 12 ns

CLKOUT High to SCLKOUT 0.25t

0.25tCK + 6 ns SCLK High to DT Enable 0 ns SCLK High to DT Valid 12 ns TFS/RFS TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 12 ns

OUT

DT Hold after SCLK High 0 ns TFS (Alt) to DT Enable 0 ns TFS (Alt) to DT Valid 12 ns SCLK High to DT Disable 12 ns RFS (Multichannel, Frame Delay Zero) to DT Valid 12 ns

CLKOUT

SCLK

TFS

RFS

OUT

TFS

OUT

TFS

OUT

ALTERNATE

FRAME MODE

RFS

OUT

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

TFS

ALTERNATE

FRAME MODE

RFS

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

SCDE

TDE

SCDV

TDV

RDV

TDV

RDV

SCS

SCH

SCDD

SCDH

SCP

SCK

SCP

Figure 26. Serial Ports

–28–

REV. 0

Page 31

ADSP-2185M

Parameter Min Max Unit

IDMA Address Latch

Timing Requirements:

IALP

IASU

IAH

IKA

IALS

IALD

NOTES

Start of Address Latch = IS Low and IAL High.

End of Address Latch = IS High or IAL Low.

Start of Write or Read = IS Low and IWR Low or IRD Low.

Duration of Address Latch IAD15–0 Address Setup before Address Latch End IAD15–0 Address Hold after Address Latch End IACK Low before Start of Address Latch Start of Write or Read after Address Latch End Address Latch Start after Address Latch End

IACK

IAL

IAD15–0

IRD OR IWR

1, 2

2, 3

1, 2

IKA

IALP

IASU

IALD

IAH

10 ns 5ns 3ns 0ns 3ns 2ns

IALP

IASU

IAH

IALS

Figure 27. IDMA Address Latch

REV. 0

–29–

Page 32

ADSP-2185M

Parameter Min Max Unit

IDMA Write, Short Write Cycle

Timing Requirements:

IKW

IWP

IDSU

IDH

IACK Low before Start of Write Duration of Write

1, 2

IAD15–0 Data Setup before End of Write IAD15–0 Data Hold after End of Write

Switching Characteristic: t

IKHW

NOTES

Start of Write = IS Low and IWR Low.

End of Write = IS High or IWR High.

If Write Pulse ends before IACK Low, use specifications t

If Write Pulse ends after IACK Low, use specifications t

Start of Write to IACK High 10 ns

IACK

IKSU

IDSU

2, 3, 4

, t

IDH

, t

IKH

IKW

IKHW

IWP

0ns 10 ns 3ns 2ns

IWR

IAD15–0

IDSU

IDH

DATA

Figure 28. IDMA Write, Short Write Cycle

–30–

REV. 0

Page 33

ADSP-2185M

Parameter Min Max Unit

IDMA Write, Long Write Cycle

Timing Requirements:

IKW

IKSU

IKH

IACK Low before Start of Write IAD15–0 Data Setup before End of Write IAD15–0 Data Hold after End of Write

Switching Characteristics: t

IKLW

IKHW

NOTES

Start of Write = IS Low and IWR Low.

If Write Pulse ends before IACK Low, use specifications t

If Write Pulse ends after IACK Low, use specifications t

This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

Start of Write to IACK Low Start of Write to IACK High 10 ns

IACK

IKSU

IDSU

2, 3, 4

, t

IDH

, t

IKH

IKW

IKHW

IKLW

0ns

0.5tCK + 5 ns 0ns

1.5t

IWR

IAD15–0

IKSU

DATA

IKH

Figure 29. IDMA Write, Long Write Cycle

REV. 0

–31–

Page 34

ADSP-2185M

Parameter Min Max Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t t

IKR

IRK

IACK Low before Start of Read End of read after IACK Low

Switching Characteristics:

IKHR

IKDS

IKDH

IKDD

IRDE

IRDV

IRDH1

IRDH2

NOTES

Start of Read = IS Low and IRD Low.

End of Read = IS High or IRD High.

DM read or first half of PM read.

Second half of PM read.

IACK High after Start of Read IAD15–0 Data Setup before IACK Low 0.5tCK – 2ns IAD15–0 Data Hold after End of Read IAD15–0 Data Disabled after End of Read IAD15–0 Previous Data Enabled after Start of Read 0 ns IAD15–0 Previous Data Valid after Start of Read 11 ns IAD15–0 Previous Data Hold after Start of Read (DM/PM1)32tCK – 5ns IAD15–0 Previous Data Hold after Start of Read (PM2)

IACK

IKR

IKHR

0ns 2ns

10 ns

0ns

10 ns

tCK – 5ns

IRD

IAD15–0

IRK

IRDE

IRDV

IRDH1 or tIRDH2

DATA

IKDS

READ DATA

Figure 30. IDMA Read, Long Read Cycle

IKDD

IKDH

–32–

REV. 0

Page 35

ADSP-2185M

Parameter Min Max Unit

IDMA Read, Short Read Cycle

Timing Requirements:

IKR

IRP1

IRP2

IACK Low before Start of Read Duration of Read (DM/PM1) Duration of Read (PM2)

Switching Characteristics: t

IKHR

IKDH

IKDD

IRDE

IRDV

NOTES

Short Read Only must be disabled in the IDMA Overlay memory mapped register.

Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.

Start of Read = IS Low and IRD Low.

DM Read or first half of PM Read.

Second half of PM Read.

End of Read = IS High or IRD High.

IACK High after Start of Read IAD15–0 Data Hold after End of Read IAD15–0 Data Disabled after End of Read IAD15–0 Previous Data Enabled after Start of Read 0 ns IAD15–0 Previous Data Valid after Start of Read 10 ns

1, 2

IACK

0ns 10 2tCK – 5ns 10 tCK – 5ns

IKR

IKHR

0ns

10 ns

IRDV

IRP

DATA

IRD

IAD15–0

IRDE

Figure 31. IDMA Read, Short Read Cycle

IKDD

IKDH

REV. 0

–33–

Page 36

ADSP-2185M

Parameter Min Max Unit

IDMA Read, Short Read Cycle in Short Read Only Mode

Timing Requirements:

IACK Low before Start of Read

IKR

Duration of Read

IRP

Switching Characteristics:

IACK High after Start of Read

IKHR

IAD15–0 Previous Data Hold after End of Read

IKDH

IAD15–0 Previous Data Disabled after End of Read

IKDD

IAD15–0 Previous Data Enabled after Start of Read 0 ns

IRDE

IAD15–0 Previous Data Valid after Start of Read 10

IRDV

NOTES

Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default.

Start of Read = IS Low and IRD Low. Previous data remains until end of read.

End of Read = IS High or IRD High.

IACK

IKR

0ns 10 ns

0ns

10 ns

IKHR

IRDV

IRP

DATA

IKDD

IRD

IAD15–0

IRDE

Figure 32. IDMA Read, Short Read Only Cycle

IKDH

–34–

REV. 0

Page 37

100-LEAD LQFP PIN CONFIGURATION

ADSP-2185M

A4/I AD3

A5/ IAD4

GND

A6/I AD5

A7/ IAD6

A8/ IAD7

A9/ IAD8

A10/ IAD9

A11/ IAD10

A12/ IAD11

A13/ IAD12

GND

CLKIN

XTAL

DDEXT

CLKOUT

GND

DDINT

RD BMS DMS PMS

IOMS

CMS

A1/IAD0

A2/IAD1

A3/IAD2

999897

100

PIN 1

IDENTIFIER

GND

IRQE+PF4

IRQL0+PF5

IRQL1+PF6

BGH

PWDACK

DT0

IRQ2+PF7

PF0 [MODE A]

PF1 [MODE B]

9493929190

TFS0

PWD

GND

ADSP-2185M

(Not to Scale)

DR0

RFS0

SCLK0

DDEXT

FL0

PF3 [MODE D]

PF2 [MODE C]

8988878685

TOP VIEW

DDEXT

DT1/FO

TFS1/IRQ1

RFS1/IRQ0

FL1

DR1/FI

FL2

GND

D20

D21

D22

D23

8483828180

EMS

SCLK1

RESET

ERESET

GND

D19

D18

797877

ECLK

ELOUT

D17

ELIN

D16

EINT

D15

D14

D13

D12

GND

D11

D10

D9 V

DDEXT

GND

D8 D7/IWR

D6/IRD

D5/IAL D4/IS

GND V

DDINT

D3/ IACK

D2/I AD15

D1/ IAD14

D0/ IAD13

BG EBG BR

EBR

REV. 0

–35–

Page 38

ADSP-2185M

The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset.

LQFP Package Pinout

Pin Pin Pin Pin No. Pin Name No. Pin Name No. Pin Name No. Pin Name

1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16 2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17 3 GND 28 GND 53 EBG 78 D18 4A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19 5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND 6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20 7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21 8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22 9 A11/IAD10 34 DR0 59 V

DDINT

10 A12/IAD11 35 SCLK0 60 GND 85 FL2 11 A13/IAD12 36 V

DDEXT

61 D4/IS 86 FL1

12 GND 37 DT1/FO 62 D5/IAL 87 FL0 13 CLKIN 38 TFS1/IRQ1 63 D6/IRD 88 PF3 [MODE D] 14 XTAL 39 RFS1/IRQ0 64 D7/IWR 89 PF2 [MODE C] 15 V

DDEXT

40 DR1/FI 65 D8 90 V

16 CLKOUT 41 GND 66 GND 91 PWD 17 GND 42 SCLK1 67 V 18 V

DDINT

43 ERESET 68 D9 93 PF1 [MODE B]

DDEXT

19 WR 44 RESET 69 D10 94 PF0 [MODE A] 20 RD 45 EMS 70 D11 95 BGH 21 BMS 46 EE 71 GND 96 PWDACK 22 DMS 47 ECLK 72 D12 97 A0 23 PMS 48 ELOUT 73 D13 98 A1/IAD0 24 IOMS 49 ELIN 74 D14 99 A2/IAD1 25 CMS 50 EINT 75 D15 100 A3/IAD2

84 D23

DDEXT

92 GND

–36–

REV. 0

Page 39

144-Ball Mini-BGA Package Pinout (Bottom View)

ADSP-2185M

D4/IS

23456789101112

D23D20D18D17D16

D21D19D15NCD14

NCD13D12NCGND

GNDD10

DDEXT

GNDNCGND

D11D8NCD9

D5/IALNCNC

D3/IACK

GNDGNDV

D7/IWR

D6/IRD

DDEXT

PF2

[MODE C]

PF3

[MODE D]

PWD

PF1

[MODE B]

FL2

DT0TFS0D2/ IAD15

A9/IAD8

PF0

[MODE A]

DDINT

A5/IAD4A7/IAD6

BGH

A8/IAD7FL0

DDEXT

A2/I AD1A1/IAD0GNDA0NCGNDNCNCNCD22GNDGND

A4/ IAD3A3/IAD2GNDNCNCGNDV

PWDACKA6/IAD5

DDEXT

A13/IAD12NCA12 /IAD11A11/ IAD10FL1NCNC

XTALNCGNDA10 /IAD9NCNCNC

CLKINGNDGNDGNDV

DDINT

EINT

DDINT

EEECLK

D1/IAD14V

ERESETEBRBREBG

ELINELOUT

EMS

RESET

RFS1/IRQ0BG

SCLK1

TFS1/IRQ1

DR0GND

SCLK0D0/IAD13

RFS0

PMS

DDEXT

GND

GNDDT1/FODR1/FIGNDNC

DDEXT

BMSDMS

CMS

NCV

IRQL1 + PF6IOMS

DDINT

CLKOUTV

NCNCNC

IRQE + PF4

IRQL0 + PF5IRQ2 + PF7

REV. 0

–37–

Page 40

ADSP-2185M

The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

Mini-BGA Package Pinout

Ball # Pin Name Ball # Pin Name Ball # Pin Name Ball # Pin Name

A01 A2/IAD1 D01 NC G01 XTAL K01 NC A02 A1/IAD0 D02 WR G02 NC K02 NC A03 GND D03 NC G03 GND K03 NC A04 A0 D04 BGH G04 A10/IAD9 K04 BMS A05 NC D05 A9/IAD8 G05 NC K05 DMS A06 GND D06 PF1 [MODE B] G06 NC K06 RFS0 A07 NC D07 PF2 [MODE C] G07 NC K07 TFS1/IRQ1 A08 NC D08 NC G08 D6/IRD K08 SCLK1 A09 NC D09 D13 G09 D5/IAL K09 ERESET A10 D22 D10 D12 G10 NC K10 EBR A11 GND D11 NC G11 NC K11 BR A12 GND D12 GND G12 D4/IS K12 EBG

B01 A4/IAD3 E01 V B02 A3/IAD2 E02 V

DDEXT

H01 CLKIN L01 IRQE + PF4 H02 GND L02 NC

B03 GND E03 A8/IAD7 H03 GND L03 IRQL1 + PF6 B04 NC E04 FL0 H04 GND L04 IOMS B05 NC E05 PF0 [MODE A] H05 V

DDINT

L05 GND

B06 GND E06 FL2 H06 DT0 L06 PMS B07 V

DDEXT

E07 PF3 [MODE D] H07 TFS0 L07 DR0

B08 D23 E08 GND H08 D2/IAD15 L08 GND B09 D20 E09 GND H09 D3/IACK L09 RESET B10 D18 E10 V

DDEXT

H10 GND L10 ELIN

B11 D17 E11 GND H11 NC L11 ELOUT B12 D16 E12 D10 H12 GND L12 EINT

C01 PWDACK F01 A13/IAD12 J01 CLKOUT M01 IRQL0 + PF5 C02 A6/IAD5 F02 NC J02 V

DDINT

M02 IRQL2 + PF7

C03 RD F03 A12/IAD11 J03 NC M03 NC C04 A5/IAD4 F04 A11/IAD10 J04 V C05 A7/IAD6 F05 FL1 J05 V

DDEXT

M04 CMS M05 GND

C06 PWD F06 NC J06 SCLK0 M06 DT1/FO C07 V

DDEXT

F07 NC J07 D0/IAD13 M07 DR1/FI

C08 D21 F08 D7/IWR J08 RFS1/IRQ0 M08 GND C09 D19 F09 D11 J09 BG M09 NC C10 D15 F10 D8 J10 D1/IAD14 M10 EMS C11 NC F11 NC J11 V C12 D14 F12 D9 J12 V

DDINT

M11 EE M12 ECLK

–38–

REV. 0

Page 41

OUTLINE DIMENSIONS

Dimensions shown in millimeters.

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

16.20

16.00 TYP SQ

15.80

14.05

14.00 TYP SQ

13.95

0.75

0.60 TYP

0.50

SEATING

PLANE

1.60 MAX

100 76

12ⴗ

TYP

12.00 BSC

TOP VIEW

(PINS DOWN)

ADSP-2185M

0.08

MAX LEAD

COPLANARITY

0ⴗ – 7ⴗ

0.15

0.05

NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

6ⴗ ± 4ⴗ

0.50 BSC

LEAD PITCH

0.27

0.22 TYP

0.17

LEAD WIDTH

REV. 0

–39–

Page 42

ADSP-2185M

OUTLINE DIMENSIONS

Dimensions shown in millimeters.

144-Ball Mini-BGA

10.10

10.00 SQ

9.90

10.10

TOP VIEW

1.40 MAX

NOTES:

THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.150 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.

THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION.

10.00 SQ

9.90

DETAIL A

(CA-144)

8.80

BSC

0.40

0.25

12 11 10 9 8 7 6 5 4 3 2 1

0.80

BSC

DETAIL A

0.55

0.50

0.45

BALL DIAMETER

0.80 BSC

8.80 BSC

0.12 MAX

A B C D E F G H J K L M

1.00

0.85

SEATING PLANE

C02047–3.5–10/00 (rev. 0)

ORDERING GUIDE

Ambient Temperature Instruction Package Package

Part Number Range Rate Description* Option

ADSP-2185MKST-300 0°C to 70°C 75 100-Lead LQFP ST-100 ADSP-2185MBST-266 –40°C to +85°C 66 100-Lead LQFP ST-100 ADSP-2185MKCA-300 0°C to 70°C 75 144-Ball Mini-BGA CA-144 ADSP-2185MBCA-266 –40°C to +85°C 66 144-Ball Mini-BGA CA-144

*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm

thick) are now designated as LQFP.

PRINTED IN U.S.A.

–40–

REV. 0

ANALOG DEVICES ADSP-2185 MKSTZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

GENERAL DESCRIPTION

DEVELOPMENT SYSTEM

ARCHITECTURE OVERVIEW

PIN DESCRIPTIONS

LOW POWER OPERATION

SYSTEM INTERFACE

MEMORY ARCHITECTURE

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

PM, DM, BM, IOM, AND CM

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

TIMING SPECIFICATIONS

GENERAL NOTES

TIMING NOTES

MEMORY TIMING SPECIFICATIONS

FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS

ENVIRONMENTAL CONDITIONS

POWER DISSIPATION

100-LEAD LQFP PIN CONFIGURATION

LQFP Package Pinout

144-Ball Mini-BGA Package Pinout (Bottom View)

Mini-BGA Package Pinout

OUTLINE DIMENSIONS

ORDERING GUIDE