ANALOG DEVICES ADSP-21467, ADSP-21469 Service Manual

SUMMARY

INTERNAL MEMORY INTERFACE

BLOCK 0

RAM/ROM

B0D

64-BIT

INSTRUCTION

CACHE

5 STAGE

SEQUENCER

PEX PEY

PMD

64-BIT

IOD0 32-BIT

EPD BUS 64-BIT

CORE BUS

CROSS BAR

DAI ROUTING/PINS

S/PDIF
TX/RX

PCG
A

-

D

DPI ROUTING/PINS

SPI/B

UART

BLOCK 1

RAM/ROM

BLOCK 2

RAM

BLOCK 3

RAM

AMI

DDR2

CTL

EP

EXTERNAL PORT PIN MUX

TIMER

1

-

0

SPORT

7

-

0

ASRC

3-0

PWM

3

-

0

DAG1/2 TIMER

PDAP/

IDP
7

-

0

TWI

IOD0 BUS

DTCP/

MTM

PCG
C

-

D

CORE

FLAGS

JTAG

DMD

64-BIT

PMD 64-BIT

DMD

64-BIT

CORE

FLAGS

IOD1
32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI PERIPHERALS DAI PERIPHERALS PERIPHERALS

EXTERNAL
PORT

S

THERMAL

DIODE

FFT
FIR

IIR

LINK

PORT

1

-

0

MLB

SPEP BUS

INTERNAL MEMORY

SIMD CORE

PERIPHERAL
BUS 32-BIT

FLAGx/IRQx/
TMREXP

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture
5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM
Up to 450 MHz operating frequency
Qualified for automotive applications, see Automotive Prod-

ucts on Page 72

Code compatible with all other members of the SHARC family

SHARC Processor

ADSP-21467/ADSP-21469

Available with unique audiocentric peripherals such as the

digital applications interface, DTCP (digital transmission
content protection protocol), serial ports, precision clock
generators, S/PDIF transceiver, asynchronous sample rate
converters, input data port, and more.

For complete ordering information, see Ordering Guide on

Page 72

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADSP-21467/ADSP-21469

TABLE OF CONTENTS

Summary ............................................................... 1

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

System Design .................................................... 10

Development Tools ............................................. 11

Additional Information ........................................ 11

Related Signal Chains .......................................... 11

Pin Function Descriptions ....................................... 12

Specifications ........................................................ 18

Operating Conditions .......................................... 18

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 21

REVISION HISTORY

12/11—Rev. 0 to Rev A

Revised both footnotes in SHARC Family Features .......... 3

Added the ADSP-21467 model with internal ROM.

SHARC Family Features ............................................ 3

Internal Memory Space ............................................. 6

Automotive Products .............................................. 72

Added information on correct pin termination for unused pins
and revised pin descriptions and ball assignments.

Unused Pin Terminations ........................................ 12

Pin Descriptions .................................................... 13

CSP_BGA Ball Assignment—Standard Models ............. 68

Corrected document errata associated with the following speci­fications.

Pin Function Descriptions ....................................... 12

DDR2 SDRAM Read Cycle Timing ............................ 32

DDR2 SDRAM Write Cycle Timing ........................... 33

AMI Read ............................................................ 34

Added information for shared memory support.

Shared External Memory ........................................... 7

Pin Function Descriptions ....................................... 12

Shared Memory Bus Request .................................... 37

CSP_BGA Ball Assignment—Automotive Models ......... 65

CSP_BGA Ball Assignment—Standard Models ............. 68

Package Information ............................................ 21

ESD Sensitivity ................................................... 22

Timing Specifications ........................................... 22

Test Conditions .................................................. 60

Output Drive Currents ......................................... 60

Capacitive Loading .............................................. 61

Thermal Characteristics ........................................ 63

CSP_BGA Ball Assignment—Automotive Models .......... 65

CSP_BGA Ball Assignment—Standard Models .............. 68

Outline Dimensions ................................................ 71

Surface-Mount Design .......................................... 71

Automotive Products .............................................. 72

Ordering Guide ..................................................... 72

Rev. A | Page 2 of 72 | December 2011

GENERAL DESCRIPTION

ADSP-21467/ADSP-21469

The ADSP-21467/ADSP-21469 SHARC® processors are mem­bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x,
ADSP-2137x, and ADSP-2116x DSPs, as well as with first
generation ADSP-2106x SHARC processors in SISD (single­instruction, single-data) mode. These 32-bit/40-bit floating­point processors are optimized for high performance audio
applications with their large on-chip SRAM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative digital
applications/peripheral interfaces (DAI/DPI).

Table 1 shows performance benchmarks for the processor, and
Table 2 shows the product’s features.

Table 1. Processor Benchmarks

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s
FIR Filter (Per Tap)
IIR Filter (Per Biquad)
Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]

Divide (y/x) 6.67 ns
Inverse Square Root 10.0 ns

1

Assumes two files in multichannel SIMD mode

1

1

(at 450 MHz)

1.11 ns

4.43 ns

10.0 ns

17.78 ns

Table 2. SHARC Family Features

Feature ADSP-21467 ADSP-21469

Maximum Frequency 450 MHz
RAM 5 Mbits
ROM 4 Mbits N/A
Audio Decoders in ROM
DTCP Hardware Accelerator
Pulse-Width Modulation Yes
S/PDIF Yes
DDR2 Memory Interface Yes
DDR2 Memory Bus Width 16 Bits
Shared DDR2 External Memory Yes
Direct DMA from SPORTs to

External Memory Yes
FIR, IIR, FFT Accelerator Yes
MLB Interface Automotive Models Only
IDP Yes
Serial Ports 8
DAI (SRU)/DPI (SRU2) 20/14 pins
UART 1
Link Ports 2
AMI Interface with 8-Bit Support Yes

1

2

Ye s N o

No

Table 2. SHARC Family Features (Continued)

Feature ADSP-21467 ADSP-21469

SPI 2
TWI Yes
SRC Performance –128 dB
Package 324-Ball CSP_BGA

1

Factory programmed ROM includes: Dolby AC-3 5.1 Decode, Dolby Pro Logic IIx,

Dolby Intelligent Mixer (eMix), Dolby Volume postprocessor, Dolby Headphone
v2, DTS Neo:6 and Decode, DTS 5.1 Decode (96/24), Math Tables/Twiddle
Factors/256 and 512 FFT, and ASRC. Please visit www.analog.com for complete
product information and availability.

2

Contact your local Analog Devices sales office for more information regarding

availability of ADSP-21467/ADSP-21469 processors which support DTCP.

Figure 1 on Page 1 shows the two clock domains that make up

the processor. The core clock domain contains the following
features:

• Two processing elements (PEx, PEy), each of which com­prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• One periodic interval timer with pinout

• PM and DM buses capable of supporting 2 × 64-bit data
transfers between memory and the core at every core pro­cessor cycle

•On-chip SRAM (5 Mbits)

• On-chip mask-programmable ROM (4 Mbits)

• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break­points which allows flexible exception handling.

Figure 1 on Page 1 also shows the peripheral clock domain (also

known as the I/O processor) which contains the following
features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and DDR2 controller

• 4 units for PWM control

• 1 MTM unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2­wire interface, one UART, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible
signal routing unit (DPI SRU).

Rev. A | Page 3 of 72 | December 2011

ADSP-21467/ADSP-21469

As shown in Figure 1 on Page 1, the processor uses two compu­tational units to deliver a significant performance increase over
the previous SHARC processors on a range of DSP algorithms.
With its SIMD computational hardware, the processors can
perform 2.7 GFLOPS running at 450 MHz and 2.4 GFLOPS
running at 400 MHz.

FAMILY CORE ARCHITECTURE

The processors are code compatible at the assembly level with
the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21467/ADSP-21469 processors
share architectural features with the ADSP-2126x, ADSP-2136x,
ADSP-2137x, and ADSP-2116x SIMD SHARC processors, as
shown in Figure 2 and detailed in the following sections.

SIMD Computational Engine

The processor contains two computational processing
elements that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro­cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele­ments. These computation units support IEEE 32-bit single­precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Timer

A core timer that can generate periodic software interrupts.
The core timer can be configured to use FLAG3 as a timer
expired signal.

Data Register File

A general-purpose data register file is contained in each pro­cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the processor’s enhanced Harvard
architecture, allow unconstrained data flow between computa­tion units and internal memory. The registers in PEX are
referred to as R0-R15 and in PEY as S0-S15.

Context Switch

Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.

Universal Registers

These registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.

The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data buses.
These registers contain hardware to handle the data width
difference.

Single-Cycle Fetch of Instruction and Four Operands

The processors feature an enhanced Harvard Architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the its separate program and data memory
buses and on-chip instruction cache, the processor can simulta­neously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.

Instruction Cache

The processors contain an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

The two data address generators (DAGs) are used for indirect
addressing and implementing circular data buffers in hardware.
Circular buffers allow efficient programming of delay lines and
other data structures required in digital signal processing, and
are commonly used in digital filters and Fourier transforms.
The two DAGs of the processors contain sufficient registers to
allow the creation of up to 32 circular buffers (16 primary
register sets, 16 secondary). The DAGs automatically handle
address pointer wraparound, reduce overhead, increase perfor­mance, and simplify implementation. Circular buffers can start
and end at any memory location.

Rev. A | Page 4 of 72 | December 2011

ADSP-21467/ADSP-21469

S

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1

16 × 32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

RF

Rx/Fx

PEx

16 × 40-BIT

JTAG

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

TIMER

RF

Sx/SFx

PEy

16 × 40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

US TAT

4 × 32-BIT

PX

64-BIT

DAG2

16 × 32

ALU

MULTIPLIER

SHIFTER

DATA
SWAP

PM ADDRESS 24

PM DATA 48

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
processor can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­ing up to four 32-bit values from memory—all in a single
instruction.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the processors support new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
DDR2 memory. Source modules need to be built using the
VISA option in order to allow code generation tools to create
these more efficient opcodes.

Figure 2. SHARC Core Block Diagram

On-Chip Memory

The processors contain 5 Mbits of internal RAM. Each block
can be configured for different combinations of code and data
storage (see Table 4). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The memory architecture, in combination with its separate on­chip buses, allows two data transfers from the core and one
from the I/O processor in a single cycle.

The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 Mbits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conver­sion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each
memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.

Rev. A | Page 5 of 72 | December 2011

ADSP-21467/ADSP-21469

Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.

The memory map in Table 3 displays the internal memory
address space of the processors. The 48-bit space section
describes what this address range looks like to an instruction
that retrieves 48-bit memory. The 32-bit section describes what
this address range looks like to an instruction that retrieves 32-

ROM-Based Security

The ROM security feature provides hardware support for secur­ing user software code by preventing unauthorized reading
from the internal code when enabled. When using this feature,
the processors do not boot-load any external code, executing
exclusively from internal ROM. Additionally, the processors are
not freely accessible via the JTAG port. Instead, a unique 64-bit
key, which must be scanned in through the JTAG or Test Access
Port will be assigned to each customer.

bit memory.

Digital Transmission Content Protection

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 × 64-bits, CCLK speed) and
the IOD0/1 buses (2 × 32-bit, PCLK speed).

Nonsecured ROM

The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) is protected by this copy protection system.

For nonsecured ROM, booting modes are selected using the
BOOTCFG pins as shown in Table 8 on Page 10. In this mode,
emulation is always enabled, and the IVT is placed on the inter­nal RAM except for the case where BOOTCFGx = 011.

Table 3. Internal Memory Space

Long Word (64 Bits)

Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF

Reserved
0x0004 8000–0x0004 8FFF

Block 0 SRAM
0x0004 9000–0x0004 EFFF

Reserved
0x0004 F000–0x0004 FFFF

Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF

Reserved
0x0005 8000–0x0005 8FFF

Block 1 SRAM
0x0005 9000–0x0005 EFFF

Reserved
0x0005 F000–0x0005 FFFF

Block 2 SRAM
0x0006 0000–0x0006 3FFF

Reserved
0x0006 4000– 0x0006 FFFF

Block 3 SRAM
0x0007 0000–0x0007 3FFF

Reserved
0x0007 4000–0x0007 FFFF

1

Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

1

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or
Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9

Reserved
0x0008 AAAA–0x0008 BFFF

Block 0 SRAM
0x0008 C000–0x0009 3FFF

Reserved
0x0009 4000–0x0009 FFFF

Block 1 ROM (Reserved)
0x000A 0000–0x000A AAA9

Reserved
0x000A AAAA–0x000A BFFF

Block 1 SRAM
0x000A C000–0x000B 3FFF

Reserved
0x000B 4000–0x000B FFFF

Block 2 SRAM
0x000C 0000–0x000C 5554

Reserved
0x000C 5555–0x000D FFFF

Block 3 SRAM
0x000E 0000–0x000E 5554

Reserved
0x000E 5555–0x0000F FFFF

Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF

Reserved
0x0009 0000–0x0009 1FFF

Block 0 SRAM
0x0009 2000–0x0009 DFFF

Reserved
0x0009 E000–0x0009 FFFF

Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF

Reserved
0x000B 0000–0x000B 1FFF

Block 1 SRAM
0x000B 2000–0x000B DFFF

Reserved
0x000B E000–0x000B FFFF

Block 2 SRAM
0x000C 0000–0x000C 7FFF

Reserved
0x000C 8000–0x000D FFFF

Block 3 SRAM
0x000E 0000–0x000E 7FFF

Reserved
0x000E 8000–0x000F FFFF

Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF

Reserved
0x0012 0000–0x0012 3FFF

Block 0 SRAM
0x0012 4000–0x0013 BFFF

Reserved
0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF

Reserved
0x0016 0000–0x0016 3FFF

Block 1 SRAM
0x0016 4000–0x0017 BFFF

Reserved
0x0017 C000–0x0017 FFFF

Block 2 SRAM
0x0018 0000–0x0018 FFFF

Reserved
0x0019 0000–0x001B FFFF

Block 3 SRAM
0x001C 0000–0x001C FFFF

Reserved
0x001D 0000–0x001F FFFF

Rev. A | Page 6 of 72 | December 2011

ADSP-21467/ADSP-21469

FAMILY PERIPHERAL ARCHITECTURE

The processors contain a rich set of peripherals that support a
wide variety of applications including high quality audio, medi­cal imaging, communications, military, test equipment, 3D
graphics, speech recognition, motor control, imaging, and other
applications.

External Port

The external port interface supports access to the external mem­ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro­grammed as either asynchronous or synchronous memory. The
external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates
with SRAM, Flash, and other devices that meet the stan­dard asynchronous SRAM access protocol. The AMI
supports 2M words of external memory in bank 0 and 4M
words of external memory in bank 1, bank 2, and bank 3.

• A DDR2 DRAM controller. External memory devices up to
2 Gbits in size can be supported.

• Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the external
port.

External Memory

The external port on the processors provide a high perfor­mance, glueless interface to a wide variety of industry-standard
memory devices. The external port may be used to interface to
synchronous and/or asynchronous memory devices through the
use of its separate internal DDR2 memory controller. The 16-bit
DDR2 DRAM controller connects to industry-standard syn­chronous DRAM devices, while the second 8-bit asynchronous
memory controller is intended to interface to a variety of mem­ory devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of syn­chronous and asynchronous device types. Non-DDR2 DRAM
external memory address space is shown in Table 4.

Table 4. External Memory for Non-DDR2 DRAM Addresses

Bank Size in Words Address Range

Bank 0 2M 0x0020 0000 – 0x003F FFFF
Bank 1 4M 0x0400 0000 – 0x043F FFFF
Bank 2 4M 0x0800 0000 – 0x083F FFFF
Bank 3 4M 0x0C00 0000 – 0x0C3F FFFF

SIMD Access to External Memory

The DDR2 controller supports SIMD access on the 64-bit EPD
(external port data bus) which allows to access the complemen­tary registers on the PEy unit in the normal word space (NW).
This improves performance since there is no need to explicitly
load the complimentary registers as in SISD mode.

VISA and ISA Access to External Memory

The DDR2 controller also supports VISA code operation which
reduces the memory load since the VISA instructions are com­pressed. Moreover, bus fetching is reduced because, in the best
case, one 48-bit fetch contains three valid instructions. Code
execution from the traditional ISA operation is also supported.
Note that code execution is only supported from bank 0 regard­less of VISA/ISA. Table 5 shows the address ranges for
instruction fetch in each mode.

Table 5. External Bank 0 Instruction Fetch

Access Type Size in Words Address Range

ISA (NW) 4M 0x0020 0000 – 0x005F FFFF
VISA (SW) 10M 0x0060 0000 – 0x00FF FFFF

Shared External Memory

The processors support connection to common shared external
DDR2 memory with other ADSP-2146x processors to create
shared external bus processor systems. This support includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

• Bus lock

Multiple processors can share the external bus with no addi­tional arbitration logic. Arbitration logic is included on-chip to
allow the connection of up to two processors. Table 10 on

Page 13 provides descriptions of the pins used in multiprocessor

systems.

DDR2 Support

The processors support a 16-bit DDR2 interface operating at a
maximum frequency of half the core clock. Execution from
external memory is supported. External memory devices up to
2 Gbits in size can be supported.

DDR2 DRAM Controller

The DDR2 DRAM controller provides a 16-bit interface to up to
four separate banks of industry-standard DDR2 DRAM devices.
Fully compliant with the DDR2 DRAM standard, each bank can
have its own memory select line (DDR2_CS3 – DDR2_CS0),
and can be configured to contain between 32 Mbytes and
256 Mbytes of memory. DDR2 DRAM external memory
address space is shown in Table 6.

A set of programmable timing parameters is available to config­ure the DDR2 DRAM banks to support memory devices.

Table 6. External Memory for DDR2 DRAM Addresses

Bank Size in Words Address Range

Bank 0 62M 0x0020 0000 – 0x03FF FFFF
Bank 1 64M 0x0400 0000 – 0x07FF FFFF
Bank 2 64M 0x0800 0000 – 0x0BFF FFFF
Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF

Rev. A | Page 7 of 72 | December 2011

ADSP-21467/ADSP-21469

Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions, as well as
32-bit data, are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif­ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, Flash, and EPROM, as well
as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 2M word window and banks 1, 2, and 3
occupy a 4M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous
by the memory controller logic.

External Port Throughput

The throughput for the external port, based on a 400 MHz
clock, is 66M bytes/s for the AMI and 800M bytes/s for DDR2.

Link Ports

Two 8-bit wide link ports can connect to the link ports of other
DSPs or peripherals. Link ports are bidirectional ports having
eight data lines, an acknowledge line, and a clock line. Link
ports can operate at a maximum frequency of 166 MHz.

MediaLB

The automotive model has a MLB interface which allows the
processors to function as a media local bus device. It includes
support for both 3-pin and 5-pin media local bus protocols. It
supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz)
and up to 31 logical channels, with up to 124 bytes of data per
media local bus frame.

The MLB interface supports MOST25 and MOST50 data rates.
The isochronous mode of transfer is not supported.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM
waveforms. In addition, it can generate complementary signals
on two outputs in paired mode or independent signals in non­paired mode (applicable to a single group of four PWM
waveforms). The PWM generator is capable of operating in two
distinct modes while generating center-aligned PWM wave­forms: single update mode or double update mode.

The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DAI pins
(DAI_P20–1).

Programs make these connections using the signal routing unit
(SRU), shown in Figure 1 on Page 1.

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon­figurable signal paths.

The DAI includes the peripherals described in the following
sections.

Serial Ports

The processors feature eight synchronous serial ports that pro­vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA
channels of audio data when all eight SPORTs are enabled, or
four full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of f
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan­nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro­vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

2

•I

S mode

•Packed I

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan­nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the receiver/
transmitter can be formatted as left justified, I
fied with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources, such as the
SPORTs, external pins, and the precision clock generators
(PCGs), and are controlled by the SRU control registers.

2

S mode

2

S or right justi-

PCLK

/4.

Rev. A | Page 8 of 72 | December 2011

ADSP-21467/ADSP-21469

Asynchronous Sample Rate Converter

The asynchronous sample rate converter (ASRC) contains four
ASRC blocks, is the same core as that used in the AD1896 192
kHz stereo asynchronous sample rate converter, and provides
up to 128 dB SNR. The ASRC block is used to perform synchro­nous or asynchronous sample rate conversion across
independent stereo channels, without using internal processor
resources. The four SRC blocks can also be configured to oper­ate together to convert multichannel audio data without phase
mismatches. Finally, the ASRC can be used to clean up audio
data from jittery clock sources such as the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processors support 24- and 32-bit I
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right­justified formats.

Precision Clock Generators

The precision clock generators (PCG) consist of four units—A,
B, C, and D, each of which generates a pair of signals (clock and
frame sync) derived from a clock input signal. The units are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.

2

S, left-justified sample pair, or right-justified

2

S, 24-

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro­nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers. The DPI includes the
peripherals described in the following sections.

Serial Peripheral Interface

The processors contain two serial peripheral interface ports
(SPI). The SPI is an industry-standard synchronous serial link,
enabling the SPI-compatible port to communicate with other
SPI compatible devices. The SPI consists of two data pins, one
device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes. The SPI port can operate in a multimaster environment
by interfacing with up to four other SPI-compatible devices,
either acting as a master or slave device. The SPI-compatible
peripheral implementation also features programmable baud
rate, clock phase, and polarities. The SPI-compatible port uses
open-drain drivers to support a multimaster configuration and
to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli­fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa­bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:

• PIO (programmed I/O) – The processors send or receive
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans­fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory.

Ti me rs

The processors have a total of three timers: a core timer that can
generate periodic software interrupts and two general­purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirec­tional pin and four registers that implement its mode of
operation. A single control and status register enables or dis­ables both general-purpose timers independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional, 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I
The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

2

C bus protocol.

I/O Processor Features

Automotive versions of the I/O processor provide 67 channels
of DMA, while standard versions provide 36 channels of DMA,
as well as an extensive set of peripherals that are described in the
following sections.

Rev. A | Page 9 of 72 | December 2011

ADSP-21467/ADSP-21469

DMA Controller

The DMA controller allows data transfers without processor
intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the processor’s
internal memory and its serial ports, the SPI-compatible (serial
peripheral interface) ports, the IDP (input data port), the paral­lel data acquisition port (PDAP), or the UART.

Up to 67 channels of DMA are available as shown in Table 7.
Programs can be downloaded to the processor using DMA
transfers. Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.

Delay Line DMA

Delay line DMA allows processor reads and writes to external
delay line buffers (and hence to external memory) with limited
core interaction.

Scatter/Gather DMA

Scatter/gather DMA allows DMA reads/writes to/from non­contiguous memory blocks.

Table 7. DMA Channels

Peripheral DMA Channels

SPORTs 16
IDP/PDAP 8
SPI 2
UART 2
External Port 2
Link Port 2
Accelerators 2
Memory-to-Memory 2

1

MLB

1

Automotive models only.

31

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi­cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR accel­erator runs at the peripheral clock frequency.

FFT Accelerator

FFT accelerator implements radix-2 complex/real input, com­plex output FFT with no core intervention. The FFT accelerator
runs at the peripheral clock frequency.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.

SYSTEM DESIGN

The following sections provide an introduction to system design
options and power supply issues.

Program Booting

The internal memory boots at system power-up from an 8-bit
EPROM via the external port, link port, an SPI master, or an SPI
slave. Booting is determined by the boot configuration
(BOOTCFG2–0) pins in Table 8.

Table 8. Boot Mode Selection

BOOTCFG2–0 Booting Mode

000 SPI Slave Boot
001 SPI Master Boot
010 AMI Boot (for 8-bit Flash boot)
011 No boot occurs, processor executes from

internal ROM after reset
100 Link Port 0 Boot
101 Reserved

The running reset feature allows programs to perform a reset of
the processor core and peripherals, without resetting the PLL
and DDR2 DRAM controller or performing a boot. The
function of the RESETOUT
ing a running reset. For more information, see the ADSP-214xx
SHARC Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections
for the internal (V

) power supplies. The internal and analog supplies must

(V

DD_A

meet the V
the V

DD_EXT

DD_INT

specifications. The external supply must meet

DD_INT

specification. All external supply pins must be con-

nected to the same power supply.

Note that the analog power supply pin (V
cessor’s internal clock generator PLL. To produce a stable clock,
it is recommended that PCB designs use an external filter circuit
for the V
ble to the V

pin. Place the filter components as close as possi-

DD_A

/AGND pins. For an example circuit, see

DD_A

Figure 3. (A recommended ferrite chip is the muRata

BLM18AG102SN1D).

To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
traces to connect the bypass capacitors to the analog power

) and ground (AGND) pins. Note that the V

(V

DD_A

AGND pins specified in Figure 3 are inputs to the processor and
not the analog ground plane on the board—the AGND pin
should connect directly to digital ground (GND) at the chip.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to moni­tor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators pro­vides emulation at full processor speed, allowing inspection and

pin also acts as the input for initiat-

), external (V

DD_INT

), and analog

DD_EXT

) powers the pro-

DD_A

and GND. Use wide

DD_A

and

Rev. A | Page 10 of 72 | December 2011

HI Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS
CLOSE TO VDD_A AND AGND PINS

VDD_A

100nF 10nF 1nF

ADSP-2146x

V

DD_INT

AGND

Figure 3. Analog Power (V

) Filter Circuit

DD_A

modification of memory, registers, and processor stacks. The
processor's JTAG interface ensures that the emulator will not
affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate Emulator Hardware User's Guide.

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSS-

®

CORE

software and hardware development tools, including
Analog Devices emulators and VisualDSP++
environment. The same emulator hardware that supports other
SHARC processors also fully emulates the ADSP-21467/
ADSP-21469 processors.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite® board
being developed by Analog Devices. The board comes with on­chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in­circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter­mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.

®

development

ADSP-21467/ADSP-21469

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat­forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a stand­alone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, non­intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21467/
ADSP-21469 architecture and functionality. For detailed infor­mation on the core architecture and instruction set, refer to the
SHARC Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com­ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

TM

Lab

site (http://www.analog.com/signal chains) provides:

• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection
guides and application information

• Reference designs applying best practice design techniques

Rev. A | Page 11 of 72 | December 2011

ADSP-21467/ADSP-21469

PIN FUNCTION DESCRIPTIONS

Use the termination descriptions in Table 9 when not using the
DDR2 or MLB interfaces.

Warning: System designs must comply with these termination
rules to avoid causing issues of quality, reliability, and power
leakage at these pins.

Table 9. Unused Pin Terminations

Pin Name Unused Termination

DDR2_CKE, DDR2_CS
DDR2_DQSx
DDR2_WE, DDR2_CLKx, DDR2_CLKx
DDR2_ADDR, DDR2_BA, DDR2_DATA

V

DD_DDR2

V

REF

MLBCLK, MLBDAT, MLBSIG, MLBDO, MLBSO Available on automotive models only. In standard products using silicon revision 0.2

1

When the DDR2 controller is not used power down the receive path by setting the PWD bits of the DDR2PADCTLx register.

, DDR2_RAS, DDR2_CAS,

1

, DDR2_DM, DDR2_DQSx,

Leave floating.
Internally three-state by setting the DIS_DDRCTL bit of the DDR2CTL0 register

Connect to the V
Leave floating/unconnected

and above connect to ground (GND). In standard products using silicon revisions
previous to revision 0.2, leave these pins floating if unused.

DD_INT

supply

Rev. A | Page 12 of 72 | December 2011

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions

State Dur ing/ After

Name Type

AMI_ADDR

AMI_DATA

7–0

I/O/T (ipu) High-Z/

23–0

I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory

AMI_ACK I (ipu) Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to

AMI_MS

0–1

O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asser ted whenever the processor reads a word from

AMI_WR

FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2

O/T (ipu) High-Z External Port Write Enable. AMI_WR is asserted when the processor writes a word

I/O (ipu) FLAG[0] INPUT FLAG0/Interrupt Request0.
I/O (ipu) FLAG[1] INPUT FLAG1/Interrupt Request1.

/

I/O (ipu) FLAG[2] INPUT FLAG2/Interrupt Request2/Async Memory Select2.

AMI_MS2
FLAG[3]/TMREXP/

I/O (ipu) FLAG[3] INPUT FLAG3/Timer Expired/Async Memory Select3.

AMI_MS3
The following symbols appear in the Type column of Tab le 10 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are d esi gn ed t o h old th e in te rna l p ath fr om t he pi ns a t t he e xpected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

Reset Description

External Address. The processor outputs addresses for external memory and periph-

driven low (boot)

erals on these pins. The data pins can be multiplexed to support the PDAP (I) and PWM
(O). After reset, all AMI_ADDR
FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL
register, IDP channel 0 scans the AMI_ADDR
AMI pins can be left unconnected.

interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA
pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). Unused AMI
pins can be left unconnected.

add wait states to an external memory access. AMI_ACK is used by I/O devices,
memory controllers, or other peripherals to hold off completion of an external
memory access. Unused AMI pins can be left unconnected.

sponding banks of external memory on the AMI interface. The MS
memory address lines that change at the same time as the other address lines. When
no external memory access is occurring the MS
however when a conditional memory access instruction is executed, whether or not
the condition is true. Unused AMI pins can be left unconnected. The MS1 pin can be
used in EPORT/FLASH boot mode. For more information, see the ADSP-214xx SHARC
Processor Hardware Reference.

external memory.

to external memory.

pins are in external memory interface mode and

23–0

pins for parallel input data. Unused

23–0

lines are decoded

1-0

lines are inactive; they are active

1-0

DD_EXT

level; at

Rev. A | Page 13 of 72 | December 2011

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions (Continued)

State During/ After

Name Type

DDR2_ADDR

DDR2_BA

2-0

O/T High-Z/

15–0

O/T High-Z/

DDR2_CAS O/T High-Z/

DDR2_CKE O/T High-Z/

DDR2_CS

3-0

DDR2_DATA
DDR2_DM

1-0

DDR2_DQS
DDR2_DQS

DDR2_RAS

DDR2_WE

DDR2_CLK0,
DDR2_CLK0

O/T High-Z/

I/O/T High-Z DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.

15-0

O/T High-Z/

I/O/T

1-0

(Differential)

1-0

O/T High-Z/

O/T High-Z/

O/T
(Differential)

,
DDR2_CLK1,
DDR2_CLK1

DDR2_ODT O/T High-Z/

The following symbols appear in the Type column of Tab le 10 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are de si gned to hol d t he i nt ern al path fr om t he pin s a t th e e xpected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

Reset Description

DDR2 Address. DDR2 address pins.

driven low

DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,

driven low

or PRECHARGE command is being applied to. BA

define which mode registers,

2–0

including MR, EMR, EMR( 2), an d EMR(3) are lo aded d uring the LOAD MODE REG ISTER
command.

DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with other

driven high

DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE signal.

driven low

driven high

DDR2 Chip Select. All commands are masked when DDR2_CS
DDR2_CS

are decoded memory address lines. Each DDR2_CS

3-0

is driven high.

3-0

line selects the

3-0

corresponding external bank.

DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on both

driven high

edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and DM1
corresponds to DDR2_DATA15–8.

High-Z Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to

DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software
control via the DDR2CTL3 register, this pin can be single-ended or differential.

DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other

driven high

DDR2 command pins, defines the operation for the DDR2 to perform.
DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2

driven high
High-Z/

driven low

command pins, defines the operation for the DDR2 to perform.
DDR2 Memory Clocks. Two differential outputs available via software control

(DDR2CTL0 register). Free running, minimum frequency not guaranteed during reset.

DDR2 On Die Termination. ODT pin when driven high (along with other require-

driven low

ments) enables the DDR2 termination resistances. ODT is enabled/disabled regardless
of read or write commands.

level; at

DD_EXT

Rev. A | Page 14 of 72 | December 2011

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions (Continued)

State Dur ing/ After

Name Type

DAI _P

20–1

DPI _P

14–1

LDAT0

7–0

LDAT1

7–0

LCLK0
LCLK1

LACK0
LACK1

THD_P I Thermal Diode Anode. If unused, can be left floating.
THD_M O Thermal Diode Cathode. If unused, can be left floating.
MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-

MLBDAT I/O/T in 3 pin

MLBSIG I/O/T in 3 pin

MLBDO O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB

MLBSO O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

The following symbols appear in the Type column of Tab le 10 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are d esi gn ed t o h old th e in te rna l p ath fr om t he pi ns a t t he e xpected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI

I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

I/O/T (ipd) High-Z Link Port Data (Link Ports 0–1). When configured as a transmitter, the port drives

I/O/T (ipd) High-Z Link Port Clock (Link Ports 0–1). Allows asynchronous data transfers. When

I/O/T (ipd) High-Z Link Port Acknowledge (Link Port 0–1). Provides handshaking. When the link ports

mode. I/T in 5
pin mode.

mode.
I/T in 5 pin
mode.

Reset Description

SRU. The DAI SRU configuration registers define the combination of on-chip audio­centric peripheral inputs or outputs connected to the pin and to the pin’s output
enable. The configuration registers of these peripherals then determine the exact
behavior of the pin. Any input or output signal present in the DAI SRU may be routed
to any of these pins. The DAI SRU provides the connection from the serial ports, the
S/PDIF module, input data ports (2), and the precision clock generators (4), to the
DAI_P20–1 pins.

The DPI SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The configu­ration registers of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the DPI SRU may be routed to any of these pins.
The DPI SRU provides the connection from the timers (2), SPIs (2), UART (1), flags (12),
and general-purpose I/O (9) to the DPI_P14–1 pins.

both the data lines.

configured as a transmitter, the port drives LCLKx lines. An external 25 k pull-down
resistor is required for the proper operation of this pin.

are configured as a receiver, the port drives the LACKx line. An external 25 k pull­down resistor is required for the proper operation of this pin.

nized to the MOST network and provides the timing for the entire MLB interface.

49.152 MHz at FS = 48 kHz. If unused, connect to ground (see Tabl e 9 on Pag e 12 ).

High-Z Media Local Bus Data. T he M LB DAT li ne is dr ive n b y t he tr an sm it tin g M LB de vi ce an d

is received by all other MLB devices including the MLB controller. The MLBDAT line
carries the actual data. In 5-pin MLB mode, this pin is an input only. If unused, connect
to ground (see Ta b le 9 o n Page 12).

High-Z Media Local Bus Signal. This is a multiplexed signal which carries the channel/

address generated by the MLB controller, as well as the command and RxStatus bytes
from MLB devices. In 5-pin mode, this pin is an input only. If unused, connect to ground
(see Tab le 9 on Pa ge 12).

mode. This serves as the output data pin in 5-pin mode. If unused, connect to ground
(see Tab le 9 on Pa ge 12).

mode and serves as the output signal pin in 5-pin mode. If unused, connect to ground
(see Tab le 9 on Pa ge 12).

level; at

DD_EXT

Rev. A | Page 15 of 72 | December 2011

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions (Continued)

State During/ After

Name Type

BR

2-1

ID

1-0

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO O /T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine.
TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK signal must be

TRST

EMU

CLK_CFG

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

The following symbols appear in the Type column of Tab le 10 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are de si gned to hol d t he i nt ern al path fr om t he pin s a t th e e xpected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

1–0

I/P (ipu) BR1 = driven low by

I Chip ID. Determines which bus request (BR

I (ipu) Test Reset (JTAG). Resets the test state machine. The TRST signal must be asserted

O/D (ipu) High-Z Emulation Status. Must be connected to the ADSP-21467/ADSP-21469 Analog

I Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that

Reset Description

Bus request. Used by the processor to arbitrate for bus mastership. A processor only

the processor with
(ID1=0, ID0=1)

= driven high by

BR2
the processor with
(ID1=1, ID0=0)

= High-Z if ID

BR2–1
pins are at zero

drives its own BRx
all others. The processor’s own BRx
output.

corresponds to BR1 and ID = 010 corresponds to BR2. Use ID = 000 or 001 in single­processor systems. These lines are a system configuration selection that should be
hardwired or only changed at reset. ID = 101, 110, and 111 are reserved.

asserted (pulsed low) after power-up or held low for proper operation of the device.

(pulsed low) after power-up or held low for proper operation of the processor.

Devices DSP Tools product line of JTAG emulators target board connector only.

the operating frequency can be changed by programming the PLL multiplier and
divider in the PMCTL register at any time after the core comes out of reset. The allowed
values are:

00 = 6:1
01 = 32:1
10 = 16:1
11 = reserved

the processor to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processor to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.

crystal.

line (corresponding to the value of its ID1–0 inputs) and monitors

line must not be tied high or low because it is an

) is used by the processor. ID = 001

2-1

level; at

DD_EXT

Rev. A | Page 16 of 72 | December 2011

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions (Continued)

State Dur ing/ After

Name Type

RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

RESETOUT

/

I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

RUNRSTIN

BOOT_CFG

I Boot Configuration Select. These pins select the boot mode for the processor. The

2–0

The following symbols appear in the Type column of Tab le 10 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are d esi gn ed t o h old th e in te rna l p ath fr om t he pi ns a t t he e xpected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

Table 11. Pin List, Power and Ground

Reset Description

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET
(low) at power-up.

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-214xx SHARC Processor Hardware
Reference.

BOOT_CFG pins must be valid before RESET

input must be asserted

(hardware and software) is de-asserted.

level; at

DD_EXT

Name Type Description

V

DD_INT

V

DD_EXT

V

DD_A

V

DD_THD

V

DD_DDR2

V

REF

1

PDDR2 Interface Power

PInternal Power
PExternal Power
PAnalog Power for PLL
PThermal Diode Power

PDDR2 Input Voltage Reference
GND G Ground
AGND G Analog Ground

1

Applies to DDR2 signals.

Rev. A | Page 17 of 72 | December 2011

ADSP-21467/ADSP-21469

SPECIFICATIONS

OPERATING CONDITIONS

450 MHz 400 MHz

1

Description Min Nom Max Min Nom Max

V

DD_INT

V

DD_EXT

2

V

DD_A

V

DD_DDR2

V

DD_THD

V

REF

5

V

IH

5

V

Low Level Input Voltage @

IL

V

IH_CLKIN

6

V

IL_CLKIN

V

(DC) DC Low Level Input Voltage V

IL_DDR2

V

IH_DDR2

V

(AC) AC Low Level Input Voltage V

IL_DDR2

V

IH_DDR2

T

J

Internal (Core) Supply Voltage 1.05 1.1 1.15 1.0 1.05 1.1 V
External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 V
Analog Power Supply Voltage 1.05 1.1 1.15 1.0 1.05 1.1 V

3, 4

DDR2 Controller Supply Voltage 1.7 1.8 1.9 1.7 1.8 1.9 V
Thermal Diode Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 V
DDR2 Reference Voltage 0.84 0.9 0.96 0.84 0.9 0.96 V
High Level Input Voltage @

= Max

V

DD_EXT

2.0 2.0 V

0.8 0.8 V

V

= Min

6

(DC) DC High Level Input Voltage V

(AC) AC High Level Input Voltage V

DD_EXT

High Level Input Voltage @

= Max

V

DD_EXT

Low Level Input Voltage @
V

= Min

DD_EXT

Junction Temperature 324-Lead
CSP_BGA @ T

AMBIENT

0°C to

2.0 2.0 V

1.32 1.32 V

– 0.125 V

REF

+ 0.125 V

REF

– 0.25 V

REF

+ 0.25 V

REF

+ 0.125 V

REF

+ 0.25 V

REF

0 115 0 110 °C

– 0.125 V

REF

– 0.25 V

REF

+70°C

T

J

Junction Temperature 324-Lead
CSP_BGA @ T

AMBIENT

–40°C to

N/A N/A –40 125 °C

+85°C

1

Specifications subject to change without notice.

2

See Figure 3 on Page 11 for an example filter circuit.

3

Applies to DDR2 signals.

4

If unused, see Table 9 on Page 12.

5

Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, BOOTCFGx, CLKCFGx, (RUNRSTIN), RESET, TCK, TMS, TDI,

TRST.

6

Applies to input pin CLKIN.

UnitParameter

Rev. A | Page 18 of 72 | December 2011

ADSP-21467/ADSP-21469

ELECTRICAL CHARACTERISTICS

450 MHz 400 MHz

1

Description Test Conditions Min Max Min Max

2

V

OH

2

V

OL

V

OH_DDR2

V

OL_DDR2

4, 5

I

IH

4, 6

I

IL

5

I

ILPU

6

I

IHPD

7, 8

I

OZH

7, 9

I

Three-State Leakage

OZL

8

I

OZLPU

9

I

OZHPD

I

DD-INTYP

11

I

DD_A

12, 13

C

IN

1

Specifications subject to change without notice.

2

Applies to output and bidirectional pins: AMI_ADDR23-0, AMI_DATA7-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO.

3

See Output Drive Currents on Page 60 for typical drive current capabilities.

4

Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

5

Applies to input pins with internal pull-ups: TRST, TMS, TDI.

6

Applies to input pins with internal pull-downs: MLBCLK

7

Applies to three-statable pins: all DDR2 pins.

8

Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

9

Applies to three-statable pins with pull-downs: MLBDAT, MLBSIG, MLBDO, MLBSO, LDAT07-0, LDAT17-0, LCLK0, LCLK1, LACK0, LACK1.

10

See Engineer-to-Engineer Note EE-348 “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information.

11

Characterized but not tested.

12

Applies to all signal pins.

13

Guaranteed, but not tested.

High Level Output
Voltage

Low Level Output
Voltage

High Level Output
Voltage for DDR2

Low Level Output
Voltage for DDR2

High Level Input
Current

Low Level Input
Current

Low Level Input
Current Pull-up

High Level Input
Current Pull-down

Three-State Leakage
Current

Current

Three-State Leakage
Current Pull-up

Three-State Leakage
Current Pull-down

10

Supply Current
(Internal)

Supply Current
(Analog)

Input Capacitance T

@ V

@ V

@ V

@ V

@ V
V

IN

@ V

@ V

@ V
V

IN

@ V
VIN = V

@ V

= Min, IOH = –1.0 mA32.4 2.4 V

DD_EXT

Max

3

0.4 0.4 V

10 10 μA

200 200 μA

10 10 μA

10 10 μA

= Min, IOL = 1.0 mA

DD_EXT

= Min, IOH = –13.4 mA 1.4 1.4 V

DD_DDR

= Min, IOL = 13.4 mA 0.29 0.29 V

DD_DDR

= Max,

DD_EXT

= V

DD_EXT

DD_EXT

DD_EXT

= V

DD_EXT/VDD_DDR

DD_EXT/VDD_DDR

Max

DD_EXT

= Max, VIN = 0 V 10 10 μA

= Max, VIN = 0 V 200 200 μA

= Max,

Max

DD_EXT

= Max,

DD_EXT/VDD_DDR

= Max,

VIN = 0 V

@ V

@ V
VIN = V

f

CCLK

V

DD_A

CASE

= Max, VIN = 0 V 200 200 μA

DD_EXT

= Max,

DD_EXT

DD_EXT

Max

> 0 MHz Tab le 13 +

200 200 μA

Ta ble 1 3 +

Tab le 14 × ASF

Ta ble 1 4 × ASF

= Max 10 10 mA

= 25°C 5 5 pF

UnitParameter

mA

Rev. A | Page 19 of 72 | December 2011

ADSP-21467/ADSP-21469

Total Power Dissipation

Total power dissipation has two components:

1. Internal power consumption

2. External power consumption

Internal power consumption also comprises two components:

1. Static, due to leakage current. Table 13 shows the static cur­rent consumption (I
temperature (T

2. Dynamic (I

DD-DYNAMC

DD-STATIC

) and core voltage (V

J

acteristics and activity level of the processor. The activity
level is reflected by the Activity Scaling Factor (ASF), which
represents application code running on the processor core
and having various levels of peripheral and external port
activity (Table 12). Dynamic current consumption is calcu­lated by scaling the specific application by the ASF and
using baseline dynamic current consumption as a
reference.

) as a function of junction

).

DD_INT

), due to transistor switching char-

The ASF is combined with the CCLK frequency and V

DD_INT

dependent data in Table 14 to calculate this part. External power
consumption is due to the switching activity of the external
pins.

Table 12. Activity Scaling Factors (ASF)

1

Activity Scaling Factor (ASF)

Idle 0.38
Low 0.58
High 1.23
Peak 1.35
Peak-typical (50:50)

2

0.87
Peak-typical (60:40) 0.94
Peak-typical (70:30) 1.00

1

See Estimating Power for SHARC Processors (EE-348) for more information on

the explanation of the power vectors specific to the ASF table.

2

Ratio of continuous instruction loop (core) to DDR2 control code; reads:writes.

Table 13. I

1

TJ (°C)

DD-STATIC

(mA)

(V)

1

V

DD_INT

0.95 V 1.0 V 1.05 V 1.10 V 1.15 V

–45 72 91 110 140 167
–35 79 99 119 149 181
–25 89 109 131 163 198
–15 101 122 145 182 220
–5 115 140 166 206 249
5 134 162 192 237 284
15 158 189 223 273 326
25 186 222 260 318 377
35 218 259 302 367 434
45 258 305 354 428 503
55 305 359 413 497 582
65 360 421 484 578 675
75 424 496 566 674 781
85 502 580 660 783 904
95 586 683 768 912 1048
105 692 794 896 1054 1212
115 806 921 1036 1220 1394
125 939 1070 1198 1404 1601

1

Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18.

Rev. A | Page 20 of 72 | December 2011

ADSP-21467/ADSP-21469

vvvvvv.x n.n

tppZ-cc

S

ADSP-2146x

a

yyww country_of_origin

Table 14. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)

f

CCLK

(MHz)

2

0.95 V 1.0 V 1.05 V 1.10 V 1.15 V

Voltage (V

1

DD_INT

2

)

1007882869198
150 115 121 130 136 142
200 150 159 169 177 188
250 186 197 208 219 231

300 222 236 249 261 276
350 259 275 288 304 319
400 293 309 328 344 361
450 N/A N/A 366 385 406

1

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 19.

2

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 15 may cause perma­nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi­tions greater than those indicated in the operational sections of

PACKAGE INFORMATION

The information presented in Figure 4 and Table 16 provides
details about the package branding for the processor. For a com­plete listing of product availability, see Ordering Guide on

Page 72.

this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Table 15. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (V
External (I/O) Supply Voltage (V
Thermal Diode Supply Voltage

(V

DD_THD

)

DDR2 Controller Supply Voltage
(V

DD_DDR2)

) –0.3 V to +1.32 V

DD_INT

) –0.3 V to +1.15 V

DD_A

) –0.3 V to +3.6 V

DD_EXT

–0.3 V to +3.6 V

–0.3 V to +1.9 V

DDR2 Input Voltage –0.3 V to +1.9 V
Input Voltage –0.3 V to +3.6 V
Output Voltage Swing –0.3 V to V

DD_EXT

Storage Temperature Range –65C to +150C
Junction Temperature While Biased 125C

+0.5 V

Figure 4. Typical Package Brand

Table 16. Package Brand Information

1

Brand Key Field Description

t Temperature Range
pp Package Type
Z RoHS Compliant Option
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code

1

Non-automotive only. For branding information specific to automotive

products, contact Analog Devices, Inc.

Rev. A | Page 21 of 72 | December 2011

ADSP-21467/ADSP-21469

ESD

(electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid

performance degradation or loss of functionality.

ESD SENSITIVITY

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See

Figure 46 on Page 60 under Test Conditions for voltage refer-

ence levels.

In the following sections, Switching Characteristics specify how
the processor changes its signals. Circuitry external to the pro­cessor must be designed for compatibility with these signal
characteristics. Switching characteristics describe what the pro­cessor will do in a given circumstance. Use switching
characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.

In the following sections, Timing Requirements apply to signals
that are controlled by circuitry external to the processor, such as
the data input for a read operation. Timing requirements guar­antee that the processor operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces­sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.

Voltage Controlled Oscillator (VCO)

In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f

specified in Table 19.

VCO

• The product of CLKIN and PLLM must never exceed 1/2 of
f

(max) in Table 19 if the input divider is not enabled

VCO

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed
f

(max) in Table 19 if the input divider is enabled

VCO

(INDIV = 1).

The VCO frequency is calculated as follows:

f

= 2 × PLLM × f

VCO

f

= (2 × PLLM × f

CCLK

INPUT

INPUT

) ÷ (PLLD)

where:

f

= VCO output

VCO

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.

PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value
programmed on the PMCTL register. During reset this value
is 2.

f

= input frequency to the PLL

INPUT

f

= CLKIN when the input divider is disabled, or

INPUT

f

= CLKIN  2 when the input divider is enabled

INPUT

Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and

Table 17. All of the timing specifications for the peripherals are

defined in relation to t

. See the peripheral specific section

PCLK

for each peripheral’s timing information.

Table 17. Clock Periods

Timing
Requirements Description

t

CK

t

CCLK

t

PCLK

CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t

CCLK

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.

Rev. A | Page 22 of 72 | December 2011