Datasheet ADSP-2137x Datasheet (ANALOG DEVICES)

ADSP-2137x SHARC® Processor

Hardware Reference

Includes ADSP-21367, ADSP-21368,

ADSP-21369, ADSP-21371, ADSP-21375

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Revision 2.1, May 2010

Part Number

82-000100-01

a

Copyright Information

© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

Contents

PREFACE

Purpose of This Manual ............................................................... xliii

Intended Audience ....................................................................... xliii

Manual Contents .......................................................................... xliv

What’s New in This Manual ......................................................... xlvii

Technical or Customer Support .................................................. xlviii

Registration for MyAnalog.com ............................................... xlix

EngineerZone .......................................................................... xlix

Social Networking Web Sites ....................................................... l

Supported Processors ......................................................................... l

Product Information ......................................................................... l

Analog Devices Web Site ............................................................. l

VisualDSP++ Online Documentation ......................................... li

Technical Library CD ................................................................ lii

Notation Conventions ..................................................................... lii

INTRODUCTION

Design Advantages ........................................................................ 1-1

SHARC Family Product Offerings ........................................... 1-2

ADSP-2137x SHARC Processor Hardware Reference iii

Contents

Processor Architectural Overview .................................................. 1-3

Processor Core ........................................................................ 1-3

I/O Peripherals ....................................................................... 1-3

I/O Processor ..................................................................... 1-3

Digital Audio Interface (DAI) ............................................. 1-4

Interrupt Controller ........................................................... 1-4

Signal Routing Unit ............................................................ 1-4

Digital Peripheral Interface (DPI) ....................................... 1-5

Interrupt Controller ........................................................... 1-5

Signal Routing Unit 2 ......................................................... 1-5

Development Tools ....................................................................... 1-5

Differences from Previous Processors ............................................. 1-6

I/O Architecture Enhancements .............................................. 1-6

I/O PROCESSOR

Features ........................................................................................ 2-2

Register Overview ......................................................................... 2-2

DMA Channel Registers ............................................................... 2-3

DMA Channel Allocation ....................................................... 2-3

Standard DMA Parameter Registers ......................................... 2-3

Extended DMA Parameter Registers ........................................ 2-7

Data Buffers ........................................................................... 2-8

Chain Pointer Registers ........................................................... 2-9

TCB Storage ............................................................................... 2-11

Serial Port TCB .................................................................... 2-11

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SPI TCB ............................................................................... 2-11

UART TCB .......................................................................... 2-12

External Port TCB ................................................................. 2-12

Clocking ..................................................................................... 2-15

Functional Description ............................................................... 2-15

Automated Data Transfer ....................................................... 2-15

DMA Transfer Types ............................................................. 2-16

DMA Direction ..................................................................... 2-17

Internal to External Memory ............................................. 2-17

Peripheral to Internal Memory .......................................... 2-18

Internal Memory to Internal Memory ................................ 2-18

DMA Controller Addressing .................................................. 2-18

Internal Index Register Addressing ..................................... 2-20

External Index Register Addressing .................................... 2-21

DMA Channel Status ............................................................ 2-21

DMA Start and Stop Conditions ............................................ 2-22

Operating Modes ........................................................................ 2-23

DMA Chaining ..................................................................... 2-24

TCB Memory Storage ....................................................... 2-25

Chain Assignment ............................................................. 2-26

Starting Chain Loading ..................................................... 2-27

TCB Chain Loading Priority ............................................. 2-28

Chain Insert Mode (SPORTs Only) ................................... 2-28

Fixed DMA Channel Arbitration ........................................... 2-29

ADSP-2137x SHARC Processor Hardware Reference v

Contents

Peripheral DMA Bus ......................................................... 2-33

External Port DMA Bus .................................................... 2-34

Rotating DMA Channel Arbitration ...................................... 2-34

Rotating Priority by Group ............................................... 2-34

Interrupts ................................................................................... 2-35

Sources ................................................................................. 2-36

Unchained DMA Interrupts .............................................. 2-36

Chained DMA Interrupts ................................................. 2-36

Transfer Completion Types .................................................... 2-37

Internal Transfer Completion ............................................ 2-37

Access Completion ........................................................... 2-37

Core Single Word Transfer Interrupts .................................... 2-38

Interrupt Versus Channel Priorities ........................................ 2-38

Debug Features ........................................................................... 2-39

Emulation Considerations ..................................................... 2-40

Effect Latency ............................................................................ 2-40

Write Effect Latency ............................................................. 2-40

IOP Effect Latency ............................................................... 2-40

IOP Throughput .................................................................. 2-40

Programming Model ................................................................... 2-41

General Procedure for Configuring DMA .............................. 2-41

EXTERNAL PORT

Features ........................................................................................ 3-2

Pin Descriptions ........................................................................... 3-3

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Contents

Pin Multiplexing ..................................................................... 3-4

Register Overview ......................................................................... 3-4

Clocking ....................................................................................... 3-5

Functional Description ................................................................. 3-6

External Port Arbitration ......................................................... 3-7

External Port Bus Arbitration Conflicts ............................... 3-8

Channel Freezing ..................................................................... 3-8

Asynchronous Memory Interface ................................................... 3-8

AMI Features .......................................................................... 3-9

Functional Description ............................................................ 3-9

Asynchronous Reads ......................................................... 3-10

Asynchronous Writes ......................................................... 3-11

Parameter Timing ............................................................. 3-12

Idle Cycles ........................................................................ 3-12

Address Mapping .............................................................. 3-12

Operating Modes ................................................................... 3-13

Data Packing .................................................................... 3-13

External Access Extension .................................................. 3-14

Predictive Reads ................................................................ 3-15

SDRAM Controller ..................................................................... 3-16

Features ................................................................................. 3-16

Functional Description .......................................................... 3-17

SDRAM Commands ......................................................... 3-18

Load Mode Register ...................................................... 3-19

ADSP-2137x SHARC Processor Hardware Reference vii

Contents

Address Mapping .............................................................. 3-26

Single Bank Activation .................................................. 3-20

Multibank Activation (ADSP-2137x Processors) ............ 3-20

Single Precharge (ADSP-2137x Processors) .................... 3-21

Precharge All ................................................................ 3-21

Read/Write ................................................................... 3-21

Read/Write Full Page Burst (ADSP-2137x Processors) ... 3-24

Burst Stop (ADSP-2137x Processors) ............................ 3-24

Auto-Refresh ................................................................ 3-25

No Operation/Command Inhibit .................................. 3-25

Command Truth Table ................................................. 3-25

External Addressing Modes ........................................... 3-27

Refresh Rate Control ........................................................ 3-32

Internal SDRAM Bank Access ........................................... 3-34

Single Bank Access ........................................................ 3-34

Multibank Access (ADSP-2137x Processors) .................. 3-34

Multi Bank Operation with Data Packing

(ADSP-2137x) ........................................................... 3-36

Timing Parameters ............................................................ 3-36

Fixed Timing Parameters ............................................... 3-36

Data Mask (DQM) ........................................................... 3-37

Resetting the Controller .................................................... 3-37

Operating Modes .................................................................. 3-37

Parallel Connection of SDRAMs ....................................... 3-38

Buffering Controller for Multiple SDRAMs .................. 3-38

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Contents

SDRAM Read Optimization ............................................. 3-38

Core Accesses ................................................................ 3-41

DMA Access ................................................................. 3-42

Notes on Read Optimization ......................................... 3-43

Self-Refresh Mode ............................................................. 3-43

Forcing SDRAM Commands ............................................. 3-44

Force Precharge All ....................................................... 3-44

Force Load Mode Register (ADSP-2137x Only) ............. 3-45

Force Auto-Refresh ........................................................ 3-45

Shared Memory Interface (ADSP-21368) .................................... 3-45

Pin Descriptions .................................................................... 3-46

Functional Description .......................................................... 3-46

Bus Arbitration Protocol ................................................... 3-48

Bus Synchronization After Reset ........................................ 3-52

Shared AMI Protocol ........................................................ 3-54

Shared SDRAM Protocol .................................................. 3-54

Operating Modes ................................................................... 3-55

Rotating Priority Bus Arbitration (RPBA) .......................... 3-55

Bus Mastership Time-Out ................................................. 3-56

Data Transfer .............................................................................. 3-57

Data Buffers .......................................................................... 3-58

Receive Buffer ................................................................... 3-58

Transmit Buffer ................................................................. 3-58

Core Access ........................................................................... 3-59

ADSP-2137x SHARC Processor Hardware Reference ix

Contents

External Port Dual Data Fetch .......................................... 3-59

Conditional Instructions ................................................... 3-59

External Instruction Fetch (ADSP-2137x) ......................... 3-59

Fetching Instructions From External Memory ................ 3-60

External Port DMA Transfers ................................................ 3-69

External Port DMA Parameter Registers ............................ 3-70

Operating Modes .............................................................. 3-72

Internal DMA Addressing ............................................. 3-72

Standard DMA ............................................................. 3-72

Circular Buffered DMA ................................................ 3-73

Chained DMA Mode ........................................................ 3-74

Changing DMA Direction on the Fly (ADSP-2137x) .... 3-74

Scatter/Gather DMA (ADSP-2137x) ................................. 3-76

External Address Calculation ......................................... 3-76

Delay Line DMA .............................................................. 3-81

External Address Calculation for Reads ......................... 3-83

Interrupts ................................................................................... 3-85

Access Completion (ADSP-2137x) ........................................ 3-85

Internal Transfer Completion ................................................ 3-86

Interrupt Dependency on DMA Mode .................................. 3-86

External Port Throughput ........................................................... 3-87

AMI Data Throughput ......................................................... 3-87

SDRAM Throughput ............................................................ 3-87

Throughput Conditional Instructions ............................... 3-88

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Contents

External Instruction Fetch Throughput (ADSP-2137x) .......... 3-88

Effect Latency ............................................................................. 3-90

Shared Memory ..................................................................... 3-90

Write Effect Latency .............................................................. 3-90

Programming Models .................................................................. 3-90

External Port ......................................................................... 3-91

AMI Initialization ............................................................. 3-91

DMA .................................................................................... 3-91

Standard DMA (ADSP-21367/8/9) ................................... 3-92

Chained DMA (ADSP-21367/8/9) .................................... 3-93

Standard DMA (ADSP-21371/5) ...................................... 3-94

Chained DMA (ADSP-21371/5) ....................................... 3-95

Delay Line DMA .............................................................. 3-96

Disabling and Re-enabling DMA ....................................... 3-96

Additional Information ..................................................... 3-97

SDRAM Controller ............................................................... 3-98

Power-Up Sequence .......................................................... 3-98

Output Clock Generator Programming Model ................... 3-99

Self-Refresh Mode ........................................................... 3-100

Changing the VCO Clock During Runtime ..................... 3-100

Bus Synchronization with Shared SDRAM ...................... 3-101

Bus Synchronization Notes .............................................. 3-103

Conditional Bus Master Instruction ................................. 3-104

External Instruction Fetch ................................................... 3-104

ADSP-2137x SHARC Processor Hardware Reference xi

Contents

AMI Configuration ........................................................ 3-104

SDRAM Configuration .................................................. 3-104

External Memory Access Restrictions ................................... 3-105

ADSP-21367/8/9 Only ................................................... 3-105

ADSP-2137x Only ......................................................... 3-106

MEMORY-TO-MEMORY PORT DMA

Features ........................................................................................ 4-2

Register Overview ......................................................................... 4-2

Clocking ...................................................................................... 4-2

Functional Description ................................................................. 4-3

Data Transfer ............................................................................... 4-3

Data Buffer ............................................................................. 4-3

DMA Transfer ........................................................................ 4-4

Interrupts ..................................................................................... 4-4

MTM Throughput ....................................................................... 4-5

Effect Latency .............................................................................. 4-5

Write Effect Latency ............................................................... 4-5

MTM Effect Latency .............................................................. 4-5

Programming Model ..................................................................... 4-5

PULSE WIDTH MODULATION

Features ........................................................................................ 5-2

Pin Descriptions ........................................................................... 5-4

Multiplexing Scheme .............................................................. 5-4

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Register Overview ......................................................................... 5-5

Clocking ....................................................................................... 5-6

Functional Description ................................................................. 5-6

Two-Phase PWM Generator .................................................... 5-6

Switching Frequencies ......................................................... 5-6

Duty Cycles ........................................................................ 5-7

Dead Time ....................................................................... 5-12

Output Control Unit ............................................................. 5-12

Output Enable .................................................................. 5-13

Output Polarity ................................................................. 5-13

Complementary Outputs .................................................. 5-13

Crossover .......................................................................... 5-13

Emergency Dead Time for Over Modulation .......................... 5-14

Output Control Feature Precedence ................................... 5-16

Operating Modes ........................................................................ 5-17

Waveform Modes .................................................................. 5-17

Edge-Aligned Mode .......................................................... 5-17

Center-Aligned Mode ........................................................ 5-18

PWM Timer Edge Aligned Update ........................................ 5-20

Single Update Mode .......................................................... 5-21

Double Update Mode ....................................................... 5-22

Effective Accuracy ................................................................. 5-23

Synchronization of PWM Groups .......................................... 5-24

Interrupts ................................................................................... 5-24

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Contents

Debug Features ........................................................................... 5-26

Status Debug Register ........................................................... 5-26

Emulation Considerations ..................................................... 5-26

Effect Latency ............................................................................ 5-26

Write Effect Latency ............................................................. 5-27

PWM Effect Latency ............................................................. 5-27

DIGITAL APPLICATION/DIGITAL PERIPHERAL

INTERFACES

Features ........................................................................................ 6-2

Register Overview ......................................................................... 6-3

Clocking ...................................................................................... 6-4

Functional Description ................................................................. 6-4

DAI/DPI Signal Naming Conventions ..................................... 6-7

I/O Pin Buffers ....................................................................... 6-7

Pin Buffers as Signal Output ............................................... 6-8

Pin Buffers as Signal Input ................................................ 6-10

Pin Buffers as Open Drain ................................................ 6-11

Programmable Pull-Up Resistors ....................................... 6-11

DAI/DPI Pin Buffer Status ............................................... 6-12

Unused DAI/DPI Pins ...................................................... 6-12

Miscellaneous Buffers ............................................................ 6-12

DAI/DPI Peripherals ............................................................. 6-14

Output Signals With Pin Buffer Enable Control ................ 6-14

Output Signals Without Pin Buffer Enable Control ........... 6-16

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Contents

Signal Routing Units (SRUs) ................................................. 6-16

Signal Routing Matrix by Groups ...................................... 6-16

DAI/DPI Group Routing .................................................. 6-18

Rules for SRU Connections ............................................... 6-20

Making SRU Connections ................................................. 6-20

DAI Routing Capabilities .................................................. 6-24

DPI Routing Capabilities .................................................. 6-25

Pin Buffer Input ............................................................ 6-26

Pin Buffer Enable .......................................................... 6-26

Miscellaneous Signals .................................................... 6-27

DAI Default Routing ............................................................. 6-28

DPI Default Routing ............................................................. 6-31

Interrupts ................................................................................... 6-32

System versus Exception Interrupts ........................................ 6-32

Functional Description .......................................................... 6-33

DAI Interrupt Channels ........................................................ 6-33

DAI Interrupt Priorities ......................................................... 6-34

DPI Interrupt Channels ......................................................... 6-34

DPI Interrupt Priorities ......................................................... 6-34

DAI Miscellaneous Interrupts ................................................ 6-35

DPI Miscellaneous Interrupts ................................................ 6-35

DAI/DPI Interrupt Mask Events ............................................ 6-36

DAI Interrupt Acknowledge .................................................. 6-38

DPI Interrupt Acknowledge ................................................... 6-39

ADSP-2137x SHARC Processor Hardware Reference xv

Contents

Core Versus DAI/DPI Interrupts ........................................... 6-39

Debug Features ........................................................................... 6-40

DAI Shadow Registers ........................................................... 6-40

DPI Shadow Registers ........................................................... 6-40

Loop Back Routing ............................................................... 6-41

Effect Latency ............................................................................ 6-42

Write Effect Latency ............................................................. 6-42

Signal Routing Unit Effect Latency ........................................ 6-42

Programming Model ................................................................... 6-42

DAI Example System ............................................................ 6-43

SERIAL PORTS

Features ........................................................................................ 7-2

Pin Descriptions ........................................................................... 7-4

SRU Programming ....................................................................... 7-5

SRU SPORT Receive Master ................................................... 7-6

SRU SPORT Signal Integrity .................................................. 7-6

Register Overview ......................................................................... 7-7

Clocking ...................................................................................... 7-8

Master Clock .......................................................................... 7-9

Master Frame Sync .................................................................. 7-9

Slave Mode ........................................................................... 7-10

Functional Description ............................................................... 7-11

Architecture .......................................................................... 7-11

Data Types and Companding ................................................ 7-12

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Companding the Data Stream ........................................... 7-14

Transmit Path ................................................................... 7-15

Receive Path ..................................................................... 7-15

Frame Sync ........................................................................... 7-16

Frame Sync and Data Sampling ......................................... 7-16

Serial Word Length ........................................................... 7-17

Internal Versus External Frame Syncs ................................. 7-18

External Frame Sync Sampling ...................................... 7-19

Logic Level Frame Syncs ................................................ 7-19

Data-Independent Frame Sync ...................................... 7-20

Operating Modes ........................................................................ 7-20

Mode Selection ...................................................................... 7-22

Channel Order First .......................................................... 7-24

Standard Serial Mode ............................................................. 7-24

Timing Control Bits .......................................................... 7-24

Clocking Options ............................................................. 7-25

Frame Sync Options .......................................................... 7-25

Framed Versus Unframed Frame Syncs ............................... 7-25

Early Versus Late Frame Syncs ........................................... 7-26

Left-Justified Mode ............................................................... 7-28

Master Serial Clock and Frame Sync Rates ......................... 7-28

Timing Control Bits .......................................................... 7-29

2

I

S Mode .............................................................................. 7-29

Master Serial Clock and Frame Sync Rates ......................... 7-29

ADSP-2137x SHARC Processor Hardware Reference xvii

Contents

2

I

S Compatibility ............................................................. 7-30

Timing Control Bits ......................................................... 7-30

Multichannel Mode .............................................................. 7-31

Clocking Options ............................................................. 7-31

Frame Sync Options ......................................................... 7-32

Frame Sync Delay (MFD) ................................................. 7-32

Transmit Data Valid Signal ............................................... 7-33

Transmit Data Valid Output ......................................... 7-34

Timing Control Bits ......................................................... 7-35

Number of Channels (NCH) ............................................ 7-35

Packed Mode ........................................................................ 7-36

Clocking Options ............................................................. 7-37

Frame Sync Options ......................................................... 7-37

Timing Control Bits ......................................................... 7-37

Active Channel Selection Registers ........................................ 7-38

Transmit Selection Registers .............................................. 7-38

Receive Selection Registers ................................................ 7-39

Companding Selection ...................................................... 7-39

Companding Limitations .................................................. 7-39

Data Transfer Types .................................................................... 7-40

Data Buffers ......................................................................... 7-40

Transmit Buffers (TXSPxA/B) ........................................... 7-41

Receive Buffers (RXSPxA/B) ............................................. 7-41

Buffer Status ..................................................................... 7-41

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Contents

Data Buffer Packing .......................................................... 7-43

Core Transfers ....................................................................... 7-43

Single Word Transfers ....................................................... 7-43

Frame Sync Generation ..................................................... 7-44

Internal Memory DMA Transfers ........................................... 7-45

Standard DMA ................................................................. 7-46

DMA Chaining ................................................................. 7-47

DMA Chain Insertion Mode ............................................. 7-48

Frame Sync Generation ..................................................... 7-49

Interrupts ................................................................................... 7-49

Internal Transfer Completion ................................................. 7-50

Shared Channels .................................................................... 7-51

Error Detection ..................................................................... 7-51

Error Status ........................................................................... 7-53

Debug Features ........................................................................... 7-54

SPORT Loopback ................................................................. 7-54

LoopBack Routing ............................................................ 7-54

Buffer Hang Disable (BHD) .................................................. 7-54

Effect Latency ............................................................................. 7-55

Write Effect Latency .............................................................. 7-55

SPORT Effect Latency ........................................................... 7-55

Programming Model ................................................................... 7-55

Setting Up and Starting DMA Master Mode .......................... 7-56

Setting Up and Starting Chained DMA .................................. 7-56

ADSP-2137x SHARC Processor Hardware Reference xix

Contents

Enter DMA Chain Insertion Mode ........................................ 7-57

Setting Up and Starting Multichannel Mode .......................... 7-57

Multichannel Mode Backward Compatibility .................... 7-58

Programming Packed Mode ................................................... 7-59

Additional Information for External

Frame Sync Operation ........................................................ 7-60

Companding As a Function ................................................... 7-60

INPUT DATA PORT

Features ........................................................................................ 8-2

Pin Descriptions ........................................................................... 8-3

SRU Programming ....................................................................... 8-4

Register Overview ......................................................................... 8-5

Clocking ...................................................................................... 8-6

Functional Description ................................................................. 8-6

Operating Modes .......................................................................... 8-7

PDAP Port Selection ............................................................... 8-8

Data Hold .............................................................................. 8-9

PDAP Data Masking ............................................................. 8-10

PDAP Data Packing .............................................................. 8-10

No Packing ....................................................................... 8-10

Packing by 2 ..................................................................... 8-11

Packing by 3 ..................................................................... 8-12

Packing by 4 ..................................................................... 8-13

Data Transfer ............................................................................. 8-14

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Data Buffer ........................................................................... 8-14

Core Transfers ....................................................................... 8-15

SIP Data Buffer Format ..................................................... 8-16

PDAP Data Buffer Format ................................................ 8-18

DMA Transfers ...................................................................... 8-19

Data Buffer Format for DMA ............................................ 8-19

DMA Channel Priority ..................................................... 8-20

Standard DMA ................................................................. 8-20

Ping-Pong DMA ............................................................... 8-21

Multichannel DMA Operation .......................................... 8-21

Multichannel FIFO Status ................................................. 8-22

Interrupts ................................................................................... 8-23

Interrupt Acknowledge .......................................................... 8-23

Threshold Interrupts ............................................................. 8-23

DMA Interrupts .................................................................... 8-24

FIFO Overflow Interrupts ..................................................... 8-24

Debug Features ........................................................................... 8-25

Status Register Debug ............................................................ 8-25

Buffer Hang Disable .............................................................. 8-25

Shadow Registers ................................................................... 8-25

Core FIFO Write ................................................................... 8-26

Effect Latency ............................................................................. 8-26

Write Effect Latency .............................................................. 8-26

IDP Effect Latency ................................................................ 8-26

ADSP-2137x SHARC Processor Hardware Reference xxi

Contents

Programming Model ................................................................... 8-26

Setting Miscellaneous Bits ..................................................... 8-27

Starting Core Interrupt-Driven Transfer ................................ 8-27

Additional Notes .............................................................. 8-28

Starting A Standard DMA Transfer ........................................ 8-29

Starting a Ping-Pong DMA Transfer ...................................... 8-30

Servicing Interrupts for DMA ............................................... 8-31

ASYNCHRONOUS SAMPLE RATE CONVERTER

Features ........................................................................................ 9-2

Pin Descriptions ........................................................................... 9-3

SRU Programming ....................................................................... 9-3

Register Overview ......................................................................... 9-4

Clocking ...................................................................................... 9-5

Functional Description ................................................................. 9-5

Operating Modes .......................................................................... 9-9

TDM Daisy Chain Mode ...................................................... 9-11

TDM Input Daisy Chain .................................................. 9-11

TDM Output Daisy Chain ............................................... 9-12

Bypass Mode ......................................................................... 9-12

Matched-Phase Mode ............................................................ 9-12

Data Format Matched-Phase Mode ................................... 9-14

Group Delay .................................................................... 9-14

Decimation Rate ................................................................... 9-15

Muting Modes ...................................................................... 9-15

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Soft Mute ......................................................................... 9-15

Hard Mute ........................................................................ 9-16

Auto Mute ........................................................................ 9-16

Interrupts ................................................................................... 9-16

Debug Features ........................................................................... 9-17

Effect Latency ............................................................................. 9-17

Write Effect Latency .............................................................. 9-17

SRC Effect Latency ............................................................... 9-18

SONY/PHILIPS DIGITAL INTERFACE

Features ...................................................................................... 10-2

Pin Descriptions ......................................................................... 10-3

SRU Programming ...................................................................... 10-5

Register Overview ....................................................................... 10-6

Clocking ..................................................................................... 10-7

S/PDIF Transmitter .................................................................... 10-7

Functional Description .......................................................... 10-7

Input Data Format .......................................................... 10-10

Operating Modes ................................................................. 10-12

Full Serial Mode ............................................................. 10-12

Standalone Mode ............................................................ 10-12

Data Output Mode ......................................................... 10-13

S/PDIF Receiver ....................................................................... 10-14

Functional Description ........................................................ 10-14

Clock Recovery ............................................................... 10-16

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Contents

Output Data Format ...................................................... 10-16

Channel Status ............................................................... 10-17

Operating Modes ................................................................ 10-17

Compressed or Non-linear Audio Data ............................ 10-17

Emphasized Audio Data .............................................. 10-18

Single-Channel Double-Frequency Mode .................... 10-19

Clock Recovery Modes ................................................... 10-19

Digital On-Chip PLL ................................................. 10-19

External Analog PLL ................................................... 10-20

Interrupts ................................................................................. 10-20

Transmitter Interrupt .......................................................... 10-20

Receiver Interrupts .............................................................. 10-21

Receiver Error Interrupts ..................................................... 10-21

Debug Features ......................................................................... 10-22

Loop Back Routing ............................................................. 10-22

Effect Latency .......................................................................... 10-22

Write Effect Latency ........................................................... 10-22

S/PDIF Effect Latency ........................................................ 10-22

S/PDIF Transmit ............................................................ 10-22

S/PDIF Receive .............................................................. 10-23

Programming Model ................................................................. 10-23

Programming the Transmitter .............................................. 10-24

Programming the Receiver ................................................... 10-24

Interrupted Data Streams on the Receiver ............................ 10-25

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PRECISION CLOCK GENERATOR

Features ...................................................................................... 11-2

Pin Descriptions ......................................................................... 11-3

SRU Programming ...................................................................... 11-4

Register Overview ....................................................................... 11-5

Clocking ..................................................................................... 11-5

Functional Description ............................................................... 11-6

Serial Clock ........................................................................... 11-6

Frame Sync ........................................................................... 11-7

Frame Sync Output ........................................................... 11-7

Divider Mode Selection ..................................................... 11-8

Phase Shift ........................................................................ 11-8

Pulse Width ...................................................................... 11-9

Default Pulse Width ....................................................... 11-10

Timing Example for I2S Mode ........................................ 11-10

Operating Modes ...................................................................... 11-11

Normal Mode ...................................................................... 11-11

Bypass Mode ....................................................................... 11-12

One-Shot Mode .................................................................. 11-13

External Event Trigger ......................................................... 11-14

External Event Trigger Delay ........................................... 11-15

Audio System Example ........................................................ 11-15

Clock Configuration Examples ............................................ 11-17

Effect Latency ........................................................................... 11-18

ADSP-2137x SHARC Processor Hardware Reference xxv

Contents

Write Effect Latency ........................................................... 11-18

PCG Effect Latency ............................................................ 11-19

Programming Model ................................................................. 11-19

Frame Sync Phase Setting .................................................... 11-20

External Event Trigger ......................................................... 11-20

Debug Features ......................................................................... 11-20

SERIAL PERIPHERAL INTERFACE PORTS

Features ...................................................................................... 12-2

Pin Descriptions ......................................................................... 12-3

SRU Programming ..................................................................... 12-4

Register Overview ....................................................................... 12-5

Clocking .................................................................................... 12-6

Choosing the Pin Enable for the SPI Clock ............................ 12-7

Functional Description ............................................................... 12-7

Single Master Systems ........................................................... 12-9

Multi Master Systems .......................................................... 12-10

Operating Modes ...................................................................... 12-12

Transfer Initiate Mode ......................................................... 12-12

SPI Modes .......................................................................... 12-13

Slave Select Outputs ............................................................ 12-15

Frame Delay for Slave ......................................................... 12-16

Data Transfer ........................................................................... 12-17

Data Buffer ......................................................................... 12-17

Core Transfers ..................................................................... 12-18

xxvi ADSP-2137x SHARC Processor Hardware Reference

Contents

DMA Transfers .................................................................... 12-19

Slave DMA Transfer Preparation ..................................... 12-20

SPI DMA Chaining ........................................................ 12-21

Setting Up and Starting Chained DMA ....................... 12-21

Core and DMA Transfers ..................................................... 12-22

Changing SPI Configuration ........................................... 12-22

Starting and Stopping SPI Data Transfers ........................ 12-23

Interrupts ................................................................................. 12-24

Interrupt Sources ................................................................. 12-25

Internal Transfer Completion .......................................... 12-26

Multi Master Error .............................................................. 12-26

Debug Features ......................................................................... 12-27

Shadow Receive Buffers ....................................................... 12-28

Internal Loopback Mode ..................................................... 12-28

Loop Back Routing ......................................................... 12-28

Effect Latency ........................................................................... 12-29

Write Effect Latency ............................................................ 12-29

SPI Effect Latency ............................................................... 12-29

Programming Model ................................................................. 12-29

Master Mode Core Transfers ................................................ 12-29

Multimaster Transfers ...................................................... 12-31

Slave Mode Core Transfers ................................................... 12-31

Master Mode DMA Transfers ............................................... 12-33

Slave Mode DMA Transfers ................................................. 12-34

ADSP-2137x SHARC Processor Hardware Reference xxvii

Contents

Chained DMA Transfers ..................................................... 12-36

Stopping Core Transfers ...................................................... 12-36

Stopping DMA Transfers ..................................................... 12-37

Switching from Transmit To Transmit/Receive DMA ........... 12-38

Switching from Receive to Receive/Transmit DMA .............. 12-39

DMA Error Interrupts ......................................................... 12-40

PERIPHERAL TIMERS

Features ...................................................................................... 13-2

Pin Descriptions ......................................................................... 13-3

SRU Programming ..................................................................... 13-3

Register Overview ....................................................................... 13-4

Read-Modify-Write ............................................................... 13-5

Clocking .................................................................................... 13-5

Functional Description ............................................................... 13-6

Operating Modes ........................................................................ 13-7

Pulse Width Modulation Mode (PWM_OUT) ...................... 13-8

PWM Waveform Generation .......................................... 13-10

Single-Pulse Generation .................................................. 13-12

Pulse Mode .................................................................... 13-12

Pulse Width Count and Capture Mode (WDTH_CAP) ....... 13-13

External Event Watchdog Mode (EXT_CLK) ...................... 13-15

Interrupts ................................................................................. 13-17

Sources ............................................................................... 13-18

Watchdog Functionality ...................................................... 13-19

xxviii ADSP-2137x SHARC Processor Hardware Reference

Contents

Debug Features ......................................................................... 13-19

Loop Back Routing .............................................................. 13-19

Emulation Considerations ................................................... 13-19

Effect Latency ........................................................................... 13-20

Write Effect Latency ............................................................ 13-20

Peripheral Timers Effect Latency .......................................... 13-20

Programming Model ................................................................. 13-20

PWM Out Mode ................................................................. 13-21

WDTH_CAP Mode ............................................................ 13-23

EXT_CLK Mode ................................................................. 13-24

UART PORT CONTROLLER

Features ...................................................................................... 14-2

SRU Programming ...................................................................... 14-2

Register Overview ....................................................................... 14-3

Clocking ..................................................................................... 14-4

Functional Description ............................................................... 14-5

Serial Communication ........................................................... 14-7

Operating Modes ........................................................................ 14-8

Data Packing ......................................................................... 14-8

9-Bit Transmission Mode ....................................................... 14-8

Packed Mode .................................................................... 14-9

Data Transfer ............................................................................ 14-10

Data Buffers ........................................................................ 14-10

Transmit Holding Registers (UARTxTHR) ...................... 14-10

ADSP-2137x SHARC Processor Hardware Reference xxix

Contents

Receive Buffer Registers (UARTxRBR) ............................ 14-11

Core Transfers ..................................................................... 14-12

DMA Transfers ................................................................... 14-13

DMA Chaining .............................................................. 14-14

Interrupts ................................................................................. 14-14

Interrupt Routing ............................................................... 14-15

DPI ................................................................................ 14-15

UART ............................................................................ 14-16

DMA Interrupts .................................................................. 14-16

Core Interrupts ................................................................... 14-17

Error Interrupts .................................................................. 14-19

Debug Features ......................................................................... 14-20

Shadow Registers ................................................................ 14-20

Shadow Buffer .................................................................... 14-20

Loop Back Routing ............................................................. 14-20

Effect Latency .......................................................................... 14-20

Write Effect Latency ........................................................... 14-20

UART Effect Latency .......................................................... 14-21

Programming Model ................................................................. 14-21

Autobaud Detection ............................................................ 14-21

Programming Model for DMA Transfers .............................. 14-22

Setting Up and Starting Chained DMA ........................... 14-22

Notes on Using UART DMA .......................................... 14-23

Programming Model for Core Transfers ............................... 14-23

xxx ADSP-2137x SHARC Processor Hardware Reference

Contents

TWO WIRE INTERFACE CONTROLLER

Features ...................................................................................... 15-2

Pin Descriptions ......................................................................... 15-3

SRU Programming ...................................................................... 15-4

Clocking ..................................................................................... 15-4

Register Overview ....................................................................... 15-5

Functional Description ............................................................... 15-6

Bus Arbitration ..................................................................... 15-9

Start and Stop Conditions ................................................... 15-10

Slave Mode Addressing ........................................................ 15-11

Master Mode Addressing ..................................................... 15-11

Data Transfer ............................................................................ 15-11

Data Buffers ........................................................................ 15-11

8-Bit Transmit FIFO Register .......................................... 15-12

16-Bit Transmit FIFO Register ........................................ 15-12

8-Bit Receive FIFO Register ............................................ 15-13

16-Bit Receive FIFO Register .......................................... 15-13

Operating Modes ...................................................................... 15-14

General Call Addressing ...................................................... 15-14

Fast Mode ........................................................................... 15-15

Interrupts ................................................................................. 15-15

Interrupt Routing ................................................................ 15-16

DPI ................................................................................ 15-16

TWI ............................................................................... 15-16

ADSP-2137x SHARC Processor Hardware Reference xxxi

Contents

Interrupt Sources ................................................................ 15-17

Debug Features ......................................................................... 15-18

Buffer Hang Disable ........................................................... 15-18

Loop Back Routing ............................................................. 15-18

Effect Latency .......................................................................... 15-18

Write Effect Latency ........................................................... 15-18

TWI Effect Latency ............................................................ 15-18

Programming Model ................................................................. 15-19

General Setup ..................................................................... 15-19

Slave Mode ......................................................................... 15-19

Master Mode Clock Setup ................................................... 15-21

Master Mode Transmit ........................................................ 15-21

Master Mode Receive .......................................................... 15-22

Repeated Start Condition .................................................... 15-23

Transmit/Receive Repeated Start Sequence ...................... 15-24

Receive/Transmit Repeated Start Sequence ...................... 15-25

Electrical Specifications ............................................................ 15-26

POWER MANAGEMENT

Features ...................................................................................... 16-1

Register Overview ....................................................................... 16-1

Phase-Locked Loop (PLL) ........................................................... 16-2

Functional Description ......................................................... 16-2

PLL Input Clock ................................................................... 16-3

Pre Divider Input .................................................................. 16-3

xxxii ADSP-2137x SHARC Processor Hardware Reference

Contents

PLL Multiplier ...................................................................... 16-4

PLLM Hardware Control .................................................. 16-4

PLLM Software Control .................................................... 16-4

PLL VCO ............................................................................. 16-5

Output Clock Generator ....................................................... 16-6

Core Clock (CCLK) ......................................................... 16-6

IOP Clock (PCLK) ........................................................... 16-6

SDRAM Clock (SDCLK) .................................................. 16-6

Default PLL Hardware Settings .............................................. 16-7

Operating Modes ........................................................................ 16-7

Bypass Mode ......................................................................... 16-7

Normal Mode ........................................................................ 16-8

Clocking Golden Rules .......................................................... 16-8

Power-Up Sequence .................................................................... 16-8

PLL Start-Up ........................................................................ 16-9

Power Management ................................................................... 16-10

Peripherals .......................................................................... 16-10

DAI Routing Unit ............................................................... 16-10

External Port Control .......................................................... 16-11

Example for Clock Management ...................................... 16-11

General Notes on Power Savings ...................................... 16-12

Programming Model ................................................................. 16-12

Post Divider ........................................................................ 16-13

Multiplier and Post Divider Programming Model ................. 16-13

ADSP-2137x SHARC Processor Hardware Reference xxxiii

Contents

Back to Back Bypass ............................................................ 16-15

SYSTEM DESIGN

Features ...................................................................................... 17-2

Pin Descriptions ......................................................................... 17-2

Register Overview ....................................................................... 17-2

Processor Reset ........................................................................... 17-3

Hardware Reset ..................................................................... 17-4

Software Reset ...................................................................... 17-4

Running Reset (ADSP-2137x Only) ...................................... 17-5

System Considerations ...................................................... 17-6

External Host ............................................................... 17-7

Processor Booting ....................................................................... 17-7

Boot Mechanisms .................................................................. 17-8

External Port Booting ............................................................ 17-8

SPI Port Booting ................................................................. 17-12

Master Boot Mode .......................................................... 17-13

Master Header Information ............................................ 17-14

Slave Boot Mode ............................................................ 17-16

SPI Boot Packing ............................................................ 17-17

32-Bit SPI Packing ..................................................... 17-19

16-Bit SPI Packing ..................................................... 17-20

8-Bit SPI Packing ....................................................... 17-21

Kernel Boot Time ............................................................... 17-22

ROM Booting ..................................................................... 17-23

xxxiv ADSP-2137x SHARC Processor Hardware Reference

Contents

Programming Model ................................................................. 17-23

Running Reset ..................................................................... 17-24

Running The Boot Kernel ................................................... 17-24

Loading the Boot Kernel Using DMA .............................. 17-24

Executing the Boot Kernel ............................................... 17-25

Loading the Application .................................................. 17-25

Loading the Application’s Interrupt Vector Table .............. 17-25

Starting Program Execution ............................................. 17-26

Memory Aliasing in Internal Memory .................................. 17-26

Pin Multiplexing ....................................................................... 17-27

Core FLAG Pins Multiplexing ............................................. 17-27

Backward Compatibility .................................................. 17-28

External Port Pin Multiplexing ............................................ 17-28

Multiplexed External Port Pins ........................................ 17-29

Backward Compatibility .................................................. 17-30

Parallel Connection of External Port and

DPI Flag Pins ................................................................... 17-30

External Port Multiplexing Examples ............................... 17-32

High Frequency Design ............................................................. 17-33

Circuit Board Design ........................................................... 17-33

Clock Input Specifications and Jitter ............................... 17-33

RESETOUT ................................................................... 17-34

Input Pin Hysteresis ........................................................ 17-34

Pull-Up/Pull-Down Resistors ........................................... 17-35

Memory Select Pins ......................................................... 17-35

ADSP-2137x SHARC Processor Hardware Reference xxxv

Contents

Edge Triggered I/O ......................................................... 17-36

Asynchronous Inputs ...................................................... 17-36

Decoupling and Grounding ................................................. 17-37

Circuit Board Layout .......................................................... 17-37

Other Recommendations and Suggestions ............................ 17-37

EZ-KIT Lite Schematics ...................................................... 17-39

Oscilloscope Probes ............................................................. 17-39

Recommended Reading ....................................................... 17-40

System Components ................................................................. 17-41

Supervisory Circuits ............................................................ 17-41

Definition of Terms .................................................................. 17-43

REGISTERS REFERENCE

Overview ...................................................................................... A-2

Register Diagram Conventions ................................................ A-2

Bit Types and Settings ............................................................. A-3

System and Power Management Registers ...................................... A-4

System Control Register (SYSCTL) ......................................... A-4

Power Management Control Registers (PMCTL) ..................... A-7

Running Reset Control Register (RUNRSTCTL) ................... A-11

Peripheral Registers ..................................................................... A-11

External Port Registers .......................................................... A-11

Control Register (EPCTL) ................................................ A-11

ADSP-21367/8/9 External Port DMA Control

Registers (DMACx) ....................................................... A-14

xxxvi ADSP-2137x SHARC Processor Hardware Reference

Contents

ADSP-2137x External Port DMA Control Registers

(DMACx) ..................................................................... A-16

AMI Control Registers (AMICTLx) ................................. A-20

AMI Status Register (AMISTAT) ...................................... A-23

SDRAM Registers ................................................................ A-24

Control Register (SDCTL) ............................................... A-24

Control Status Register (SDSTAT) ................................... A-28

Refresh Rate Control Register (SDRRC) ........................... A-29

Shared Memory Status Register

(SYSTAT, ADSP-21368 Only) ........................................... A-30

Memory-to-Memory Registers .............................................. A-31

DMA Control (MTMCTL Register) ................................ A-31

Pulse Width Modulation Registers ........................................ A-32

Global Control Register (PWMGCTL) ............................ A-32

Global Status Register (PWMGSTAT) .............................. A-34

Control Register (PWMCTLx) ......................................... A-34

Status Registers (PWMSTATx) ......................................... A-36

Output Disable Registers (PWMSEGx) ............................ A-36

Polarity Select Registers (PWMPOLx) .............................. A-37

Period Registers (PWMPERIODx) ................................... A-38

Duty Cycle High Side Registers (PWMAx, PWMBx) ........ A-38

Duty Cycle Low Side Registers (PWMALx, PWMBLx) ..... A-39

Dead Time Registers (PWMDTx) .................................... A-39

Debug Status Registers (PWMDBGx) .............................. A-39

DAI Signal Routing Unit Registers ............................................. A-39

ADSP-2137x SHARC Processor Hardware Reference xxxvii

Contents

Clock Routing Control Registers

(SRU_CLKx, Group A) ...................................................... A-40

Serial Data Routing Registers (SRU_DATx, Group B) ........... A-45

Frame Sync Routing Control Registers

(SRU_FSx, Group C) ......................................................... A-50

Pin Signal Assignment Registers

(SRU_PINx, Group D) ...................................................... A-54

Miscellaneous Signal Routing Registers

(SRU_MISCx, Group E) .................................................... A-60

Pin Buffer Enable Registers (SRU_PBENx, Group F) ............. A-63

Pin Buffer Registers ............................................................... A-67

Pin Buffer Status Registers (DAI_PIN_STAT) ................... A-67

Resistor Pull-up Enable Register (DAI_PIN_PULLUP) ..... A-67

Interrupt Controller Registers ................................................ A-68

Peripherals Routed Through the DAI .......................................... A-69

Serial Port Registers ............................................................... A-69

Divisor Registers (DIVx) ................................................... A-69

Serial Control Registers (SPCTLx) .................................... A-70

Multichannel Control Registers (SPMCTLx) ..................... A-85

Multichannel Active Channel Select Registers .................... A-88

Transmit Channel Select Registers (MTxCSy) ................ A-89

Transmit Channel Compand Select Registers

(MTxCCSy) .............................................................. A-89

Receive Channel Select Registers (MRxCSy) .................. A-89

Receive Compand Channel Select Registers

(MRxCCSy) .............................................................. A-90

xxxviii ADSP-2137x SHARC Processor Hardware Reference

Contents

Error Control Register (SPERRCTLx) .......................... A-90

Error Status Register (SPERRSTAT) ............................. A-92

Input Data Port Registers ..................................................... A-92

Serial Input Port Control Register 0 (IDP_CTL0) ............ A-92

Serial Input Port Control Register 1 (IDP_CTL1) ............ A-95

Parallel Data Acquisition Port Control Register

(IDP_PP_CTL) ............................................................ A-96

Status Register (DAI_STAT0) .......................................... A-98

Status Debug Register 1 (DAI_STAT1) .......................... A-100

Sample Rate Converter Registers ......................................... A-101

Control Registers (SRCCTLx) ........................................ A-101

Mute Register (SRCMUTE) ........................................... A-105

Ratio Registers (SRCRATx) ............................................ A-106

Precision Clock Generator Registers .................................... A-108

Control Registers (PCG_CTLxy) ................................... A-108

Pulse Width Registers (PCG_PWx) ................................ A-110

Frame Synchronization Registers (PCG_SYNCx) ............ A-112

Sony/Philips Digital Interface Registers ............................... A-116

Transmitter Registers ...................................................... A-116

Transmit Control Register (DITCTL) ......................... A-116

Transmit Status Bit Registers for Subframe A/B

(DITCHANAx/Bx) ................................................. A-118

Transmit User Bits Buffer Registers for Subframe A/B

Registers (DITUSRBITAx/Bx) ................................. A-119

User Bit Update Register (DITUSRUPD) ................... A-120

ADSP-2137x SHARC Processor Hardware Reference xxxix

Contents

Receiver Registers ........................................................... A-121

Receive Control Register (DIRCTL) ........................... A-121

Receive Status Register (DIRSTAT) ............................. A-122

Receive Status Registers for Subframe A

(DIRCHANL) ......................................................... A-125

Receive Status Registers for Subframe B

(DIRCHANR) ......................................................... A-126

DPI Signal Routing Unit Registers ............................................ A-126

Miscellaneous Signal Routing Registers

(SRU2_INPUTx, Group A) .............................................. A-126

Pin Assignment Signal Routing

(SRU2_PINx, Group B) .................................................. A-131

Pin Enable Signal Routing

(SRU2_PBENx, Group C) .............................................. A-134

Pin Buffer Registers ............................................................. A-138

Pin Buffer Status Register (DPI_PIN_STAT) .................. A-138

Resistor Pull-up Enable Register (DPI_PIN_PULLUP) ... A-138

Interrupt Controller Registers .............................................. A-139

Peripherals Routed Through the DPI ........................................ A-140

Serial Peripheral Interface Registers ...................................... A-140

Control Registers (SPICTL, SPICTLB) ........................... A-140

DMA Configuration Registers (SPIDMAC,

SPIDMACB) ............................................................... A-146

Baud Rate Registers (SPIBAUD, SPIBAUDB) ................. A-148

Status Registers (SPISTAT, SPISTATB) ........................... A-148

Flags Registers (SPIFLG, SPIFLGB) ................................ A-150

xl ADSP-2137x SHARC Processor Hardware Reference

UART Control and Status Registers .................................... A-152

Line Control Register (UARTxLCR) .............................. A-152

Line Status Registers (UARTxLSR, UARTxLSRSH) ........ A-154

Interrupt Enable Register (UARTxIER) .......................... A-155

Interrupt Identification Registers (UARTxIIR,

UARTxIIRSH) ............................................................ A-156

Divisor Latch Registers (UARTxDLL, UARTxDLH) ...... A-158

Scratch Register (UARTxSCR) ....................................... A-158

Mode Register (UARTxMODE) ..................................... A-158

Buffer Control Registers (UARTxTXCTL,

UARTxRXCTL) .......................................................... A-160

DMA Status Registers (UARTxTXSTAT,

UARTxRXSTAT) ........................................................ A-161

Two Wire Interface Registers .............................................. A-162

Master Internal Time Register (TWIMITR) ................... A-162

Clock Divider Register (TWIDIV) ................................. A-163

Slave Mode Control Register (TWISCTL) ...................... A-163

Slave Address Register (TWISADDR) ............................ A-165

Slave Status Register (TWISSTAT) ................................. A-165

Master Control Register (TWIMCTL) ........................... A-165

Master Address Register (TWIMADDR) ........................ A-168

Master Mode Status Register (TWIMSTAT) ................... A-168

FIFO Control Register (TWIFIFOCTL) ........................ A-171

FIFO Status Register (TWIFIFOSTAT) ......................... A-172

Interrupt Latch Register (TWIIRPTL) ............................ A-173

ADSP-2137x SHARC Processor Hardware Reference xli

Interrupt Mask Register (TWIIMASK) ........................... A-175

Peripheral Timer Registers ................................................... A-177

Read-Modify-Write Timer Control Register .................... A-177

Configuration Registers (TMxCTL) ................................ A-178

Status Registers (TMxSTAT) ........................................... A-178

Register Listing ......................................................................... A-181

PERIPHERAL INTERRUPT CONTROL

Interrupt Latency ......................................................................... B-1

Interrupt Acknowledge ................................................................. B-2

Interrupt Completion ................................................................... B-3

Interrupt Priority .......................................................................... B-4

Peripherals with Multiple Interrupt Vector Addresses ............... B-6

Priority Interrupt Control Registers (PICRx) ........................... B-7

AUDIO FRAME FORMATS

Overview ...................................................................................... C-2

Standard Serial Mode .................................................................... C-2

2

S Mode ..................................................................................... C-3

I

Left-Justified Mode ....................................................................... C-5

Right-Justified Mode .................................................................... C-5

TDM Mode ................................................................................. C-6

Packed TDM Mode ................................................................ C-7

MOST Mode .......................................................................... C-8

AES/EBU/SPDIF Formats ............................................................ C-9

xlii ADSP-2137x SHARC Processor Hardware Reference

Subframe Format .................................................................. C-12

Channel Coding ................................................................... C-14

Preambles ............................................................................. C-15

INDEX

ADSP-2137x SHARC Processor Hardware Reference xliii

xliv ADSP-2137x SHARC Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using ADSP-21367/8/9
and ADSP-21371/75 SHARC® processors from Analog Devices, Inc.

Purpose of This Manual

The ADSP-2137x SHARC Processor Hardware Reference contains informa-
tion about the peripheral set and I/O properties for the ADSP-21367/8/9
and ADSP-2137x processors. These are 32-bit, fixed- and floating-point
digital signal processors from Analog Devices for use in computing, com­munications, and consumer applications.

The manual provides information on the processor’s I/O architecture and
the operation of the peripherals associated with each model.

Intended Audience

The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the appropriate hardware reference manuals and data sheets) that
describe your target architecture.

ADSP-2137x SHARC Processor Hardware Reference xliii

Manual Contents

Manual Contents

This manual consists of:

• Chapter 1, “Introduction”
Provides an architectural overview of the ADSP-21367/8/9 and
ADSP-2137/75 SHARC processors.

• Chapter 2, “I/O Processor”
Describes the input/output processor architecture, and provides
direct memory access (DMA) procedures for the processor
peripherals.

• Chapter 3, “External Port”
Describes how the processor’s on-chip DMA controller acts as a
machine for transferring data without core interruption.

• Chapter 4, “Memory-to-Memory Port DMA”
The memory-to-memory port DMA module is used for internal
memory transfers only.

• Chapter 5, “Pulse Width Modulation”
Describes the implementation and use of the pulse width modula­tion module which provides a technique for controlling analog
circuits with the microprocessor’s digital outputs.

• Chapter 6, “Digital Application/Digital Peripheral Interfaces”
Provides information about the digital audio interface (DAI) which
allows you to attach an arbitrary number and variety of peripherals
to the processor while retaining high levels of compatibility.

• Chapter 7, “Serial Ports”
Describes the up to eight dual data line serial ports. Each SPORT
contains a clock, a frame sync, and two data lines that can be con­figured as either a receiver or transmitter pair.

xliv ADSP-2137x SHARC Processor Hardware Reference

Preface

• Chapter 8, “Input Data Port”
Discusses the function of the input data port (IDP) which provides
a low overhead method of routing signal routing unit (SRU) sig­nals back to the core’s memory.

• Chapter 9, “Asynchronous Sample Rate Converter”
Provides information on the sample rate converter (SRC) module.
This module performs synchronous or asynchronous sample rate
conversion across independent stereo channels, without using any
internal processor resources.

• Chapter 10, “Sony/Philips Digital Interface”
Provides information on the use of the Sony/Philips Digital Inter­face which is a standard audio file transfer format that allows the
transfer of digital audio signals from one device to another without
having to be converted to an analog signal.

• Chapter 11, “Precision Clock Generator”
Details the precision clock generators (PCG), each of which gener­ates a pair of signals derived from a clock input signal.

• Chapter 12, “Serial Peripheral Interface Ports”
Describes the operation of the serial peripheral interface (SPI) port.
SPI devices communicate using a master-slave relationship and can
achieve high data transfer rate because they can operate in
full-duplex mode.

• Chapter 13, “Peripheral Timers”
In addition to the internal core timer, the processors contain iden­tical 32-bit peripheral timers that can be used to interface with
external devices.

• Chapter 14, “UART Port Controller”
Describes the operation of the Universal Asynchronous
Receiver/Transmitter (UART) which is a full-duplex peripheral
compatible with PC-style industry-standard UART.

ADSP-2137x SHARC Processor Hardware Reference xlv

Manual Contents

• Chapter 15, “Two Wire Interface Controller”
The two wire interface is fully compatible with the widely used I
bus standard. It is designed with a high level of functionality and is
compatible with multimaster, multislave bus configurations.

• Chapter 16, “Power Management”
Contains information on managing the clock, PLL and the periph­erals in order to maximize system efficiency with minimum power
consumption.

• Chapter 17, “System Design”
Describes system design features of the SHARC processors. These,
include resetting and booting the processor, as well as pin descrip­tions and other system-level information.

• Appendix A, “Registers Reference”
Provides a graphical presentation of all registers and describes the
bit usage in each register.

• Appendix B “Peripheral Interrupt Control”
Provides a complete listing of the registers that are used to config­ure and control interrupts.

2

C

• Appendix C “Audio Frame Formats”
Provides specific information on all the serial timing protocols used
for audio inter-chip communications.



xlvi ADSP-2137x SHARC Processor Hardware Reference

This hardware reference is a companion document to the SHARC
Processor Programming Reference. The programming reference pro­vides information relating to the processor core, such as processing
elements, internal memory, and program sequencing. It also pro­vides programming specific information, such as complete
descriptions of the ADSP-21xxx instruction set and the compute
operations, including their assembly language syntax and opcode
fields.

What’s New in This Manual

This is the second edition (Revision 2.1) of this hardware reference. In
previous revisions, this manual was titled ADSP-21368 SHARC Processor
Hardware Reference. In order to avoid confusion, this manual has been
retitled ADSP-2137x SHARC Processor Hardware Reference.

All chapters of this document have been revised to correct errors (not
reported through the errata system), to remove redundant information,
and to reorganize information so that it is presented logically and
consistently.

Where appropriate, the chapters contain the following information, pre­sented in this order:

• Primary features

• Hardware interface (pins)

Preface

• Primary registers used by this peripheral

• Peripheral clocking

• Basic function of the peripheral

• Basic peripheral operation, including DMA

• Debug features

• Effect latency

• Programming model (illustrates programming sequences)

The following additional changes should be noted.

• All document errata for this manual has been corrected.

ADSP-2137x SHARC Processor Hardware Reference xlvii

Technical or Customer Support

• New sections that deal more extensively with DMA have been
added. See “Scatter/Gather DMA (ADSP-2137x)” on page 3-76,
and “Interrupts” on page 3-85, and “Standard DMA Parameter

Registers” on page 2-3.

• A new table has been created and placed at the beginning of each
chapter that provides a list of the primary features contained in that
peripheral. This is intended to provide an “at-a-glance” summary
so that you may quickly decide whether this module is desirable for
your particular design.

• “Register Listing” on page A-181 provides a listing of all registers
that are user accessible for the products described in this manual
and includes the register mnemonic, address, description, and reset
state.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technical_support

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

xlviii ADSP-2137x SHARC Processor Hardware Reference

Preface

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

Registration for MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows
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Use EngineerZone to connect with other DSP developers who face similar
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and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

ADSP-2137x SHARC Processor Hardware Reference xlix

Supported Processors

Social Networking Web Sites

You can now follow Analog Devices SHARC development on Twitter and
LinkedIn. To access:

• Twitter: http://twitter.com/ADISHARC

• LinkedIn: Network with the LinkedIn group, Analog Devices
SHARC:

http://www.linkedin.com

Supported Processors

The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++® currently supports the following
SHARC families:

ADSP-2106x, ADSP-2116x, ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-2146x, ADSP-2147x and ADSP-2148x.

Product Information

Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a

l ADSP-2137x SHARC Processor Hardware Reference

Preface

link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.

Also note,

MyAnalog.com is a free feature of the Analog Devices Web site

that allows customization of a Web page to display only the latest infor­mation on products you are interested in. You can also choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals.

MyAnalog.com provides access to books, application notes, data sheets,

code examples, and more.

Visit www.myanalog.com to sign up. If you are already a registered user, just
log on. Your user name is your e-mail address.

VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, Dinkum
Abridged C++ library, and FLEXnet License Tools software
documentation. You can easily search across the entire VisualDSP++ doc­umentation set for any topic of interest.

For easy printing, supplementary Portable Documentation Format (.pdf)
files for all manuals are provided on the VisualDSP++ installation CD.

Each documentation file type is described as follows.

File Description

.chm Help system files and manuals in Microsoft Help format

.htm or
.html

.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the

Dinkum Abridged C++ library and FLEXnet License Tools software documenta­tion. Viewing and printing the .html files requires a browser, such as Internet
Explorer 6.0 (or higher).

.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

ADSP-2137x SHARC Processor Hardware Reference li

Notation Conventions

Technical Library CD

The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals,
VisualDSP++ software manuals, and hardware tools manuals for the fol­lowing processor families: Blackfin®, SHARC, TigerSHARC®,
ADSP-218x, and ADSP-219x.

To order the technical library CD, go to http://www.analog.com/proces-

sors/manuals

request CD check mark, and fill out the order form.

Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.

, navigate to the manuals page for your processor, click the

Notation Conventions

Text conventions used in this manual are identified and described as fol­lows. Note that additional conventions, which apply only to specific
chapters, may appear throughout this document.

Example Description

Close command
(File menu)

{this | that} Alternative items in syntax descriptions appear within curly brackets and sepa-

[this | that] Optional items in syntax descriptions appear within brackets and separated by

[this,…] Optional item lists in syntax descriptions appear within brackets delimited by

lii ADSP-2137x SHARC Processor Hardware Reference

Titles in reference sections indicate the location of an item within the Visu­alDSP++ environment’s menu system (for example, the Close command
appears on the File menu).

rated by vertical bars; read the example as
required.

vertical bars; read the example as an optional

commas and terminated with an ellipse; read the example as an optional
comma-separated list of

this.

this or that. One or the other is

this or that.

Preface







Example Description

.SECTION Commands, directives, keywords, and feature names are in text with letter

gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...
A Note: provides supplementary information on a related topic. In the online

version of this book, the word Note appears instead of this symbol.

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...

A Caution: identifies conditions or inappropriate usage of the product that
could lead to undesirable results or product damage. In the online version of
this book, the word Caution appears instead of this symbol.

War ni ng : Injury to device users may result if ...
A Warning: identifies conditions or inappropriate usage of the product that
could lead to conditions that are potentially hazardous for devices users. In the
online version of this book, the word War ni ng appears instead of this symbol.

ADSP-2137x SHARC Processor Hardware Reference liii

Notation Conventions

liv ADSP-2137x SHARC Processor Hardware Reference

1 INTRODUCTION

The ADSP-21367/8/9 and ADSP-21371/75 SHARC processors are high
performance 32-bit processors used for high quality audio, medical imag­ing, communications, military, test equipment, 3D graphics, speech
recognition, motor control, imaging, and other applications. By adding
on-chip SRAM, integrated I/O peripherals, and an additional processing
element for single-instruction, multiple-data (SIMD) support, this proces­sor builds on the ADSP-21000 family DSP core to form a complete
system-on-a-chip.

Design Advantages

A digital signal processor’s data format determines its ability to handle sig­nals of differing precision, dynamic range, and signal-to-noise ratios.
Because floating-point DSP math reduces the need for scaling and the
probability of overflow, using a floating-point processor can simplify algo­rithm and software development. The extent to which this is true depends
on the floating-point processor’s architecture. Consistency with IEEE
workstation simulations and the elimination of scaling are clearly two
ease-of-use advantages. High level language programmability, large
address spaces, and wide dynamic range allow system development time to
be spent on algorithms and signal processing concerns, rather than assem­bly language coding, code paging, and/or error handling. The SHARC
processors are highly integrated, 32-bit floating-point processor which
provides all of these design advantages.

ADSP-2137x SHARC Processor Hardware Reference 1-1

Design Advantages

SHARC Family Product Offerings

Table 1-1 provides information on the products covered in this manual.

Note that some models are available for automotive applications with con­trolled manufacturing. These special models may have specifications that
differ from the general release models. For information on which models
are available as automotive, see the product specific data sheet.

Table 1-1. SHARC Processor Family Features

Feature

RAM 2M bit 1M bit 0.5M bit

ROM 6M bit 4M bit 2M bit

Audio Decoders

in ROM

Serial Ports 8 4

UART 2 1

Pulse Width
Modulation

S/PDIF Yes No

Shared Memory No Yes No

SRC
Per formance

Package Option

Processor Speed 400 MHz 266 MHz

1 The ADSP-21367 processor includes a customer-definable ROM block. Please contact your Analog Devic-

2 Audio decoding algorithms include PCM, Dolby Digital EX, PCM, Dolby Digital EX, Dolby Prologic IIx,

3 Analog Devices offers these packages in RoHS compliant versions.

2

es sales representative for additional details.

DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MPEG2 2channel, MP3, and functions like bass management,
delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combina­tion support will vary depending upon the chip version and the system configurations. Please visit

www.analog.com/sharc for complete information.

ADSP-21367

128 db 140 dB 128 dB No SRC No SRC

3

256-ball BGA
208-lead LQFP,
exposed pad

1

ADSP-21368 ADSP-21369 ADSP-21371 ADSP-21375

Yes No

Yes No

256-ball BGA 256-ball BGA

208-lead LQFP,
exposed pad

208-lead LQFP, exposed pad

1-2 ADSP-2137x SHARC Processor Hardware Reference

Introduction

Processor Architectural Overview

The ADSP-21367/8/9 and ADSP-2137x processors form a complete sys­tem-on-a-chip, integrating a large, high speed SRAM and I/O peripherals
supported by a dedicated I/O bus. The following sections summarize the
features of each functional block in the processor architecture.

Processor Core

The processor core contains two processing elements (each with three
computation units and data register file), a program sequencer, two data
address generators, a timer, and an instruction cache. All digital signal
processing occurs in the processor core. For complete information, see the
SHARC Processor Programming Reference.

I/O Peripherals

These peripherals are coupled with the external port and therefore inde­pendent from the routing units.

• Asynchronous Memory Interface (AMI)

• SDRAM controller

• Shared Memory controller (ADSP-21368 only)

• 4 PWM modules

I/O Processor

The input/output processor (IOP) manages the off-chip data I/O to free
the core from this burden. Up to thirty-four channels of DMA are avail­able on the ADSP-21367/8/9 and ADSP-2137x processors—sixteen via
the serial ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI
interface, 2 for the external port, and 2 for memory-to-memory transfers.

ADSP-2137x SHARC Processor Hardware Reference 1-3

Processor Architectural Overview

The I/O processor can perform DMA transfers between the peripherals
and internal memory at the full core clock speed. The architecture of the
internal memory allows the IOP and the core to access internal memory
simultaneously with no reduction in throughput.

Digital Audio Interface (DAI)

The digital audio interface (DAI) unit consists of an interrupt controller, a
signal routing unit, and many peripherals:

• 8 or 4 serial ports (SPORT)

• Input Data Port (IDP)

• Four precision clock generators (PCG)

• Some family members have an S/PDIF receiver/transmitter

• Four asynchronous sample rate converters (ASRC)

• DTCP encryption

Interrupt Controller

The DAI contains its own interrupt controller that indicates to the core
when DAI audio events have occurred. This interrupt controller offer 32
independently configurable channels.

Signal Routing Unit

Conceptually similar to a “patch-bay” or multiplexer, the SRU provides a
group of registers that define the interconnection of the DAI peripherals
to the DAI pins or to other DAI peripherals.

1-4 ADSP-2137x SHARC Processor Hardware Reference

Introduction

Digital Peripheral Interface (DPI)

The digital audio interface (DPI) unit consists of an interrupt controller, a
signal routing unit, and many peripherals:

• 2 serial peripheral interface ports (SPI)

• 2 peripheral timers

• 1 or 2 UARTs

• 1 TWI controller (I

Interrupt Controller

The DPI contains its own interrupt controller that indicates to the core
when DPI audio events have occurred. This interrupt controller offer 12
independently configurable channels.

Signal Routing Unit 2

Conceptually similar to a “patch-bay” or multiplexer, the SRU2 provides a
group of registers that define the interconnection of the DPI peripherals
to the DPI pins or to other DPI peripherals.

2

C compatible)

Development Tools

The processors are supported by VisualDSP++, an easy to use Integrated
Development and Debugging Environment (IDDE). VisualDSP++ allows
you to manage projects from start to finish from within a single, inte­grated interface. Because the project development and debug
environments are integrated, you can move easily between editing, build­ing, and debugging activities.

ADSP-2137x SHARC Processor Hardware Reference 1-5

Differences from Previous Processors

Differences from Previous Processors

This section identifies differences between the ADSP-21367/8/9 and
ADSP-2137x processors and previous SHARC processors: ADSP-21161,
ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and
ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC
processor family is based on the original ADSP-2106x SHARC family.
The ADSP-21367/8/9 and ADSP-2137x processors preserve much of the
ADSP-2106x architecture and is code compatible to the ADSP-21160,
while extending performance and functionality. For background
information on SHARC processors and the ADSP-2106x family DSPs, see
the ADSP-2106x SHARC User’s Manual or the ADSP-21065L SHARC
DSP Technical Reference.

I/O Architecture Enhancements

The I/O processor provides much greater throughput than the
ADSP-2106x processors. This architecture incorporates two independent
DMA buses versus the previous SHARC DMA controllers:

• one peripheral DMA bus (IOD0)

• one external port DMA bus (IOD1)

This allows to operate all external port DMA accesses independently from
the peripheral busses since up to four internal memory blocks are address­able without any bus conflicts.

1-6 ADSP-2137x SHARC Processor Hardware Reference

2 I/O PROCESSOR

In applications that use extensive off-chip data I/O, programs may find it
beneficial to use a processor resource other than the processor core to per­form data transfers. The SHARC contains an I/O processor (IOP) that
supports a variety of DMA (direct memory access) operations. Each DMA
operation transfers an entire block of data. The I/O processor specifica­tions are shown in Table 2-1.

Table 2-1. I/O Processor Specifications

Feature Availability

Total DMA channels 34

Rotating DMA channel priority Yes

SPORT DMA channels 16

IDP DMA channel 8

UART DMA channel 4

SPI DMA channel 2

MTM/DTCP DMA channel 2

External Port DMA channel 2

PDAP DMA channel 1

DMA channel interrupts 16

Clock Operation Peripheral clock (PCLK)

ADSP-2137x SHARC Processor Hardware Reference 2-1

Features

Features

I/O processor features are briefly described in the following list.

• Internal memory ↔ SPORT (DAI)

• Internal memory ← IDP (DAI) unidirectional

• Internal memory ↔ SPI

• Internal memory ↔ UART

• Internal memory ↔ External memory (External port)

• Internal memory ↔ Internal memory (MTM, External port)

By managing DMA, the I/O processor frees the processor core, allowing it
to perform other operations while off-chip data I/O occurs as a back­ground task. The multi-bank architecture of the processor’s internal
memory allows the core and IOP to simultaneously access the internal
memory if the accesses are to different memory banks. This means that
DMA transfers to internal memory do not impact core performance. The
processor core continues to perform computations without penalty.

To further increase off-chip I/O, multiple DMAs can occur at the same
time. The IOP accomplishes this by managing multiple DMAs of proces­sor memory through the different peripherals. Each DMA is referred to as
a channel and each channel is configured independently.

Register Overview

Two global IOP registers control the DMA arbitration over the I/O
buses—the first for the peripheral bus and the second for the external port
bus. This section provides brief descriptions of the major IOP registers.
For complete information, see “System Control Register (SYSCTL)” on

page A-4 and “External Port Registers” on page A-11.

2-2 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

System control register (SYSCTL). Controls the peripheral DMA opera­tion for fixed or rotating DMA channel arbitration.

External port control register (EPCTL). Controls the external port DMA
operation for fixed or rotating DMA channel arbitration and between the
core and DMA.

DMA Channel Registers

The following sections provide information on the registers that control
all DMA operations for each peripheral. Additional information on DMA
operations can be found in specific peripheral chapters. Note that all
DMA parameter registers are read-write (RW). For details of the DMA
related registers, see “Register Listing” on page A-181.

DMA Channel Allocation

Each DMA channel has a set of parameter registers which are used to set
up DMA transfers. Table 2-21 on page 2-29 shows the DMA channel
allocation and parameter register assignments for the ADSP-2136x and
ADSP-2137x processors.



DMA channels vary by processor model. For a breakdown of DMA
channels for a particular model, see the appropriate product data
sheet. Also note that each DMA channel has a specific peripheral
assigned to it.

Standard DMA Parameter Registers

The parameter registers described below control the source and destina­tion of the data, the size of the data buffer, and the step size used.

Index registers. Shown in Table 2-2, provide an internal memory address,
acting as a pointer to the next internal memory DMA read or write

ADSP-2137x SHARC Processor Hardware Reference 2-3

DMA Channel Registers

location. All internal index addresses are based on an internal memory off­set of 0x80000.

Table 2-2. Index Registers

Register Name Width (Bits) Description

IISP0-7A 19 SPORTA

IISP0-7B 19 SPORTB

IISPI 19 SPI

IISPIB 19 SPIB

IDP_DMA_I0-7 19 IDP

IDP_DMA_I0-7A 19 IDP index A (ping pong)

IDP_DMA_I0-7B 19 IDP index B (ping pong)

IIUART0RX 19 UART0 Receiver

IIUART1RX 19 UART1 Receiver

IIUART0TX 19 UART0 Transmitter

IIUART1TX 19 UART1 Transmitter

IIMTMW 19 MTM Write

IIMTMR 19 MTM Read

IIEP0-1 19 External Port

EIEP0-1 28 External Port (external)

Modify registers. Shown in Table 2-3, provide the signed increment by
which the DMA controller post-modifies the corresponding memory
index register after the DMA read or write.

Table 2-3. Modify Registers

Register Name Width (Bits) Description

IMSP0-7A 16 SPORTA

IMSP0-7B 16 SPORTB

2-4 ADSP-2137x SHARC Processor Hardware Reference

Table 2-3. Modify Registers (Cont’d)

Register Name Width (Bits) Description

IMSPI 16 SPI

IMSPIB 16 SPIB

IDP_DMA_M0-7 6 IDP

IDP_DMA_M0-7A 6 IDP modify A (ping pong)

IDP_DMA_M0-7B 6 IDP modify B (ping pong)

IMUART0RX 16 UART0 Receiver

IMUART1RX 16 UART1 Receiver

IMUART0TX 16 UART0 Transmitter

IMUART1TX 16 UART1 Transmitter

IMMTMW 16 MTM Write

IMMTMR 16 MTM Read

IMEP0-1 16 External Port

EMEP0-1 27 External Port (external)

I/O Processor

Count registers. Shown in Table 2-4, indicate the number of words
remaining to be transferred to or from memory on the corresponding
DMA channel.

Table 2-4. Count Registers

Register Name Width (Bits) Description

ICSP0-7A 16 SPORTA

ICSP0-7B 16 SPORTB

ICSPI 16 SPI

ICSPIB 16 SPIB

IDP_DMA_C0–7 16 IDP

CUART0RX 16 UART0 Receiver

CUART1RX 16 UART1 Receiver

ADSP-2137x SHARC Processor Hardware Reference 2-5

DMA Channel Registers

Table 2-4. Count Registers (Cont’d)

Register Name Width (Bits) Description

CUART0TX 16 UART0 Transmitter

CUART1TX 16 UART1 Transmitter

ICMTMW 16 MTM Write

ICMTMR 16 MTM Read

ICEP0-1 16 External Port

ECEP0-1 16 External Port (external)

Chain pointer registers. Shown in Table 2-5, chain pointer registers hold
the starting address of the TCB (parameter register values) for the next
DMA operation on the corresponding channel. These registers also con­trol whether the I/O processor generates an interrupt when the current
DMA process ends.

Table 2-5. Chain Pointer Registers

Register Name Width (Bits) Description

CPSP0-7A 29 SPORTA

CPSP0-7B 29 SPORTB

CPSPI 20 SPI

CPSPIB 20 SPIB

CPUART0RX 20 UART0 Receiver

CPUART1RX 20 UART1 Receiver

CPUART0TX 20 UART0 Transmitter

CPUART1TX 20 UART1 Transmitter

CPEP0-1 21 External Port

2-6 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

Extended DMA Parameter Registers

This section describes the enhanced parameter registers used for the exter­nal port.

Base registers. Shown in Table 2-6, base registers indicate the start
address of the circular buffer to be transferred to/from memory on the cor­responding DMA channel.

Table 2-6. Base Registers

Register Name Width (Bits) Description

EBEP0–1 28 External Port (external base)

Length registers. Shown in Table 2-7, define the length of the circular
buffer to be transferred to/from memory on the corresponding DMA
channel.

Table 2-7. Length Registers

Register Name Width (Bits) Description

ELEP0–1 26 External Port (external length)

Miscellaneous External Port Parameter registers. Shown in Table 2-8,
these registers are used for the delay line and scatter/gather DMA to read
from tap list buffers, store counters and index pointers.

Table 2-8. Miscellaneous External Port Parameter Registers

Register Name Width (Bits) Description

RCEP 16 Delay line DMA read block size

REIP 19 Delay line DMA read internal index

RMEP 27 Delay line DMA read external modifier

ADSP-2137x SHARC Processor Hardware Reference 2-7

DMA Channel Registers

Table 2-8. Miscellaneous External Port Parameter Registers (Cont’d)

Register Name Width (Bits) Description

TCEP 16 Delay line DMA tap list count

TPEP 19 Delay line DMA tap list pointer

Data Buffers

The data buffers or FIFOs (shown in Table 2-9) are used by each DMA
channel to store data during the priority arbitration time period. The buf­fers (depending on the peripheral) are accessed by both DMA and the
core. Note that all transmit buffers are write-only-to-clear (WOC) and all
receive buffers are read-only-to-clear (ROC) bit types.

Table 2-9. Data Buffers

Buffer Name FIFO Depth Description

TXSP0–7A 2 SPORTA Transmit

TXSP0–7B 2 SPORTB Transmit

RXSP0–7A 2 SPORTA Receive

RXSP0–7B 2 SPORTB Receive

TXSPI 2 SPI Transmit

TXSPIB 2 SPIB Transmit

RXSPI 2 SPI Receive

RXSPIB 2 SPIB Receive

RXSPI_SHADOW 2 SPI Receive Shadow (RO)

RXSPIB_SHADOW 2 SPIB Receive Shadow (RO)

SPI DMA 4 DMA only

SPIB DMA 4 DMA only

IDP_FIFO 8 IDP FIFO Receive

UARTRBR0 1 UART0 Receiver

2-8 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

Table 2-9. Data Buffers (Cont’d)

Buffer Name FIFO Depth Description

UARTRBR1 1 UART1 Receiver

UARTTHR0 1 UART0 Transmitter

UARTTHR1 1 UART1 Transmitter

MTM read/write 2 DMA only

DFEP0–1 6 DMA only

TPEP0–1 4 Delay Line DMA (ADSP-2136x only)

AMIRX 1 AMI Receive Packer

AMITX 1 AMI Transmit Packer

TXTWI8 1 (1 byte) TWI Transmit

TXTWI16 1 (2 bytes) TWI Transmit

RXTWI8 1 (1 byte) TWI Receive

RXTWI16 1 (2 bytes) TWI Receiver

Chain Pointer Registers

The chain pointer registers, described in Table 2-10 (generic) and

Table 2-11 (external port) are 20 bits wide. The lower 19 bits are the

memory address field. Like other I/O processor address registers, the chain
pointer register’s value is offset to match the starting address of the proces­sor’s internal memory before it is used by the I/O processor. On the
SHARC processor, this offset value is 0x80000.



ADSP-2137x SHARC Processor Hardware Reference 2-9

The example chain pointer register shown in Table 2-10 is valid for
all peripherals unless otherwise noted.

DMA Channel Registers

Table 2-10. Generic Chain Pointer Register (CPx)

Bit Name Description

18–0 IIx address Next chain pointer address

19 PCI Program controlled interrupt

0 = interrupt after end of entire chain
1 = interrupt after current TCB

Table 2-11. External Port Chain Pointer Register (EPCPx)

Bit Name Description

18–0 IIx address Next chain pointer address

19 PCI Program controlled interrupt

0 = interrupt after end of entire chain
1 = interrupt after current TCB

20 CPDR DMA direction for next TCB

0 = write to internal memory
1 = read from internal memory
(ADSP-2137x only)

Bit 19 of the chain pointer register is the program controlled interrupt
(

PCI) bit. This bit controls whether an interrupt is latched after every

DMA in the chain (when set = 1), or whether the interrupt is latched after
the entire DMA sequence completes (if cleared = 0).

The PCI bit only effects DMA channels that have chaining enabled.



Also, interrupt requests enabled by the PCI bit are maskable with
the

IMASK register.

2-10 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

TCB Storage

This section lists all the different TCB memory allocations used for DMA
chaining on the peripherals. Note that all TCBs must be located in inter­nal memory.

Serial Port TCB

The serial ports support single and chained DMA. Table 2-12 shows the
required TCBs for chained DMA. Note that when using the serial ports,
programs can insert a TCB in an active chain.

Table 2-12. SPORT TCBs

Address Register

CP[18:0] CPSPx Chain Pointer

CP[18:0] + 0x1 ICSPx Internal Count

CP[18:0] + 0x2 IMSPx Internal Modifier

CP[18:0] + 0x3 IISPx Internal Index

SPI TCB

Table 2-13 shows the required TCBs for a SPI chained DMA.

Table 2-13. SPI/SPIB TCBs

Address Register

CP[18:0] CPSPI/B Chain Pointer

CP[18:0] + 0x1 ICSPI/B Internal Count

CP[18:0] + 0x2 IMSPI/B Internal Modifier

CP[18:0] + 0x3 IISPI/B Internal Index

ADSP-2137x SHARC Processor Hardware Reference 2-11

TCB Storage

UART TCB

Table 2-14 shows the required TCBs for chained UART DMA.

Table 2-14. UART1–0 TCBs

Address Register

CP[18:0] CPUARTxRX/CPUARTxTX Chain Pointer

CP[18:0] + 0x1 ICUARTxRX/ICUARTxTX Internal Count

CP[18:0] + 0x2 IMUARTxRX/IMUARTxTX Internal Modifier

CP[18:0] + 0x3 IIUARTxRX/IIUARTxTX Internal Index

External Port TCB

The external port interface supports many different types of DMA, result­ing in different lengths of TCBs. The TCB size varies from six locations
(chained DMA) to 10 locations (circular scatter/gather DMA). Table 2-15
shows the required TCBs for chained DMA. Note this TCB is also valid
for the ADSP-21367/8/9 processors in circular buffering mode (the EBEP
and ELEP registers are not part of the TCB).

Table 2-15. External Port TCBs for Standard DMA

Address Register

CP[18:0] CPEP

CP[18:0] + 0x1 EMEP

CP[18:0] + 0x2 EIEP

CP[18:0] + 0x3 ICEP

CP[18:0] + 0x4 IMEP

CP[18:0] + 0x5 IIEP

2-12 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

The order the descriptors are fetched with circular buffering enabled is
shown in Table 2-15.

Table 2-16. External Port TCBs for Circular DMA (ADSP-2137x Only)

Address Register

CP[18:0] CPEP

CP[18:0] + 0x1 ELEP

CP[18:0] + 0x2 EBEP

CP[18:0] + 0x3 EMEP

CP[18:0] + 0x4 EIEP

CP[18:0] + 0x5 ICEP

CP[18:0] + 0x6 IMEP

CP[18:0] + 0x7 IIEP

For delay line DMA, TCB loading is split into two sequences to improve
overall priority. The first TCB loads the write parameters (

IIEP–ELEP) and

the second loads the read parameters (RIEP–CPEP). This two stage loading
is transparent to the application. The order the descriptors are fetched
with circular buffering enabled is shown in Table 2-17.

Table 2-17. External Port TCBs for Delay Line DMA

Address Register

Delay Line Read

CP[18:0] CPEP

CP[18:0] + 0x1 TPEP

CP[18:0] + 0x2 TCEP

CP[18:0] + 0x3 RMEP

CP[18:0] + 0x4 RCEP

CP[18:0] + 0x5 RIEP

ADSP-2137x SHARC Processor Hardware Reference 2-13

TCB Storage

Table 2-17. External Port TCBs for Delay Line DMA (Cont’d)

Address Register

Delay Line Write

CP[18:0] + 0x6 ELEP

CP[18:0] + 0x7 EBEP

CP[18:0] + 0x8 EMEP

CP[18:0] + 0x9 EIEP

CP[18:0] + 0xA ICEP

CP[18:0] + 0xB IMEP

CP[18:0] + 0xC IIEP

The order the descriptors are fetched for scatter/gather DMA with circular
buffering enabled is shown in Table 2-18 and Table 2-19.

Table 2-18. External Port TCBs for Scatter/Gather DMA

Address Register

CP[18:0] CPEP

CP[18:0] + 0x1 TPEP

CP[18:0] + 0x2 TCEP

CP[18:0] + 0x3 EMEP

CP[18:0] + 0x4 EIEP

CP[18:0] + 0x5 ICEP

CP[18:0] + 0x6 IMEP

CP[18:0] + 0x7 IIEP

2-14 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

Table 2-19. External Port TCBs for Circular Scatter/Gather DMA

Address Register

CP[18:0] CPEP

CP[18:0] + 0x1 ELEP

CP[18:0] + 0x2 EBEP

CP[18:0] + 0x3 TPEP

CP[18:0] + 0x4 TCEP

CP[18:0] + 0x5 EMEP

CP[18:0] + 0x6 EIEP

CP[18:0] + 0x7 ICEP

CP[18:0] + 0x8 IMEP

CP[18:0] + 0x9 IIEP

Clocking

The fundamental timing clock of the IOP is peripheral clock (PCLK). All
DMA data transfers over the IO0 or IO1 buses are clocked at PCLK speed.

Functional Description

The following several sections provide detail on the function of the I/O
processor.

Automated Data Transfer

Because the IOP registers are memory-mapped, the processors have access
to program DMA operations. A program sets up a DMA channel by writ­ing the transfer's parameters to the DMA parameter registers. After the
index, modify, and count registers (among others) are loaded with a start-

ADSP-2137x SHARC Processor Hardware Reference 2-15

Functional Description

ing source or destination address, an address modifier, and a word count,
the processor is ready to start the DMA.

The peripherals each have a DMA enable (

xDEN) bits in their channel con-

trol registers. Setting this bit for a DMA channel with configured DMA
parameters starts the DMA on that channel. If the parameters configure
the channel to receive, the I/O processor transfers data words received at
the buffer to the destination in internal memory. If the parameters config­ure the channel to transmit, the I/O processor transfers a word
automatically from the source memory to the channel's buffer register.
These transfers continue until the I/O processor transfers the selected
number of words as determined by the count parameter. DMA through
the IDP ports occurs in internal memory only.

DMA Transfer Types

Standard DMA. A standard DMA (once it is configured) transfers data
from location A to location B. An interrupt can be used to indicate the
end of the transfer. To start a new DMA sequence after the current one is
finished, a program must first clear the DMA enable bit (control register),
write new parameters to the index, modify, and count registers (parameter
registers), then set the DMA enable bit to re-enable DMA (control
register).

An instance where standard DMA can be used is to copy data from a
peripheral to internal memory for processor booting. With the help of the
loader tool, the tag (header information) of the boot stream is decoded to
get the storage information which includes the index, modify, and count
of a specific array to start another standard DMA.

Chained DMA. Chained DMA sequences are a set of multiple DMA
operations, each autoinitializing the next in line. To start a new DMA
sequence after the current one is finished, the IOP automatically loads
new index, modify, and count values from an internal memory location
(or external memory location for DMA to external ports) pointed to by

2-16 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

that channel’s chain pointer register. Using chaining, programs can set up
consecutive DMA operations and each operation can have different
attributes.

Chained DMA with direction on the fly (External Port). The external
port DMA controller supports chained DMA sequences with the an addi­tional feature that allows the port to change the data direction for each
individual TCB. An additional bit in the TCB differentiates between a
read or write operation.



The IDP port does not support DMA chaining.

Ping-pong DMA (IDP). In ping-pong DMA, the parameters have two
memory index values (index A and index B), one count value and one
modifier value. The DMA starts the transfer with the memory indexed by
A. When the transfer is completed as per the value in the count register,
the DMA restarts with the memory location indexed by B. The DMA
restarts with index A after the transfer to memory with index B is com­pleted as per the count value. This repeats until the DMA is stopped by
resetting the DMA enable bit.

Circular Buffering DMA (External Port). This mode resembles the
chained DMA mode, however two additional registers (base and length)
are used. This mode performs DMA within the circular buffer, which is
useful for filter implementation since core interaction is limited, conserv-

ing bandwidth.

DMA Direction

The IOP supports DMA in three directions. These are described in the
following sections.

Internal to External Memory

DMA transfers between internal memory and external memory devices use
the processor’s external port. For these types of transfers, the application

ADSP-2137x SHARC Processor Hardware Reference 2-17

Functional Description

code provides the DMA controller with the internal memory buffer size,
address, and address modifier, as well as the external memory buffer size,
address, address modifier, and the direction of transfer. After setup, the
DMA transfers begin when the program enables the channel and contin­ues until the I/O processor transfers the entire buffer to processor
memory. Table 2-21 on page 2-29 shows the parameter registers for each
DMA channel.

Peripheral to Internal Memory

Similarly, DMA transfers between internal memory and serial, IDP, or
SPI ports have DMA parameters. When the I/O processor performs DMA
between internal memory and one of these ports, the program sets up the
parameters, and the I/O uses the port instead of the external bus.

The direction (receive or transmit) of the peripheral determines the direc­tion of data transfer. When the port receives data, the I/O processor
automatically transfers the data to internal memory. When the port needs
to transmit a word, the I/O processor automatically fetches the data from
internal memory. Figure 2-1 on page 2-19 shows more detail on DMA
channel data paths.

Internal Memory to Internal Memory

The ADSP-2136x and ADSP-2137x processors can use memory-to-mem­ory DMA to transfer 64-bit blocks of data between internal memory
locations.

DMA Controller Addressing

Figure 2-1 shows a block diagram of the I/O processor’s address generator

(DMA controller). “Standard DMA Parameter Registers” on page 2-3 lists
the parameter registers for each DMA channel. The parameter registers are
uninitialized following a processor reset.

2-18 ADSP-2137x SHARC Processor Hardware Reference

LOCAL BUS

MODIFI ER

INTERNAL

MEMORY

ADDRESS

DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)

LOCAL BUS

COUNT

CHAIN POINTER

MUX

DMA WORD COUNTER

–1

WORKING REGISTER

INDEX (ADDRESS)

+/-

POST-MODIFY

+

LOCAL BUS

EXTERNAL

MODIFIER

EXTERNAL

COUNT

–1

EXTERNAL

MEMORY

ADDRESS

POST-MODIF Y

EXTERNAL

INDEX (ADDRESS)

DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)

+

+

I/O Processor

Figure 2-1. DMA Address Generator

The I/O processor generates addresses for DMA channels much the same
way that the Data Address Generators (DAGs) generate addresses for data
memory accesses. Each channel has a set of parameter registers including
an index register and modify register that the I/O processor uses to address

ADSP-2137x SHARC Processor Hardware Reference 2-19

Functional Description

a data buffer in internal memory. The index register must be initialized
with a starting address for the data buffer. As part of the DMA operation,
the I/O processor outputs the address in the index register onto the pro­cessor’s I/O address bus and applies the address to internal memory
during each DMA cycle—a clock cycle in which a DMA transfer is taking
place.

Internal Index Register Addressing

All addresses in the index registers are offset by a value matching the pro­cessor’s first internal normal word addressed RAM location, before the
I/O processor uses the addresses. For the products in this manual, this off­set value is 0x0008 0000.

The following rules for data transfers must be followed.

• DMA index addresses must always be normal word space (32-bit).

• DMA Data packing can only happen in the associated peripheral,
for example external port booting, the AMI does 8 to 32-bit pack­ing via the external port DMA channel 0.



After transferring each data word to or from internal memory, the I/O
processor adds the modify value to the index register to generate the
address for the next DMA transfer and writes the modified index value to
the index register. The modify value in the modify register is a signed inte­ger, which allows both increment and decrement modifies. The modify
value can have any positive or negative integer value. Note that:

2-20 ADSP-2137x SHARC Processor Hardware Reference

The DMA controller only supports index addresses in the normal
word space (32-bit).

• If the I/O processor modifies the internal index register past the
maximum 19-bit value to indicate an address out of internal mem­ory, the index wraps around to zero. With the offset for the
SHARC processor, the wraparound address is 0x80000.

I/O Processor

• If a DMA channel is disabled, the I/O processor does not service
requests for that channel, whether or not the channel has data to
transfer.



External Index Register Addressing

The external port DMA channels each contain additional parameter regis­ters: the external index registers (EIEPx), external modify registers (EMEPx),
and external count registers (ECEPx). The DMA controller generates 28-bit
external memory addresses over the IOD1 bus using the EIEPx register
during DMA transfers between internal memory and external memory.

If a program loads the count register with zero, the I/O processor
does not disable DMA transfers on that channel. The I/O proces­sor interprets the zero as a request for 216 transfers. This count
occurs because the I/O processor starts the first transfer before test­ing the count value. The only way to disable a DMA channel is to
clear its DMA enable bit.

DMA Channel Status

There are two methods the processor uses to monitor the progress of
DMA operations; interrupts, which are the primary method, and status
polling. The same program can use either method for each DMA channel.

Programs can check the appropriate DMA status bits (for example the sta­tus bits in the
channels are performing a DMA or chained DMA. All DMA channels can
be active or inactive. If a channel is active, a DMA is in progress on that
channel. The I/O processor indicates the active status by setting the chan­nel’s bit in the status register.

SPMCTL register for the serial ports) to determine which



ADSP-2137x SHARC Processor Hardware Reference 2-21

Note that there is 1 PCLK cycle latency between a change in DMA
channel status and the status update in the corresponding register.

Functional Description

The peripheral’s DMA controller tracks status information of the channels
in each of the peripheral registers (for example

DAI_STAT, DMACx, and MTMCTL).

SPMCTLx, SPIDMACx,

• DMA channel status (status bit is set until the DMA terminates)

• TCB chain loading status (status bit is set until TCB loading
completes)

If polling the status of a chained DMA, the DMA status bit is first set
when the TCB has terminated, then it is cleared. The TCB status loading
bit is set until the load is finished and cleared on load completion. This
procedure is repeated for all subsequent DMA blocks.

Note that polling the DMA status registers (especially chained DMA)
reduces I/O bandwidth.

DMA Start and Stop Conditions

The difference between single DMA and chained DMA is based on the
auto-linkage process where the DMA’s attributes are stored in internal
memory and automatically loaded by the IOP if requested.

A DMA sequence starts when one of the following occurs.

• Chaining is disabled, and the DMA enable bit transitions from low
to high.

• Chaining is enabled, DMA is enabled, and the chain pointer regis­ter address field is written with a non zero value. In this case, TCB
chain loading of the channel parameter registers occurs first.

• Chaining is enabled, the chain pointer register address field is non­zero, and the current DMA sequence finishes. Again, TCB chain
loading occurs.

2-22 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

A DMA sequence ends when one of the following occurs.

• The count register decrements to zero, and the chain pointer regis­ter is zero.

• Chaining is disabled and the channel’s DMA enable bit transitions
from high to low. If the DMA enable bit goes low (=0) and chain­ing is enabled, the channel enters chain insertion mode (SPORT
only) and the DMA sequence continues.

Once a program starts a DMA process, the process is influenced by two
external controls; DMA channel priority and DMA chaining.

Operating Modes

This section provides information on IOP operating modes.

The SHARC processor contains two independent 32-bit DMA buses
(Figure 2-2). The IOD0 bus is used for the peripherals to the internal
memory and the IOD1 bus is used for external-to-internal memory
transfers.

The IOD0 bus is the path that the IOP uses to transfer data between
internal memory and the peripherals. When there are two or more periph­erals with active DMAs in progress, they may all require data to be moved
to or from memory in the same cycle. For example, the SPI port may fill
its buffer just as a SPORT shifts a word into its buffer. To determine
which word is transferred first, the DMA channels for each of the
processor’s I/O ports negotiate channel priority with the I/O processor
using an internal DMA request/grant handshake.



ADSP-2137x SHARC Processor Hardware Reference 2-23

The IOD0 and IOD1 buses operate independently. However, in
some cases there may be address conflicts if both buses access the
same internal memory block. In this case, the IOD0 bus has first
priority.

Operating Modes

EXTERNAL

PORT ARBITER

DATA

MUX

PERIPHERAL

ARBITER

DATA

MUX

INTERNAL

MEMORY I/F

ARBITER

IOD1 BUS IOD0 BUS

...

SPORTxAMI SDRAM SPI

IDP

MTM

UART

PERIPHERAL DMA BUS

EXTERNAL PORT
DMA BUS

CORE BUS

CORE BUS

Figure 2-2. I/O Processor Bus Structure

Each I/O port has one or more DMA channels, and each channel has a
single request and a single grant. When a particular channel needs to read
or write data to internal memory, the channel asserts an internal DMA
request. The I/O processor prioritizes the request with all other valid
DMA requests. When a channel becomes the highest priority requester,
the I/O processor asserts the channel’s internal DMA grant. In the next
clock cycle, the DMA transfer starts. Table 2-21 on page 2-29 shows the
paths for internal DMA requests within the I/O processor.

DMA Chaining

In the SHARC processors, DMA data transfers can be set up as continu­ous or periodic. Furthermore, these DMA transfers can be configured to

2-24 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

run automatically using chained DMA. With chained DMA, the attri­butes of a specific DMA are stored in internal memory and are referred to
as a Transfer Control Block or TCB. The DMA controller loads these attri­butes in chains for execution. This allows for multiple chains that are an
finite or infinite.



TCB Memory Storage

The location of the DMA parameters for the next sequence comes from
the chain pointer register that points to the next set of DMA parameters
stored in the processor’s internal memory. In chained DMA operations,
the processor automatically initializes and then begins another DMA
transfer when the current DMA transfer is complete. Each new set of
parameters is stored in a user-initialized memory buffer or TCB for a cho­sen peripheral. Table 2-20 provides a brief description of the TCBs.

Table 2-20. Principal TCB Allocation for a Serial Peripheral

Address Register Description

CPx Chain pointer register Chain pointer for DMA chaining

CPx + 0x1 (ICx) Internal count register Length of internal buffer

CPx + 0x2 (IMx) Internal modify register Stride for internal buffer

CPx + 0x3 (IIx) Internal index register Internal memory buffer

If chaining is enabled on a DMA channel, programs should not use
polling to determine channel status as this gives inaccurate infor­mation where the DMA appears inactive if it is sampled while the
next TCB is loading.



ADSP-2137x SHARC Processor Hardware Reference 2-25

The size of TCB varies and is based on the peripheral to be used:
the SPORTs and SPI require four locations, the external port
requires six to 13 locations. Allowing different TCB sizes reduces
the memory load since only the required TCBs are allocated in
internal memory.

Operating Modes

CPx

IIx

IMx

Cx

CPx

IIx

IMx

Cx

TCB 1

TCB 2

If pointing to zero,
chain operation ends

Chain Assignment

The structure of a TCB is conceptually the same as that of a traditional
linked-list. Each TCB has several data values and a pointer to the next
TCB. Further, the chain pointer of a TCB may point to itself to continu­ously re run the same DMA. The I/O processor reads each word of the
TCB and loads it into the corresponding register (see Listing 2-1).



address of the TCB (containing the index parameter). This means
that if a program declares an array to hold the TCB, the chain
pointer register should point to the last location of the array and
not to the first TCB location.

Programs must assign the TCB in memory in the order shown in

Figure 2-3, placing the index parameter at the address pointed to by the

chain pointer register of the previous DMA operation of the chain. The
end of the chain (no further TCBs are loaded) is indicated by a TCB with
a chain pointer register value of zero.

Figure 2-3. Chaining in the SPI and Serial Ports

The address in the chain pointer register points to the highest

The address field of the chain pointer registers is only 19 bits wide. If a
program writes a symbolic address to bit 19 of the chain pointer there may
be a conflict with the
address then AND the

PCI bit. Programs should clear the upper bits of the

PCI bit separately, if needed, as shown below.

Clear the chain pointer register before chaining is enabled.



2-26 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

Listing 2-1. Chain Assignment

Chain Assignment (according to Figure 2-3):
R0=0;

dm(CPx)=R0; /* clear CPx register */

/* init DMA control registers */

R2=(TCB1+3) & 0x7FFFF; /* load IIx address of next TCB
and mask address */
R2=bset R2 by 19; /* set PCI bit */
dm(TCB2)=R2; /* write address to CPx location of

current TCB */

R2=(TCB2+3) & 0x7FFFF; /* load IIx address of next TCB and

mask address*/

R2=bclr R2 by 19; /* clear PCI bit */

dm(TCB1)=R2; /* write address to CPx location of

current TCB */

dm(CPx)=R2; /* write IIx address of TCB1 to CPx

register to start chaining*/

Chained DMA operations may only occur within the same chan-



nel. The processor does not support cross-channel chaining.

Starting Chain Loading

A DMA sequence is defined as the sum of the DMA transfers for a single
channel, from when the parameter registers initialize to when the count
register decrements to zero. Each DMA channel has a chaining enable bit

CHEN) in the corresponding control register.

(

To start the chain, write the internal index address of the first TCB to the
chain pointer register. When chaining is enabled, DMA transfers are initi­ated by writing a memory address to the chain pointer register. This is also
an easy way to start a single DMA sequence, with no subsequent chained
DMAs.

ADSP-2137x SHARC Processor Hardware Reference 2-27

Operating Modes

During TCB chain loading, the I/O processor loads the DMA channel
parameter registers with values retrieved from internal memory.



The chain pointer register can be loaded at any time during the DMA
sequence. This allows a DMA channel to have chaining disabled (chain
pointer register address field = 0x0) until some event occurs that loads the
chain pointer register with a non zero value. Writing all zeros to the
address field of the chain pointer register also disables chaining.

TCB Chain Loading Priority

A TCB chain load request is prioritized like all DMA channels. Therefore,
the TCB chain loading request has the same priority level as the DMA
channel itself. The I/O processor latches a TCB loading request and holds
it until the load request has the highest priority. If multiple chaining
requests are present, the I/O processor services the TCB block for the
highest priority DMA channel first.



When starting chain loading, note that the SPI port is an exception
to the above. To execute the first DMA in a chain for this periph­eral, the DMA parameter registers also need to be explicitly
programmed. For more information, see “DMA Transfers” on

page 12-19.

A channel that is in the process of chain loading cannot be inter­rupted by any other request (TCB, DMA channel). The chain
loading sequence is atomic and the I/O bus is locked until all the
DMA parameter registers are loaded. For a list of DMA channels in
priority order, see Table 2-21.

Chain Insert Mode (SPORTs Only)

It is possible to insert a single SPORT DMA operation or another DMA
chain within an active SPORT DMA chain. Programs may need to per­form insertion when a high priority DMA requires service and cannot wait

2-28 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

for the current chain to finish. This is supported only for SPORT DMA
channels only. For more information, see Chapter 7, Serial Ports.

Fixed DMA Channel Arbitration

The shaded region in Table 2-21 (DMA channels 32 and 33) illustrates
that the priority shown is only valid if the IOD1 bus (external port DMA
channels) has a memory address block conflict with the IOD0 peripherals
bus. Otherwise, the IOD1 bus operates fully independently. Also note the
external port DMA channel changes priority, depending on the external
index addresses. If an external index address is assigned to an internal
index address, then the DMA channel priority will change.

Table 2-21. DMA Channel 0–33 Priorities

DMA
Channel
Number

IOD0 Peripheral Bus

0 (Highest
Priority

1 IISP1B, IMSP1B,

2 SPCTL0,

3 IISP0B, IMSP0B,

4BSPCTL3,

5 IISP3B, IMSP3B,

6 SPCTL2,

7 IISP2B, IMSP2B,

Peripheral
Group

A SPCTL1,

Control/Status
Registers

SPMCTL1

SPMCTL0

SPMCTL3

SPMCTL2

Parameter
Registers

IISP1A, IMSP1A,
CSP1A, CPSP1A

CSP1B, CPSP1B

IISP0A, IMSP0A,
CSP0A, CPSP0A

CSP0B, CPSP0B

IISP3A, IMSP3A,
CSP3A, CPSP3A

CSP3B, CPSP3B

IISP2A, IMSP2A,
CSP2A, CPSP2A

CSP2B, CPSP2B

Data Buffer Description

RXSP1A or
TXSP1A

RXSP1B or
TXSP1B

RXSP0A or
TXSP0A

RXSP0B or
TXSP0B

RXSP3A or
TXSP3A

RXSP3B or
TXSP3B

RXSP2A or
TXSP2A

RXSP2B or
TXSP2B

Serial Port 1A Data

Serial Port 1B Data

Serial Port 0A Data

Serial Port 0B Data

Serial Port 3A Data

Serial Port 3B Data

Serial Port 2A Data

Serial Port 2B Data

ADSP-2137x SHARC Processor Hardware Reference 2-29

Operating Modes

Table 2-21. DMA Channel 0–33 Priorities (Cont’d)

DMA
Channel
Number

8CSPCTL5,

9 IISP5B, IMSP5B,

10 SPCTL4,

11 IISP4B, IMSP4B,

12 D IDP_CTL0,

13 IDP_CTL0,

Peripheral
Group

Control/Status
Registers

SPMCTL5

SPMCTL4

IDP_CTL1,
IDP_PP_CTL,
DAI_STAT

IDP_CTL1,
DAI_STAT

Parameter
Registers

IISP5A, IMSP5A,
CSP5A, CPSP5A

CSP5B, CPSP5B

IISP4A, IMSP4A,
CSP4A, CPSP4A

CSP4B, CPSP4B

IDP_DMA_I0,
IDP_DMA_M0,
IDP_DMA_C0,
IDP_DMA_I0A,
IDP_DMA_I0B,
IDP_DMA_PC0

IDP_DMA_I1,
IDP_DMA_M1,
IDP_DMA_C1,
IDP_DMA_I1A,
IDP_DMA_I1B,
IDP_DMA_PC1

Data Buffer Description

RXSP5A or
TXSP5A

RXSP5B or
TXSP5B

RXSP4A or
TXSP4A

RXSP4B or
TXSP4B

IDP_FIFO DAI IDP or

Serial Port 5A Data

Serial Port 5B Data

Serial Port 4A Data

Serial Port 4B Data

PDAP
(only channel 0 sup­ports both

Serial Input DAI IDP
Channel 1

14 IDP_DMA_I2,

IDP_DMA_M2,
IDP_DMA_C2,
IDP_DMA_I2A,
IDP_DMA_I2B,
IDP_DMA_PC2

15 IDP_DMA_I3,

IDP_DMA_M3,
IDP_DMA_C3,
IDP_DMA_I3A,
IDP_DMA_I3B,
IDP_DMA_PC3

Serial Input DAI IDP
Channel 2

Serial Input DAI IDP
Channel 3

2-30 ADSP-2137x SHARC Processor Hardware Reference

Table 2-21. DMA Channel 0–33 Priorities (Cont’d)

I/O Processor

DMA
Channel
Number

16 D IDP_CTL0,

17 IDP_DMA_I5,

18 IDP_DMA_I6,

19 IDP_DMA_I7,

20 E SPICTL,

21 G SPICTLB,

Peripheral
Group

Control/Status
Registers

IDP_CTL1,
DAI_STAT

SPIDMAC,
SPIBAUD
SPISTAT

SPIDMACB,
SPIBAUDB,
SPISTATB

Parameter
Registers

IDP_DMA_I4,
IDP_DMA_M4,
IDP_DMA_C4,
IDP_DMA_I4A,
IDP_DMA_I4B,
IDP_DMA_PC4

IDP_DMA_M5,
IDP_DMA_C5,
IDP_DMA_I5A,
IDP_DMA_I5B,
IDP_DMA_PC5

IDP_DMA_M6,
IDP_DMA_C6,
IDP_DMA_I6A,
IDP_DMA_I6B,
IDP_DMA_PC6

IDP_DMA_M7,
IDP_DMA_C7,
IDP_DMA_I7A,
IDP_DMA_I7B,
IDP_DMA_PC7

IISPI, IMSPI,
CSPI, CPSPI

IISPIB, IMSPIB,
CSPIB, CPSPIB

Data Buffer Description

IDP_FIFO Serial Input DAI IDP

Channel 4

Serial Input DAI IDP
Channel 5

Serial Input DAI IDP
Channel 6

Serial Input DAI IDP
Channel 7

RXSPI or TXSPI
and DMA Buffer

RXSPIB or
TXSPIB and
DMA Buffer

SPI Data

SPI B Data

22 H MTMCTL (or

DTCP)

IIMTMW,
IMMTMW,
CMTMW

MTM FIFO Memory-to-

memory write data

ADSP-2137x SHARC Processor Hardware Reference 2-31

Operating Modes

Table 2-21. DMA Channel 0–33 Priorities (Cont’d)

DMA
Channel
Number

23 I MTMCTL (or

24 J UART0RXCTL,

25 J UART0TXCTL,

26 J UART1RXCTL,

27 J UART1TXCTL,

28 L SPCTL7,

29 L IISP7B, IMSP7B,

30 L SPCTL6,

31 L IISP6B, IMSP6B,

Peripheral
Group

Control/Status
Registers

DTCP)

UART0RXSTAT

UART0TXSTAT

UART1RXSTAT

UART1TXSTAT

SPMCTL7

SPMCTL6

Parameter
Registers

IIMTMR,
IMMTMR,
CMTMR

IIUART0RX,
IMUART0RX,
CUART0RX,
CPUART0RX,

IIUART0TX,
IMUART0TX,
CUART0TX,
CPUART0TX,

IIUART1RX,
IMUART1RX,
CUART1RX,
CPUART1RX,

IIUART1TX,
IMUART1TX,
CUART1TX,
CPUART1TX,

IISP7A, IMSP7A,
CSP7A, CPSP7A

CSP7B, CPSP7B

IISP6A, IMSP6A,
CSP6A, CPSP6A

CSP6B, CPSP6B

Data Buffer Description

MTM FIFO Memory-to-

memory read data

UART0RBR UART0 Receive Buffer

Register

UART0THR UART0 Transmit

Holding Register

UART1RBR UART1 Receive Buffer

Register

UART1THR UART1 Transmit

Holding Register

RXSP7A
or
TXSP7A

RXSP7B
or
TXSP7B

RXSP6A
or
TXSP6A

RXSP6B
or
TXSP6B

Serial Port 7A Data

Serial Port 7B Data

Serial Port 6A Data

Serial Port 6B Data

2-32 ADSP-2137x SHARC Processor Hardware Reference

Table 2-21. DMA Channel 0–33 Priorities (Cont’d)

I/O Processor

DMA
Channel
Number

IOD1 External Port Bus

32 Q DMAC0 IIEP0, IMEP0,

33 R DMAC1 IIEP1, IMEP1,

Peripheral
Group

Control/Status
Registers

Parameter
Registers

ICEP0,
EIEP0, EMEP0
ELEP0, EBEP0
RIEP0, RCEP0
RMEP0, TCEP0,
TPEP0, CPEP0

ICEP1,
EIEP1, EMEP1
ELEP1, EBEP1
RIEP1, RCEP1
RMEP1, TCEP1,
TPEP1, CPEP1

Peripheral DMA Bus

DMA-capable peripherals execute DMA data transfers to and from inter­nal memory over the IOD0 bus. When more than one of these peripherals
requests access to the IOD0 bus in a clock cycle, the bus arbiter, which is
attached to the IOD0 bus, determines which master should have access to
the bus and grants the bus to that master.

Data Buffer Description

DFEP0
and
AMIRX
AMITX
(AMI only)

DFEP1
and
AMIRX
AMITX
(AMI only)

External Port Memory
DMA 0

External Port Memory
DMA 1.
Note if the DMAC0
channel runs int-int
memory and DMAC1
channel int-ext mem­ory, then DMAC1 has
higher priority
(ADSP-2137x only).

IOP channel arbitration can be set to use either a fixed or rotating algo­rithm by setting or clearing RPBR bit in the SYSCTL register as follows.

• (=0) fixed arbitration (default)

• (=1) rotating arbitration

ADSP-2137x SHARC Processor Hardware Reference 2-33

Operating Modes

In the fixed priority scheme, the lower indexed peripheral has the highest
priority.

External Port DMA Bus

External port DMA channels transfer data between internal memories or
between internal and external memory over the IOD1 bus. When both
external port channels request access to the IOD1 bus in a clock cycle, the
external port bus arbiter, which is attached to the IOD1 bus, determines
which master should have access to the bus and grants the bus to that
master.

IOP/external port channel arbitration can be set to use either a fixed or
rotating algorithm by setting or clearing the

DMAPR bits in the EPCTL regis-

ter as follows.

• (=10) fixed arbitration channel 0

• (=11) rotating arbitration (default)

Note the independency is only broken if there is an internal memory
block conflict. In this case, if both rotating bits are set, the peripheral
DMA channels always have the highest priority and the DMAPR bit allows
the change in priority among the two external port DMA channels.

Rotating DMA Channel Arbitration

DMA channel arbitration is the method that the arbiter uses to determine
how groups rotate priority with other channels. The default DMA channel
priority is fixed prioritization by DMA channel group.

Rotating Priority by Group

In the rotating priority scheme, the default priorities at reset are the same
as that of the fixed priority. However, the peripheral priority is

2-34 ADSP-2137x SHARC Processor Hardware Reference

I/O Processor

determined by group, not individually by DMA channel. Peripheral
groups are shown in Table 2-21 on page 2-29.

Initially, group A has the highest priority and group I the lowest. As one
group completes its DMA operation, it is assigned the lowest priority
(moves to the back of the line) and the next group is given the highest
priority.

When none of the peripherals request bus access, the highest priority
peripheral, for example, peripheral 0, is granted the bus. However, this
does not change the currently assigned priorities to various peripherals.

Within a peripheral group, the priority is highest for the higher indexed
peripheral (see Table 2-21 on page 2-29). For example, of the SPORT
pair SP01 (which is in group A), SP1 has the highest priority.

Programs can change DMA arbitration modes between fixed and rotate on
the fly which incurs an effect latency of 2

PCLK cycles.

Interrupts

The primary type of DMA communication is interrupt driven I/O where
the core continues to execute instructions while DMA executes in the
background. This allows high levels of parallelism achieving over all better
system performance. Because the interrupt vector directs the core to
respond to specific transactions very efficiently, programs do not need to
poll status bits.

During interrupt-driven DMA, programs use the interrupt mask bits in
the IMASK, LIRPTL, DPI_IMASK, DAI_IMASK_x registers to selectively mask
DMA channel interrupts that the I/O processor latches into the

LIRPTL, DPI_IRPTL, DAI_IRPTL_x registers. A channel interrupt mask in the
IMASK, LIRPTL, DPI_IMASK, DAI_IMASK_x registers determines whether a

latched interrupt is serviced or not. When an interrupt is masked, it is
latched but not serviced.

ADSP-2137x SHARC Processor Hardware Reference 2-35

IRPTL,

Interrupts

Sources

The following sections describe the two sources of interrupts.

Unchained DMA Interrupts

When an unchained (single block) DMA process reaches completion (the
DMA count decrements to zero) on any DMA channel, the I/O processor
latches that DMA channel’s interrupt. It does this by setting the DMA
channel’s interrupt latch bit in the IRPTL, LIRPTL, DPI_IRPTL, or

DAI_IRPTLH_x registers.

Chained DMA Interrupts

For chained DMA, the channel generates interrupts in one of two ways:

1. If PCI = 1, (bit 19 of the chain pointer register is the program con­trolled interrupts, or PCI bit) an interrupt occurs for each DMA in
the chain.

2. If PCI = 0, an interrupt occurs at the end of a completed chain. For
more information on DMA chaining, see “Functional Description”

on page 2-15.

Figure 2-4 shows the PCI timing during TCB loading. After the DMA

count for the last word of frame N becomes zero, the PCI interrupt is
latched. At the same time the DMA reloads the TCB for that specific
channel (assuming no higher priority DMA requests). Finally the DMA
channel resumes operation for frame N–1.



2-36 ADSP-2137x SHARC Processor Hardware Reference

By clearing a channel’s PCI bit during chained DMA, programs
mask the DMA complete interrupt for a DMA process within a
chained DMA sequence.

I/O Processor

DMA Channel
TCB Loading

DMA

Count=1

PCI INTERRUPT
LATCHED FOR
FRAME N

FRAME N FRAME N

-

1

IOD BUS

DMA

Count=N

-

1

DMA

Count=N

DMA

Count=0

Figure 2-4. DMA Chaining

Transfer Completion Types

The next two sections describe the two types of interrupts that are used to
signal interrupt completion. These are based on the type of peripheral
used.

Internal Transfer Completion

This mode of interrupt generation resembles the traditional SHARC
DMA interrupt generation. The interrupt is generated once the DMA
internal transfers are complete, independent of whether the DMA is a
transmit or receive. Therefore, for external transmit DMAs, when the
completion interrupt is generated there may still be an external access
pending at the external DMA interface.

The I/O processor only generates a DMA complete interrupt when



the channel’s count register decrements to zero as a result of actual
DMA transfers. Writing zero to a count register does not generate
the interrupt. To stop a DMA preemptively, write a one to the
count register. This causes one additional word to be transferred or
received, and an interrupt is then generated.

Access Completion

A DMA complete interrupt is generated when accesses are finished. For an
external write DMA, the DMA complete interrupt is generated only after

ADSP-2137x SHARC Processor Hardware Reference 2-37

Interrupts

the external writes on the DMA external interface are complete. For an
external read DMA, the complete interrupt is generated when the internal
DMA writes are complete. In this DMA mode the DMA interface could
be disabled as soon as the interrupt is received.

This mode is supported by the external port on the ADSP-2137x proces­sors only.

Core Single Word Transfer Interrupts

When a DMA channel’s buffer is not being used for a DMA process, the
core can generate an interrupt on single word transfers (writes or reads) of
the buffer of the respective peripheral. This interrupt service differs
slightly for each peripheral. In this case, the peripheral’s buffer generates
an interrupt when data becomes available at the receive buffer or when the
transmit buffer is not full (when there is room for the core to write to the
buffer). Generating interrupts in this manner lets programs implement
interrupt-driven I/O under control of the processor core. Refer to the spe­cific peripheral chapter for more information.

Interrupt Versus Channel Priorities

At their default setting shown in Table 2-22, the DMA interrupt priorities
do not match the DMA channel priorities. However, if both priorities
schemes should match, the DMA interrupt priorities can be re-assigned by
dedicated settings of the PICRx registers.

2-38 ADSP-2137x SHARC Processor Hardware Reference