ANALOG DEVICES ADSP-2137x Service Manual

ADSP-2137x SHARC® Processor

Hardware Reference

Includes ADSP-21367, ADSP-21368,

ADSP-21369, ADSP-21371, ADSP-21375

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 2.1, May 2010

Part Number

82-000100-01

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

Contents

PREFACE

Purpose of This Manual ............................................................... xliii

Intended Audience ....................................................................... xliii

Manual Contents .......................................................................... xliv

What’s New in This Manual ......................................................... xlvii

Technical or Customer Support .................................................. xlviii

Registration for MyAnalog.com ............................................... xlix

EngineerZone .......................................................................... xlix

Social Networking Web Sites ....................................................... l

Supported Processors ......................................................................... l

Product Information ......................................................................... l

Analog Devices Web Site ............................................................. l

VisualDSP++ Online Documentation ......................................... li

Technical Library CD ................................................................ lii

Notation Conventions ..................................................................... lii

INTRODUCTION

Design Advantages ........................................................................ 1-1

SHARC Family Product Offerings ........................................... 1-2

ADSP-2137x SHARC Processor Hardware Reference iii

Contents

Processor Architectural Overview .................................................. 1-3

Processor Core ........................................................................ 1-3

I/O Peripherals ....................................................................... 1-3

I/O Processor ..................................................................... 1-3

Digital Audio Interface (DAI) ............................................. 1-4

Interrupt Controller ........................................................... 1-4

Signal Routing Unit ............................................................ 1-4

Digital Peripheral Interface (DPI) ....................................... 1-5

Interrupt Controller ........................................................... 1-5

Signal Routing Unit 2 ......................................................... 1-5

Development Tools ....................................................................... 1-5

Differences from Previous Processors ............................................. 1-6

I/O Architecture Enhancements .............................................. 1-6

I/O PROCESSOR

Features ........................................................................................ 2-2

DMA Channel Registers ............................................................... 2-3

DMA Channel Allocation ....................................................... 2-3

Standard DMA Parameter Registers ......................................... 2-3

Extended DMA Parameter Registers ........................................ 2-7

Data Buffers ........................................................................... 2-8

Chain Pointer Registers ........................................................... 2-9

TCB Storage ............................................................................... 2-11

Serial Port TCB .................................................................... 2-11

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SPI TCB ............................................................................... 2-11

UART TCB .......................................................................... 2-12

External Port TCB ................................................................. 2-12

Clocking ..................................................................................... 2-15

Functional Description ............................................................... 2-15

Automated Data Transfer ....................................................... 2-15

DMA Transfer Types ............................................................. 2-16

DMA Direction ..................................................................... 2-17

Internal to External Memory ............................................. 2-17

Peripheral to Internal Memory .......................................... 2-18

Internal Memory to Internal Memory ................................ 2-18

DMA Controller Addressing .................................................. 2-18

Internal Index Register Addressing ..................................... 2-20

External Index Register Addressing .................................... 2-21

DMA Channel Status ............................................................ 2-21

DMA Start and Stop Conditions ............................................ 2-22

Operating Modes ........................................................................ 2-23

DMA Chaining ..................................................................... 2-24

TCB Memory Storage ....................................................... 2-25

Chain Assignment ............................................................. 2-26

Starting Chain Loading ..................................................... 2-27

TCB Chain Loading Priority ............................................. 2-28

Chain Insert Mode (SPORTs Only) ................................... 2-28

Fixed DMA Channel Arbitration ........................................... 2-29

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Contents

Peripheral DMA Bus ......................................................... 2-33

External Port DMA Bus .................................................... 2-34

Rotating DMA Channel Arbitration ...................................... 2-34

Rotating Priority by Group ............................................... 2-34

Interrupts ................................................................................... 2-35

Sources ................................................................................. 2-36

Unchained DMA Interrupts .............................................. 2-36

Chained DMA Interrupts ................................................. 2-36

Transfer Completion Types .................................................... 2-37

Internal Transfer Completion ............................................ 2-37

Access Completion ........................................................... 2-37

Core Single Word Transfer Interrupts .................................... 2-38

Interrupt Versus Channel Priorities ........................................ 2-38

Debug Features ........................................................................... 2-39

Emulation Considerations ..................................................... 2-40

Effect Latency ............................................................................ 2-40

Write Effect Latency ............................................................. 2-40

IOP Effect Latency ............................................................... 2-40

IOP Throughput .................................................................. 2-40

Programming Model ................................................................... 2-41

General Procedure for Configuring DMA .............................. 2-41

EXTERNAL PORT

Features ........................................................................................ 3-2

Pin Descriptions ........................................................................... 3-3

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Contents

Pin Multiplexing ..................................................................... 3-4

Clocking ....................................................................................... 3-5

Functional Description ................................................................. 3-6

External Port Arbitration ......................................................... 3-7

External Port Bus Arbitration Conflicts ............................... 3-8

Channel Freezing ..................................................................... 3-8

Asynchronous Memory Interface ................................................... 3-8

AMI Features .......................................................................... 3-9

Functional Description ............................................................ 3-9

Asynchronous Reads ......................................................... 3-10

Asynchronous Writes ......................................................... 3-11

Parameter Timing ............................................................. 3-12

Idle Cycles ........................................................................ 3-12

Address Mapping .............................................................. 3-12

Operating Modes ................................................................... 3-13

Data Packing .................................................................... 3-13

External Access Extension .................................................. 3-14

Predictive Reads ................................................................ 3-15

SDRAM Controller ..................................................................... 3-16

Features ................................................................................. 3-16

Functional Description .......................................................... 3-17

SDRAM Commands ......................................................... 3-18

Load Mode Register ...................................................... 3-19

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Contents

Address Mapping .............................................................. 3-26

Single Bank Activation .................................................. 3-20

Multibank Activation (ADSP-2137x Processors) ............ 3-20

Single Precharge (ADSP-2137x Processors) .................... 3-21

Precharge All ................................................................ 3-21

Read/Write ................................................................... 3-21

Read/Write Full Page Burst (ADSP-2137x Processors) ... 3-24

Burst Stop (ADSP-2137x Processors) ............................ 3-24

Auto-Refresh ................................................................ 3-25

No Operation/Command Inhibit .................................. 3-25

Command Truth Table ................................................. 3-25

External Addressing Modes ........................................... 3-27

Refresh Rate Control ........................................................ 3-32

Internal SDRAM Bank Access ........................................... 3-34

Single Bank Access ........................................................ 3-34

Multibank Access (ADSP-2137x Processors) .................. 3-34

Multi Bank Operation with Data Packing

(ADSP-2137x) ........................................................... 3-36

Timing Parameters ............................................................ 3-36

Fixed Timing Parameters ............................................... 3-36

Data Mask (DQM) ........................................................... 3-37

Resetting the Controller .................................................... 3-37

Operating Modes .................................................................. 3-37

Parallel Connection of SDRAMs ....................................... 3-38

Buffering Controller for Multiple SDRAMs .................. 3-38

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SDRAM Read Optimization ............................................. 3-38

Core Accesses ................................................................ 3-41

DMA Access ................................................................. 3-42

Notes on Read Optimization ......................................... 3-43

Self-Refresh Mode ............................................................. 3-43

Forcing SDRAM Commands ............................................. 3-44

Force Precharge All ....................................................... 3-44

Force Load Mode Register (ADSP-2137x Only) ............. 3-45

Force Auto-Refresh ........................................................ 3-45

Shared Memory Interface (ADSP-21368) .................................... 3-45

Pin Descriptions .................................................................... 3-46

Functional Description .......................................................... 3-46

Bus Arbitration Protocol ................................................... 3-48

Bus Synchronization After Reset ........................................ 3-52

Shared AMI Protocol ........................................................ 3-54

Shared SDRAM Protocol .................................................. 3-54

Operating Modes ................................................................... 3-55

Rotating Priority Bus Arbitration (RPBA) .......................... 3-55

Bus Mastership Time-Out ................................................. 3-56

Data Transfer .............................................................................. 3-57

Data Buffers .......................................................................... 3-58

Receive Buffer ................................................................... 3-58

Transmit Buffer ................................................................. 3-58

Core Access ........................................................................... 3-59

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Contents

External Port Dual Data Fetch .......................................... 3-59

Conditional Instructions ................................................... 3-59

External Instruction Fetch (ADSP-2137x) ......................... 3-59

Fetching Instructions From External Memory ................ 3-60

External Port DMA Transfers ................................................ 3-69

External Port DMA Parameter Registers ............................ 3-70

Operating Modes .............................................................. 3-72

Internal DMA Addressing ............................................. 3-72

Standard DMA ............................................................. 3-72

Circular Buffered DMA ................................................ 3-73

Chained DMA Mode ........................................................ 3-74

Changing DMA Direction on the Fly (ADSP-2137x) .... 3-74

Scatter/Gather DMA (ADSP-2137x) ................................. 3-76

External Address Calculation ......................................... 3-76

Delay Line DMA .............................................................. 3-81

External Address Calculation for Reads ......................... 3-83

Interrupts ................................................................................... 3-85

Access Completion (ADSP-2137x) ........................................ 3-85

Internal Transfer Completion ................................................ 3-86

Interrupt Dependency on DMA Mode .................................. 3-86

External Port Throughput ........................................................... 3-87

AMI Data Throughput ......................................................... 3-87

SDRAM Throughput ............................................................ 3-87

Throughput Conditional Instructions ............................... 3-88

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External Instruction Fetch Throughput (ADSP-2137x) .......... 3-88

Effect Latency ............................................................................. 3-90

Shared Memory ..................................................................... 3-90

Write Effect Latency .............................................................. 3-90

Programming Models .................................................................. 3-90

External Port ......................................................................... 3-91

AMI Initialization ............................................................. 3-91

DMA .................................................................................... 3-91

Standard DMA (ADSP-21367/8/9) ................................... 3-92

Chained DMA (ADSP-21367/8/9) .................................... 3-93

Standard DMA (ADSP-21371/5) ...................................... 3-94

Chained DMA (ADSP-21371/5) ....................................... 3-95

Delay Line DMA .............................................................. 3-96

Disabling and Re-enabling DMA ....................................... 3-96

Additional Information ..................................................... 3-97

SDRAM Controller ............................................................... 3-98

Power-Up Sequence .......................................................... 3-98

Output Clock Generator Programming Model ................... 3-99

Self-Refresh Mode ........................................................... 3-100

Changing the VCO Clock During Runtime ..................... 3-100

Bus Synchronization with Shared SDRAM ...................... 3-101

Bus Synchronization Notes .............................................. 3-103

Conditional Bus Master Instruction ................................. 3-104

External Instruction Fetch ................................................... 3-104

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Contents

AMI Configuration ........................................................ 3-104

SDRAM Configuration .................................................. 3-104

External Memory Access Restrictions ................................... 3-105

ADSP-21367/8/9 Only ................................................... 3-105

ADSP-2137x Only ......................................................... 3-106

MEMORY-TO-MEMORY PORT DMA

Features ........................................................................................ 4-2

Clocking ...................................................................................... 4-2

Functional Description ................................................................. 4-3

Data Transfer ............................................................................... 4-3

Data Buffer ............................................................................. 4-3

DMA Transfer ........................................................................ 4-4

Interrupts ..................................................................................... 4-4

MTM Throughput ....................................................................... 4-5

Effect Latency .............................................................................. 4-5

Write Effect Latency ............................................................... 4-5

MTM Effect Latency .............................................................. 4-5

Programming Model ..................................................................... 4-5

PULSE WIDTH MODULATION

Features ........................................................................................ 5-2

Pin Descriptions ........................................................................... 5-4

Multiplexing Scheme .............................................................. 5-4

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Clocking ....................................................................................... 5-6

Functional Description ................................................................. 5-6

Two-Phase PWM Generator .................................................... 5-6

Switching Frequencies ......................................................... 5-6

Duty Cycles ........................................................................ 5-7

Dead Time ....................................................................... 5-12

Output Control Unit ............................................................. 5-12

Output Enable .................................................................. 5-13

Output Polarity ................................................................. 5-13

Complementary Outputs .................................................. 5-13

Crossover .......................................................................... 5-13

Emergency Dead Time for Over Modulation .......................... 5-14

Output Control Feature Precedence ................................... 5-16

Operating Modes ........................................................................ 5-17

Waveform Modes .................................................................. 5-17

Edge-Aligned Mode .......................................................... 5-17

Center-Aligned Mode ........................................................ 5-18

PWM Timer Edge Aligned Update ........................................ 5-20

Single Update Mode .......................................................... 5-21

Double Update Mode ....................................................... 5-22

Effective Accuracy ................................................................. 5-23

Synchronization of PWM Groups .......................................... 5-24

Interrupts ................................................................................... 5-24

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Contents

Debug Features ........................................................................... 5-26

Status Debug Register ........................................................... 5-26

Emulation Considerations ..................................................... 5-26

Effect Latency ............................................................................ 5-26

Write Effect Latency ............................................................. 5-27

PWM Effect Latency ............................................................. 5-27

DIGITAL APPLICATION/DIGITAL PERIPHERAL

INTERFACES

Features ........................................................................................ 6-2

Clocking ...................................................................................... 6-4

Functional Description ................................................................. 6-4

DAI/DPI Signal Naming Conventions ..................................... 6-7

I/O Pin Buffers ....................................................................... 6-7

Pin Buffers as Signal Output ............................................... 6-8

Pin Buffers as Signal Input ................................................ 6-10

Pin Buffers as Open Drain ................................................ 6-11

Programmable Pull-Up Resistors ....................................... 6-11

DAI/DPI Pin Buffer Status ............................................... 6-12

Unused DAI/DPI Pins ...................................................... 6-12

Miscellaneous Buffers ............................................................ 6-12

DAI/DPI Peripherals ............................................................. 6-14

Output Signals With Pin Buffer Enable Control ................ 6-14

Output Signals Without Pin Buffer Enable Control ........... 6-16

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Contents

Signal Routing Units (SRUs) ................................................. 6-16

Signal Routing Matrix by Groups ...................................... 6-16

DAI/DPI Group Routing .................................................. 6-18

Rules for SRU Connections ............................................... 6-20

Making SRU Connections ................................................. 6-20

DAI Routing Capabilities .................................................. 6-24

DPI Routing Capabilities .................................................. 6-25

Pin Buffer Input ............................................................ 6-26

Pin Buffer Enable .......................................................... 6-26

Miscellaneous Signals .................................................... 6-27

DAI Default Routing ............................................................. 6-28

DPI Default Routing ............................................................. 6-31

Interrupts ................................................................................... 6-32

System versus Exception Interrupts ........................................ 6-32

Functional Description .......................................................... 6-33

DAI Interrupt Channels ........................................................ 6-33

DAI Interrupt Priorities ......................................................... 6-34

DPI Interrupt Channels ......................................................... 6-34

DPI Interrupt Priorities ......................................................... 6-34

DAI Miscellaneous Interrupts ................................................ 6-35

DPI Miscellaneous Interrupts ................................................ 6-35

DAI/DPI Interrupt Mask Events ............................................ 6-36

DAI Interrupt Acknowledge .................................................. 6-38

DPI Interrupt Acknowledge ................................................... 6-39

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Contents

Core Versus DAI/DPI Interrupts ........................................... 6-39

Debug Features ........................................................................... 6-40

DAI Shadow Registers ........................................................... 6-40

DPI Shadow Registers ........................................................... 6-40

Loop Back Routing ............................................................... 6-41

Effect Latency ............................................................................ 6-42

Write Effect Latency ............................................................. 6-42

Signal Routing Unit Effect Latency ........................................ 6-42

Programming Model ................................................................... 6-42

DAI Example System ............................................................ 6-43

SERIAL PORTS

Features ........................................................................................ 7-2

Pin Descriptions ........................................................................... 7-4

SRU Programming ....................................................................... 7-5

SRU SPORT Receive Master ................................................... 7-6

SRU SPORT Signal Integrity .................................................. 7-6

Clocking ...................................................................................... 7-8

Master Clock .......................................................................... 7-9

Master Frame Sync .................................................................. 7-9

Slave Mode ........................................................................... 7-10

Functional Description ............................................................... 7-11

Architecture .......................................................................... 7-11

Data Types and Companding ................................................ 7-12

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Companding the Data Stream ........................................... 7-14

Transmit Path ................................................................... 7-15

Receive Path ..................................................................... 7-15

Frame Sync ........................................................................... 7-16

Frame Sync and Data Sampling ......................................... 7-16

Serial Word Length ........................................................... 7-17

Internal Versus External Frame Syncs ................................. 7-18

External Frame Sync Sampling ...................................... 7-19

Logic Level Frame Syncs ................................................ 7-19

Data-Independent Frame Sync ...................................... 7-20

Operating Modes ........................................................................ 7-20

Mode Selection ...................................................................... 7-22

Channel Order First .......................................................... 7-24

Standard Serial Mode ............................................................. 7-24

Timing Control Bits .......................................................... 7-24

Clocking Options ............................................................. 7-25

Frame Sync Options .......................................................... 7-25

Framed Versus Unframed Frame Syncs ............................... 7-25

Early Versus Late Frame Syncs ........................................... 7-26

Left-Justified Mode ............................................................... 7-28

Master Serial Clock and Frame Sync Rates ......................... 7-28

Timing Control Bits .......................................................... 7-29

S Mode .............................................................................. 7-29

Master Serial Clock and Frame Sync Rates ......................... 7-29

ADSP-2137x SHARC Processor Hardware Reference xvii

Contents

S Compatibility ............................................................. 7-30

Timing Control Bits ......................................................... 7-30

Multichannel Mode .............................................................. 7-31

Clocking Options ............................................................. 7-31

Frame Sync Options ......................................................... 7-32

Frame Sync Delay (MFD) ................................................. 7-32

Transmit Data Valid Signal ............................................... 7-33

Transmit Data Valid Output ......................................... 7-34

Timing Control Bits ......................................................... 7-35

Number of Channels (NCH) ............................................ 7-35

Packed Mode ........................................................................ 7-36

Clocking Options ............................................................. 7-37

Frame Sync Options ......................................................... 7-37

Timing Control Bits ......................................................... 7-37

Active Channel Selection Registers ........................................ 7-38

Transmit Selection Registers .............................................. 7-38

Receive Selection Registers ................................................ 7-39

Companding Selection ...................................................... 7-39

Companding Limitations .................................................. 7-39

Data Transfer Types .................................................................... 7-40

Data Buffers ......................................................................... 7-40

Transmit Buffers (TXSPxA/B) ........................................... 7-41

Receive Buffers (RXSPxA/B) ............................................. 7-41

Buffer Status ..................................................................... 7-41

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Data Buffer Packing .......................................................... 7-43

Core Transfers ....................................................................... 7-43

Single Word Transfers ....................................................... 7-43

Frame Sync Generation ..................................................... 7-44

Internal Memory DMA Transfers ........................................... 7-45

Standard DMA ................................................................. 7-46

DMA Chaining ................................................................. 7-47

DMA Chain Insertion Mode ............................................. 7-48

Frame Sync Generation ..................................................... 7-49

Interrupts ................................................................................... 7-49

Internal Transfer Completion ................................................. 7-50

Shared Channels .................................................................... 7-51

Error Detection ..................................................................... 7-51

Error Status ........................................................................... 7-53

Debug Features ........................................................................... 7-54

SPORT Loopback ................................................................. 7-54

LoopBack Routing ............................................................ 7-54

Buffer Hang Disable (BHD) .................................................. 7-54

Effect Latency ............................................................................. 7-55

Write Effect Latency .............................................................. 7-55

SPORT Effect Latency ........................................................... 7-55

Programming Model ................................................................... 7-55

Setting Up and Starting DMA Master Mode .......................... 7-56

Setting Up and Starting Chained DMA .................................. 7-56

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Contents

Enter DMA Chain Insertion Mode ........................................ 7-57

Setting Up and Starting Multichannel Mode .......................... 7-57

Multichannel Mode Backward Compatibility .................... 7-58

Programming Packed Mode ................................................... 7-59

Additional Information for External

Frame Sync Operation ........................................................ 7-60

Companding As a Function ................................................... 7-60

INPUT DATA PORT

Features ........................................................................................ 8-2

Pin Descriptions ........................................................................... 8-3

SRU Programming ....................................................................... 8-4

Clocking ...................................................................................... 8-6

Functional Description ................................................................. 8-6

Operating Modes .......................................................................... 8-7

PDAP Port Selection ............................................................... 8-8

Data Hold .............................................................................. 8-9

PDAP Data Masking ............................................................. 8-10

PDAP Data Packing .............................................................. 8-10

No Packing ....................................................................... 8-10

Packing by 2 ..................................................................... 8-11

Packing by 3 ..................................................................... 8-12

Packing by 4 ..................................................................... 8-13

Data Transfer ............................................................................. 8-14

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Data Buffer ........................................................................... 8-14

Core Transfers ....................................................................... 8-15

SIP Data Buffer Format ..................................................... 8-16

PDAP Data Buffer Format ................................................ 8-18

DMA Transfers ...................................................................... 8-19

Data Buffer Format for DMA ............................................ 8-19

DMA Channel Priority ..................................................... 8-20

Standard DMA ................................................................. 8-20

Ping-Pong DMA ............................................................... 8-21

Multichannel DMA Operation .......................................... 8-21

Multichannel FIFO Status ................................................. 8-22

Interrupts ................................................................................... 8-23

Interrupt Acknowledge .......................................................... 8-23

Threshold Interrupts ............................................................. 8-23

DMA Interrupts .................................................................... 8-24

FIFO Overflow Interrupts ..................................................... 8-24

Debug Features ........................................................................... 8-25

Status Register Debug ............................................................ 8-25

Buffer Hang Disable .............................................................. 8-25

Shadow Registers ................................................................... 8-25

Core FIFO Write ................................................................... 8-26

Effect Latency ............................................................................. 8-26

Write Effect Latency .............................................................. 8-26

IDP Effect Latency ................................................................ 8-26

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Contents

Programming Model ................................................................... 8-26

Setting Miscellaneous Bits ..................................................... 8-27

Starting Core Interrupt-Driven Transfer ................................ 8-27

Additional Notes .............................................................. 8-28

Starting A Standard DMA Transfer ........................................ 8-29

Starting a Ping-Pong DMA Transfer ...................................... 8-30

Servicing Interrupts for DMA ............................................... 8-31

ASYNCHRONOUS SAMPLE RATE CONVERTER

Features ........................................................................................ 9-2

Pin Descriptions ........................................................................... 9-3

SRU Programming ....................................................................... 9-3

Clocking ...................................................................................... 9-5

Functional Description ................................................................. 9-5

Operating Modes .......................................................................... 9-9

TDM Daisy Chain Mode ...................................................... 9-11

TDM Input Daisy Chain .................................................. 9-11

TDM Output Daisy Chain ............................................... 9-12

Bypass Mode ......................................................................... 9-12

Matched-Phase Mode ............................................................ 9-12

Data Format Matched-Phase Mode ................................... 9-14

Group Delay .................................................................... 9-14

Decimation Rate ................................................................... 9-15

Muting Modes ...................................................................... 9-15

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Soft Mute ......................................................................... 9-15

Hard Mute ........................................................................ 9-16

Auto Mute ........................................................................ 9-16

Interrupts ................................................................................... 9-16

Debug Features ........................................................................... 9-17

Effect Latency ............................................................................. 9-17

Write Effect Latency .............................................................. 9-17

SRC Effect Latency ............................................................... 9-18

SONY/PHILIPS DIGITAL INTERFACE

Features ...................................................................................... 10-2

Pin Descriptions ......................................................................... 10-3

SRU Programming ...................................................................... 10-5

Clocking ..................................................................................... 10-7

S/PDIF Transmitter .................................................................... 10-7

Functional Description .......................................................... 10-7

Input Data Format .......................................................... 10-10

Operating Modes ................................................................. 10-12

Full Serial Mode ............................................................. 10-12

Standalone Mode ............................................................ 10-12

Data Output Mode ......................................................... 10-13

S/PDIF Receiver ....................................................................... 10-14

Functional Description ........................................................ 10-14

Clock Recovery ............................................................... 10-16

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Contents

Output Data Format ...................................................... 10-16

Channel Status ............................................................... 10-17

Operating Modes ................................................................ 10-17

Compressed or Non-linear Audio Data ............................ 10-17

Emphasized Audio Data .............................................. 10-18

Single-Channel Double-Frequency Mode .................... 10-19

Clock Recovery Modes ................................................... 10-19

Digital On-Chip PLL ................................................. 10-19

External Analog PLL ................................................... 10-20

Interrupts ................................................................................. 10-20

Transmitter Interrupt .......................................................... 10-20

Receiver Interrupts .............................................................. 10-21

Receiver Error Interrupts ..................................................... 10-21

Debug Features ......................................................................... 10-22

Loop Back Routing ............................................................. 10-22

Effect Latency .......................................................................... 10-22

Write Effect Latency ........................................................... 10-22

S/PDIF Effect Latency ........................................................ 10-22

S/PDIF Transmit ............................................................ 10-22

S/PDIF Receive .............................................................. 10-23

Programming Model ................................................................. 10-23

Programming the Transmitter .............................................. 10-24

Programming the Receiver ................................................... 10-24

Interrupted Data Streams on the Receiver ............................ 10-25

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PRECISION CLOCK GENERATOR

Features ...................................................................................... 11-2

Pin Descriptions ......................................................................... 11-3

SRU Programming ...................................................................... 11-4

Clocking ..................................................................................... 11-5

Functional Description ............................................................... 11-6

Serial Clock ........................................................................... 11-6

Frame Sync ........................................................................... 11-7

Frame Sync Output ........................................................... 11-7

Divider Mode Selection ..................................................... 11-8

Phase Shift ........................................................................ 11-8

Pulse Width ...................................................................... 11-9

Default Pulse Width ....................................................... 11-10

Timing Example for I2S Mode ........................................ 11-10

Operating Modes ...................................................................... 11-11

Normal Mode ...................................................................... 11-11

Bypass Mode ....................................................................... 11-12

One-Shot Mode .................................................................. 11-13

External Event Trigger ......................................................... 11-14

External Event Trigger Delay ........................................... 11-15

Audio System Example ........................................................ 11-15

Clock Configuration Examples ............................................ 11-17

Effect Latency ........................................................................... 11-18

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Contents

Write Effect Latency ........................................................... 11-18

PCG Effect Latency ............................................................ 11-19

Programming Model ................................................................. 11-19

Frame Sync Phase Setting .................................................... 11-20

External Event Trigger ......................................................... 11-20

Debug Features ......................................................................... 11-20

SERIAL PERIPHERAL INTERFACE PORTS

Features ...................................................................................... 12-2

Pin Descriptions ......................................................................... 12-3

SRU Programming ..................................................................... 12-4

Clocking .................................................................................... 12-6

Choosing the Pin Enable for the SPI Clock ............................ 12-7

Functional Description ............................................................... 12-7

Single Master Systems ........................................................... 12-9

Multi Master Systems .......................................................... 12-10

Operating Modes ...................................................................... 12-12

Transfer Initiate Mode ......................................................... 12-12

SPI Modes .......................................................................... 12-13

Slave Select Outputs ............................................................ 12-15

Frame Delay for Slave ......................................................... 12-16

Data Transfer ........................................................................... 12-17

Data Buffer ......................................................................... 12-17

Core Transfers ..................................................................... 12-18

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Contents

DMA Transfers .................................................................... 12-19

Slave DMA Transfer Preparation ..................................... 12-20

SPI DMA Chaining ........................................................ 12-21

Setting Up and Starting Chained DMA ....................... 12-21

Core and DMA Transfers ..................................................... 12-22

Changing SPI Configuration ........................................... 12-22

Starting and Stopping SPI Data Transfers ........................ 12-23

Interrupts ................................................................................. 12-24

Interrupt Sources ................................................................. 12-25

Internal Transfer Completion .......................................... 12-26

Multi Master Error .............................................................. 12-26

Debug Features ......................................................................... 12-27

Shadow Receive Buffers ....................................................... 12-28

Internal Loopback Mode ..................................................... 12-28

Loop Back Routing ......................................................... 12-28

Effect Latency ........................................................................... 12-29

Write Effect Latency ............................................................ 12-29

SPI Effect Latency ............................................................... 12-29

Programming Model ................................................................. 12-29

Master Mode Core Transfers ................................................ 12-29

Multimaster Transfers ...................................................... 12-31

Slave Mode Core Transfers ................................................... 12-31

Master Mode DMA Transfers ............................................... 12-33

Slave Mode DMA Transfers ................................................. 12-34

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Contents

Chained DMA Transfers ..................................................... 12-36

Stopping Core Transfers ...................................................... 12-36

Stopping DMA Transfers ..................................................... 12-37

Switching from Transmit To Transmit/Receive DMA ........... 12-38

Switching from Receive to Receive/Transmit DMA .............. 12-39

DMA Error Interrupts ......................................................... 12-40

PERIPHERAL TIMERS

Features ...................................................................................... 13-2

Pin Descriptions ......................................................................... 13-3

SRU Programming ..................................................................... 13-3

Read-Modify-Write ............................................................... 13-5

Clocking .................................................................................... 13-5

Functional Description ............................................................... 13-6

Operating Modes ........................................................................ 13-7

Pulse Width Modulation Mode (PWM_OUT) ...................... 13-8

PWM Waveform Generation .......................................... 13-10

Single-Pulse Generation .................................................. 13-12

Pulse Mode .................................................................... 13-12

Pulse Width Count and Capture Mode (WDTH_CAP) ....... 13-13

External Event Watchdog Mode (EXT_CLK) ...................... 13-15

Interrupts ................................................................................. 13-17

Sources ............................................................................... 13-18

Watchdog Functionality ...................................................... 13-19

xxviii ADSP-2137x SHARC Processor Hardware Reference

Contents

Debug Features ......................................................................... 13-19

Loop Back Routing .............................................................. 13-19

Emulation Considerations ................................................... 13-19

Effect Latency ........................................................................... 13-20

Write Effect Latency ............................................................ 13-20

Peripheral Timers Effect Latency .......................................... 13-20

Programming Model ................................................................. 13-20

PWM Out Mode ................................................................. 13-21

WDTH_CAP Mode ............................................................ 13-23

EXT_CLK Mode ................................................................. 13-24

UART PORT CONTROLLER

Features ...................................................................................... 14-2

SRU Programming ...................................................................... 14-2

Clocking ..................................................................................... 14-4

Functional Description ............................................................... 14-5

Serial Communication ........................................................... 14-7

Operating Modes ........................................................................ 14-8

Data Packing ......................................................................... 14-8

9-Bit Transmission Mode ....................................................... 14-8

Packed Mode .................................................................... 14-9

Data Transfer ............................................................................ 14-10

Data Buffers ........................................................................ 14-10

Transmit Holding Registers (UARTxTHR) ...................... 14-10

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Contents

Receive Buffer Registers (UARTxRBR) ............................ 14-11

Core Transfers ..................................................................... 14-12

DMA Transfers ................................................................... 14-13

DMA Chaining .............................................................. 14-14

Interrupts ................................................................................. 14-14

Interrupt Routing ............................................................... 14-15

DPI ................................................................................ 14-15

UART ............................................................................ 14-16

DMA Interrupts .................................................................. 14-16

Core Interrupts ................................................................... 14-17

Error Interrupts .................................................................. 14-19

Debug Features ......................................................................... 14-20

Shadow Registers ................................................................ 14-20

Shadow Buffer .................................................................... 14-20

Loop Back Routing ............................................................. 14-20

Effect Latency .......................................................................... 14-20

Write Effect Latency ........................................................... 14-20

UART Effect Latency .......................................................... 14-21

Programming Model ................................................................. 14-21

Autobaud Detection ............................................................ 14-21

Programming Model for DMA Transfers .............................. 14-22

Setting Up and Starting Chained DMA ........................... 14-22

Notes on Using UART DMA .......................................... 14-23

Programming Model for Core Transfers ............................... 14-23

xxx ADSP-2137x SHARC Processor Hardware Reference

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