ANALOG DEVICES ADSP-2136x Service Manual

ADSP-2136x SHARC® Processor

Programming Reference

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Revision 1.1, March 2007

Part Number

82-000500-01

a

Copyright Information

© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC
logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog
Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

Contents

PREFACE

Purpose of This Manual .............................................................. xxiii

Intended Audience ...................................................................... xxiii

Manual Contents ......................................................................... xxiv

What’s New in This Manual ......................................................... xxvi

Technical or Customer Support .................................................... xxvi

Supported Processors ................................................................... xxvii

Product Information ................................................................... xxvii

MyAnalog.com ..................................................................... xxviii

Processor Product Information .............................................. xxviii

Related Documents ................................................................ xxix

Online Technical Documentation ............................................ xxx

Accessing Documentation From VisualDSP++ .................... xxxi

Accessing Documentation From Windows .......................... xxxi

Accessing Documentation From the Web ........................... xxxii

Printed Manuals .................................................................... xxxii

VisualDSP++ Documentation Set ...................................... xxxii

Hardware Tools Manuals .................................................. xxxiii

ADSP-2136x SHARC Processor Programming Reference iii

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Processor Manuals ........................................................... xxxiii

Data Sheets ..................................................................... xxxiii

Conventions ............................................................................... xxxiv

INTRODUCTION

ADSP-2136x Design Advantages ................................................... 1-1

ADSP-2136x Architectural Overview ............................................ 1-5

Processor Core ........................................................................ 1-6

Processing Elements ............................................................ 1-6

Program Sequence Control ................................................. 1-7

Processor Internal Buses .................................................... 1-10

Processor Peripherals ............................................................. 1-11

Internal Memory (SRAM) ................................................ 1-13

Timers ............................................................................. 1-14

JTAG Port ........................................................................ 1-14

Rom Based Security .......................................................... 1-14

Development Tools ..................................................................... 1-15

Differences From Previous SHARC Processors ............................. 1-15

Processor Core Enhancements ............................................... 1-16

Processor Internal Bus Enhancements .................................... 1-16

Memory Organization Enhancements .................................... 1-17

JTAG Port Enhancements ..................................................... 1-17

Instruction Set Enhancements ............................................... 1-17

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PROCESSING ELEMENTS

Numeric Formats .......................................................................... 2-2

IEEE Single-Precision Floating-Point Data Format ................... 2-2

Extended-Precision Floating-Point Format ............................... 2-5

Short Word Floating-Point Format ........................................... 2-6

Packing for Floating-Point Data ............................................... 2-6

Fixed-Point Formats ................................................................ 2-8

Setting Computational Modes ..................................................... 2-11

32-Bit Floating-Point Format (Normal Word) ........................ 2-12

40-Bit Floating-Point Format ................................................. 2-13

16-Bit Floating-Point Format (Short Word) ........................... 2-13

32-Bit Fixed-Point Format ..................................................... 2-14

Rounding Mode .................................................................... 2-14

Using Computational Status ........................................................ 2-15

Arithmetic Logic Unit (ALU) ...................................................... 2-16

ALU Operation ..................................................................... 2-17

ALU Saturation ..................................................................... 2-17

ALU Status Flags ................................................................... 2-18

ALU Instruction Summary .................................................... 2-19

Multiply Accumulator (Multiplier) .............................................. 2-22

Multiplier Operation ............................................................. 2-22

Multiplier Result Register (Fixed-Point) ................................. 2-23

Multiplier Status Flags ........................................................... 2-26

Multiplier Instruction Summary ............................................ 2-27

ADSP-2136x SHARC Processor Programming Reference v

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Barrel Shifter (Shifter) ................................................................ 2-30

Shifter Operation .................................................................. 2-30

Shifter Status Flags ................................................................ 2-34

Shifter Instruction Summary ................................................. 2-35

Data Register File ....................................................................... 2-37

Alternate (Secondary) Data Registers ........................................... 2-39

Multifunction Computations ...................................................... 2-41

Secondary Processing Element (PEy) ........................................... 2-45

Dual Compute Units Sets ...................................................... 2-46

Dual Register Files ................................................................ 2-48

Dual Alternate Registers ........................................................ 2-49

SIMD (Computational) Operations ....................................... 2-49

SIMD and Status Flags .......................................................... 2-52

PROGRAM SEQUENCER

Instruction Pipeline ...................................................................... 3-2

Memory Conflicts ........................................................................ 3-5

Bus Conflicts .......................................................................... 3-5

Block Conflicts ....................................................................... 3-7

Instruction Cache ......................................................................... 3-8

Using the Cache ...................................................................... 3-8

Optimizing Cache Usage ......................................................... 3-9

Instruction Pipeline Stalls ........................................................... 3-11

Structural Hazard Stalls ......................................................... 3-12

Data Access and Instruction Fetch on the PM Bus ............. 3-12

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Data Access Over the DM and PM Buses .......................... 3-12

Update and Load Index Register ........................................ 3-13

Reading I, M, B, L Registers .............................................. 3-13

DMA Block Conflict with PM or DM Access .................... 3-13

Data and Control Hazard Stalls ............................................. 3-14

Address Generation ........................................................... 3-14

Branch .............................................................................. 3-16

Compute with Post-modify ............................................... 3-17

A JUMP With a LA Modifier Is Used To Abort a Loop ...... 3-18

Loops ............................................................................... 3-18

Stalls in Conditional Branches ............................................... 3-19

Address Generation Using I Registers After a CJUMP ........ 3-20

RFRAME Instruction ........................................................ 3-21

Other Instructions ............................................................ 3-22

Latency ....................................................................................... 3-22

Branches and Sequencing ............................................................ 3-26

Conditional Branches ............................................................ 3-28

Delayed Branches .................................................................. 3-29

Restrictions and Limitations When Using Delayed Branches 3-32

Other Jumps, or Calls With RTI, RTS ........................... 3-32

Pushes or Pops of the PC Stack ...................................... 3-33

Writes to the PC Stack or PC Stack Pointer ................... 3-34

IDLE Instruction .......................................................... 3-35

Stacks and Sequencing ................................................................ 3-35

ADSP-2136x SHARC Processor Programming Reference vii

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Loops and Sequencing ................................................................ 3-37

Counter Based Loops ............................................................ 3-37

Arithmetic Loops .................................................................. 3-39

Conditional Sequencing ........................................................ 3-40

Restrictions on Ending Loops ................................................ 3-43

Short Loops .......................................................................... 3-44

Restrictions on Short Loops .................................................. 3-46

Evaluation of NOT LCE Condition in Counter Based Loops 3-52

Arithmetic or Non-Counter Based Loops .......................... 3-53

Loop Address Stack ............................................................... 3-55

Loop Status ........................................................................... 3-56

SIMD Mode and Sequencing ...................................................... 3-58

Conditional Compute Operations ......................................... 3-61

Conditional Branches and Loops ........................................... 3-61

Conditional Data Moves ....................................................... 3-61

Case #1: Complementary Register Pair Data Move ............ 3-62

Example 1 – Register-to-Memory Move – PEx Explicit Register

3-62

Example 2 Register-to-Memory Move – PEy Explicit Register

3-63

Example 3 Register-to-Register Move – PEx Explicit Registers

3-63

Example 4 Register-to-Register Move – PEy Explicit Register .

3-64

Case #2: Uncomplimentary-to-Complementary

Register Move ................................................................ 3-65

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Case #3: Complementary-to-Uncomplimentary

Register Move ................................................................ 3-66

Case #4: External Memory or IOP Memory Space Data Move 3-67

Example: Register-to-Memory Moves – IOP Memory

Space Data Move ........................................................ 3-68

Case #5: Uncomplimentary Register Data Move ................ 3-68

Case #6: Conditional DAG Operations ............................. 3-68

Interrupts and Sequencing ........................................................... 3-68

Sensing External Interrupts .................................................... 3-74

Masking Interrupts ................................................................ 3-76

Latching Interrupts ................................................................ 3-76

Stacking Status During Interrupts .......................................... 3-78

Nesting Interrupts ................................................................. 3-79

Reusing Interrupts ................................................................. 3-81

Interrupting IDLE ................................................................. 3-82

Summary .................................................................................... 3-83

DATA ADDRESS GENERATORS

Setting DAG Modes ...................................................................... 4-2

Circular Buffering Mode .......................................................... 4-4

Broadcast Loading Mode ......................................................... 4-5

Alternate (Secondary) DAG Registers ....................................... 4-6

Example 1 ........................................................................... 4-8

Example 2 ........................................................................... 4-8

Bit-Reverse Addressing Mode ................................................... 4-8

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Using DAG Status ........................................................................ 4-9

DAG Operations ........................................................................ 4-10

Addressing With DAGs ......................................................... 4-10

Data Addressing Stalls ........................................................... 4-12

Addressing Circular Buffers ................................................... 4-13

Modifying DAG Registers ..................................................... 4-19

Addressing in SISD and SIMD Modes ................................... 4-20

DAGs, Registers, and Memory .................................................... 4-20

DAG Register-to-Bus Alignment ........................................... 4-21

DAG Register Transfer Restrictions ....................................... 4-23

DAG Instruction Summary ......................................................... 4-24

MEMORY

Internal Memory .......................................................................... 5-3

Processor Memory Architecture ............................................... 5-3

Buses ............................................................................................ 5-5

Internal Address and Data Buses .............................................. 5-5

Internal Data Bus Exchange .................................................... 5-7

ADSP-2136x Memory Maps ....................................................... 5-12

Internal Memory ................................................................... 5-13

Shared Memory .................................................................... 5-16

External Memory .................................................................. 5-16

External Address Space ..................................................... 5-17

SDRAM Address Mapping ................................................ 5-18

Memory Organization and Word Size .................................... 5-19

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Placing 32-Bit and 48-Bit Words ....................................... 5-20

Mixing 32-Bit Words and 48-Bit Words ............................ 5-21

Restrictions on Mixing 32-Bit Words and 48-Bit Words ..... 5-23

Example: Calculating a Starting Address for 32-Bit Addresses 5-25

48-Bit Word Allocation ..................................................... 5-25

Using Boot Memory .............................................................. 5-26

Reading From Boot Memory ............................................. 5-26

Internal Interrupt Vector Table .............................................. 5-26

Internal Memory Data Width ................................................ 5-27

Secondary Processor Element (PEy) ........................................ 5-28

Broadcast Register Loads ....................................................... 5-28

Illegal I/O Processor Register Access ....................................... 5-29

Unaligned 64-Bit Memory Access .......................................... 5-29

Using Memory Access Status ....................................................... 5-30

Accessing Memory ...................................................................... 5-31

Access Word Size ................................................................... 5-32

Long Word (64-Bit) Accesses ............................................. 5-32

Instruction Word (48-Bit) and

Extended-Precision Normal Word (40-Bit) Accesses ........ 5-34

Normal Word (32-Bit) Accesses ......................................... 5-35

Short Word (16-Bit) Accesses ............................................ 5-35

Setting Data Access Modes .................................................... 5-35

SYSCTL Register Control Bits .......................................... 5-36

Mode 1 Register Control Bits ............................................ 5-36

Mode 2 Register Control Bits ............................................ 5-37

ADSP-2136x SHARC Processor Programming Reference xi

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SISD, SIMD, and Broadcast Load Modes .............................. 5-37

Single- and Dual-Data Accesses ............................................. 5-37

Instruction Examples ........................................................ 5-38

Data Access Options ............................................................. 5-38

Short Word Addressing of Single-Data in SISD Mode ....... 5-39

Short Word Addressing of Single-Data in SIMD Mode ...... 5-42

Short Word Addressing of Dual-Data in SISD Mode ......... 5-44

Short Word Addressing of Dual-Data in SIMD Mode ....... 5-46

32-Bit Normal Word Addressing of Single-Data in SISD Mode 5-48
32-Bit Normal Word Addressing of Single-Data in SIMD Mode

5-50
32-Bit Normal Word Addressing of Dual-Data in SISD Mode 5-52
32-Bit Normal Word Addressing of Dual-Data in SIMD Mode 5-54
Extended-Precision Normal Word Addressing of Single-Data 5-56
Extended-Precision Normal Word Addressing of Dual-Data in SISD

Mode ............................................................................ 5-58

Extended-Precision Normal Word Addressing of Dual-Data in SIMD

Mode ............................................................................ 5-60

Long Word Addressing of Single-Data ............................... 5-62

Long Word Addressing of Dual-Data in SISD Mode .......... 5-64

Long Word Addressing of Dual-Data in SIMD Mode ........ 5-66

Mixed-Word Width Addressing of Dual-Data in SISD Mode 5-68
Mixed-Word Width Addressing of Dual-Data in SIMD Mode 5-70

Broadcast Load Access ...................................................... 5-72

Shadow Write FIFO ................................................................... 5-81

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Shadow Write FIFO Use in SIMD Mode ............................... 5-81

JTAG TEST EMULATION PORT

JTAG Test Access Port ................................................................... 6-1

Boundary Scan .............................................................................. 6-2

Background Telemetry Channel (BTC) .......................................... 6-4

User-Definable Breakpoint Interrupts ............................................ 6-4

Restrictions ............................................................................. 6-5

Silicon Revision ID ................................................................. 6-5

JTAG Related Registers ................................................................. 6-5

Instruction Register ................................................................. 6-6

Emulation Control Register (EMUCTL) .................................. 6-8

Breakpoint Control Register (BRKCTL) ................................ 6-11

Breakpoint Registers (PSx, DMx, IOx, and EPx) ................ 6-11

Enhanced Emulation Status Register (EEMUSTAT) ............... 6-13

EEMUIN Register ................................................................. 6-14

EEMUOUT Register ............................................................. 6-14

Emulation Clock Counter Registers (EMUCLK, EMUCLK2) 6-14

Boundary Register ................................................................. 6-15

EMUN Register .................................................................... 6-15

EMUIDLE Instruction .......................................................... 6-15

Operating System Process ID Register (OSPID) ..................... 6-16

Private Instructions ..................................................................... 6-17

References ................................................................................... 6-17

ADSP-2136x SHARC Processor Programming Reference xiii

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TIMER

Timer Architecture ....................................................................... 7-1

Timer and Sequencing .................................................................. 7-3

Timer Status and Control ............................................................. 7-5

Timer Interrupts ..................................................................... 7-7

Enabling a Timer .......................................................................... 7-8

Pulse Width Modulation Mode (PWM_OUT) ........................ 7-9

PWM Waveform Generation ............................................ 7-11

Single-Pulse Generation .................................................... 7-12

Pulse Width Count and Capture Mode (WDTH_CAP) ......... 7-12

External Event Watchdog Mode (EXT_CLK) ........................ 7-14

Timer Programming Examples .................................................... 7-15

INSTRUCTION SET

Group I Instructions ..................................................................... 8-1

Type 1: Compute, Dreg«···»DM | Dreg«···»PM .............................. 8-3

Type 2: Compute .......................................................................... 8-6

Type 3: Compute, ureg«···»DM | PM, register modify .................... 8-8

Type 4: Compute, dreg«···»DM | PM, data modify ...................... 8-13

Type 5: Compute, ureg«··· »ureg | Xdreg<->Ydreg ........................ 8-18

Type 6: Immediate Shift, dreg«···»DM | PM ................................ 8-22

Type 7: Compute, modify ........................................................... 8-27

Group II Instructions ................................................................. 8-30

Type 8: Direct Jump | Call .......................................................... 8-31

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Type 9: Indirect Jump | Call, Compute ........................................ 8-35

Type 10: Indirect Jump | Compute, dreg«···»DM ......................... 8-42

Type 11: Return From Subroutine | Interrupt, Compute .............. 8-48

Type 12: Do Until Counter Expired ............................................ 8-53

Type 13: Do Until ....................................................................... 8-55

Group III Instructions ................................................................. 8-57

Type 14: Ureg«···»DM | PM (direct addressing) ........................... 8-59

Type 15: Ureg«···»DM | PM (indirect addressing) ........................ 8-62

Type 16: Immediate data···»DM | PM ......................................... 8-66

Type 17: Immediate data···»Ureg ................................................. 8-69

Group IV Instructions ................................................................. 8-71

Type 18: System Register Bit Manipulation .................................. 8-72

Type 19: I Register Modify | Bit-Reverse ...................................... 8-75

Type 20: Push, Pop Stacks, Flush Cache ....................................... 8-78

Type 21: Nop .............................................................................. 8-80

Type 22: Idle ............................................................................... 8-81

Type 25: Cjump/Rframe ............................................................. 8-82

COMPUTATIONS REFERENCE

Compute Field .............................................................................. 9-1

ALU Operations ........................................................................... 9-3

ALU Fixed-Point Operations ................................................... 9-3

ALU Floating-Point Operations ............................................... 9-4

Rn = Rx + Ry ................................................................................ 9-6

Rn = Rx – Ry ................................................................................ 9-7

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Rn = Rx + Ry + CI ........................................................................ 9-8

Rn = Rx – Ry + CI – 1 .................................................................. 9-9

Rn = (Rx + Ry)/2 ........................................................................ 9-10

COMP(Rx, Ry) .......................................................................... 9-11

COMPU(Rx, Ry) ....................................................................... 9-12

Rn = Rx + CI .............................................................................. 9-13

Rn = Rx + CI – 1 ........................................................................ 9-14

Rn = Rx + 1 ................................................................................ 9-15

Rn = Rx – 1 ................................................................................ 9-16

Rn = –Rx .................................................................................... 9-17

Rn = ABS Rx .............................................................................. 9-18

Rn = PASS Rx ............................................................................ 9-19

Rn = Rx AND Ry ....................................................................... 9-20

Rn = Rx OR Ry .......................................................................... 9-21

Rn = Rx XOR Ry ........................................................................ 9-22

Rn = NOT Rx ............................................................................ 9-23

Rn = MIN(Rx, Ry) ..................................................................... 9-24

Rn = MAX(Rx, Ry) ..................................................................... 9-25

Rn = CLIP Rx BY Ry .................................................................. 9-26

Fn = Fx + Fy ............................................................................... 9-27

Fn = Fx – Fy ............................................................................... 9-28

Fn = ABS (Fx + Fy) .................................................................... 9-29

Fn = ABS (Fx – Fy) .................................................................... 9-30

Fn = (Fx + Fy)/2 ......................................................................... 9-31

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COMP(Fx, Fy) ........................................................................... 9-32

Fn = –Fx ..................................................................................... 9-33

Fn = ABS Fx ............................................................................... 9-34

Fn = PASS Fx .............................................................................. 9-35

Fn = RND Fx ............................................................................. 9-36

Fn = SCALB Fx BY Ry ................................................................ 9-37

Rn = MANT Fx .......................................................................... 9-38

Rn = LOGB Fx ........................................................................... 9-39

Rn = FIX Fx

Rn = TRUNC Fx
Rn = FIX Fx BY Ry

Rn = TRUNC Fx BY Ry ........................................................... 9-40

Fn = FLOAT Rx BY Ry

Fn = FLOAT Rx ....................................................................... 9-42

Fn = RECIPS Fx ......................................................................... 9-43

Fn = RSQRTS Fx ........................................................................ 9-45

Fn = Fx COPYSIGN Fy .............................................................. 9-47

Fn = MIN(Fx, Fy) ....................................................................... 9-48

Fn = MAX(Fx, Fy) ...................................................................... 9-49

Fn = CLIP Fx BY Fy ................................................................... 9-50

Multiplier Operations ................................................................. 9-50

Multiplier Fixed-Point Operations ......................................... 9-51

Multiplier Floating-Point Operations ..................................... 9-52

Mod1 and Mod2 Modifiers .................................................... 9-52

ADSP-2136x SHARC Processor Programming Reference xvii

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Rn = Rx * Ry mod2

MRF = Rx * Ry mod2

MRB Rx * Ry mod2 ................................................................ 9-54

Rn = MRF + Rx * Ry mod2

Rn = MRB + Rx * Ry mod2
MRF = MRF + Rx * Ry mod2

MRB = MRB + Rx * Ry mod2 ................................................. 9-55

Rn = MRF – Rx * Ry mod2

Rn = MRB – Rx * Ry mod2
MRF = MRF – Rx * Ry mod2

MRB = MRB – Rx * Ry mod2 ................................................. 9-56

Rn = SAT MRF mod1

Rn = SAT MRB mod1
MRF = SAT MRF mod1

MRB = SAT MRB mod1 .......................................................... 9-57

Rn = RND MRF mod1

Rn = RND MRB mod1
MRF = RND MRF mod1

MRB = RND MRB mod1 ........................................................ 9-58

MRF = 0

MRB = 0 ................................................................................. 9-59

MRxF/B = Rn/Rn = MRxF/B ..................................................... 9-60

Fn = Fx * Fy ............................................................................... 9-62

Shifter Operations ...................................................................... 9-62

Shifter Opcodes .................................................................... 9-62

Rn = LSHIFT Rx BY Ry

Rn = LSHIFT Rx BY <data8> .................................................. 9-64

Rn = Rn OR LSHIFT Rx BY Ry

Rn = Rn OR LSHIFT Rx BY <data8> ...................................... 9-65

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Rn = ASHIFT Rx BY Ry

Rn = ASHIFT Rx BY <data8> .................................................. 9-66

Rn = Rn OR ASHIFT Rx BY Ry

Rn = Rn OR ASHIFT Rx BY <data8> ...................................... 9-67

Rn = ROT Rx BY Ry

Rn = ROT Rx BY <data8> ........................................................ 9-68

Rn = BCLR Rx BY Ry

Rn = BCLR Rx BY <data8> ...................................................... 9-69

Rn = BSET Rx BY Ry

Rn = BSET Rx BY <data8> ....................................................... 9-70

Rn = BTGL Rx BY Ry

Rn = BTGL Rx BY <data8> ...................................................... 9-71

BTST Rx BY Ry

BTST Rx BY <data8> ............................................................... 9-72

Rn = FDEP Rx BY Ry

Rn = FDEP Rx BY <bit6>:<len6> ............................................. 9-73

Rn = Rn OR FDEP Rx BY Ry

Rn = Rn OR FDEP Rx BY <bit6>:<len6> ................................. 9-75

Rn = FDEP Rx BY Ry (SE)

Rn = FDEP Rx BY <bit6>:<len6> (SE) ..................................... 9-77

Rn = Rn OR FDEP Rx BY Ry (SE)

Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) ......................... 9-79

Rn = FEXT Rx BY Ry

Rn = FEXT Rx BY <bit6>:<len6> ............................................. 9-81

Rn = FEXT Rx BY Ry (SE)

Rn = FEXT Rx BY <bit6>:<len6> (SE) ..................................... 9-83

Rn = EXP Rx .............................................................................. 9-85

Rn = EXP Rx (EX) ...................................................................... 9-86

ADSP-2136x SHARC Processor Programming Reference xix

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Rn = LEFTZ Rx ......................................................................... 9-87

Rn = LEFTO Rx ......................................................................... 9-88

Rn = FPACK Fx ......................................................................... 9-89

Fn = FUNPACK Rx ................................................................... 9-90

Multifunction Computations ...................................................... 9-91

Operand Constraints ............................................................. 9-91

Parallel Add and Subtract ............................................................ 9-93

Parallel Multiplier and ALU ........................................................ 9-95

Parallel Multiplier With Add and Subtract ................................... 9-98

INSTRUCTION SET QUICK REFERENCE

Chapter Overview ........................................................................ A-1

Compute and Move/Modify Summary .......................................... A-2

Program Flow Control Summary ................................................... A-4

Immediate Move Summary ........................................................... A-5

Miscellaneous Operations Summary .............................................. A-7

Register Types Summary ............................................................... A-9

Memory Addressing Summary .................................................... A-13

Instruction Set Notation Summary .............................................. A-14

Conditional Execution Codes Summary ...................................... A-16

SISD/SIMD Conditional Testing Summary ................................. A-18

Instruction Opcode Acronym Summary ...................................... A-19

Universal Register Codes ............................................................. A-23

ADSP-2136x Instruction Opcode Map ....................................... A-28

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REGISTERS

Control and Status System Registers ............................................. B-2

Mode Control 1 Register (MODE1) ....................................... B-3

Mode Mask Register (MMASK) .............................................. B-7

Mode Control 2 Register (MODE2) ..................................... B-11

Arithmetic Status Registers (ASTATx and ASTATy) ............... B-12

Sticky Status Registers (STKYx and STKYy) .......................... B-17

User-Defined Status Registers (USTATx) .............................. B-21

Processing Element Registers ...................................................... B-22

Data File Data Registers (Rx, Fx, Sx) ..................................... B-22

Multiplier Results Registers (MRFx, MRBx) ......................... B-22

Program Memory Bus Exchange Register (PX) ...................... B-23

Program Sequencer Registers ...................................................... B-24

Flag Value Register (FLAGS) ................................................ B-25

Program Counter Register (PC) ............................................ B-30

Program Counter Stack Register (PCSTK) ............................ B-30

Program Counter Stack Pointer Register (PCSTKP) .............. B-31

Fetch Address Register (FADDR) .......................................... B-31

Decode Address Register (DADDR) ...................................... B-32

Loop Address Stack Register (LADDR) ................................. B-32

Current Loop Counter Register (CURLCNTR) .................... B-32

Loop Counter Register (LCNTR) ......................................... B-33

Timer Period Register (TPERIOD) ....................................... B-33

Timer Count Register (TCOUNT) ....................................... B-33

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Data Address Generator Registers ................................................ B-34

Index Registers (Ix) ............................................................... B-34

Modify Registers (Mx) .......................................................... B-34

Length and Base Registers (Lx, Bx) ........................................ B-34

Timer Registers .......................................................................... B-35

Timer Configuration Registers (TMxCTL) ............................ B-35

Timer Counter Registers (TMxCNT) .................................... B-36

Timer Period Registers (TMxPRD) ........................................ B-36

Timer Width Register (TMxW) ............................................ B-37

Timer Global Status and Control Register (TMSTAT) ........... B-37

Power Management Registers ...................................................... B-38

Power Management Control Register (PMCTL) .................... B-38

Revision ID Register (REVPID) ............................................ B-42

I/O Processor Registers ............................................................... B-43

GLOSSARY

INDEX

xxii ADSP-2136x SHARC Processor Programming Reference

PREFACE

Thank you for purchasing and developing systems using the ADSP-2136x

SHARC® processor from Analog Devices.

Purpose of This Manual

The ADSP-2136x SHARC Processor Programming Reference provides archi-

tectural and programming information about the ADSP-2136x SHARC

processor. The architectural descriptions cover the processor’s functional

blocks and buses, including features and processes that they support. The

programming information covers the Instruction Set and Compute opera-

tions. The companions to this manual are the ADSP-2136x SHARC

Processor Hardware Reference for the ADSP-21362/3/4/5/6 Processors and

the ADSP-2136x SHARC Processor Hardware Reference for the

ADSP-21367/8/9 Processors. These manuals provide information on the

I/O capabilities and peripherals supported on these processors. For tim-

ing, electrical, and package specifications, see the processor specific data

sheet listed in “Related Documents” on page xxix.

Intended Audience

The primary audience for this manual is a programmer who is familiar

with Analog Devices processors. This manual assumes that the audience

has a working knowledge of the appropriate processor architecture and

instruction set. Programmers who are unfamiliar with Analog Devices

ADSP-2136x SHARC Processor Programming Reference xxiii

Manual Contents

processors can use this manual, but should supplement it with other texts
(such as the appropriate hardware reference manuals and data sheets) that
describe your target architecture.

Manual Contents

This manual provides detailed information about the ADSP-2136x pro­cessor family in the following chapters:

• Chapter 1, “Introduction”
Provides an architectural overview of the ADSP-2136x processors.

• Chapter 2, “Processing Elements”
Describes the arithmetic/logic units (ALUs), multiplier/accumula­tor units, and shifter. The chapter also discusses data formats, data
types, and register files.

• Chapter 3, “Program Sequencer”
Describes the operation of the program sequencer, which controls
program flow by providing the address of the next instruction to be
executed. The chapter also discusses loops, subroutines, jumps,
interrupts, exceptions, and the IDLE instruction.

• Chapter 4, “Data Address Generators”
Describes the Data Address Generators (DAGs), addressing modes,
how to modify DAG and pointer registers, memory address align­ment, and DAG instructions.

• Chapter 5, “Memory”
Describes aspects of processor memory including internal memory,
address and data bus structure, and memory accesses.

xxiv ADSP-2136x SHARC Processor Programming Reference

Preface

• Chapter 6, “JTAG Test Emulation Port”
Discusses the JTAG standard and how to use the ADSP-2136x
processors in a test environment. Includes boundary-scan architec­ture, instruction and boundary registers, and breakpoint control
registers.

• Chapter 7 “Timer”
Describes the three general purpose timers that can be configured
in any of three modes: pulse width modulation, pulse width count
and capture, and external event watchdog modes.

• Chapter 8, “Instruction Set”
Provides reference information for the machine language opcode
for the processor.

• Chapter 9, “Computations Reference”
Describes each compute operation in detail, including its assembly
language syntax and opcode field. Compute operations execute in
the multiplier, the ALU, and the shifter.

• Appendix A, “Instruction Set Quick Reference”
The instruction set summary provides a syntax summary for each
instruction and includes a cross reference to each instruction’s ref­erence page.

• Appendix B, “Registers”
Provides register and bit descriptions for all of the registers that are
used to control the operation of the ADSP-2136x processor core.

L

ADSP-2136x SHARC Processor Programming Reference xxv

This programming reference is a companion document to the

ADSP-2136x SHARC Processor Hardware Reference for the
ADSP-21362/3/4/5/6 Processors and the ADSP-2136x SHARC Pro­cessor Hardware Reference for the ADSP-21367/8/9 Processors.

What’s New in This Manual

What’s New in This Manual

This is revision 1.1 of the ADSP-2136x SHARC Processor Programming
Reference. The only changes for this revisions are corrections to cross references

(and links in the online version of the book).

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

xxvi ADSP-2136x SHARC Processor Programming Reference

Preface

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and fixed-point
[8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the
following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

SHARC (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, and
ADSP-2136x.

Blackfin® (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin families:
ADSP-BF53x and ADSP-BF56x.

Product Information

You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at
mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.

ADSP-2136x SHARC Processor Programming Reference xxvii

www.analog.com. Our Web site provides infor-

Product Information

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.

Registration

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as a means to select the
information you want to receive.

If you are already a registered user, just log on. Your user name is your
e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product
announcements.

You may also obtain additional information about Analog Devices and its
products in any of the following ways.

• E-mail questions or requests for information to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

xxviii ADSP-2136x SHARC Processor Programming Reference

Preface

• Fax questions or requests for information to

1-781-461-3010 (North America)
[phone] (Europe)

• Access the FTP Web site at

ftp ftp.analog.com (or ftp 137.71.25.69)
ftp://ftp.analog.com

Related Documents

The following publications that describe the ADSP-2136x processors can
be ordered from any Analog Devices sales office:

• ADSP-21362 SHARC Processor Data Sheet

• ADSP-21363 SHARC Processor Data Sheet

• ADSP-21364 SHARC Processor Data Sheet

• ADSP-21365 SHARC Processor Data Sheet

• ADSP-21366 SHARC Processor Data Sheet

• ADSP-21367 SHARC Processor Preliminary Data Sheet

• ADSP-21368 SHARC Processor Preliminary Data Sheet

• ADSP-21369 SHARC Processor Preliminary Data Sheet

• ADSP-2136x SHARC Processor Hardware Reference for the
ADSP-21362/3/4/5/6 Processors

• ADSP-2136x SHARC Processor Hardware Reference for the
ADSP-21367/8/9 Processors

ADSP-2136x SHARC Processor Programming Reference xxix

Product Information

For information on product related development software and Analog
Devices processors, see these publications:

• VisualDSP++ User’s Guide

• VisualDSP++ C/C++ Compiler and Library Manual

• VisualDSP++ Assembler and Preprocessor Manual

• VisualDSP++ Linker and Utilities Manual

• VisualDSP++ Kernel (VDK) User’s Guide

Visit the Technical Library Web site to access all processor and tools
manuals and data sheets:

http://www.analog.com/processors/resources/technicalLibrary

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are also provided.

Each documentation file type is described as follows.

File Description

.CHM Help system files and manuals in Help format

.HTM or
.HTML

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Dinkum Abridged C++ library and FlexLM network license manager software doc­umentation. Viewing and printing the .HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).

Viewing and printing the
Reader (4.0 or higher).

.PDF files requires a PDF reader, such as Adobe Acrobat

xxx ADSP-2136x SHARC Processor Programming Reference