ANALOG DEVICES ADSP-21367 Service Manual

ADSP-21368 SHARC® Processor

Hardware Reference

Includes ADSP-21367, ADSP-21369,

ADSP-21371, ADSP-21375

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 1.0, September 2006

Part Number

82-000100-01

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo and icon bar, Blackfin, EZ-KIT Lite, SHARC, the SHARC logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

PREFACE

Purpose of This Manual ............................................................... xxxi

Intended Audience ....................................................................... xxxi

Manual Contents ........................................................................ xxxii

What’s New in This Manual ....................................................... xxxiv

Technical or Customer Support ................................................... xxxv

Supported Processors .................................................................. xxxvi

Product Information .................................................................. xxxvi

MyAnalog.com .................................................................... xxxvii

Processor Product Information ............................................. xxxvii

Related Documents ............................................................ xxxviii

Online Technical Documentation ......................................... xxxix

Printed Manuals ....................................................................... xli

Conventions ................................................................................ xliii

INTRODUCTION

Design Advantages ........................................................................ 1-1

Architectural Overview ................................................................. 1-6

Processor Core ......................................................................... 1-7

ADSP-21368 SHARC Processor Hardware Reference iii

Contents

Processor Peripherals ............................................................... 1-7

I/O Processor ..................................................................... 1-7

Digital Audio Interface (DAI) ............................................. 1-9

Digital Peripheral Interface (DPI) ..................................... 1-10

Development Tools ..................................................................... 1-10

Differences From Previous Processors .......................................... 1-11

I/O Architecture Enhancements ............................................ 1-11

Instruction Set Enhancements ............................................... 1-12

I/O PROCESSOR

General Procedure for Configuring DMA ...................................... 2-2

Core Access to IOP Registers ........................................................ 2-3

Configuring IOP/Core Interaction ................................................ 2-6

Interrupt-Driven I/O .............................................................. 2-6

Interrupt Latency in Interrupt-Driven Transfers ................ 2-11

Polling/Status-Driven I/O ..................................................... 2-12

DMA Controller Operation .................................................. 2-13

Chaining DMA Processes .................................................. 2-14

Transfer Control Block Chain Loading (TCB) ................... 2-16

Setting Up DMA Channel Allocation and Priorities ............... 2-18

Managing DMA Channel Priority ..................................... 2-19

DMA Bus Arbitration ....................................................... 2-20

Setting Up DMA Parameter Registers .......................................... 2-24

DMA Transfer Direction ....................................................... 2-24

Data Buffer Registers ............................................................ 2-25

iv ADSP-21368 SHARC Processor Hardware Reference

Contents

Port, Buffer, and DMA Control Registers ............................... 2-26

Addressing ............................................................................ 2-29

External Port DMA ..................................................................... 2-35

Setting Up and Starting Chained DMA .................................. 2-36

Delay Line DMA ................................................................... 2-38

Serial Port DMA ......................................................................... 2-40

Setting Up and Starting Chained DMA .................................. 2-40

Inserting a TCB in an Active Chain ....................................... 2-41

Serial Peripheral Interface DMA .................................................. 2-42

Setting Up and Starting Chained DMA over the SPI .............. 2-42

UART DMA ............................................................................... 2-44

Notes On Using DMA With the UART ................................. 2-47

Memory-to-Memory DMA ......................................................... 2-48

Summary .................................................................................... 2-48

Programming Example ................................................................ 2-49

EXTERNAL PORT

External Memory Interface ............................................................ 3-2

External Memory Interface on the ADSP-2137x Processors ...... 3-3

Direct Execution of Instructions From External Memory ..... 3-3

Throughput and Instruction Execution Rate ........................ 3-3

Location of Interrupt Vector Table (IVT) ............................ 3-4

Instruction Cache ............................................................... 3-5

Instruction Storage and Packing .......................................... 3-9

ADSP-21368 SHARC Processor Hardware Reference v

Contents

EMI Registers and Signals ..................................................... 3-16

External Port Arbitration Logic ......................................... 3-18

Channel Freezing .............................................................. 3-18

Managing Data Paths ........................................................ 3-18

External Memory Interface Pins ............................................ 3-19

Asynchronous Memory Interface ................................................. 3-20

AMI Timing Control .................................................................. 3-21

Wait States ............................................................................ 3-21

Bus Idle Cycles ...................................................................... 3-22

Bus Hold Cycles .................................................................... 3-23

Setting AMI Modes .................................................................... 3-24

External Memory Reads ........................................................ 3-25

Data Packing .................................................................... 3-25

External Memory Writes ....................................................... 3-26

Data Packing .................................................................... 3-27

Read/Write Throughput ........................................................ 3-28

External Access Addressing .................................................... 3-28

External Port DMA ............................................................... 3-30

Booting Through the AMI .................................................... 3-30

SDRAM Controller .................................................................... 3-30

Definition of Terms .............................................................. 3-31

Timing External Memory Accesses ......................................... 3-36

Parallel Connection of SDRAMs ........................................... 3-39

SDRAM Control Register (SDCTL) ...................................... 3-39

vi ADSP-21368 SHARC Processor Hardware Reference

Contents

SDRAM Control Status Register (SDSTAT) ........................... 3-49

SDRAM Refresh Rate Control Register (SDRRC) .................. 3-49

SDRAM Initialization ........................................................... 3-51

SDRAM Address Mapping .................................................... 3-51

SDRAM Controller Address Mapping ............................... 3-58

SDC Operation ..................................................................... 3-58

Single Bank Operation ...................................................... 3-60

Multibank Operation (ADSP-2137x Processors) ................ 3-60

Data Mask (DQM) ........................................................... 3-61

SDC Configuration ............................................................... 3-61

SDC Commands ................................................................... 3-63

Load Mode Register .......................................................... 3-64

Single Bank Activation ...................................................... 3-65

Multibank Activation (ADSP-2137x Processors) ................ 3-66

Single Precharge (ADSP-2137x Processors) ........................ 3-66

Precharge All ..................................................................... 3-66

Read/Write ....................................................................... 3-67

Read/Write (ADSP-2137x Processors) ............................... 3-69

Burst Stop (ADSP-2137x Processors) ................................. 3-69

Auto-Refresh ..................................................................... 3-70

Self-Refresh Mode ............................................................. 3-70

No Operation/Command Inhibit ...................................... 3-71

Changing System Clock During Runtime .......................... 3-73

ADSP-21368 SHARC Processor Hardware Reference vii

Contents

SDRAM Timing ................................................................... 3-74

SDRAM Read Optimization ............................................. 3-75

External Memory Access Restrictions ................................ 3-78

Shared Memory Interface ............................................................ 3-79

Shared Memory Bus Arbitration ............................................ 3-79

Bus Arbitration Protocol ................................................... 3-82

Bus Arbitration Priority (RPBA) ....................................... 3-86

Bus Mastership Time-out .................................................. 3-87

Bus Synchronization After Reset ............................................ 3-88

Bus Synchronization Notes ............................................... 3-91

Bus Lock and Semaphores ..................................................... 3-92

Shared Memory Interface Status ........................................ 3-93

Shared Memory and the SDRAM Controller ......................... 3-94

Shared Memory Booting ....................................................... 3-94

DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES

Structure of the Interfaces ............................................................. 4-2

DAI/DPI System Design ............................................................... 4-3

Signal Routing Units .................................................................... 4-8

Connecting Peripherals ........................................................... 4-8

Pin Interface ......................................................................... 4-10

Pin Buffers as Signal Output Pins .......................................... 4-11

Pin Buffers as Signal Input Pins ............................................. 4-12

Bidirectional Pin Buffers ....................................................... 4-13

viii ADSP-21368 SHARC Processor Hardware Reference

Contents

Making Connections in the SRUs ................................................ 4-15

DAI/SRU1 Connection Groups ............................................. 4-18

Group A Connections—Clock Signals ............................... 4-19

Group B Connections—Data Signals ................................. 4-25

Group C Connections—Frame Sync Signals ...................... 4-31

Group D Connections—Pin Signal Assignments ................ 4-36

Group E Connections—Interrupts and Miscellaneous

Signals ........................................................................... 4-43

Group F—Pin Enable Signals ............................................ 4-47

DPI/SRU2 Connection Groups ............................................. 4-51

Group A Connections—Input Routing Signals .................. 4-52

Group B Connections—Pin Assignment Signals ............... 4-56

Group C Connections—Pin Enable Signals ...................... 4-60

General-Purpose I/O (GPIO) and Flags ....................................... 4-64

DAI GPIO and Flags ............................................................. 4-64

DPI GPIO and Flags ............................................................. 4-65

Miscellaneous Signals .................................................................. 4-65

DAI/DPI Interrupt Controller ..................................................... 4-65

Relationship to the Core ........................................................ 4-65

DAI Interrupts ...................................................................... 4-66

DPI Interrupts ...................................................................... 4-67

High and Low Priority Latches .............................................. 4-69

Rising and Falling Edge Masks ............................................... 4-70

ADSP-21368 SHARC Processor Hardware Reference ix

Contents

Configuring Peripherals Using SRU1 .......................................... 4-71

Configuring the SPORTs ...................................................... 4-71

Configuring the PCGs .......................................................... 4-72

Configuring Peripherals Using SRU2 .......................................... 4-72

Configuring the SPI .............................................................. 4-72

Choosing the Pin Enable for the SPI Clock ....................... 4-72

Configuring the Two Wire Interface ...................................... 4-73

Using the SRU() Macro to Configure

the DAI ................................................................................... 4-76

SERIAL PORTS

Features ........................................................................................ 5-2

Operation Modes ......................................................................... 5-3

Serial Port Signals ......................................................................... 5-5

Serial Port Signal Sensitivity .................................................... 5-9

SPORT Operation Modes ........................................................... 5-10

Standard DSP Serial Mode .................................................... 5-12

Standard DSP Serial Mode Control Bits ............................ 5-13

Clocking Options ............................................................. 5-13

Frame Sync Options ......................................................... 5-13

Data Formatting ............................................................... 5-14

Data Transfers .................................................................. 5-15

Status Information ............................................................ 5-15

Left-Justified Sample Pair Mode ............................................ 5-16

Setting the Internal Serial Clock and Frame Sync Rates ..... 5-17

x ADSP-21368 SHARC Processor Hardware Reference

Contents

Left-Justified Sample Pair Mode Control Bits ..................... 5-17

Setting Word Length (SLEN) ............................................ 5-17

Enabling SPORT Master Mode (MSTR) ........................... 5-18

Selecting Transmit and Receive Channel Order (FRFS) ...... 5-18

Selecting Frame Sync Options (DIFS) ............................... 5-18

Enabling SPORT DMA (SDEN) ....................................... 5-19

I2S Mode .............................................................................. 5-20

Setting the Internal Serial Clock and Frame Sync Rates ...... 5-21

I2S Mode Control Bits ...................................................... 5-21

Setting Word Length (SLEN) ............................................ 5-22

Enabling SPORT Master Mode (MSTR) ........................... 5-23

Selecting Transmit and Receive Channel Order (FRFS) ...... 5-23

Selecting Frame Sync Options (DIFS) ............................... 5-23

Enabling SPORT DMA (SDEN) ....................................... 5-24

Multichannel Operation ........................................................ 5-25

Frame Syncs in Multichannel Mode ................................... 5-28

Multichannel Mode Control Bits ....................................... 5-29

Packed I2S Mode ................................................................... 5-33

Programming Packed I2S Mode ......................................... 5-34

SPORT Loopback ................................................................. 5-35

Clock Signal Options .................................................................. 5-36

Frame Sync Options .................................................................... 5-37

Framed Versus Unframed Frame Syncs ................................... 5-37

Internal Versus External Frame Syncs ..................................... 5-38

ADSP-21368 SHARC Processor Hardware Reference xi

Contents

Active Low Versus Active High Frame Syncs .......................... 5-39

Sampling Edge for Data and Frame Syncs .............................. 5-39

Early Versus Late Frame Syncs ............................................... 5-40

Data-Independent Frame Syncs ............................................. 5-41

Frame Sync Error Detection .................................................. 5-42

Data Word Formats .................................................................... 5-43

Word Length ........................................................................ 5-43

Endian Format ...................................................................... 5-45

Data Packing and Unpacking ................................................ 5-45

Data Type ........................................................................ 5-46

Companding .................................................................... 5-47

SPORT Control Registers and Data Buffers ................................ 5-49

Serial Port Control Registers (SPCTLx) ................................. 5-59

Transmit and Receive Data Buffers

(TXSPxA/B, RXSPxA/B) .................................................... 5-67

Clock and Frame Sync Frequency Registers (DIVx) ................ 5-69

SPORT Reset ........................................................................ 5-71

SPORT Interrupts ................................................................ 5-72

Moving Data Between SPORTs and Internal Memory ................. 5-73

DMA Block Transfers ............................................................ 5-73

Setting Up DMA on SPORT Channels ............................. 5-75

SPORT DMA Parameter Registers ......................................... 5-76

SPORT DMA Chaining ................................................... 5-81

Single Word Transfers ........................................................... 5-81

xii ADSP-21368 SHARC Processor Hardware Reference

Contents

SPORT Programming Examples .................................................. 5-82

SERIAL PERIPHERAL INTERFACE PORTS

Functional Description ................................................................. 6-2

SPI Interface Signals ..................................................................... 6-4

SPI Clock Signal (SPICLK) ..................................................... 6-4

SPICLK Timing .................................................................. 6-5

SPI Slave Select Input (SPIDS) ............................................ 6-6

SPI Flag Signals (SPIFLG3-0) .................................................. 6-6

Master Out Slave In (MOSI) ................................................... 6-7

Master In Slave Out (MISO) ................................................... 6-7

SPI General Operations ................................................................. 6-8

SPI Enable .............................................................................. 6-9

Open Drain Mode (OPD) ....................................................... 6-9

Master Mode Operation ........................................................ 6-10

Slave Mode Operation ........................................................... 6-11

Multimaster Operation .......................................................... 6-12

SPI Data Transfer Operations ...................................................... 6-13

SPI Operation Using the Core ............................................... 6-13

SPI Operation Using DMA .................................................... 6-14

Master Mode DMA Operation .......................................... 6-15

Slave Mode DMA Operation ............................................. 6-19

Changing SPI Configuration ............................................. 6-21

Switching From Transmit To Receive DMA ....................... 6-23

Switching From Receive to Transmit DMA ........................ 6-24

ADSP-21368 SHARC Processor Hardware Reference xiii

Contents

DMA Error Interrupts ...................................................... 6-25

DMA Chaining ................................................................ 6-27

SPI Transfer Formats .................................................................. 6-27

Beginning and Ending an SPI Transfer .................................. 6-29

SPI Word Lengths ...................................................................... 6-31

8-Bit Word Lengths .............................................................. 6-31

16-Bit Word Lengths ............................................................ 6-32

32-Bit Word Lengths ............................................................ 6-32

Packing ................................................................................. 6-32

SPI Interrupts ............................................................................. 6-33

Error Signals and Flags ............................................................... 6-35

Mode Fault Error (MME) ..................................................... 6-35

Transmission Error Bit (TUNF) ............................................ 6-37

Reception Error Bit (ROVF) ................................................. 6-37

Transmit Collision Error Bit (TXCOL) ................................. 6-37

Programming Notes .................................................................... 6-38

Routing SPI Signals Using The DPI ...................................... 6-38

Programming Examples .............................................................. 6-38

INPUT DATA PORT

Serial Inputs ................................................................................. 7-3

Parallel Data Acquisition Port (PDAP) .......................................... 7-8

Masking .................................................................................. 7-9

Packing Unit ........................................................................... 7-9

Packing Mode 11 ................................................................ 7-9

xiv ADSP-21368 SHARC Processor Hardware Reference

Contents

Packing Mode 10 .............................................................. 7-10

Packing Mode 01 .............................................................. 7-11

Packing Mode 00 .............................................................. 7-11

Clocking Edge Selection ........................................................ 7-12

Hold Input ............................................................................ 7-12

PDAP Strobe ......................................................................... 7-14

FIFO Control and Status ............................................................ 7-15

FIFO to Memory Data Transfer ................................................... 7-16

IDP Transfers Using the Core ................................................ 7-17

Starting an Interrupt-Driven Transfer ................................ 7-18

Core Transfer Notes .......................................................... 7-19

IDP Transfers Using DMA .................................................... 7-20

Simple DMA .................................................................... 7-20

Ping-Pong DMA ............................................................... 7-22

DMA Transfer Notes ......................................................... 7-25

DMA Channel Parameter Registers ........................................ 7-27

IDP (DAI) Interrupt Service Routines for DMAs ................... 7-28

FIFO Overflow ..................................................................... 7-30

Input Data Port Programming Example ....................................... 7-31

PULSE WIDTH MODULATION

PWM Implementation .................................................................. 8-1

PWM Waveforms .................................................................... 8-1

Edge-Aligned Mode ............................................................ 8-2

Center-Aligned Mode .......................................................... 8-3

ADSP-21368 SHARC Processor Hardware Reference xv

Contents

Switching Frequencies ............................................................. 8-5

Dead Time ............................................................................. 8-6

Duty Cycles ............................................................................ 8-7

Duty Cycles and Dead Time ............................................... 8-8

Over Modulation .............................................................. 8-12

Update Modes ...................................................................... 8-15

Single Update ................................................................... 8-15

Double Update ................................................................. 8-15

Configurable Polarity ............................................................ 8-15

PWM Pins and Signals .......................................................... 8-16

Crossover ......................................................................... 8-16

PWM Accuracy ..................................................................... 8-17

PWM Registers .......................................................................... 8-18

Duty Cycles .......................................................................... 8-19

Output Enable ...................................................................... 8-20

Programming Example ................................................................ 8-21

S/PDIF TRANSMITTER/RECEIVER

AES3/SPDIF Stream Format ......................................................... 9-2

Subframe Format .................................................................... 9-3

Channel Coding ..................................................................... 9-5

Preambles ............................................................................... 9-6

S/PDIF Transmitter ...................................................................... 9-7

Channel Status ........................................................................ 9-9

SRU1 Signals for the S/PDIF Transmitter .............................. 9-10

xvi ADSP-21368 SHARC Processor Hardware Reference

Contents

S/PDIF Transmitter Registers ................................................ 9-12

Modes of Operation .............................................................. 9-12

Standalone Mode .............................................................. 9-13

Structure of the Serial Input Data .......................................... 9-14

S/PDIF Receiver ......................................................................... 9-16

S/PDIF Receiver Registers ..................................................... 9-17

SRU1 Receiver Signals ........................................................... 9-18

Phase-Locked Loop ..................................................................... 9-19

Channel Status Decoding ............................................................ 9-19

Compressed or Non-Linear Audio Data ................................. 9-20

Emphasized Audio Data ........................................................ 9-21

Single-Channel, Double-Sampling Frequency Mode ............... 9-21

Error Handling ........................................................................... 9-22

Interrupts ................................................................................... 9-24

DAI Programming Examples ....................................................... 9-24

S/PDIF Transmitter Programming Guidelines ........................ 9-24

Control Register ............................................................... 9-24

SRU1 Programming for Input and Output Streams ............ 9-25

Control Register Programming and Enable ........................ 9-25

S/PDIF Receiver Programming Guidelines ............................. 9-25

Control Register ............................................................... 9-25

SRU1 Programming .......................................................... 9-26

Control Register Programming .......................................... 9-26

Receiver Locking ............................................................... 9-26

ADSP-21368 SHARC Processor Hardware Reference xvii

Contents

Status Bits ........................................................................ 9-26

Interrupted Data Streams on the Receiver .......................... 9-27

ASYNCHRONOUS SAMPLE RATE CONVERTER

Theory of Operation .................................................................. 10-2

Conceptual Model ................................................................ 10-4

Hardware Model ................................................................... 10-7

Sample Rate Converter Architecture ............................................ 10-8

Group Delay ....................................................................... 10-12

SRC Operation ......................................................................... 10-12

Enabling the SRC ............................................................... 10-13

Serial Data Ports ................................................................. 10-13

Data Format ................................................................... 10-13

Time-Division Multiplex (TDM) Output Mode .............. 10-15

TDM Input Mode .......................................................... 10-16

Matched-Phase Mode ..................................................... 10-16

Bypass Mode .................................................................. 10-18

De-Emphasis Filter ............................................................. 10-18

Mute Control ..................................................................... 10-19

Soft Mute ....................................................................... 10-20

Hard Mute ..................................................................... 10-20

Auto Mute ...................................................................... 10-20

SRC Registers ........................................................................... 10-21

Programming the SRC Module ................................................. 10-22

SRC Control Register Programming .................................... 10-22

xviii ADSP-21368 SHARC Processor Hardware Reference

Contents

SRU Programming .............................................................. 10-22

SRC Mute-Out Interrupt ..................................................... 10-23

Sample Rate Ratio ............................................................... 10-23

Programming Summary ....................................................... 10-23

UART PORT CONTROLLER

Serial Communications ............................................................... 11-2

UART Control and Status Registers ............................................. 11-3

UARTxLCR Registers ............................................................ 11-3

UARTxLSR Register .............................................................. 11-4

UARTxTHR Register ............................................................ 11-4

UARTxRBR Register ............................................................. 11-5

UARTxIER Register .............................................................. 11-7

UARTxIIR Register ............................................................... 11-9

UARTxDLL and UARTxDLH Registers .............................. 11-11

UARTxSCR Register ........................................................... 11-12

UARTxMODE Register ...................................................... 11-13

I/O Mode ................................................................................. 11-13

Packing Mode ........................................................................... 11-15

TWO WIRE INTERFACE CONTROLLER

Overview .................................................................................... 12-1

Architecture ................................................................................ 12-2

TWI Master Internal Time Register ....................................... 12-4

ADSP-21368 SHARC Processor Hardware Reference xix

Contents

TWIDIV Register ................................................................. 12-5

Slave Mode Control Register ................................................. 12-5

Slave Mode Address Register ................................................. 12-6

Slave Mode Status Register .................................................... 12-6

Master Mode Control Register .............................................. 12-6

Master Mode Address Register ............................................... 12-6

Master Mode Status Register ................................................. 12-7

FIFO Control Register .......................................................... 12-7

FIFO Status Register ............................................................. 12-7

Interrupt Source Register ...................................................... 12-7

Interrupt Enable Register ...................................................... 12-8

8-Bit Transmit FIFO Register ................................................ 12-8

16-Bit Transmit FIFO Register .............................................. 12-8

8-Bit Receive FIFO Register .................................................. 12-9

16-Bit Receive FIFO Register .............................................. 12-10

Data Transfer Mechanics ........................................................... 12-10

Clock Generation and Synchronization ................................ 12-11

Bus Arbitration ................................................................... 12-12

Start and Stop Conditions ................................................... 12-12

General Call Support .......................................................... 12-14

Fast Mode ........................................................................... 12-14

Programming Examples ............................................................ 12-15

General Setup ..................................................................... 12-15

Slave Mode ......................................................................... 12-15

xx ADSP-21368 SHARC Processor Hardware Reference

Contents

Master Mode Clock Setup ................................................... 12-17

Master Mode Transmit ........................................................ 12-17

Master Mode Receive ........................................................... 12-18

Repeated Start Condition .................................................... 12-19

Transmit/Receive Repeated Start Sequence ....................... 12-19

Receive/Transmit Repeated Start Sequence ....................... 12-21

Electrical Specifications ............................................................. 12-22

PRECISION CLOCK GENERATORS

Clock Outputs ............................................................................ 13-3

Frame Sync Outputs ................................................................... 13-4

Normal Mode ........................................................................ 13-5

Bypass Mode ......................................................................... 13-6

Frame Sync Output Synchronization With an External Clock ...... 13-7

Frame Sync ........................................................................... 13-8

Phase Shift .................................................................................. 13-9

Phase Shift Settings ............................................................. 13-10

Pulse Width ........................................................................ 13-10

Bypass Mode ....................................................................... 13-12

Bypass as a Pass Through ................................................. 13-12

Bypass as a One-Shot ...................................................... 13-13

Programming Examples ............................................................. 13-14

PCG Setup for I2S or Left-Justified DAI .............................. 13-15

Clock and Frame Sync Divisors PCG Channel B .................. 13-20

PCG Channel A and B Output Example .............................. 13-23

ADSP-21368 SHARC Processor Hardware Reference xxi

Contents

SYSTEM DESIGN

Processor Pin Descriptions .......................................................... 14-2

Pin Multiplexing ................................................................... 14-2

Choosing EP Data Mode .................................................. 14-6

Interrupt and Timer Pins ...................................................... 14-8

Core-Based Flag Pins ............................................................. 14-8

Programming Flags ........................................................... 14-9

RESETOUT/CLKOUT/RUNRSTIN ............................. 14-12

JTAG Interface Pins ............................................................ 14-12

Clock Derivation ...................................................................... 14-13

Power Management Control Register ................................... 14-14

PLL Programming Examples ........................................... 14-16

Phase-Locked Loop Startup ................................................. 14-19

RESET and CLKIN ............................................................ 14-20

Running Reset (ADSP-2137x) ............................................ 14-22

System Design Considerations ........................................ 14-23

Running Reset Control Register (RUNRSTCTL) ............ 14-25

Programming The RUNRSTCTL Register ...................... 14-26

Reset Generators ............................................................. 14-27

Timing Specifications .......................................................... 14-28

Input Synchronization Delay ............................................... 14-32

Conditioning Input Signals ....................................................... 14-32

RESET Input Hysteresis ...................................................... 14-33

xxii ADSP-21368 SHARC Processor Hardware Reference

Contents

Designing for High Frequency Operation .................................. 14-33

Clock Specifications and Jitter ............................................. 14-33

Other Recommendations and Suggestions ............................ 14-34

Decoupling Capacitors and Ground Planes .......................... 14-35

Oscilloscope Probes ............................................................. 14-35

Recommended Reading ....................................................... 14-36

Booting .................................................................................... 14-37

External Port Booting .......................................................... 14-39

Booting Through the AMI .............................................. 14-39

Shared Memory Booting ................................................. 14-40

SPI Port Booting ................................................................. 14-42

32-Bit SPI Host Boot ...................................................... 14-43

16-Bit SPI Host Boot ...................................................... 14-44

8-Bit SPI Host Boot ........................................................ 14-46

Slave Boot Mode ............................................................. 14-47

Master Boot .................................................................... 14-48

Booting From an SPI Flash .............................................. 14-51

Booting From an SPI PROM (16-Bit address) .................. 14-52

Booting From an SPI Host Processor ............................... 14-52

Data Delays, Latencies, and Throughput ................................... 14-52

Execution Stalls ................................................................... 14-53

DAG Stalls .......................................................................... 14-54

Memory Stalls ..................................................................... 14-54

IOP Register Stalls ............................................................... 14-55

ADSP-21368 SHARC Processor Hardware Reference xxiii

Contents

DMA Stalls ......................................................................... 14-56

IOP Buffer Stalls ................................................................. 14-56

I/O Processor Registers ................................................................. A-2

Notes on Reading Register Drawings ....................................... A-3

System Control Register (SYSCTL) ......................................... A-5

System Status Register (SYSTAT) ............................................ A-9

External Port Registers ................................................................ A-10

External Port Control Register (EPCTL) ............................... A-10

External Port DMA Control Registers (DMACx) ................... A-14

AMI Control Registers (AMICTLx) ...................................... A-17

AMI Status Register (AMISTAT) ........................................... A-20

SDRAM Control Register (SDCTL) ...................................... A-21

SDRAM Control Status Register (SDSTAT) .......................... A-26

SDRAM Refresh Rate Control Register (SDRRC) .................. A-26

Memory-to-Memory DMA Register ............................................ A-28

Serial Port Registers .................................................................... A-29

SPORT Serial Control Registers (SPCTLx) ............................ A-29

SPORT Multichannel Control Registers (SPMCTLx) ............ A-40

SPORT Transmit Buffer Registers (TXSPx) ........................... A-43

SPORT Receive Buffer Registers (RXSPx) .............................. A-44

SPORT Divisor Registers (DIVx) .......................................... A-44

SPORT Count Registers (SPCNTx) ...................................... A-45

SPORT Active Channel Select Registers (SPxCSy) ................. A-46

xxiv ADSP-21368 SHARC Processor Hardware Reference

Contents

SPORT Compand Registers (SPxCCSy) ................................ A-47

SPORT Error Control Register (SPERRCTLx) ...................... A-48

SPORT Error Status Register (SPERRSTAT) ......................... A-49

SPORT DMA Index Registers (IISPx) ................................... A-50

SPORT DMA Modifier Registers (IMSPx) ............................ A-50

SPORT DMA Count Registers (CSPx) ................................. A-51

SPORT Chain Pointer Registers (CPSPx) .............................. A-51

Serial Peripheral Interface Registers ............................................. A-52

SPI Control Registers (SPICTL, SPICTLB) .......................... A-52

SPI Port Status (SPISTAT, SPISTATB) Registers ................... A-56

SPI Port Flags Registers (SPIFLG, SPIFLGB) ........................ A-58

SPI Receive Buffer Registers (RXSPI, RXSPIB) ..................... A-59

RXSPI Shadow Registers

(RXSPI_SHADOW, RXSPIB_SHADOW) ......................... A-59

SPI Transmit Buffer Registers (TXSPI, TXSPIB) ................... A-59

SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) ................ A-60

SPI DMA Registers .............................................................. A-61

SPI DMA Configuration Registers (SPIDMAC,

SPIDMACB) ................................................................ A-62

SPI DMA Start Address Registers (IISPI, IISPIB) .............. A-64

SPI DMA Address Modify Registers (IMSPI, IMSPIB) ..... A-64

SPI DMA Word Count Registers (CSPI, CSPIB) .............. A-64

SPI DMA Chain Pointer Registers (CPSPI, CPSPIB) ........ A-65

Input Data Port Registers ........................................................... A-65

Input Data Port Control Register 0 (IDP_CTL0) .................. A-66

ADSP-21368 SHARC Processor Hardware Reference xxv

Contents

Input Data Port Control Register 1 (IDP_CTL1) .................. A-68

Input Data Port FIFO Register (IDP_FIFO) .......................... A-69

Input Data Port DMA Control Registers ............................... A-70

IDP_DMA_Ix .................................................................. A-70

IDP_DMA_Mx ................................................................ A-71

IDP_DMA_Cx ................................................................. A-71

Input Data Port Ping-Pong DMA Registers ............................ A-72

IDP Ping-Pong Index Registers (IDP_DMA_IxA) ............. A-72

IDP Ping-Pong Count Registers (IDP_DMA_PCx) ........... A-73

Parallel Data Acquisition Port Control Register

(IDP_PP_CTL) ................................................................. A-74

Pulse Width Modulation Registers .............................................. A-78

PWM Global Control Register (PWMGCTL) ....................... A-78

PWM Global Status Register (PWMGSTAT) ......................... A-79

PWM Control Register (PWMCTLx) .................................... A-80

PWM Status Registers (PWMSTATx) .................................... A-81

PWM Period Registers (PWMPERIODx) .............................. A-81

PWM Output Disable Registers (PWMSEGx) ....................... A-82

PWM Polarity Select Registers (PWMPOLx) ......................... A-83

PWM Channel Duty Control Registers

(PWMAx, PWMBx) ........................................................... A-84

PWM Channel Low Duty Control Registers

(PWMALx, PWMBLx) ...................................................... A-84

PWM Dead Time Registers (PWMDTx) ............................... A-85

xxvi ADSP-21368 SHARC Processor Hardware Reference

Contents

Sony/Philips Digital Interface Registers ...................................... A-86

Transmitter Control Register (DITCTL) ............................... A-86

Left Channel Status for Subframe A

Registers (DITCHANAx) .................................................. A-89

Right Channel Status for Subframe B

Registers (DITCHANBx) .................................................. A-90

User Bits Buffer Registers for Subframe A

Registers (DITUSRBITAx) ................................................ A-90

User Bits Buffer Registers for Subframe B

Registers (DITUSRBITBx) ................................................ A-91

Receiver Control Register (DIRCTL) .................................... A-92

Receiver Status Register (DIRSTAT) ..................................... A-94

Left Channel Status for Subframe A

Right Channel Status for Subframe B

Sample Rate Converter Registers ................................................ A-97

SRC Control Registers (SRCCTLx) ...................................... A-97

SRC Mute Register (SRCMUTE) ....................................... A-107

SRC Ratio Registers (SRCRATx) ........................................ A-108

DAI/DPI Registers ................................................................... A-109

Digital Audio Interface Status Register (DAI_STAT) ........... A-109

DAI Resistor Pull-up Enable Register

(DAI_PIN_PULLUP) ...................................................... A-111

DAI Pin Buffer Status Register (DAI_PIN_STAT) .............. A-112

DAI Interrupt Controller Registers ..................................... A-112

ADSP-21368 SHARC Processor Hardware Reference xxvii

Contents

DPI Resistor Pull-up Enable Register

(DPI_PIN_PULLUP) ...................................................... A-115

DPI Pin Buffer Status Register (DPI_PIN_STAT) ................ A-116

DPI Interrupt Controller Registers ...................................... A-116

UART Control and Status Registers .......................................... A-118

Line Control Registers (UARTxLCR) .................................. A-118

Line Status Registers (UARTxLSR) ...................................... A-120

Transmit Hold Registers (UARTxTHR) ............................... A-121

Receive Buffer Registers (UARTxRBR) ................................ A-122

Interrupt Enable Registers (UARTxIER) .............................. A-123

Interrupt Identification Registers (UARTxIIR) ..................... A-124

Divisor Latch Registers (UARTxDLL, UARTxDLH) ........... A-125

Scratch Registers (UARTxSCR) ........................................... A-126

Mode Registers (UARTxMODE) ......................................... A-126

UART DMA Registers ........................................................ A-127

DMA Control Registers (UARTxTXCTL,

UARTxRXCTL) .......................................................... A-128

DMA Status Registers (UARTxTXSTAT,

UARTxRXSTAT) ........................................................ A-129

Two Wire Interface Registers ..................................................... A-130

Master Internal Time Register (TWIMITR) ........................ A-131

Clock Divider Register (TWIDIV) ...................................... A-132

Slave Mode Control Register (TWISCTL) ........................... A-133

Slave Address Register (TWISADDR) ................................. A-135

Slave Status Register (TWISSTAT) ...................................... A-135

xxviii ADSP-21368 SHARC Processor Hardware Reference

Contents

Master Control Register (TWIMCTL) ................................ A-136

Master Address Register (TWIMADDR) ............................. A-139

Master Status Register (TWIMSTAT) ................................. A-140

FIFO Control Register (TWIFIFOCTL) ............................. A-143

FIFO Status Register (TWIFIFOSTAT) .............................. A-145

Interrupt Source Register (TWIIRPTL) .............................. A-147

Interrupt Enable Register (TWIIMASK) ............................. A-150

8-Bit Transmit FIFO Register (TXTWI8) ........................... A-152

16-Bit Transmit FIFO Register (TXTWI16) ....................... A-153

8-Bit Receive FIFO Register (RXTWI8) .............................. A-154

16-Bit Receive FIFO Register (RXTWI16) .......................... A-154

Precision Clock Generator Registers ......................................... A-155

Control Registers (PCG_CTLxx) ........................................ A-155

PCG Pulse Width Registers ................................................ A-158

PCG Frame Synchronization Registers (PCG_SYNCx) ........ A-160

Peripheral Interrupt Priority Control Registers .......................... A-164

Peripheral Interrupt Priority Control

Registers (PICRx) ............................................................ A-164

Peripheral Interrupt Priority0 Control

Peripheral Interrupt Priority1 Control

Peripheral Interrupt Priority2 Control

Peripheral Interrupt Priority3 Control

ADSP-21368 SHARC Processor Hardware Reference xxix

Contents

Power Management Control

Hardware Breakpoint Control Register ...................................... A-175

Enhanced Emulation Status Register ......................................... A-179

INTERRUPTS

Interrupt Vector Tables ................................................................. B-1

Interrupt Priorities .................................................................. B-4

Interrupt Registers ........................................................................ B-6

Interrupt Register (LIRPTL) ................................................... B-6

Interrupt Latch Register (IRPTL) .......................................... B-13

Interrupt Mask Register (IMASK) ......................................... B-18

Interrupt Mask Pointer Register (IMASKP) ........................... B-22

INDEX

xxx ADSP-21368 SHARC Processor Hardware Reference

+ 864 hidden pages

ANALOG DEVICES ADSP-21367 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS