Datasheet ADSP-21367 Datasheet (ANALOG DEVICES)

ADSP-21368 SHARC® Processor
Hardware Reference
Includes ADSP-21367, ADSP-21369,
ADSP-21371, ADSP-21375
Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106
Revision 1.0, September 2006
82-000100-01
a
Copyright Information
© 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo and icon bar, Blackfin, EZ-KIT Lite, SHARC, the SHARC logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

PREFACE
Purpose of This Manual ............................................................... xxxi
Intended Audience ....................................................................... xxxi
Manual Contents ........................................................................ xxxii
What’s New in This Manual ....................................................... xxxiv
Technical or Customer Support ................................................... xxxv
Supported Processors .................................................................. xxxvi
Product Information .................................................................. xxxvi
MyAnalog.com .................................................................... xxxvii
Processor Product Information ............................................. xxxvii
Related Documents ............................................................ xxxviii
Online Technical Documentation ......................................... xxxix
Printed Manuals ....................................................................... xli
Conventions ................................................................................ xliii
INTRODUCTION
Design Advantages ........................................................................ 1-1
Architectural Overview ................................................................. 1-6
Processor Core ......................................................................... 1-7
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Contents
Processor Peripherals ............................................................... 1-7
I/O Processor ..................................................................... 1-7
Digital Audio Interface (DAI) ............................................. 1-9
Digital Peripheral Interface (DPI) ..................................... 1-10
Development Tools ..................................................................... 1-10
Differences From Previous Processors .......................................... 1-11
I/O Architecture Enhancements ............................................ 1-11
Instruction Set Enhancements ............................................... 1-12
I/O PROCESSOR
General Procedure for Configuring DMA ...................................... 2-2
Core Access to IOP Registers ........................................................ 2-3
Configuring IOP/Core Interaction ................................................ 2-6
Interrupt-Driven I/O .............................................................. 2-6
Interrupt Latency in Interrupt-Driven Transfers ................ 2-11
Polling/Status-Driven I/O ..................................................... 2-12
DMA Controller Operation .................................................. 2-13
Chaining DMA Processes .................................................. 2-14
Transfer Control Block Chain Loading (TCB) ................... 2-16
Setting Up DMA Channel Allocation and Priorities ............... 2-18
Managing DMA Channel Priority ..................................... 2-19
DMA Bus Arbitration ....................................................... 2-20
Setting Up DMA Parameter Registers .......................................... 2-24
DMA Transfer Direction ....................................................... 2-24
Data Buffer Registers ............................................................ 2-25
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Port, Buffer, and DMA Control Registers ............................... 2-26
Addressing ............................................................................ 2-29
External Port DMA ..................................................................... 2-35
Setting Up and Starting Chained DMA .................................. 2-36
Delay Line DMA ................................................................... 2-38
Serial Port DMA ......................................................................... 2-40
Setting Up and Starting Chained DMA .................................. 2-40
Inserting a TCB in an Active Chain ....................................... 2-41
Serial Peripheral Interface DMA .................................................. 2-42
Setting Up and Starting Chained DMA over the SPI .............. 2-42
UART DMA ............................................................................... 2-44
Notes On Using DMA With the UART ................................. 2-47
Memory-to-Memory DMA ......................................................... 2-48
Summary .................................................................................... 2-48
Programming Example ................................................................ 2-49
EXTERNAL PORT
External Memory Interface ............................................................ 3-2
External Memory Interface on the ADSP-2137x Processors ...... 3-3
Direct Execution of Instructions From External Memory ..... 3-3
Throughput and Instruction Execution Rate ........................ 3-3
Location of Interrupt Vector Table (IVT) ............................ 3-4
Instruction Cache ............................................................... 3-5
Instruction Storage and Packing .......................................... 3-9
Register Configurations for External Memory Execution .... 3-15
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EMI Registers and Signals ..................................................... 3-16
External Port Arbitration Logic ......................................... 3-18
Channel Freezing .............................................................. 3-18
Managing Data Paths ........................................................ 3-18
External Memory Interface Pins ............................................ 3-19
Asynchronous Memory Interface ................................................. 3-20
AMI Timing Control .................................................................. 3-21
Wait States ............................................................................ 3-21
Bus Idle Cycles ...................................................................... 3-22
Bus Hold Cycles .................................................................... 3-23
Setting AMI Modes .................................................................... 3-24
External Memory Reads ........................................................ 3-25
Data Packing .................................................................... 3-25
External Memory Writes ....................................................... 3-26
Data Packing .................................................................... 3-27
Read/Write Throughput ........................................................ 3-28
External Access Addressing .................................................... 3-28
External Port DMA ............................................................... 3-30
Booting Through the AMI .................................................... 3-30
SDRAM Controller .................................................................... 3-30
Definition of Terms .............................................................. 3-31
Timing External Memory Accesses ......................................... 3-36
Parallel Connection of SDRAMs ........................................... 3-39
SDRAM Control Register (SDCTL) ...................................... 3-39
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SDRAM Control Status Register (SDSTAT) ........................... 3-49
SDRAM Refresh Rate Control Register (SDRRC) .................. 3-49
SDRAM Initialization ........................................................... 3-51
SDRAM Address Mapping .................................................... 3-51
SDRAM Controller Address Mapping ............................... 3-58
SDC Operation ..................................................................... 3-58
Single Bank Operation ...................................................... 3-60
Multibank Operation (ADSP-2137x Processors) ................ 3-60
Data Mask (DQM) ........................................................... 3-61
SDC Configuration ............................................................... 3-61
SDC Commands ................................................................... 3-63
Load Mode Register .......................................................... 3-64
Single Bank Activation ...................................................... 3-65
Multibank Activation (ADSP-2137x Processors) ................ 3-66
Single Precharge (ADSP-2137x Processors) ........................ 3-66
Precharge All ..................................................................... 3-66
Read/Write ....................................................................... 3-67
Read/Write (ADSP-2137x Processors) ............................... 3-69
Burst Stop (ADSP-2137x Processors) ................................. 3-69
Auto-Refresh ..................................................................... 3-70
Self-Refresh Mode ............................................................. 3-70
No Operation/Command Inhibit ...................................... 3-71
Changing System Clock During Runtime .......................... 3-73
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SDRAM Timing ................................................................... 3-74
SDRAM Read Optimization ............................................. 3-75
External Memory Access Restrictions ................................ 3-78
Shared Memory Interface ............................................................ 3-79
Shared Memory Bus Arbitration ............................................ 3-79
Bus Arbitration Protocol ................................................... 3-82
Bus Arbitration Priority (RPBA) ....................................... 3-86
Bus Mastership Time-out .................................................. 3-87
Bus Synchronization After Reset ............................................ 3-88
Bus Synchronization Notes ............................................... 3-91
Bus Lock and Semaphores ..................................................... 3-92
Shared Memory Interface Status ........................................ 3-93
Shared Memory and the SDRAM Controller ......................... 3-94
Shared Memory Booting ....................................................... 3-94
DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES
Structure of the Interfaces ............................................................. 4-2
DAI/DPI System Design ............................................................... 4-3
Signal Routing Units .................................................................... 4-8
Connecting Peripherals ........................................................... 4-8
Pin Interface ......................................................................... 4-10
Pin Buffers as Signal Output Pins .......................................... 4-11
Pin Buffers as Signal Input Pins ............................................. 4-12
Bidirectional Pin Buffers ....................................................... 4-13
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Making Connections in the SRUs ................................................ 4-15
DAI/SRU1 Connection Groups ............................................. 4-18
Group A Connections—Clock Signals ............................... 4-19
Group B Connections—Data Signals ................................. 4-25
Group C Connections—Frame Sync Signals ...................... 4-31
Group D Connections—Pin Signal Assignments ................ 4-36
Group E Connections—Interrupts and Miscellaneous
Signals ........................................................................... 4-43
Group F—Pin Enable Signals ............................................ 4-47
DPI/SRU2 Connection Groups ............................................. 4-51
Group A Connections—Input Routing Signals .................. 4-52
Group B Connections—Pin Assignment Signals ............... 4-56
Group C Connections—Pin Enable Signals ...................... 4-60
General-Purpose I/O (GPIO) and Flags ....................................... 4-64
DAI GPIO and Flags ............................................................. 4-64
DPI GPIO and Flags ............................................................. 4-65
Miscellaneous Signals .................................................................. 4-65
DAI/DPI Interrupt Controller ..................................................... 4-65
Relationship to the Core ........................................................ 4-65
DAI Interrupts ...................................................................... 4-66
DPI Interrupts ...................................................................... 4-67
High and Low Priority Latches .............................................. 4-69
Rising and Falling Edge Masks ............................................... 4-70
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Configuring Peripherals Using SRU1 .......................................... 4-71
Configuring the SPORTs ...................................................... 4-71
Configuring the PCGs .......................................................... 4-72
Configuring Peripherals Using SRU2 .......................................... 4-72
Configuring the SPI .............................................................. 4-72
Choosing the Pin Enable for the SPI Clock ....................... 4-72
Configuring the Two Wire Interface ...................................... 4-73
Using the SRU() Macro to Configure
the DAI ................................................................................... 4-76
SERIAL PORTS
Features ........................................................................................ 5-2
Operation Modes ......................................................................... 5-3
Serial Port Signals ......................................................................... 5-5
Serial Port Signal Sensitivity .................................................... 5-9
SPORT Operation Modes ........................................................... 5-10
Standard DSP Serial Mode .................................................... 5-12
Standard DSP Serial Mode Control Bits ............................ 5-13
Clocking Options ............................................................. 5-13
Frame Sync Options ......................................................... 5-13
Data Formatting ............................................................... 5-14
Data Transfers .................................................................. 5-15
Status Information ............................................................ 5-15
Left-Justified Sample Pair Mode ............................................ 5-16
Setting the Internal Serial Clock and Frame Sync Rates ..... 5-17
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Left-Justified Sample Pair Mode Control Bits ..................... 5-17
Setting Word Length (SLEN) ............................................ 5-17
Enabling SPORT Master Mode (MSTR) ........................... 5-18
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-18
Selecting Frame Sync Options (DIFS) ............................... 5-18
Enabling SPORT DMA (SDEN) ....................................... 5-19
I2S Mode .............................................................................. 5-20
Setting the Internal Serial Clock and Frame Sync Rates ...... 5-21
I2S Mode Control Bits ...................................................... 5-21
Setting Word Length (SLEN) ............................................ 5-22
Enabling SPORT Master Mode (MSTR) ........................... 5-23
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-23
Selecting Frame Sync Options (DIFS) ............................... 5-23
Enabling SPORT DMA (SDEN) ....................................... 5-24
Multichannel Operation ........................................................ 5-25
Frame Syncs in Multichannel Mode ................................... 5-28
Multichannel Mode Control Bits ....................................... 5-29
Packed I2S Mode ................................................................... 5-33
Programming Packed I2S Mode ......................................... 5-34
SPORT Loopback ................................................................. 5-35
Clock Signal Options .................................................................. 5-36
Frame Sync Options .................................................................... 5-37
Framed Versus Unframed Frame Syncs ................................... 5-37
Internal Versus External Frame Syncs ..................................... 5-38
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Active Low Versus Active High Frame Syncs .......................... 5-39
Sampling Edge for Data and Frame Syncs .............................. 5-39
Early Versus Late Frame Syncs ............................................... 5-40
Data-Independent Frame Syncs ............................................. 5-41
Frame Sync Error Detection .................................................. 5-42
Data Word Formats .................................................................... 5-43
Word Length ........................................................................ 5-43
Endian Format ...................................................................... 5-45
Data Packing and Unpacking ................................................ 5-45
Data Type ........................................................................ 5-46
Companding .................................................................... 5-47
SPORT Control Registers and Data Buffers ................................ 5-49
Register Writes and Effect Latency ......................................... 5-58
Serial Port Control Registers (SPCTLx) ................................. 5-59
Transmit and Receive Data Buffers
(TXSPxA/B, RXSPxA/B) .................................................... 5-67
Clock and Frame Sync Frequency Registers (DIVx) ................ 5-69
SPORT Reset ........................................................................ 5-71
SPORT Interrupts ................................................................ 5-72
Moving Data Between SPORTs and Internal Memory ................. 5-73
DMA Block Transfers ............................................................ 5-73
Setting Up DMA on SPORT Channels ............................. 5-75
SPORT DMA Parameter Registers ......................................... 5-76
SPORT DMA Chaining ................................................... 5-81
Single Word Transfers ........................................................... 5-81
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SPORT Programming Examples .................................................. 5-82
SERIAL PERIPHERAL INTERFACE PORTS
Functional Description ................................................................. 6-2
SPI Interface Signals ..................................................................... 6-4
SPI Clock Signal (SPICLK) ..................................................... 6-4
SPICLK Timing .................................................................. 6-5
SPI Slave Select Input (SPIDS) ............................................ 6-6
SPI Flag Signals (SPIFLG3-0) .................................................. 6-6
Master Out Slave In (MOSI) ................................................... 6-7
Master In Slave Out (MISO) ................................................... 6-7
SPI General Operations ................................................................. 6-8
SPI Enable .............................................................................. 6-9
Open Drain Mode (OPD) ....................................................... 6-9
Master Mode Operation ........................................................ 6-10
Slave Mode Operation ........................................................... 6-11
Multimaster Operation .......................................................... 6-12
SPI Data Transfer Operations ...................................................... 6-13
SPI Operation Using the Core ............................................... 6-13
SPI Operation Using DMA .................................................... 6-14
Master Mode DMA Operation .......................................... 6-15
Slave Mode DMA Operation ............................................. 6-19
Changing SPI Configuration ............................................. 6-21
Switching From Transmit To Receive DMA ....................... 6-23
Switching From Receive to Transmit DMA ........................ 6-24
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DMA Error Interrupts ...................................................... 6-25
DMA Chaining ................................................................ 6-27
SPI Transfer Formats .................................................................. 6-27
Beginning and Ending an SPI Transfer .................................. 6-29
SPI Word Lengths ...................................................................... 6-31
8-Bit Word Lengths .............................................................. 6-31
16-Bit Word Lengths ............................................................ 6-32
32-Bit Word Lengths ............................................................ 6-32
Packing ................................................................................. 6-32
SPI Interrupts ............................................................................. 6-33
Error Signals and Flags ............................................................... 6-35
Mode Fault Error (MME) ..................................................... 6-35
Transmission Error Bit (TUNF) ............................................ 6-37
Reception Error Bit (ROVF) ................................................. 6-37
Transmit Collision Error Bit (TXCOL) ................................. 6-37
Programming Notes .................................................................... 6-38
Routing SPI Signals Using The DPI ...................................... 6-38
Programming Examples .............................................................. 6-38
INPUT DATA PORT
Serial Inputs ................................................................................. 7-3
Parallel Data Acquisition Port (PDAP) .......................................... 7-8
Masking .................................................................................. 7-9
Packing Unit ........................................................................... 7-9
Packing Mode 11 ................................................................ 7-9
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Packing Mode 10 .............................................................. 7-10
Packing Mode 01 .............................................................. 7-11
Packing Mode 00 .............................................................. 7-11
Clocking Edge Selection ........................................................ 7-12
Hold Input ............................................................................ 7-12
PDAP Strobe ......................................................................... 7-14
FIFO Control and Status ............................................................ 7-15
FIFO to Memory Data Transfer ................................................... 7-16
IDP Transfers Using the Core ................................................ 7-17
Starting an Interrupt-Driven Transfer ................................ 7-18
Core Transfer Notes .......................................................... 7-19
IDP Transfers Using DMA .................................................... 7-20
Simple DMA .................................................................... 7-20
Ping-Pong DMA ............................................................... 7-22
DMA Transfer Notes ......................................................... 7-25
DMA Channel Parameter Registers ........................................ 7-27
IDP (DAI) Interrupt Service Routines for DMAs ................... 7-28
FIFO Overflow ..................................................................... 7-30
Input Data Port Programming Example ....................................... 7-31
PULSE WIDTH MODULATION
PWM Implementation .................................................................. 8-1
PWM Waveforms .................................................................... 8-1
Edge-Aligned Mode ............................................................ 8-2
Center-Aligned Mode .......................................................... 8-3
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Switching Frequencies ............................................................. 8-5
Dead Time ............................................................................. 8-6
Duty Cycles ............................................................................ 8-7
Duty Cycles and Dead Time ............................................... 8-8
Over Modulation .............................................................. 8-12
Update Modes ...................................................................... 8-15
Single Update ................................................................... 8-15
Double Update ................................................................. 8-15
Configurable Polarity ............................................................ 8-15
PWM Pins and Signals .......................................................... 8-16
Crossover ......................................................................... 8-16
PWM Accuracy ..................................................................... 8-17
PWM Registers .......................................................................... 8-18
Duty Cycles .......................................................................... 8-19
Output Enable ...................................................................... 8-20
Programming Example ................................................................ 8-21
S/PDIF TRANSMITTER/RECEIVER
AES3/SPDIF Stream Format ......................................................... 9-2
Subframe Format .................................................................... 9-3
Channel Coding ..................................................................... 9-5
Preambles ............................................................................... 9-6
S/PDIF Transmitter ...................................................................... 9-7
Channel Status ........................................................................ 9-9
SRU1 Signals for the S/PDIF Transmitter .............................. 9-10
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S/PDIF Transmitter Registers ................................................ 9-12
Modes of Operation .............................................................. 9-12
Standalone Mode .............................................................. 9-13
Structure of the Serial Input Data .......................................... 9-14
S/PDIF Receiver ......................................................................... 9-16
S/PDIF Receiver Registers ..................................................... 9-17
SRU1 Receiver Signals ........................................................... 9-18
Phase-Locked Loop ..................................................................... 9-19
Channel Status Decoding ............................................................ 9-19
Compressed or Non-Linear Audio Data ................................. 9-20
Emphasized Audio Data ........................................................ 9-21
Single-Channel, Double-Sampling Frequency Mode ............... 9-21
Error Handling ........................................................................... 9-22
Interrupts ................................................................................... 9-24
DAI Programming Examples ....................................................... 9-24
S/PDIF Transmitter Programming Guidelines ........................ 9-24
Control Register ............................................................... 9-24
SRU1 Programming for Input and Output Streams ............ 9-25
Control Register Programming and Enable ........................ 9-25
S/PDIF Receiver Programming Guidelines ............................. 9-25
Control Register ............................................................... 9-25
SRU1 Programming .......................................................... 9-26
Control Register Programming .......................................... 9-26
Receiver Locking ............................................................... 9-26
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Status Bits ........................................................................ 9-26
Interrupted Data Streams on the Receiver .......................... 9-27
ASYNCHRONOUS SAMPLE RATE CONVERTER
Theory of Operation .................................................................. 10-2
Conceptual Model ................................................................ 10-4
Hardware Model ................................................................... 10-7
Sample Rate Converter Architecture ............................................ 10-8
Group Delay ....................................................................... 10-12
SRC Operation ......................................................................... 10-12
Enabling the SRC ............................................................... 10-13
Serial Data Ports ................................................................. 10-13
Data Format ................................................................... 10-13
Time-Division Multiplex (TDM) Output Mode .............. 10-15
TDM Input Mode .......................................................... 10-16
Matched-Phase Mode ..................................................... 10-16
Bypass Mode .................................................................. 10-18
De-Emphasis Filter ............................................................. 10-18
Mute Control ..................................................................... 10-19
Soft Mute ....................................................................... 10-20
Hard Mute ..................................................................... 10-20
Auto Mute ...................................................................... 10-20
SRC Registers ........................................................................... 10-21
Programming the SRC Module ................................................. 10-22
SRC Control Register Programming .................................... 10-22
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SRU Programming .............................................................. 10-22
SRC Mute-Out Interrupt ..................................................... 10-23
Sample Rate Ratio ............................................................... 10-23
Programming Summary ....................................................... 10-23
UART PORT CONTROLLER
Serial Communications ............................................................... 11-2
UART Control and Status Registers ............................................. 11-3
UARTxLCR Registers ............................................................ 11-3
UARTxLSR Register .............................................................. 11-4
UARTxTHR Register ............................................................ 11-4
UARTxRBR Register ............................................................. 11-5
UARTxIER Register .............................................................. 11-7
UARTxIIR Register ............................................................... 11-9
UARTxDLL and UARTxDLH Registers .............................. 11-11
UARTxSCR Register ........................................................... 11-12
UARTxMODE Register ...................................................... 11-13
I/O Mode ................................................................................. 11-13
Packing Mode ........................................................................... 11-15
TWO WIRE INTERFACE CONTROLLER
Overview .................................................................................... 12-1
Architecture ................................................................................ 12-2
Register Descriptions .................................................................. 12-4
TWI Master Internal Time Register ....................................... 12-4
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TWIDIV Register ................................................................. 12-5
Slave Mode Control Register ................................................. 12-5
Slave Mode Address Register ................................................. 12-6
Slave Mode Status Register .................................................... 12-6
Master Mode Control Register .............................................. 12-6
Master Mode Address Register ............................................... 12-6
Master Mode Status Register ................................................. 12-7
FIFO Control Register .......................................................... 12-7
FIFO Status Register ............................................................. 12-7
Interrupt Source Register ...................................................... 12-7
Interrupt Enable Register ...................................................... 12-8
8-Bit Transmit FIFO Register ................................................ 12-8
16-Bit Transmit FIFO Register .............................................. 12-8
8-Bit Receive FIFO Register .................................................. 12-9
16-Bit Receive FIFO Register .............................................. 12-10
Data Transfer Mechanics ........................................................... 12-10
Clock Generation and Synchronization ................................ 12-11
Bus Arbitration ................................................................... 12-12
Start and Stop Conditions ................................................... 12-12
General Call Support .......................................................... 12-14
Fast Mode ........................................................................... 12-14
Programming Examples ............................................................ 12-15
General Setup ..................................................................... 12-15
Slave Mode ......................................................................... 12-15
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Master Mode Clock Setup ................................................... 12-17
Master Mode Transmit ........................................................ 12-17
Master Mode Receive ........................................................... 12-18
Repeated Start Condition .................................................... 12-19
Transmit/Receive Repeated Start Sequence ....................... 12-19
Receive/Transmit Repeated Start Sequence ....................... 12-21
Electrical Specifications ............................................................. 12-22
PRECISION CLOCK GENERATORS
Clock Outputs ............................................................................ 13-3
Frame Sync Outputs ................................................................... 13-4
Normal Mode ........................................................................ 13-5
Bypass Mode ......................................................................... 13-6
Frame Sync Output Synchronization With an External Clock ...... 13-7
Frame Sync ........................................................................... 13-8
Phase Shift .................................................................................. 13-9
Phase Shift Settings ............................................................. 13-10
Pulse Width ........................................................................ 13-10
Bypass Mode ....................................................................... 13-12
Bypass as a Pass Through ................................................. 13-12
Bypass as a One-Shot ...................................................... 13-13
Programming Examples ............................................................. 13-14
PCG Setup for I2S or Left-Justified DAI .............................. 13-15
Clock and Frame Sync Divisors PCG Channel B .................. 13-20
PCG Channel A and B Output Example .............................. 13-23
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SYSTEM DESIGN
Processor Pin Descriptions .......................................................... 14-2
Pin Multiplexing ................................................................... 14-2
Choosing EP Data Mode .................................................. 14-6
Interrupt and Timer Pins ...................................................... 14-8
Core-Based Flag Pins ............................................................. 14-8
Programming Flags ........................................................... 14-9
RESETOUT/CLKOUT/RUNRSTIN ............................. 14-12
JTAG Interface Pins ............................................................ 14-12
Clock Derivation ...................................................................... 14-13
Power Management Control Register ................................... 14-14
PLL Programming Examples ........................................... 14-16
Phase-Locked Loop Startup ................................................. 14-19
RESET and CLKIN ............................................................ 14-20
Running Reset (ADSP-2137x) ............................................ 14-22
System Design Considerations ........................................ 14-23
Running Reset Control Register (RUNRSTCTL) ............ 14-25
Programming The RUNRSTCTL Register ...................... 14-26
Reset Generators ............................................................. 14-27
Timing Specifications .......................................................... 14-28
Input Synchronization Delay ............................................... 14-32
Conditioning Input Signals ....................................................... 14-32
RESET Input Hysteresis ...................................................... 14-33
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Designing for High Frequency Operation .................................. 14-33
Clock Specifications and Jitter ............................................. 14-33
Other Recommendations and Suggestions ............................ 14-34
Decoupling Capacitors and Ground Planes .......................... 14-35
Oscilloscope Probes ............................................................. 14-35
Recommended Reading ....................................................... 14-36
Booting .................................................................................... 14-37
External Port Booting .......................................................... 14-39
Booting Through the AMI .............................................. 14-39
Shared Memory Booting ................................................. 14-40
SPI Port Booting ................................................................. 14-42
32-Bit SPI Host Boot ...................................................... 14-43
16-Bit SPI Host Boot ...................................................... 14-44
8-Bit SPI Host Boot ........................................................ 14-46
Slave Boot Mode ............................................................. 14-47
Master Boot .................................................................... 14-48
Booting From an SPI Flash .............................................. 14-51
Booting From an SPI PROM (16-Bit address) .................. 14-52
Booting From an SPI Host Processor ............................... 14-52
Data Delays, Latencies, and Throughput ................................... 14-52
Execution Stalls ................................................................... 14-53
DAG Stalls .......................................................................... 14-54
Memory Stalls ..................................................................... 14-54
IOP Register Stalls ............................................................... 14-55
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DMA Stalls ......................................................................... 14-56
IOP Buffer Stalls ................................................................. 14-56
REGISTER REFERENCE
I/O Processor Registers ................................................................. A-2
Notes on Reading Register Drawings ....................................... A-3
System Control Register (SYSCTL) ......................................... A-5
System Status Register (SYSTAT) ............................................ A-9
External Port Registers ................................................................ A-10
External Port Control Register (EPCTL) ............................... A-10
External Port DMA Control Registers (DMACx) ................... A-14
AMI Control Registers (AMICTLx) ...................................... A-17
AMI Status Register (AMISTAT) ........................................... A-20
SDRAM Control Register (SDCTL) ...................................... A-21
SDRAM Control Status Register (SDSTAT) .......................... A-26
SDRAM Refresh Rate Control Register (SDRRC) .................. A-26
Memory-to-Memory DMA Register ............................................ A-28
Serial Port Registers .................................................................... A-29
SPORT Serial Control Registers (SPCTLx) ............................ A-29
SPORT Multichannel Control Registers (SPMCTLx) ............ A-40
SPORT Transmit Buffer Registers (TXSPx) ........................... A-43
SPORT Receive Buffer Registers (RXSPx) .............................. A-44
SPORT Divisor Registers (DIVx) .......................................... A-44
SPORT Count Registers (SPCNTx) ...................................... A-45
SPORT Active Channel Select Registers (SPxCSy) ................. A-46
xxiv ADSP-21368 SHARC Processor Hardware Reference
Contents
SPORT Compand Registers (SPxCCSy) ................................ A-47
SPORT Error Control Register (SPERRCTLx) ...................... A-48
SPORT Error Status Register (SPERRSTAT) ......................... A-49
SPORT DMA Index Registers (IISPx) ................................... A-50
SPORT DMA Modifier Registers (IMSPx) ............................ A-50
SPORT DMA Count Registers (CSPx) ................................. A-51
SPORT Chain Pointer Registers (CPSPx) .............................. A-51
Serial Peripheral Interface Registers ............................................. A-52
SPI Control Registers (SPICTL, SPICTLB) .......................... A-52
SPI Port Status (SPISTAT, SPISTATB) Registers ................... A-56
SPI Port Flags Registers (SPIFLG, SPIFLGB) ........................ A-58
SPI Receive Buffer Registers (RXSPI, RXSPIB) ..................... A-59
RXSPI Shadow Registers
(RXSPI_SHADOW, RXSPIB_SHADOW) ......................... A-59
SPI Transmit Buffer Registers (TXSPI, TXSPIB) ................... A-59
SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) ................ A-60
SPI DMA Registers .............................................................. A-61
SPI DMA Configuration Registers (SPIDMAC,
SPIDMACB) ................................................................ A-62
SPI DMA Start Address Registers (IISPI, IISPIB) .............. A-64
SPI DMA Address Modify Registers (IMSPI, IMSPIB) ..... A-64
SPI DMA Word Count Registers (CSPI, CSPIB) .............. A-64
SPI DMA Chain Pointer Registers (CPSPI, CPSPIB) ........ A-65
Input Data Port Registers ........................................................... A-65
Input Data Port Control Register 0 (IDP_CTL0) .................. A-66
ADSP-21368 SHARC Processor Hardware Reference xxv
Contents
Input Data Port Control Register 1 (IDP_CTL1) .................. A-68
Input Data Port FIFO Register (IDP_FIFO) .......................... A-69
Input Data Port DMA Control Registers ............................... A-70
IDP_DMA_Ix .................................................................. A-70
IDP_DMA_Mx ................................................................ A-71
IDP_DMA_Cx ................................................................. A-71
Input Data Port Ping-Pong DMA Registers ............................ A-72
IDP Ping-Pong Index Registers (IDP_DMA_IxA) ............. A-72
IDP Ping-Pong Count Registers (IDP_DMA_PCx) ........... A-73
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL) ................................................................. A-74
Pulse Width Modulation Registers .............................................. A-78
PWM Global Control Register (PWMGCTL) ....................... A-78
PWM Global Status Register (PWMGSTAT) ......................... A-79
PWM Control Register (PWMCTLx) .................................... A-80
PWM Status Registers (PWMSTATx) .................................... A-81
PWM Period Registers (PWMPERIODx) .............................. A-81
PWM Output Disable Registers (PWMSEGx) ....................... A-82
PWM Polarity Select Registers (PWMPOLx) ......................... A-83
PWM Channel Duty Control Registers
(PWMAx, PWMBx) ........................................................... A-84
PWM Channel Low Duty Control Registers
(PWMALx, PWMBLx) ...................................................... A-84
PWM Dead Time Registers (PWMDTx) ............................... A-85
xxvi ADSP-21368 SHARC Processor Hardware Reference
Contents
Sony/Philips Digital Interface Registers ...................................... A-86
Transmitter Control Register (DITCTL) ............................... A-86
Left Channel Status for Subframe A
Registers (DITCHANAx) .................................................. A-89
Right Channel Status for Subframe B
Registers (DITCHANBx) .................................................. A-90
User Bits Buffer Registers for Subframe A
Registers (DITUSRBITAx) ................................................ A-90
User Bits Buffer Registers for Subframe B
Registers (DITUSRBITBx) ................................................ A-91
Receiver Control Register (DIRCTL) .................................... A-92
Receiver Status Register (DIRSTAT) ..................................... A-94
Left Channel Status for Subframe A
Register (DIRCHANL) ...................................................... A-96
Right Channel Status for Subframe B
Register (DIRCHANR) ..................................................... A-96
Sample Rate Converter Registers ................................................ A-97
SRC Control Registers (SRCCTLx) ...................................... A-97
SRC Mute Register (SRCMUTE) ....................................... A-107
SRC Ratio Registers (SRCRATx) ........................................ A-108
DAI/DPI Registers ................................................................... A-109
Digital Audio Interface Status Register (DAI_STAT) ........... A-109
DAI Resistor Pull-up Enable Register
(DAI_PIN_PULLUP) ...................................................... A-111
DAI Pin Buffer Status Register (DAI_PIN_STAT) .............. A-112
DAI Interrupt Controller Registers ..................................... A-112
ADSP-21368 SHARC Processor Hardware Reference xxvii
Contents
DPI Resistor Pull-up Enable Register
(DPI_PIN_PULLUP) ...................................................... A-115
DPI Pin Buffer Status Register (DPI_PIN_STAT) ................ A-116
DPI Interrupt Controller Registers ...................................... A-116
UART Control and Status Registers .......................................... A-118
Line Control Registers (UARTxLCR) .................................. A-118
Line Status Registers (UARTxLSR) ...................................... A-120
Transmit Hold Registers (UARTxTHR) ............................... A-121
Receive Buffer Registers (UARTxRBR) ................................ A-122
Interrupt Enable Registers (UARTxIER) .............................. A-123
Interrupt Identification Registers (UARTxIIR) ..................... A-124
Divisor Latch Registers (UARTxDLL, UARTxDLH) ........... A-125
Scratch Registers (UARTxSCR) ........................................... A-126
Mode Registers (UARTxMODE) ......................................... A-126
UART DMA Registers ........................................................ A-127
DMA Control Registers (UARTxTXCTL,
UARTxRXCTL) .......................................................... A-128
DMA Status Registers (UARTxTXSTAT,
UARTxRXSTAT) ........................................................ A-129
Two Wire Interface Registers ..................................................... A-130
Master Internal Time Register (TWIMITR) ........................ A-131
Clock Divider Register (TWIDIV) ...................................... A-132
Slave Mode Control Register (TWISCTL) ........................... A-133
Slave Address Register (TWISADDR) ................................. A-135
Slave Status Register (TWISSTAT) ...................................... A-135
xxviii ADSP-21368 SHARC Processor Hardware Reference
Contents
Master Control Register (TWIMCTL) ................................ A-136
Master Address Register (TWIMADDR) ............................. A-139
Master Status Register (TWIMSTAT) ................................. A-140
FIFO Control Register (TWIFIFOCTL) ............................. A-143
FIFO Status Register (TWIFIFOSTAT) .............................. A-145
Interrupt Source Register (TWIIRPTL) .............................. A-147
Interrupt Enable Register (TWIIMASK) ............................. A-150
8-Bit Transmit FIFO Register (TXTWI8) ........................... A-152
16-Bit Transmit FIFO Register (TXTWI16) ....................... A-153
8-Bit Receive FIFO Register (RXTWI8) .............................. A-154
16-Bit Receive FIFO Register (RXTWI16) .......................... A-154
Precision Clock Generator Registers ......................................... A-155
Control Registers (PCG_CTLxx) ........................................ A-155
PCG Pulse Width Registers ................................................ A-158
PCG Frame Synchronization Registers (PCG_SYNCx) ........ A-160
Peripheral Interrupt Priority Control Registers .......................... A-164
Peripheral Interrupt Priority Control
Registers (PICRx) ............................................................ A-164
Peripheral Interrupt Priority0 Control
Register (PICR0) ......................................................... A-167
Peripheral Interrupt Priority1 Control
Register (PICR1) ......................................................... A-168
Peripheral Interrupt Priority2 Control
Register (PICR2) ......................................................... A-169
Peripheral Interrupt Priority3 Control
Register (PICR3) ......................................................... A-170
ADSP-21368 SHARC Processor Hardware Reference xxix
Contents
Power Management Control
Register (PMCTL) ................................................................. A-170
Hardware Breakpoint Control Register ...................................... A-175
Enhanced Emulation Status Register ......................................... A-179
INTERRUPTS
Interrupt Vector Tables ................................................................. B-1
Interrupt Priorities .................................................................. B-4
Interrupt Registers ........................................................................ B-6
Interrupt Register (LIRPTL) ................................................... B-6
Interrupt Latch Register (IRPTL) .......................................... B-13
Interrupt Mask Register (IMASK) ......................................... B-18
Interrupt Mask Pointer Register (IMASKP) ........................... B-22
INDEX
xxx ADSP-21368 SHARC Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using the ADSP-21367/8/9 and ADSP-2137x SHARC® processors from Analog Devices.

Purpose of This Manual

The ADSP-21368 SHARC Processor Hardware Reference contains informa- tion about the architecture and assembly language for ADSP-21367/8/9 and ADSP-2137x. These are 32-bit, fixed- and floating-point digital sig­nal processors from Analog Devices for use in computing, communications, and consumer applications.
The manual provides information on the processor’s I/O architecture and the operation of the peripherals associated with each model.

Intended Audience

The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate hardware reference manuals and data sheets) that describe your target architecture.
ADSP-21368 SHARC Processor Hardware Reference xxxi

Manual Contents

Manual Contents
The manual consists of:
Chapter 1, “Introduction” Provides an architectural overview of the ADSP-21367/8/9 and ADSP-2137x SHARC processors.
Chapter 2, “I/O Processor” Describes ADSP-21367/8/9 and ADSP-2137x processors input/output processor architecture and direct memory accesses (DMA) for the peripherals that have this feature.
Chapter 3, “External Port” Describes the operation of the asynchronous memory interface (AMI).
Chapter 4, “Digital Audio/Digital Peripheral Interfaces” Provides information about the digital applications interface (DAI) which allows you to attach an arbitrary number and a variety of peripherals to the ADSP-21367/8/9 and ADSP-2137x processors while retaining high levels of compatibility.
Chapter 5, “Serial Ports” Describes the up to eight dual data line serial ports. Each SPORT contains a clock, a frame sync, and two data lines that can be con­figured as either a receiver or transmitter pair.
Chapter 6, “Serial Peripheral Interface Ports” Describes the operation of the SPI port. SPI devices communicate using a master-slave relationship and can achieve high data transfer rates because they can operate in full-duplex mode.
Chapter 7, “Input Data Port” Discusses the function of the input data port (IDP) which provides a low overhead method of routing signal routing unit (SRU) sig­nals back to the core’s memory.
xxxii ADSP-21368 SHARC Processor Hardware Reference
Preface
Chapter 8, “Pulse Width Modulation” Describes the implementation and use of the pulse width modula­tion module which provides a technique for controlling analog circuits with the microprocessor’s digital outputs.
Chapter 9, “S/PDIF Transmitter/Receiver” Provides information on the use of the Sony/Philips Digital Inter­face which is a standard audio file transfer format that allows the transfer of digital audio signals from one device to another without having to be converted to an analog signal.
Chapter 10, “Asynchronous Sample Rate Converter” Provides information on the sample rate converter module. This module performs synchronous or asynchronous sample rate conver­sions across independent stereo channels, without using any internal processor resources.
Chapter 11, “UART Port Controller” Describes the operation of the Universal Asynchronous Receiver/Transmitter (UART) which is a full-duplex peripheral compatible with PC-style industry-standard UART.
Chapter 12, “Two Wire Interface Controller” The two wire interface is fully compatible with the widely used I
2
C bus standard. It is designed with a high level of functionality and is compatible with multi-master, multi-slave bus configurations.
Chapter 13, “Precision Clock Generators” Details the precision clock generators (PCG) each of which gener­ates a pair of signals derived from a clock input signal.
Chapter 14, “System Design” Describes system design features of the ADSP-21367/8/9 and ADSP-2137x processors. These include power, reset, clock, JTAG, and booting, as well as pin descriptions and other system level information.
ADSP-21368 SHARC Processor Hardware Reference xxxiii

What’s New in This Manual

Appendix A, “Register Reference” Provides a graphical presentation of all registers and describes the bit usage in each register.
Appendix B, “Interrupts” Provides a complete listing of the registers that are used to config­ure and control interrupts.
L
This hardware reference is a companion document to the
ADSP-2136x/ADSP-2137x SHARC Processor Programming Refer­ence. The programming reference provides information relating to
the processor core, such as processing elements, internal memory, and program sequencing. It also provides programming specific information, such as complete descriptions of the ADSP-21xxx instruction set and the compute operations, including their assem­bly language syntax and opcode fields.
What’s New in This Manual
Revision 1.0 of the ADSP-21368 SHARC Processor Hardware Reference is the first general release of this manual. The following changes should be noted.
In the preliminary version this manual was titled ADSP-2136x
SHARC Processor Hardware reference for the ADSP-21367/8/9 Pro­cessors. The title change to ADSP-21368 SHARC Processor Hardware Reference was done to reflect the fact that the
ADSP-21368 processor contains the super set of features of the ADSP-21367 and ADSP-21369 models as well as the new ADSP-21371 and ADSP-21375 models.
This version of the manual contains information about the ADSP-21371 and ADSP-21375 SHARC processors. These new models contain the same core as the ADSP-21367/8/9 processors
xxxiv ADSP-21368 SHARC Processor Hardware Reference
and as such are completely code compatible. The primary differ­ences in these new models is the ability to execute programs from external memory and a running reset feature.
For more information on these topics, see “Direct Execution of
Instructions From External Memory” on page 3-3 and “Running Reset (ADSP-2137x)” on page 14-22.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following ways:
Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/manuals
E-mail tools questions to
processor.tools.support@analog.com
Preface
E-mail processor questions to
processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support)
Phone questions to 1-800-ANALOGD
Contact your Analog Devices, Inc. local sales office or authorized distributor
Send questions by mail to:
Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA
ADSP-21368 SHARC Processor Hardware Reference xxxv

Supported Processors

Supported Processors
The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®.
Blackfin® (ADSP-BFxxx) Processors
The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin families: ADSP-BF53x, ADSP-BF54x, and ADSP-BF56x.
SHARC (ADSP-21xxx) Processors
The name SHARC refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP++ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, ADSP-2136x, and ADSP-2137x.
TigerSHARC® (ADSP-TSxxx) Processors
The name TigerSHARC refers to a family of floating-point and fixed-point (8-bit, 16-bit, and 32-bit) processors. VisualDSP++ currently supports the following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

Product Information

You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at mation about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
xxxvi ADSP-21368 SHARC Processor Hardware Reference
www.analog.com. Our Web site provides infor-
Preface

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.
Registration
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as a means to select the information you want to receive.
If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publica-
tions, data sheets, application notes, product overviews, and product announcements.
You may also obtain additional information about Analog Devices and its products in any of the following ways.
E-mail processor questions to
processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support)
ADSP-21368 SHARC Processor Hardware Reference xxxvii
Product Information
Fax questions or requests for information to
1-781-461-3010 (North America) +49-89-76903-157 (Europe)
Access the FTP Web site at
ftp ftp.analog.com or ftp://137.71.25.69 ftp://ftp.analog.com

Related Documents

The following publications that describe the ADSP-2136x SHARC pro­cessors (and related processors) can be ordered from any Analog Devices sales office:
ADSP-21362 SHARC Processor Data Sheet
ADSP-21363 SHARC Processor Data Sheet
ADSP-21364 SHARC Processor Data Sheet
ADSP-21365 SHARC Processor Data Sheet
ADSP-21366 SHARC Processor Data Sheet
ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data
Sheet
ADSP-21371 SHARC Processor Preliminary Data Sheet
ADSP-21375 SHARC Processor Preliminary Data Sheet
ADSP-2136x/ADSP-2137x SHARC Processor Programming
Reference
xxxviii ADSP-21368 SHARC Processor Hardware Reference
Preface
For information on product related development software and Analog Devices processors, see these publications:
VisualDSP++ User’s Guide
VisualDSP++ C/C++ Compiler and Library Manual for SHARC
Processors
VisualDSP++ Assembler and Preprocessor Manual
VisualDSP++ Linker and Utilities Manual
VisualDSP++ Kernel (VDK) User’s Guide
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/manuals

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary
Each documentation file type is described as follows.
If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD-ROM at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site.
ADSP-21368 SHARC Processor Hardware Reference xxxix
.PDF files of most manuals are also provided.
Product Information
File Description
.CHM Help system files and manuals in Help format
.HTM or .HTML
.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Dinkum Abridged C++ library and FlexLM network license manager software doc­umentation. Viewing and printing the Internet Explorer 4.0 (or higher).
Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).
.HTML files requires a browser, such as
Accessing Documentation From VisualDSP++
From the VisualDSP++ environment:
Access VisualDSP++ online Help from the Help menu’s Contents, Search, and Index commands.
Open online Help from context-sensitive user interface items (tool­bar buttons, menu commands, and windows).
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documenta­tion from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are located in the
Docs folder also contains the Dinkum Abridged C++ library and the
The
Docs folder of your VisualDSP++ installation CD-ROM.
FlexLM network license manager software documentation.
Using Windows Explorer
Double-click the tem, to access all the other
vdsp-help.chm file, which is the master Help sys-
.CHM files.
Double-click any file that is part of the VisualDSP++ documenta­tion set.
xl ADSP-21368 SHARC Processor Hardware Reference
Preface
Using the Windows Start Button
Access VisualDSP++ online Help by clicking the Start button and choosing Programs, Analog Devices, VisualDSP++, and VisualDSP++ Documentation.
Access the
.PDF files by clicking the Start button and choosing
Programs, Analog Devices, VisualDSP++, Documentation for Printing, and the name of the book.
Accessing Documentation From the Web
Download manuals at the following Web site:
http://www.analog.com/processors/resources/manuals
Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.

Printed Manuals

For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
ADSP-21368 SHARC Processor Hardware Reference xli
Product Information
Hardware Tools Manuals
To purchase EZ-KIT Lite® and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.
xlii ADSP-21368 SHARC Processor Hardware Reference

Conventions

Text conventions used in this manual are identified and described as follows.
Example Description
Preface
Close command (File menu)
{this | that} Alternative items in syntax descriptions appear within curly brackets
[this | that] Optional items in syntax descriptions appear within brackets and sepa-
[this,…] Optional item lists in syntax descriptions appear within brackets
.SECTION Commands, directives, keywords, and feature names are in text with
filename Non-keyword placeholders appear in text with italic style format.
L
a
Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system. For example, the Close command appears on the File menu.
and separated by vertical bars; read the example as this or that. One or the other is required.
rated by vertical bars; read the example as an optional
delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this.
letter gothic font.
Note: For correct operation, ... A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol.
Caution: Incorrect device operation may result if ... Caution: Device damage may result if ...
A Caution: identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.
this or that.
Warn in g: Injury to device users may result if ... A Warning: identifies conditions or inappropriate usage of the product
[
that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Wa rnin g appears instead of this symbol.
ADSP-21368 SHARC Processor Hardware Reference xliii
Conventions
L
Additional conventions, which apply only to specific chapters, may appear throughout this document.
xliv ADSP-21368 SHARC Processor Hardware Reference

1 INTRODUCTION

The ADSP-21367/8/9 and ADSP-2137x SHARC processors are high per­formance, 32-bit processors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recogni­tion, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruction, multiple-data (SIMD) support, this processor builds on the ADSP-21000 family DSP core to form a complete system-on-a-chip.

Design Advantages

A digital signal processor’s data format determines its ability to handle sig­nals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and the probability of overflow, using a floating-point processor can simplify algo­rithm and software development. The extent to which this is true depends on the floating-point processor’s architecture. Consistency with IEEE workstation simulations and the elimination of scaling are clearly two ease-of-use advantages. High level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assem­bly language coding, code paging, and/or error handling. The processors are highly integrated, 32-bit floating-point processors which provide all of these design advantages.
The SHARC processor architecture balances a high performance processor core with high performance program memory (PM), data memory (DM),
ADSP-21368 SHARC Processor Hardware Reference 1-1
Design Advantages
and input/output (I/O) buses. In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate.
Figure 1-1 shows a detailed block diagram of the processor core and the
I/O processor (IOP). This figures illustrates the following architectural features:
Two processing elements (PEx and PEy), each containing 32-bit, IEEE, floating-point computation units—multiplier, arithmetic logic unit (ALU), shifter, and data register file
Program sequencer with related instruction cache, interval timer, and data address generators (DAG1 and DAG2)
An SDRAM controller that provides an interface up to four sepa­rate banks of industry-standard SDRAM devices or DIMMs, at speeds up to
f
SCLK
Up to 2M bits of SRAM and 6M bits of on-chip, mask-program­mable ROM
IOP with integrated direct memory access (DMA) controller, serial peripheral interface (SPI) compatible port, and serial ports (SPORTs) for point-to-point multiprocessor communications
A variety of audio centric peripheral modules including a Sony/Philips Digital Interface (S/PDIF), sample rate converter (SRC) and pulse width modulation (PWM). Table 1-1 on page 1-5 provides details on these and other features for the current mem­bers of the ADSP-21367/8/9 and ADSP-2137x processors families.
JTAG test access port for emulation
Figure 1-1 also shows the three on-chip buses: the PM bus, DM bus, and
I/O bus. The PM bus provides access to either instructions or data. Dur­ing a single cycle, these buses let the processor access two data operands
1-2 ADSP-21368 SHARC Processor Hardware Reference
Introduction
from memory, access an instruction (from the cache), and perform a DMA transfer.
Figure 1-1 also shows the asychronous memory interface available on the
ADSP-21368 processor.
INST RUCT ION
CACHE
32X 48-BIT
2DAGS 8X4X32
2PROCESSING
ELEMENTS (PEX , PEY)
PROGR AM
SEQ UEN CER
TIMER
S
4
GPIO FLAGS/
IRQ/ TIME XP
*THEADSP-21368 PROCESSOR INCLUDES A CUSTOMER-DEFINABLE ROM BLOCK.
PLEAS E CON TACT YO UR ANAL OG DEVIC ES SAL ES REPR ESENT ATIVE FO R ADDIT IONAL D ETAILS
PX R EGISTER
CORE PR OCESS OR
PRE CISION CL OCK
GEN ERATORS (4)
SRC (8 CH ANNELS )
SPDIF(RX/TX)
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
DAI ROUTING UNIT
DIGITAL AUDIO INTERFACE
32PM ADDRESSBUS
32
64
64
ON-CHIP MEM ORY
ADD R DA T A
IOA( 24)
IOP R EGISTER (M EMORY M APPED)
CONTROL,STATUS, &DATA BUFFERS
SERIAL PORTS(8)
INPU T DAT A PORT /
PDAP
DAI PINS
20
IOD( 32)
CONTROLLER
AS YNC HR ON O US
SHA RED MEM ORY
INT ERFA CE
SPI PO RT (2)
TWO WIRE
INTERFACE
DP I PI NS
DIGITAL PERIPHERAL INTERFACE
14
EXTE RNA L PORT
SDR AM
MEMORY
INTERFACE
DMA
CONTROLLER
34 CHANNELS
FLAGS
4-15
PWM
8
3
8
MEMO RY DMA (2)
DPIROUTING UNIT
I/O PROCESSOR
Figure 1-1. ADSP-21368 Block Diagram
The ADSP-21367/8/9 and ADSP-2137x processors address the five cen­tral requirements for signal processing:
S N
I
18
P L O R
CONTROL
T N
O C
ADDRESS
ME MORY -TO -
UART(2 )
TIMERS (3)
32
DATA
24
Fast, Flexible Arithmetic. The ADSP-21000 family processors execute all instructions in a single cycle. They provide fast cycle times and a complete set of arithmetic operations. The processor is IEEE floating-point compat­ible and allows either interrupt on arithmetic exception or latched status exception handling.
ADSP-21368 SHARC Processor Hardware Reference 1-3
Design Advantages
Unconstrained Data Flow. The ADSP-21367/8/9 and ADSP-2137x pro­cessors have a Super Harvard Architecture combined with a ten-port data register file. In every cycle, the processor can write or read two operands to or from the register file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and multiplier. The processor’s 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction.
40-Bit Extended Precision. The processor handles 32-bit IEEE float­ing-point format, 32-bit integer and fractional formats (twos-complement and unsigned), and extended-precision, 40-bit floating-point format. The processors carry extended precision throughout their computation units, limiting intermediate data truncation errors (up to 80 bits of precision are maintained during multiply-accumulate operations).
Dual Address Generators. The processor has two data address generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus, bit-reverse, and broadcast operations are supported with no constraints on data buffer placement.
Efficient Program Sequencing. In addition to zero-overhead loops, the processor supports single-cycle setup and exit for loops. Loops are both nestable (six levels in hardware) and interruptable. The processors support both delayed and non-delayed branches.
The ADSP-21367/8/9 and ADSP-2137x processors also provide the fol­lowing features which increase the variety processor applications.
High Bandwidth I/O. The processors contain a dedicated, 6M bits on-chip ROM, an external port, an SPI port, serial ports, digital audio interface (DAI), and JTAG. The DAI incorporates a precision clock gen­erator, input data port, and a signal routing unit.
Serial Ports. Provides an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half the processor core clock (
CCLK) rate.
1-4 ADSP-21368 SHARC Processor Hardware Reference
Introduction
Input Data Port (IDP). The IDP provides an additional input path to the processor core, configurable as eight channels of serial data or seven chan­nels of serial data and a single channel of up to 20-bit wide parallel data.
Two Serial Peripheral Interfaces (SPI). The primary SPI has dedicated pins and the secondary is controlled through the DAI. The SPI provides master or slave serial boot through the SPI, full-duplex operation, mas­ter-slave mode, multimaster support, open drain outputs, programmable baud rates, clock polarities, and phases.
Digital Audio Interface and Digital Peripheral Interface. The digital audio interface (DAI) and the digital peripheral interface (DPI) are com­prised of groups of peripherals and their signal routing units (SRU1 and SRU2 respectively). This allows peripherals to be interconnected to suit a wide variety of systems. It also allows the processors to include an arbi­trary number and variety of peripherals while retaining high levels of compatibility without increasing pin count.
Signal Routing Units (SRU1/SRU2). The SRUs provide configuration flexibility by allowing software-programmable connections to be made between the DAI/DPI components and the 20 DAI pins and 14 DPI pins.
I/O Processor (IOP). The IOP manages the SHARC processor’s off-chip data I/O to alleviate the core of this burden. This unit manages the other processor peripherals such as the SPI, DAI, and IDP as well as direct memory accesses (DMA).
Table 1-1. SHARC Processor Features
Feature ADSP-21367 ADSP-21368 ADSP-21369 ADSP-21371 ADSP-21375
RAM 2M bit2M bit2M bit1M bit0.5M bit
ROM 6M bit
Audio Decoders in ROM
2
Yes NoNoNoNo
6M bit
1
6M bit
1
4M bit
1
2M bit
1
ADSP-21368 SHARC Processor Hardware Reference 1-5

Architectural Overview

Table 1-1. SHARC Processor Features (Cont’d)
Feature ADSP-21367 ADSP-21368 ADSP-21369 ADSP-21371 ADSP-21375
Pulse Width Modulation
S/ PD IF Yes Yes Ye s Yes No
Shared Memory
SRC Performance
Package Option
Processor Speed 333 MHz 333 MHz 333 MHz 266 MHz 266 MHz
1 The ADSP-21367 processor include a customer-definable ROM block. Please contact your Analog
Devices sales representative for additional details.
2 Audio decoding algorithms include PCM, Dolby Digital EX, PCM, Dolby Digital EX, Dolby Pro-
logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MPEG2 2channel, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-proces­sor algorithm combination support will vary depending upon the chip version and the system config­urations. Please visit www.analog.com/SHARC for complete information.
3 Analog Devices offers these packages in lead-free (Pb) versions.
Yes Yes Ye s Yes No
NoYesNoNoNo
128dB 140dB 128dB 128dB N/A
3
256-ball SBGA 208 Lead MQFP
256-ball SBGA
256-ball SBGA 208 Lead MQFP
208-lead MQFP
208-lead MQFP
Architectural Overview
The ADSP-21367/8/9 and ADSP-2137x processors form a complete sys­tem-on-a-chip, integrating a large, high speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the processor architecture, which appears in Figure 1-1.
1-6 ADSP-21368 SHARC Processor Hardware Reference
Introduction

Processor Core

The processor core of the ADSP-21367/8/9 and ADSP-2137x processors contain two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core. For complete information, see the ADSP-21367/8/9 and ADSP-2137x SHARC processors.

Processor Peripherals

The term processor peripherals refers to the multiple on-chip functional blocks used to communicate with off-chip devices. The peripherals include the JTAG, UART, serial ports, SPI ports, DAI/DPI components (PCG, timers, and IDP are a few), and any external devices that connect to the processor.
I/O Processor
The ADSP-21367/8/9 and ADSP-2137x processors input/output proces­sor (IOP) manages the off-chip data I/O to alleviate the core of this burden. Up to thirty-four channels of DMA are available on the ADSP-21367/8/9 and ADSP-2137x processors—sixteen via the serial ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface, 2 for the external port, and 2 for memory-to-memory transfers. The I/O processor can perform DMA transfers between the peripherals and inter­nal memory at the full core clock speed. The architecture of the internal memory allows the IOP and the core to access internal memory simulta­neously with no reduction in throughput.
Serial Ports. The processors feature up to eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half of the processor core clock rate with maximum of 50M bits per second. Each serial port features two data pins that function as a pair based on the
ADSP-21368 SHARC Processor Hardware Reference 1-7
Architectural Overview
same serial clock and frame sync. Accordingly, each serial port has two DMA channels and serial data buffers associated with it to service the dual serial data pins. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA. Each of the serial ports offers a TDM multichannel mode (up to 128 channels) and supports μ-law or
A-law companding. I
2
S support is also provided with the
ADSP-21367/8/9 and ADSP-2137x processors.
The serial ports can operate with least significant bit first (LSBF) or most significant bit first (MSBF) transmission order, with word lengths from 3 to 32 bits. The serial ports offer selectable synchronization and transmit modes. Serial port clocks and frame syncs can be internally or externally generated.
Serial Peripheral (Compatible) Interface (SPI). The SPI is an industry standard synchronous serial link that enables the SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface con­sisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. It can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device.
The SPI-compatible peripheral implementation also supports programma­ble baud rate and clock phase/polarities, as well as the use of open drain drivers to support the multimaster scenario to avoid data contention.
SDRAM Controller. The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs,
f
at speeds up to bank has it’s own memory select line (
. Fully compliant with the SDRAM standard, each
SCLK
MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
1-8 ADSP-21368 SHARC Processor Hardware Reference
Introduction
ROM-Based Security. For those processors with application code in the on-chip ROM, an optional ROM security feature is included. This feature provides hardware support for securing user software code by preventing unauthorized reading from the enabled code. The processor does not boot-load any external code, executing exclusively from internal ROM. Also, the processor is not freely accessible via the JTAG port. Instead, a 64-bit key is assigned to the user. This key must be scanned in through the JTAG or Test Access Port. The device ignores a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.
Digital Audio Interface (DAI)
The digital audio interface (DAI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, an interface data port, and a signal routing unit, four precision clock generators (PCGs) and three timers. Some family members have an S/PDIF receiver/transmitter and eight channels asynchronous sample rate converters (SRC).
Interrupt Controller. The DAI contains its own interrupt controller that indicates to the core when DAI audio events have occurred. This interrupt controller offer 32 independently configurable channels.
Input Data Port (IDP). The input data port provides the DAI with a way to transmit data from within the DAI to the core. The IDP provides a means for up to eight additional DMA paths from the DAI into on-chip memory. All eight channels support 24-bit wide data and share a 16-deep FIFO.
Signal Routing Unit One (SRU1). Conceptually similar to a “patch-bay” or multiplexer, the SRU provides a group of registers that define the inter­connection of the serial ports, the input data port, the DAI pins, and the precision clock generators.
ADSP-21368 SHARC Processor Hardware Reference 1-9

Development Tools

Digital Peripheral Interface (DPI)
The digital peripheral interface (DPI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, a two wire interface port (TWI), and a signal routing unit, three timers and a Universal Asynchronous Receiver/Transmitter (UART).
Interrupt Controller. The DPI contains its own interrupt controller that indicates to the core when DPI audio events have occurred. This interrupt controller offer 32 independently configurable channels.
Two Wire Interface (TWI). The two wire interface (TWI) controller allows a device to interface to an Inter IC bus as specified by the Philips
2
I
C Bus Specification version 2.1 dated January 2000.
Universal Asynchronous Receiver/Transmitter (UART). A full-duplex peripheral compatible with PC-style, industry-standard UARTs. The UART converts data between serial and parallel formats. The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events.
Signal Routing Unit Two (SRU2). Conceptually similar to a “patch-bay” or multiplexer, SRU2 provides a group of registers that define the inter­connection of the DPI’s peripherals, the DPI pins, and the timers.
Development Tools
The ADSP-21367/8/9 and ADSP-2137x processors are supported by VisualDSP++, an easy-to-use integrated development and debugging envi­ronment (IDDE). VisualDSP++ allows you to manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities.
1-10 ADSP-21368 SHARC Processor Hardware Reference
Introduction

Differences From Previous Processors

This section identifies differences between the ADSP-21367/8/9 and ADSP-2137x processors and previous SHARC processors: ADSP-21161, ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC processor family is based on the original ADSP-2106x SHARC family. The ADSP-21367/8/9 and ADSP-2137x processors preserve much of the ADSP-2106x architecture and is code compatible to the ADSP-21160, while extending performance and functionality. For background informa­tion on SHARC processors and the ADSP-2106x family DSPs, see the
ADSP-2106x SHARC User’s Manual or the ADSP-21065L SHARC DSP Technical Reference.

I/O Architecture Enhancements

The I/O processor provides much greater throughput than that on the ADSP-2106x processors.
The DMA controller supports up to 34 channels compared to 14 channels on the ADSP-21161 processor. DMA transfers occur at clock speed in parallel with full speed processor execution. The ADSP-21367/8/9 and ADSP-2137x processors also provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction.
In addition to the above, the ADSP-21367/8/9 and ADSP-2137x proces­sors have up to eight serial ports (SPORTs), a 32-bit external memory interface, a universal asynchronous transmitter/receiver (UART) and an
2
C compatible interface called the TWI (two wire interface).
I
ADSP-21368 SHARC Processor Hardware Reference 1-11
Differences From Previous Processors

Instruction Set Enhancements

The ADSP-21367/8/9 and ADSP-2137x processors provide source code compatibility with the previous SHARC processor family members to the application assembly source code level. All instructions, control registers, and system resources available in the ADSP-2106x core programming model are also available in the ADSP-21367/8/9 and ADSP-2137x proces­sors. Instructions, control registers, or other facilities required to support the new feature set of the ADSP-2116x core include:
Code compatibility to the ADSP-21160 SIMD core
Supersets of the ADSP-2106x programming model
Reserved facilities in the ADSP-2106x programming model
Symbol name changes from the ADSP-2106x programming models
These name changes can be managed through reassembly by using the development tools to apply the ADSP-21367/8/9 and ADSP-2137x pro­cessor symbol definitions header file and linker description file. While these changes have no direct impact on existing core applications, system and I/O processor initialization code and control code do require modifications.
Although the porting of source code written for the ADSP-2106x family to the ADSP-21367/8/9 and ADSP-2137x processors has been simplified, code changes are required to take full advantage of the new features. For more information, see the ADSP-2136x SHARC Processor Programming Reference.
1-12 ADSP-21368 SHARC Processor Hardware Reference

2 I/O PROCESSOR

In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to per­form data transfers. The ADSP-21367/8/9 and ADSP-2137x processors contain an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data. These operations include the transfer types listed below and shown in Figure 2-2 on page 2-25.
Internal memory external memory devices (through the external
port)
Internal memory digital audio/digital peripheral interfaces
(DAI/DPI)
Internal memory serial port I/O
Internal memory serial peripheral interface I/O
Internal memory UART I/O
Internal memory
By managing DMA, the I/O processor frees the processor core, allowing it to perform other operations while off-chip data I/O occurs as a back­ground task. The multibank architecture of the internal memory allows the core and IOP to simultaneously access the internal memory if the accesses are to different memory banks. This means that DMA transfers to internal memory do not impact core performance. The processor core continues to perform computations without penalty.
ADSP-21368 SHARC Processor Hardware Reference 2-1
internal memory

General Procedure for Configuring DMA

To further increase off-chip I/O, multiple DMAs can occur at the same time. The IOP accomplishes this by managing DMAs of processor mem­ory through the TWI, UART, SPI, input data port (IDP), and serial ports.
[
Accesses to IOP spaces (from the processor core) should not use Type 1 (dual access) or LW instructions.
General Procedure for Configuring DMA
To configure the ADSP-21367/8/9 and ADSP-2137x processors to use DMA, use the following general procedure.
1. Determine which DMA options you want to use:
IOP/core interaction method – interrupt-driven or sta­tus-driven (polling)
DMA transfer method – chained, non-chained, or delay line
Channel priority scheme – fixed or rotating
2. Determine how you want the DMA to operate:
Set up the data’s source and/or destination addresses (INDEX)
Set up the word COUNT (data buffer size)
Configure the MODIFY values (step size)
3. Configure the peripheral(s):
External port (includes AMI, SDRAM)
Serial ports (SPORTs)
Universal asynchronous receive/transmit (UART)
2-2 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Serial peripheral interface ports (SPI)
Input data port (IDP)
4. Enable DMA
Set the applicable bits in the appropriate control registers
For peripheral specific DMA information, see the following sections.
“External Port DMA” on page 2-35
“Serial Port DMA” on page 2-40
“Serial Peripheral Interface DMA” on page 2-42
“UART DMA” on page 2-44
“Memory-to-Memory DMA” on page 2-48

Core Access to IOP Registers

In certain cases, extra core cycles are needed to process register accesses. The access cycles are shown in Table 2-1 and the registers are shown in
Table 2-2.
Table 2-1. I/O Processor Stall Conditions
Type Of Access Number of Core Cycles
Core write
Core read
Unconditional, isolated I/O processor register write
Unconditional I/O processor register write after a write
Unconditional I/O processor register read
ADSP-21368 SHARC Processor Hardware Reference 2-3
1
1
2
2
2
1
2
1
2 (back-to-back)
7/8
Core Access to IOP Registers
Table 2-1. I/O Processor Stall Conditions (Cont’d)
Type Of Access Number of Core Cycles
Aborted conditional I/O processor register read/write
Conditional I/O processor register read/write
1 Applies to memory-mapped registers from Table 2-2. 2 Applies to all other memory-mapped registers not in Table 2-2.
2
3
2
9/10
Table 2-2. Memory-Mapped Emulation/Breakpoint Registers
Register Description Address
EEMUIN Emulator input FIFO 0x30020
EEMUSTAT Enhanced emulation status 0x30021
EEMUOUT Emulator output FIFO 0x30022
OSPID Operating system process ID 0x30023
SYSCTL System control 0x30024
BRKCTL Breakpoint control 0x30025
REVPID Emulation/revision ID 0x30026
PSA1S/E Instruction breakpoint address number 1
start/end
PSA2S/E Instruction breakpoint address number 2
start/end
0x300A0/ 0x300A1
0x300A2/ 0x300A3
PSA3S/E Instruction breakpoint address number 3
start/end
PSA4S/E Instruction breakpoint address number 4
start/end
EMUN Number of breakpoints before EMU
interrupt
IOAS/E I/O address breakpoint start/end 0x300B0/
0x300A4/ 0x300A5
0x300A6/ 0x300A7
0x300AE
0x300B1
2-4 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-2. Memory-Mapped Emulation/Breakpoint Registers (Cont’d)
Register Description Address
DMA1S/E Data memory breakpoint address number
1 start/end
DMA2S/E Data memory breakpoint address number
2 start/end
PMDAS/E Program memory breakpoint address
start/end
0x300B2/ 0x300B3
0x300B3/ 0x300B4
0x300B8/ 0x300B9
In addition to the above, the following situations incur additional stall cycles.
1. An aborted conditional I/O processor register read can cause one or two extra core-clock stall cycles if it immediately follows a write. Such a read is expected to take three core cycles, but it takes four or five.
2. In case of a full write FIFO, the held-off I/O processor register read or write access incurs one extra core-clock cycle.
3. Interrupted reads and writes, if preceded by another write, creates an additional one core cycle stall.
Inside of an interrupt service routine (ISR), a write into an IOP register that clears the interrupt has some latency. During this delay, the interrupt may be generated a second time if the program executes an
RTI
instruction.
For example, in the following code the interrupt isn’t cleared instanta­neously. During the delay, if the program comes out of the ISR, the interrupt is generated again.
/*.... code .....*/
dm(TXSPI) = R0; /* Write to TXSPI FIFO; disable spi; clears the interrupt */ rti;
ADSP-21368 SHARC Processor Hardware Reference 2-5

Configuring IOP/Core Interaction

In order to resolve this issue, use one of the following methods.
1. Read an IOP register from the same peripheral block before execut­ing the RTI. This read forces the write to occur first.
dm(TXSPI) = R0; /* Write to TXSPI FIFO */ R0 = dm(SPICTL); /* Dummy read. This read happens only after write */ rti;
2. Add sufficient NOP instructions after a write. In all cases, ten NOP instructions after a write is sufficient to properly update the status.
R0 = 0x0; dm(SPICTL) = R0; /* Disable spi */ nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; rti;
Configuring IOP/Core Interaction
There are two methods the processor uses to monitor the progress of DMA operations—interrupts, which are the primary method, and status polling. The same program can use either method for each DMA channel. The following sections describe both methods in detail.

Interrupt-Driven I/O

Interrupts are generated at the end of a DMA transfer. This happens when the count register for a particular channel decrements to zero. The default interrupt vector locations for each of the channels are listed in Table 2-3
on page 2-9. The interrupt register diagrams and bit descriptions are given
in Appendix B, Interrupts and “DAI Interrupt Controller Registers” on
page A-112.
2-6 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
L
Programs can check the appropriate status or configuration register to determine which channels are performing a DMA or chained DMA.
All DMA channels can be active or inactive. If a channel is active, a DMA is in progress on that channel. The I/O processor indicates the active sta­tus by setting the channel’s bit in the status register. The only exception to this is the IDP_DMAx_STAT bits of the DAI_STAT register can become active even if DMA, through some IDP channel, is not intended.
The following are some other I/O processor interrupt attributes.
The processors also have programmable interrupts using the peripheral interrupt priority control registers, PICRx. For more
information, see “Peripheral Interrupt Priority Control Registers” on page A-164.
When an unchained (single block) DMA process reaches comple­tion (as the count decrements to zero) on any DMA channel, the I/O processor latches that DMA channel’s interrupt. It does this by setting the DMA channel’s interrupt latch bit in the IRPTL, LIRPTL,
DAI_IRPTL_H, or DAI_IRPTL_L registers.
For chained DMA, the I/O processor generates interrupts in one of two ways: If PCI = 1, bit 19 of the chain pointer register is the program con­trolled interrupts bit and an interrupt occurs for each DMA in the chain. If PCI = 0, an interrupt occurs at the end of a complete chain. (For more information on DMA chaining, see “DMA Controller Oper-
ation” on page 2-13.)
When a DMA channel’s buffer is not being used for a DMA pro­cess, the I/O processor can generate an interrupt on single word writes or reads of the buffer. This interrupt service differs slightly for each port. For more information on single-word inter­rupt-driven transfers, see “Serial Port Control Registers (SPCTLx)”
on page 5-59.
ADSP-21368 SHARC Processor Hardware Reference 2-7
Configuring IOP/Core Interaction
During interrupt-driven DMA, programs use the interrupt mask bits in the
IMASK, LIRPTL, DAI_IRPTL_PRI, DAI_IRPTL_RE, and DAI_IRPTL_FE reg-
isters to selectively mask DMA channel interrupts that the I/O processor latches into the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L registers.
L
A channel interrupt mask in the IMASK, LIRPTL, DAI_IRPTL_PRI,
DAI_IRPTL_RE, and DAI_IRPTL_FE registers determines whether a latched
interrupt is to be serviced or not. When an interrupt is masked, it is latched but not serviced. For more information on the IMASK and LIRPTL registers, see “Interrupt Registers” on page B-6.
L
The I/O processor can also generate interrupts for I/O port operations that do not use DMA. In this case, the I/O processor generates an inter­rupt when data becomes available at the receive buffer or when the transmit buffer is not full (when there is room for the core to write to the buffer). Generating interrupts in this manner lets programs implement interrupt-driven I/O under control of the processor core. Care is needed because multiple interrupts can occur if several I/O ports transmit or receive data in the same cycle.
The I/O processor only generates a DMA complete interrupt when the channel’s count register decrements to zero as a result of actual DMA transfers. Writing zero to a count register does not generate the interrupt. To stop a DMA preemptively, write a one to the count register. This causes one more word to be transferred or received and an interrupt is then generated.
By clearing a channel’s PCI bit during chained DMA, programs mask the DMA complete interrupt for a DMA process within a chained DMA sequence.
The digital audio interface (DAI) has two interrupts—the lower priority option ( rupts to have priorities that are higher and lower than serial ports.
2-8 ADSP-21368 SHARC Processor Hardware Reference
DAILI) and higher priority option (DAIHI). This allows two inter-
Table 2-3. Default DMA Interrupt Vector Locations
I/O Processor
Associated Register(s) Bits Vector
Address
IRPTL/IMASK 14 0x38 SP1I 0 RXSP1A, TXSP1A
LIRPTL 0 0x44 SP0I 2 RXSP0A, TXSP0A
IRPTL/IMASK 15 0x3C SP3I 4 RXSP3A, TXSP3A
LIRPTL 1 0x48 SP2I 6 RXSP2A, TXSP2A
IRPTL/IMASK 16 0x40 SP5I 8 RXSP5A, TXSP5A
LIRPTL 2 0x4C SP4I 10 RXSP4A, TXSP4A
IRPTL/IMASK 5 0x58 SP7I 12 RXSP7A, TXSP7A
LIRPTL 19 0x6C SP6I 14 RXSP6A, TXSP6A
IRPTL/IMASK 14 0x38 SP1I 1 RXSP1B, TXSP1B
LIRPTL 0 0x44 SP0I 3 RXSP0B, TXSP0B
IRPTL/IMASK 15 0x3C SP3I 5 RXSP3B, TXSP3B
LIRPTL 1 0x48 SP2I 7 RXSP2B, TXSP2B
IRPTL/IMASK 16 0x40 SP5I 9 RXSP5B, TXSP5B
LIRPTL 2 0x4C SP4I 11 RXSP4B, TXSP4B
IRPTL/IMASK 5 0x58 SP7I 13 RXSP7B, TXSP7B
Interrupt Name
DMA Channel
Data Buffer
LIRPTL 19 0x6C SP6I 15 RXSP6B, TXSP6B
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
11
6
11
6
0x2C
0x5C
0x2C
0x5C
DAIHI
DAILI
DAIHI
DAILI
16 IDP_FIF0
Channel 0
17 IDP_FIF0
Channel 1
ADSP-21368 SHARC Processor Hardware Reference 2-9
Configuring IOP/Core Interaction
Table 2-3. Default DMA Interrupt Vector Locations (Cont’d)
Associated Register(s) Bits Vector
Address
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
IRPTL/IMASK (high priority option) LIRPTL (low priority option)
11
6
11
6
11
6
11
6
11
6
11
6
0x2C
0x5C
0x2C
0x5C
0x2C
0x5C
0x2C
0x5C
0x2C
0x5C
0x2C
0x5C
Interrupt Name
DAIHI
DAILI
DAIHI
DAILI
DAIHI
DAILI
DAIHI
DAILI
DAIHI
DAILI
DAIHI
DAILI
DMA Channel
18 IDP_FIF0
19 IDP_FIF0
20 IDP_FIF0
21 IDP_FIF0
22 IDP_FIF0
23 IDP_FIF0
Data Buffer
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
IRPTL/IMASK (high priority option)
LIRPTL (low priority option)
IRPTL/IMASK 18 0x68 MTMI 26 MTM Read FIFO
IRPTL/IMASK UART0RXI 27 RBR0
IRPTL/IMASK UART1RXI 28 RBR1
IRPTL/IMASK UART0TXI 29 THR0
12 0x30 SPIHI 24 RXSPI, TXSPI
9 0x74 SPILI 25 RXSPIB, TXSPIB
2-10 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-3. Default DMA Interrupt Vector Locations (Cont’d)
Associated Register(s) Bits Vector
Address
IRPTL/IMASK UART1TXI 30 THR1
LIRPTL 0x50 EPDMA 31 EPDF0
LIRPTL EPDMA 32 EPTF0
LIRPTL 0x50 EPDMA 33 EPDF1
IRPTL/IMASK MTMI 34 MTM Write FIFO
Interrupt Name
DMA Channel
Data Buffer
For more information, see the program sequencer “Interrupts and Sequencing” section of Chapter 3 in the ADSP-2136x SHARC Processor Programming Reference and Appendix B, Interrupts.
Interrupt Latency in Interrupt-Driven Transfers
During an interrupt-driven I/O transfer from any peripheral that uses an IOP interrupt service routine, a write into an IOP register to clear the interrupt causes a certain amount of latency. If the program comes out of the interrupt service routine during that period of latency, the interrupt is generated again.
To avoid the interrupt from being regenerated, use one of the following solutions.
1. Read an IOP register from the same peripheral block before the return from interrupt (
RTI). The read forces the write to occur as
shown in the example code below.
isr_code: R0 = 0x0; dm(SPICTL) = R0; /* disable SPI */ R0 = dm(SPICTL); /* dummy read, occurs only after write */ rti;
ADSP-21368 SHARC Processor Hardware Reference 2-11
Configuring IOP/Core Interaction
2. Add sufficient
NOP instructions after a write. In the worst case pro-
grams need to add ten NOP instructions after a write as shown in the example code below.
isr_code:
R0 = 0x0; dm(SPICTL) = R0; /* disable SPI */ nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; rti;
3. Read a status register from the same peripheral block to check whether the interrupt has cleared.

Polling/Status-Driven I/O

The second method of controlling I/O is through status polling. The I/O processor monitors the status of data transfers on DMA channels and indi­cates interrupt status in the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L registers. Note that because polling uses processor resources it is not as efficient as an interrupt-driven system. Also note that polling the DMA status registers reduces I/O bandwidth. The following provide more infor­mation on the registers that control and monitor I/O processes.
All the bits in the
IRPTL and LIRPTL registers are shown in “Inter-
rupt Latch Register (IRPTL)” on page B-13 and “Interrupt Register (LIRPTL)” on page B-6.
Figure A-44 on page A-114 lists all the bits in the
DAI_IRPTL_L registers.
DAI_IRPTL_H and
The DMA controller in the ADSP-21367/8/9 and ADSP-2137x proces­sors maintains the status information of the channels in each of the peripherals registers, SPMCTLx, EPDMACTL, DAI_STAT, DPI_PIN_STAT,
RXSTAT_UACx, TXSTAT_UACx and SPIDMAC. More information on these regis-
ters can be found at the following locations.
2-12 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Bit definitions for the
Status (SPISTAT, SPISTATB) Registers” on page A-56.
Bit definitions for the SPMCTLx register are illustrated in “SPORT
Multichannel Control Registers (SPMCTLx)” on page A-40.
Bit definitions for the DAI_STAT register are illustrated in
Figure A-41 on page A-110.
Note that there is a one-cycle latency between a change in DMA channel status and the status update in the corresponding register.
SPIDMAC register are illustrated in “SPI Port

DMA Controller Operation

There are two methods you can use to start DMA sequences: chaining and non-chaining.
Non-chained DMA. To start a new DMA sequence after the current one is finished, a program must first clear the DMA enable bit, write new parameters to the index, modify, and count registers, then set the DMA enable bit to re-enable DMA.
Chained DMA. Chained DMA sequences are a set of multiple DMA operations, each autoinitializing the next in line. To start a new DMA sequence after the current one is finished, the IOP automatically loads new index, modify, and count values from an internal memory location pointed to by that channel’s chain pointer register. Using chaining, pro­grams can set up consecutive DMA operations and each operation can have different attributes.
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ADSP-21368 SHARC Processor Hardware Reference 2-13
Chaining is only supported on the SPI and SPORT DMA chan­nels. The IDP port does not support chaining.
Configuring IOP/Core Interaction
In general, a DMA sequence starts when one of the following occurs:
Chaining is disabled, and the DMA enable bit transitions from low to high.
Chaining is enabled, DMA is enabled, and the chain pointer regis­ter address field is written with a nonzero value. In this case, TCB chain loading of the channel parameter registers occurs first.
Chaining is enabled, the chain pointer register address field is non­zero, and the current DMA sequence finishes. Again, TCB chain loading occurs.
A DMA sequence ends when one of the following occurs:
The count register decrements to zero, and the chain pointer regis­ter is zero.
Chaining is disabled and the channel’s DMA enable bit transitions from high to low. If the DMA enable bit goes low (=0) and chain­ing is enabled, the channel enters chain insertion mode and the DMA sequence continues. For more information, see “Inserting a
TCB in an Active Chain” on page 2-41.
Once a program starts a DMA process, the process is influenced by two external controls—DMA channel priority and DMA chaining. For more information, see “Managing DMA Channel Priority” on page 2-19 or
“Chaining DMA Processes” below.
Chaining DMA Processes
The location of the DMA parameters for the next sequence comes from the chain pointer register. In chained DMA operations, the processor automatically initializes and then begins another DMA transfer when the current DMA transfer is complete. In addition to the standard DMA parameter registers, each DMA channel (SPORT, eternal port, UART and SPI) also has a chain pointer register that points to the next set of DMA
2-14 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
parameters stored in the processor’s internal memory. These are the
CPSPxy registers for the SPORTs, the CPEP register for the external port,
the RXCP_UACx registers for the UART, and the CPSPI register for the SPI. Each new set of parameters is stored in a four-word, user-initialized buffer in internal memory known as a transfer control block (TCB).
The structure of a TCB is conceptually the same as that of a traditional linked list. Each TCB has several data values and a pointer to the next TCB. Further, the chain pointer of a TCB may point to itself to con­stantly reiterate the same DMA.
A DMA sequence is defined as the sum of the DMA transfers for a single channel, from when the parameter registers initialize to when the count register decrements to zero. Each DMA channel has a chaining enable bit (CHEN) in the corresponding control register. This bit must be set to one to enable chaining. When chaining is enabled, DMA transfers are initiated by writing a memory address to the chain pointer register. This is also an easy way to start a single DMA sequence, with no subsequent chained DMAs.
The chain pointer register can be loaded at any time during the DMA sequence. This allows a DMA channel to have chaining disabled (chain pointer register address field = 0x0000) until some event occurs that loads the chain pointer register with a nonzero value. Writing all zeros to the address field of the chain pointer register also disables chaining.
If chaining is enabled on a DMA channel, programs should not use poll­ing to determine channel status as it can provide inaccurate information. In this case, the DMA appears inactive if it is sampled while the next transfer control block (TCB) is loading.
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The chain pointer register is 20 bits wide. The lower 19 bits are the mem­ory address field. Like other I/O processor address registers, the chain pointer register’s value is offset to match the starting address of the
ADSP-21368 SHARC Processor Hardware Reference 2-15
Chained DMA operations may only occur within the same chan­nel. The processor does not support cross-channel chaining.
Configuring IOP/Core Interaction
processor’s internal memory before it is used by the I/O processor. On the ADSP-21367/8/9 and ADSP-2137x processors, this offset value is 0x0008 0000.
Bit 19 of the chain pointer register is the program-controlled interrupts (
PCI) bit. This bit controls whether an interrupt is latched after every
DMA in the chain (when set), or whether the interrupt is latched after the entire DMA sequence completes (if cleared).
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Because the PCI bit is not part of the memory address in the chain pointer register, programs must use care when writing and reading addresses to and from the register. To prevent errors, programs should mask out the
PCI bit (bit 19) when copying the address in a chain pointer register to
another address register.
The DMA registers are shown in Figure 2-1.
Transfer Control Block Chain Loading (TCB)
During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory. The address in the chain pointer register points to the highest address of the TCB (containing the index parameter). This means that if a program declares an array to hold the TCB, the chain pointer register should not point to the first location of the array.
Table 2-4 shows the TCB-to-register loading sequence for the serial port
and SPI port DMA channels. The I/O processor reads each word of the TCB and loads it into the corresponding register. Programs must set up the TCB in memory in the order shown in Table 2-4, placing the index parameter at the address pointed to by the chain pointer register of the
The PCI bit only effects DMA channels that have chaining enabled. Also, interrupt requests enabled by the PCI bit are maskable with the IMASK register.
2-16 ADSP-21368 SHARC Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IIx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPx
Program – Controlled Interrupt Bit If this bit is set, theI/O processor generates a DMA interrupt after every DMA in the chain.
PCI Bit
I/O Processor
Figure 2-1. DMA Parameter Registers
previous DMA operation of the chain. The end of the chain (no further TCBs are loaded) is indicated by a TCB with a chain pointer register value of zero.
ADSP-21368 SHARC Processor Hardware Reference 2-17
Configuring IOP/Core Interaction
Table 2-4. TCB Chain Loading Sequence
Address2 External Port Serial Ports SPI Port
CPSPx + 0x0008 0000 See Table 2-9, Table 2-10,
Table 2-11
CPSPx – 1 + 0x0008 0000 IMSPx IMSPI
CPSPx – 2 + 0x0008 0000 CSPx CSPI
CPSPx – 3 + 0x0008 0000 CPSPx CPSPI
CPSPx – 4 + 0x0008 0000
CPSPx – 5 + 0x0008 0000
CPSPx – 6 + 0x0008 0000
1 Chaining is not available using the IDP port. 2 An “x” denotes the DMA channel used. While the TCB is eight locations in length, SPI and serial
ports only use the first four locations.
1
IISPx IISPI
A TCB chain load request is prioritized like all other DMA operations. The I/O processor latches a TCB loading request and holds it until the load request has the highest priority. If multiple chaining requests are present, the I/O processor services the
TCB registers for the highest priority
DMA channel first. A channel that is in the process of chain loading can­not be interrupted by a higher priority channel. For a list of DMA channels in priority order, see Table 2-7 on page 2-32.

Setting Up DMA Channel Allocation and Priorities

There are between 24 and 34 channels of DMA available on the ADSP-21367/8/9 and ADSP-2137x processors, depending on the proces­sor model. The maximum number is configured as—16 via the serial ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface, 2 for the external port, and 2 for memory-to-memory transfers. Each channel has a set of parameter registers which are used to set up DMA
2-18 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
transfers. Table 2-5 shows the DMA channel allocation and parameter register assignments for the ADSP-21367/8/9 and ADSP-2137x processors.
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Managing DMA Channel Priority
The DMA channel prioritization scheme ranks channel 0 as highest prior­ity and channel 34 as the lowest priority. Table 2-7 on page 2-32 lists the DMA channels in priority order. When a channel becomes the highest priority requester, the I/O processor services the channel’s request. In the next clock cycle, the I/O processor starts the DMA transfer.
The I/O data (IOD) bus is 32 bits wide and is the only path that the IOP uses to transfer data between internal memory and the peripherals. When there are two or more peripherals with active DMAs in progress, they may all require data to be moved to or from memory in the same cycle. For example, the input data port may fill its RXPP buffer just as a SPORT shifts a word into its RXn buffer. To determine which word is transferred first, the DMA channels for each of the processor’s I/O ports negotiate channel priority with the I/O processor using an internal DMA request/grant handshake.
DMA channels vary by processor model. For a breakdown of DMA channels for a particular model, see the processor specific data sheet.
Each I/O port has one or more DMA channels, and each channel has a single request and a single grant. When a particular channel needs to read or write data to internal memory, the channel asserts an internal DMA request. The I/O processor prioritizes the request with all other valid DMA requests. When a channel becomes the highest priority requester, the I/O processor asserts the channel’s internal DMA grant. In the next clock cycle, the DMA transfer starts. Figure 2-3 on page 2-30 shows the paths for internal DMA requests within the I/O processor.
ADSP-21368 SHARC Processor Hardware Reference 2-19
Configuring IOP/Core Interaction
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The default DMA channel priority is fixed prioritization by DMA channel group (serial ports, TWI, UART, IDP, or SPI port). Table 2-7 on
page 2-32 lists the DMA channels in descending order of priority.
For information on programming serial port priority modes, see
Table 5-11 on page 5-74.
The I/O processor determines which DMA channel has the highest prior­ity internal DMA request during every cycle between each data transfer.
Processor core accesses of I/O processor registers and TCB chain loading (both of which occur after the IOD transfer) are subject to the same prior­itization scheme as the DMA channels. Applying this scheme uniformly prevents I/O bus contention, because these accesses are also performed over the internal I/O bus. For more information, see “Chaining DMA
Processes” on page 2-14.
DMA Bus Arbitration
If a DMA channel is disabled (EPDEN, SPIDEN, SDEN, or IDP_DMA_EN bits =0), the I/O processor does not issue internal DMA grants to that channel (whether or not the channel has data to transfer).
DMA channel arbitration is the method that the IOP uses to determine how groups rotate priority with other channels. This feature is enabled by setting the
DMA-capable peripherals execute DMA data transfers to and from inter­nal memory over the IOD bus. When more than one of these peripherals requests access to the IOD bus in a clock cycle, the bus arbiter, which is attached to the IOD bus, determines which master should have access to the bus and grants the bus to that master.
2-20 ADSP-21368 SHARC Processor Hardware Reference
DCPR bit in the IOP’s SYSCTL register.
I/O Processor
IOP channel arbitration can be set to use either a fixed or rotating algo­rithm by setting or clearing bit 7 (
DCPR) in the SYSCTL register:
•fixed SYSCTL[7] cleared (0)
rotating SYSCTL[7] set (1)
In the fixed priority scheme, the lower indexed peripheral has the highest priority.
In the rotating priority scheme, the default priorities at reset are the same as that of the fixed priority. However, the peripheral priority is deter­mined by group, not individually. Peripheral groups are shown in
Table 2-5.
Initially, group A has the highest priority and group F the lowest. As one group completes its DMA operation, it is assigned the lowest priority (moves to the back of the line) and the next group is given the highest priority.
When none of the peripherals request bus access, the highest priority peripheral, for example, peripheral#0, is granted the bus. However, this does not change the currently assigned priorities to various peripherals.
Within a peripheral group the priority is highest for the higher indexed peripheral (see Table 2-5). For example, in SP01 (which is in group A), SP1 has the highest priority.
Table 2-5. DMA Channel Allocation and Parameter Register Assignments
DMA Channel Number
0 (highest priority)
1 RXSP1B, TXSP1B A 0xC67, 0xC66 Serial Port 1B Data
Data Buffer Group IOP Address of
Data Buffers
RXSP1A, TXSP1A A 0xC65, 0xC64 Serial Port 1A Data
Description
ADSP-21368 SHARC Processor Hardware Reference 2-21
Configuring IOP/Core Interaction
Table 2-5. DMA Channel Allocation and Parameter Register Assignments (Cont’d)
DMA Channel Number
2 RXSP0A, TXSP0A A 0xC61, 0xC60 Serial Port 0A Data
3 RXSP0B, TXSP0B A 0xC63, 0xC62 Serial Port 0B Data
4 RXSP3A, TXSP3A B 0x465, 0x464 Serial Port 3A Data
5 RXSP3B, TXSP3B B 0x467, 0x466 Serial Port 3B Data
6 RXSP2A, TXSP2A B 0x461, 0x460 Serial Port 2A Data
7 RXSP2B, TXSP2B B 0x463, 0x462 Serial Port 2B Data
8 RXSP5A, TXSP5A C 0x865, 0x864 Serial Port 5A Data
9 RXSP5B, TXSP5B C 0x867, 0x866 Serial Port 5B Data
10 RXSP4A, TXSP4A C 0x861, 0x860 Serial Port 4A Data
11 RXSP4B, TXSP4B C 0x863, 0x862 Serial Port 4B Data
12 RXSP7A, TXSP7A C 0x04865,
13 RXSP7B, TXSP7B C 0x04867,
14 RXSP6A, TXSP6A C 0x04861 or
Data Buffer Group IOP Address of
Data Buffers
0x04864
0x04866
0x04860
Description
Serial Port 7A Data
Serial Port 7B Data
Serial Port 6A Data
15 RXSP6B, TXSP6B C 0x04863 or
0x04862
16 IDP_FIF0 D 0x24D0 DAI IDP Channel 0
17 IDP_FIF0 D 0x24D0 DAI IDP Channel 1
18 IDP_FIF0 D 0x24D0 DAI IDP Channel 2
19 IDP_FIF0 D 0x24D0 DAI IDP Channel 3
20 IDP_FIF0 D 0x24D0 DAI IPD Channel 4
21 IDP_FIF0 D 0x24D0 DAI IDP Channel 5
Serial Port 6B Data
2-22 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-5. DMA Channel Allocation and Parameter Register Assignments (Cont’d)
DMA Channel Number
22 IDP_FIF0 D 0x24D0 DAI IDP Channel 6
23 IDP_FIF0 D 0x24D0 DAI IDP Channel 7
24 RXSPI, TXSPI E 0x1004, 0x1003 SPI Data
25 RXSPIB, TXSPIB G 0x2804, 0x2803 SPI Data
26 MTM Read FIFO G Not accessible Memory-to-Memory
27 THR0 G 0x3C00 UART0 Transmit
28 RBR0 G 0x3C00 UART0 Receive Buffer
29 THR1 G 0x4000 UART1 Transmit
30 RBR1 G 0x4000 UART1 Receive Buffer
31 EPDF0 G 0x182C External Port Channel0
32 EPTF0 G 0x182D External Port Channel0
Data Buffer Group IOP Address of
Data Buffers
Description
Read Data
Holding Register
Register
Holding Register
Register
Data FIFO
Tap List FIFO
33 EPDF1 G 0x183C External Port Channel1
Data FIFO
34 EPTF1 G 0x183D External Port Channel1
Tap List FIFO
35 (lowest priority)
MTM Write FIFO G Not accessible Memory-to Memory
Write Dat a
ADSP-21368 SHARC Processor Hardware Reference 2-23

Setting Up DMA Parameter Registers

Setting Up DMA Parameter Registers
Once you have determined and configured the DMA options, you can configure the DMA parameter registers. The parameter registers control the source and destination of the data, the size of the data buffer, and the step size used. These topics are described in detail in the following sections.

DMA Transfer Direction

DMA transfers between internal memory and external memory devices use the processor’s external port. For these types of transfers, a program pro­vides the DMA controller with the internal memory buffer size, address, and address modifier, as well as the external memory buffer size, address and address modifier and the direction of transfer. After setup, the DMA transfers begin when the program enables the channel and continues until the I/O processor transfers the entire buffer to processor memory.
Table 2-6 on page 2-29 shows the parameter registers for each DMA
channel.
Similarly, DMA transfers between internal memory and serial, IDP or SPI ports have DMA parameters. When the I/O processor performs DMA between internal memory and one of these ports, the program sets up the parameters, and the I/O uses the port instead of the external bus.
Additionally, the ADSP-21367/8/9 and ADSP-2137x processors can use DMA to transfer 64-bit blocks of data between internal memory locations.
The direction (receive or transmit) of the peripheral determines the direc­tion of data transfer. When the port receives data, the I/O processor automatically transfers the data to internal memory. When the port needs to transmit a word, the I/O processor automatically fetches the data from internal memory. Figure 2-2 shows the processor’s I/O processor, related ports, and buses. Figure 2-3 on page 2-30 shows more detail on DMA channel data paths.
2-24 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
IOA BUS
SPORT
IISP 7A -0A,
IISP 7B -0B, IMS P7 A-0A , IMS P7B -0B
CSP7A-0A,
CSP7B-0B, CPSP7A-0A, CPSP7B-0B
SPI
IISP I, IM SPI, CSPI,CPSPI
IDP
IDP_DMA_Ix IDP_DMA_Mx IDP_DMA_Cx
UART
UARTxRXCTL, IIUARTxRX
IMUARTxRX, CUARTxRX
CPUARTxRX,UARTxRXSTAT
UARTxTXCTL,IIUARTxTX
IMUARTxTX, CUARTxTX
CPUARTxTX,UART xTXSTAT
EXTERNAL
PORT EIEPx, EMEPx ECEPx,IIEPx
IMEPx, ICEPx CEPx, CPEPx
EBEPx, TPEPx
ELEPx
MUX
PRIORITIZER
I/O PROCESSOR
INTERNAL
DMA
IOD BUS
MUX
(4 DEEP )
SPI DMA FIFO
DMD, PMD
BUSES (TO C ORE )
TXSP5A-0A, TXSP5B-0B, RXSP5A-0A, RXSP5B-0B
RXSPI, TXSPI
(1 DEEP EACH)
EXTERNEL
EXTERNAL
GENERATOR
DFEP0 (DATA FIFO)
TFEP0 (TAP LIST FIFO)
SPORT S
(2 DEEP )
SPI PORT
PORT
ADDRESS
IDP
IDP F IFO
8DEEP
Figure 2-2. I/O Processor Block Diagram

Data Buffer Registers

Figure 2-2 shows the data buffer registers for each port. These registers
include:
Serial port receive buffers (RXSPx). These receive buffers for the
serial ports have two-position FIFOs for receiving data when con­nected to another serial device.
ADSP-21368 SHARC Processor Hardware Reference 2-25
Setting Up DMA Parameter Registers
Serial port transmit buffers (
TXSPx). These transmit buffers for the
serial ports have two-position FIFOs for transmitting data when connected to another serial device.
SPI receive buffers (RXSPI, RXSPIB). These receive buffers for the
SPI ports have a single-position buffer for receiving data when con­nected to another serial device.
SPI transmit buffers (TXSPI, TXSPIB). These transmit buffers for
the SPI ports have a single-position buffer for transmitting data when connected to another serial device.
Input data port buffers (IDP_FIFO). This receive buffer for the
input data port has eight-position buffers for receiving data when connected to another device.

Port, Buffer, and DMA Control Registers

The port, buffer, and DMA control registers in Figure 2-2 shows the con­trol registers for the ports and DMA channels. These registers include:
External port control registers (DMACx). These are the control regis-
ters for the external port DMA channels.
Input data port control register (IDP_CTL). This is the control reg-
ister for the input data ports.
Serial port control registers (
SPCTLx, SPMCTLx). These control reg-
isters select the receive or transmit format, monitor FIFO status, enable chaining, and start DMA for each serial port.
SPI port control registers (
SPICTL, SPICTLB). These control regis-
ters configure and enable the two SPI interfaces, selecting the devices as masters or slaves, and determine the data transfer and word size. The SPIDMAC and SPIDMACB registers also control SPI DMA and FIFO status.
2-26 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Universal asynchronous receiver/transmitter registers
(
RXCTL_UACx, TXCTL_UACx). These control registers configure and
enable the UART receiver and transmitter DMA, (chaining and non chaining).
Memory-to-memory DMA control register (MTMCTL). This control
register contains the MTM DMA read and write channel enable and status bits.
Table 2-6 shows the parameter registers for each DMA channel. These
registers function similarly to data address generator registers and include:
Internal index registers (IISPx, IISPI, IISPIB, IIEP, IDP_DMA_Ix,
RXI_UAC/TXI_UAC). Index registers provide an internal memory
address, acting as a pointer to the next internal memory DMA read or write location.
Internal modify registers (IMSPx, IMEP, IMSPI, IMSPIB, IDP_DMA_Mx,
RXM_UAC/TXM_UAC). Modify registers provide the signed increment
by which the DMA controller post-modifies the corresponding internal memory index register after the DMA read or write.
Count registers (CSPx, ICEP, CSPI, CSPIB, IDP_DMA_Cx,
RXC_UAC/TXC_UAC). Count registers indicate the number of words
remaining to be transferred to or from internal memory on the cor­responding DMA channel.
Chain pointer registers (
RXCP_UAC/TXCP_UAC). Chain pointer registers hold the starting
CPSPx, CPSPI, CPSPIB, CPEP,
address of the TCB (parameter register values) for the next DMA operation on the corresponding channel. These registers also con­trol whether the I/O processor generates an interrupt when the current DMA process ends.
External index registers (
EIEPx). Index registers provide an exter-
nal memory address, acting as a pointer to the next external memory DMA read or write location.
ADSP-21368 SHARC Processor Hardware Reference 2-27
Setting Up DMA Parameter Registers
External modify registers (
EMEPx). Modify registers provide the
increment by which the DMA controller post-modifies the corre­sponding external memory index register after the DMA read or write.
External count registers (ECEPx). External count registers indicate
the number of words remaining to be transferred to or from exter­nal memory on the corresponding DMA channel.
Memory-to-memory write index register (IIMTMW). This register
provides the base address in memory where DMA writes start.
Memory-to-memory write modify register (IMMTMW). The MTM
modify register modifies the write index register after each 32-bit write.
Memory-to-memory write counter register (CMTMW). The MTM
counter register indicates the quantity of 32-bit data to be trans­ferred to memory. The counter is decremented by one after each data write.
Memory-to-memory read index register (IIMTMR). This register
provides the base address in memory where DMA reads start.
Memory-to-memory read modify register (IMMTMR). The MTM
modify register modifies the write index register after each 32-bit read.
Memory-to-memory read counter register (
CMTMR). The MTM
counter register indicates the quantity of 32-bit data to be read from memory. The counter is decremented by one after each data write.
2-28 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-6. DMA Parameter Registers
Register Function Width Description
IIy Internal Index Register 19 bits Address of buffer in internal
memory
IMxy Internal Modify Register 16 bits
Cxy Internal Count Register 16 bits Length of internal buffer
CPxy Chain Pointer Register 20 bits Chain pointer for DMA
EIEP External Index Register 19 bits Address of buffer in external
EMEP External Modify Register 16 bits Stride for external buffer
ECEP External Count Register 16 bits Length of external buffer
1 IDP_DMA_Mx registers are 6 bits wide only.
1
Stride for internal buffer
chaining
memory

Addressing

Figure 2-3 shows a block diagram of the I/O processor’s address generator
(DMA controller). Table 2-6 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset.
The I/O processor generates addresses for DMA channels much the same way that the data address generators (DAGs) generate addresses for data memory accesses. Each channel has a set of parameter registers including an index register and modify register that the I/O processor uses to address a data buffer in internal memory. The index register must be initialized with a starting address for the data buffer. As part of the DMA operation, the I/O processor outputs the address in the index register onto the pro­cessor’s I/O address bus and applies the address to internal memory during each DMA cycle—a clock cycle in which a DMA transfer is taking place.
ADSP-21368 SHARC Processor Hardware Reference 2-29
Setting Up DMA Parameter Registers
All addresses in the index registers are offset by a value that matches the processor’s first internal normal word addressed RAM location (before the I/O processor uses the addresses). For the ADSP-21367/8/9 and ADSP-2137x processors, this offset value is 0x0008 0000.
DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)
LOCAL BUS
INTER NAL
MEMORY
ADDRESS
IIX
INDEX (ADDRESS)
IMX
MODIFIER
+/-
POST-M ODIFY
DMAWORDCOUNTER
–1
CX
COUNT
CPX
CHAIN POINTER
+
WORKING REGISTER
MUX
DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)
LOCAL BUS
EXTERNAL
MEMORY
ADDRESS
EIPP
EXT. INDEX (ADDRESS)
EMPP
EXT. MODIFIER
LOCAL BUS
ECPP
EXT. COUNT
+
–1
POST-MODIFY
+
Figure 2-3. DMA Address Generator
2-30 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
The following rules for data transfers must be followed.
DMA addresses must always be normal word (32-bit) memory.
Internal memory data transfer sizes are 32 bits, while external data transfer sizes may be 32, 16, or 8 bits.
The I/O processor can transfer short word data (16-bit) using the packing capability of the serial port and SPI port DMA channels.
After transferring each data word to or from internal memory, the I/O processor adds the modify value to the index register to generate the address for the next DMA transfer and writes the modified index value to the index register. The modify value in the modify register is a signed inte­ger, which allows both increment and decrement modifies. The modify value can have any positive or negative integer value. Note that:
If the I/O processor modifies the index register past the maximum 18-bit value to indicate an address out of internal memory, the index wraps around to zero. With the offset for the ADSP-2136x SHARC processor processors, the wraparound address is 0x0008 0000.
If a DMA channel is disabled, the I/O processor does not service requests for that channel, (whether or not the channel has data to transfer).
[
The processor’s 34 DMA channels are numbered as shown in Table 2-7. This table also shows the control, parameter, and data buffer registers that correspond to each channel.
ADSP-21368 SHARC Processor Hardware Reference 2-31
If a program loads the count register with zero, the I/O processor does not disable DMA transfers on that channel. The I/O proces­sor interprets the zero as a request for 216 transfers. This count occurs because the I/O processor starts the first transfer before test­ing the count value. The only way to disable a DMA channel is to clear its DMA enable bit.
Setting Up DMA Parameter Registers
In the serial port pair SP0/1, SP1 has a higher priority. For multichannel pairs, the odd numbered channels have a higher priority (for example SP3, SP5).
Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers
DMA Channel Number
0 SPCTL1 IISP1A, IMSP1A, CSP1A,
1 SPCTL1 IISP1B, IMSP1B, CSP1B,
2 SPCTL0 IISP0A, IMSP0A, CSP0A,
3 SPCTL0 IISP0B, IMSP0B, CSP0B,
4 SPCTL3 IISP3A, IMSP3A, CSP3A,
5 SPCTL3 IISP3B, IMSP3B, CSP3B,
6 SPCTL2 IISP2A, IMSP2A, CSP2A,
7 SPCTL2 IISP2B, IMSP2B, CSP2B,
8 SPCTL5 IISP5A, IMSP5A, CSP5A,
Control Registers Parameter Registers Buffer Registers Description
CPSP1A
CPSP1B
CPSP0A
CPSP0B
CPSP3A
CPSP3B
CPSP2A
CPSP2B
CPSP5A
RXSP1A, TXSP1A
RXSP1B, TXSP1B
RXSP0A, TXSP0A
RXSP0B, TXSP0B
RXSP3A, TXSP3A
RXSP3B, TXSP3B
RXSP2A, TXSP2A
RXSP2B, TXSP2B
RXSP5A, TXSP5A
Serial Port 1A Data
Serial Port 1B Data
Serial Port 0A Data
Serial Port 0B Data
Serial Port 3A Data
Serial Port 3B Data
Serial Port 2A Data
Serial Port 2B Data
Serial Port 5A Data
9 SPCTL5 IISP5B, IMSP5B, CSP5B,
CPSP5B
10 SPCTL4 IISP4A, IMSP4A, CSP4A,
CPSP4A
11 SPCTL4 IISP4B, IMSP4B, CSP4B,
CPSP4B
RXSP5B, TXSP5B
RXSP4A, TXSP4A
RXSP4B, TXSP4B
Serial Port 5B Data
Serial Port 4A Data
Serial Port 4B Data
2-32 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d)
DMA Channel Number
12 SPCTL7 IISP7A, IM7P5A, CSP7A,
13 SPCTL7 IISP7B, IMSP7B, CSP7B,
14 SPCTL6 IISP6A, IMSP6A, CSP6A,
15 SPCTL6 IISP6B, IMSP6B, CSP6B,
16 IDP_CTL IDP_DMA_I0,
17 IDP_CTL IDP_DMA_I1,
18 IDP_CTL IDP_DMA_I2,
19 IDP_CTL IDP_DMA_I3,
Control Registers Parameter Registers Buffer Registers Description
RXSP7A,
CPSP7A
CPSP7B
CPSP6A
CPSP6B
IDP_DMA_M0, IDP_DMA_C0
IDP_DMA_M1, IDP_DMA_C1
IDP_DMA_M2, IDP_DMA_C2
IDP_DMA_M3, IDP_DMA_C3
TXSP7A
RXSP7B, TXSP7B
RXSP6A, TXSP6A
RXSP6B, TXSP6B
IDP_FIFO DAI IDP
IDP_FIFO DAI IDP
IDP_FIFO DAI IDP
IDP_FIFO DAI IDP
Serial Port 7A Data
Serial Port 7B Data
Serial Port 6A Data
Serial Port 6B Data
Channel 0
Channel 1
Channel 2
Channel 3
20 IDP_CTL IDP_DMA_I4,
IDP_DMA_M4, IDP_DMA_C4
21 IDP_CTL IDP_DMA_I5,
IDP_DMA_M5, IDP_DMA_C5
22 IDP_CTL IDP_DMA_I6,
IDP_DMA_M6, IDP_DMA_C6
IDP_FIFO DAI IDP
Channel 4
IDP_FIFO DAI IDP
Channel 5
IDP_FIFO DAI IDP
Channel 6
ADSP-21368 SHARC Processor Hardware Reference 2-33
Setting Up DMA Parameter Registers
Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d)
DMA Channel Number
23 IDP_CTL IDP_DMA_I7,
24 SPICTL IISPI, IMSPI, CSPI, CPSPI RXSPI, TXSPI SPI Data
25 SPICTLB IISPIB, IMSPIB, CSPIB,
26 MTMCTL IIMTMW
27 MTMCTL IIMTMR,
28 AMICTL EIEP0, EMEP0, ECEP0,
29 AMICTL EIEP1, EMEP1, ECEP1,
Control Registers Parameter Registers Buffer Registers Description
IDP_FIFO DAI IDP IDP_DMA_M7, IDP_DMA_C7
CPSPIB
IMMTMW, CMTMW
IMMTMR, CMTMR
IIEP0, IMEP0, ICEP0, CEP0, CPEP0, EBEP0, TPEP0, ELEP0
IIEP1, IMEP1, ICEP1, CEP1, CPEP1, EBEP1, TPEP1, ELEP1
RXSPIB,
TXSPIB
N/A MTM Write
N/A MTM Read
DFEP0, TFEP0External
DFEP1, TFEP1External
Channel 7
SPI B Data
Channel
Channel
Port Channel 0
Port Channel 1
30 RXCTL_UAC0 RXI_UAC0, RXM_UAC0,
RXC_UAC0, RXCP_UAC0, RXSTAT_UAC0
31 RXCTL_UAC1 RXI_UAC1, RXM_UAC1,
RXC_UAC1, RXCP_UAC1, RXSTAT_UAC1
RBR0,
RBRSH_UAC0
RBR1,
RBRSH_UAC1
UART0 Rx
UART1 Rx
2-34 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d)
DMA Channel Number
32 TXCTL_UAC0 TXI_UAC0, TXM_UAC0,
33 TXCTL_UAC1 TXI_UAC1, TXM_UAC1,
Control Registers Parameter Registers Buffer Registers Description
THR0 UART0 Tx TXC_UAC0, TXCP_UAC0, TXSTAT_UAC0
THR1 UART1 Tx TXC_UAC1, TXCP_UAC1, TXSTAT_UAC1
All of the I/O processor’s registers are memory-mapped, ranging from address 0x0000 0000 to 0x0003 FFFF. For more information on these registers, see “I/O Processor Registers” on page A-2.

External Port DMA

The external port has two DMA channels that can use either the SDRAM controller (SDC) or the asynchronous memory interface (AMI). The DMA chooses the correct interface (AMI or SDC) based on the external address as determined by bits 0–3 in the external port global control regis-
EPCTL, Table A-3 on page A-11). The DMA controllers support
ter ( conventional DMA, chained and circular DMA, and delay line DMA. The priority of the two DMA channels is fixed with external port 0 having pri­ority over external port 1.
The DMA controllers have two FIFOs, a four deep data FIFO for received/transmitted data and a four deep tap list FIFO for the tap list entries for the delay line DMA.
The registers that control external port DMA are described in Table 2-8.
ADSP-21368 SHARC Processor Hardware Reference 2-35
External Port DMA
Table 2-8. External Port Registers
Register Description Address
EPCTL External Port Global Control Register 0x1801
DMAC1–0 External Port DMA Control Register 0x180B, 0x180C
IIEP1–0 Internal Index Register 0x1823, 0x1833
IMEP1–0 Internal Modifier Register 0x1824, 0x1834
ICEP1–0 Internal Count Register 0x1825, 0x1835
EIEP1–0 External Index Register 0x1820, 0x1830
EMEP1–0 External Modifier Register 0x1821, 0x1831
CPEP1–0 Chain Pointer Register 0x1826, 0x1836
TPEP1–0 Tap List Pointer Register 0x1828, 0x1838
ELEP1–0 Circular Buffer Length Register 0x1829, 0x1839
EBEP1–0 External Base Address Register 0x1827, 0x1837

Setting Up and Starting Chained DMA

Use the following procedure to set up and run a chained DMA on the external port.
1. Configure the AMICTLx registers to enable the AMI, set the desired wait states, set the data bus width, and so on. Configure the register to enable the SDRAM, set the desired clock and timing set­tings, set the data bus width, and so on.
2. Initialize the CPEP register—set the PCI bit if interrupts are needed after the end of each DMA block.
2-36 ADSP-21368 SHARC Processor Hardware Reference
SDCTL
I/O Processor
3. If circular buffering is needed, then program additional writes to the
ELEP and EBEP registers. Note that for normal chained DMA,
the ELEP and EBEP registers are not part of the TCB. So if circular buffering is used with the normal chained DMA, all the DMA blocks will have same ELEP and EBEP values.l
4. Enable DMA (DEN), chaining (CHEN), and circular buffering (CBEN) if needed, in the DMACx registers. It is advised that the DMA FIFOs are flushed (DFLSH) when DMA is enabled.
Once the DMA control register is initialized, the DMA controller fetches the DMA descriptors from the address pointed to by the external port chain pointer register (CPEP). The order the descriptors are fetched is shown in Table 2-9.
Table 2-9. Chain Pointer Loading Sequence (Normal DMA)
Address Register Value
CPEP[18:0] IIEP
CPEP[18:0] – 0x1 IMEP
CPEP[18:0] – 0x2 ICEP
CPEP[18:0] – 0x3 EIEP
CPEP[18:0] – 0x4 EMEP
CPEP[18:0] – 0x5 CPEP
The order the descriptors are fetched with circular buffering enabled is shown in Table 2-10
ADSP-21368 SHARC Processor Hardware Reference 2-37
External Port DMA
Table 2-10. Chain Pointer Loading Sequence (Circular Buffering Enabled)
Address Register Value
ELEP[18:0] IIEP
CPEP[18:0] – 0x1 IMEP
CPEP[18:0] – 0x2 ICEP
CPEP[18:0] – 0x3 EIEP
CPEP[18:0] – 0x4 EMEP
CPEP[18:0] – 0x5 CPEP
EPCP[18:0] – 0x5 EPEB
EPCP[18:0] – 0x6 EPEL
Once the DMA descriptors are fetched, the normal DMA process starts. Upon completion, new DMA descriptors are loaded and the process is repeated until
CPEP = 0x00000. A DMA completion interrupt is generated
at the end of each DMA block or at the end of an entire chained DMA, depending on the PCI bit setting.

Delay Line DMA

Delay line DMA is used to support reads and writes to external delay line buffers with limited core interaction. In this sense, delay line DMA is basi­cally a quantity of integrated writes followed by reads from external memory—called a delay line DMA access. The delay line DMA access con­sists of the following accesses in the order listed.
1. Writes to external memory. The number of writes are determined by the external port internal count ICEP register. The data is fetched from the external port internal index register ( the external port internal modify register (IMEP) is used as the inter­nal modifier. The external port external index register (
2-38 ADSP-21368 SHARC Processor Hardware Reference
IIEP) and
EIEP) serves
I/O Processor
as the external index and is incremented by the external modifier register ( circular buffering is enabled.
2. In chained DMA, when the writes are complete, (ICEP = zero) the
EPEI register, which serves as the write pointer of the delay line, is
written back to the internal memory location from where it was fetched.
3. Reads from external memory. For reads, the tap list (TL) modifiers are used and the number of reads is determined by the external port read count register (RCEP). The write pointer in the external port external index register (EIEP) serves as the index address for these reads (reads start from where writes end). The EIEP register, along with tap list modifiers, are used in a pre-modify addressing mode to create the external address for the writes. For each 32-bit read the external index is:
EMEP) after each write. These writes are circular buffered if
EIEP – TL[0] is the first read address (where TL[0] is the first tap list entry in internal memory as pointed to by the external port tap list pointer register TPEP).
EIEP – TL[1] is the second address, and so on.
Therefore, for each read, the DMA controller fetches the external modifier from the tap list and the reads are circular buffered (if enabled).
L
ADSP-21368 SHARC Processor Hardware Reference 2-39
The external address generation follows pre-modify addressing for reads in delay line DMA and therefore EIEP values are not modi­fied. Also the line reads.
EMEP register does not have any effect during delay

Serial Port DMA

4. Once the read count completes, the delay line DMA access is com­plete and the DMA complete interrupt is generated. Note that if chaining is enabled, the interrupt is generated based on the setting. For more information on the PCI bit, see “Interrupt-Driven
I/O” on page 2-6.
Table 2-11. Chain Pointer Loading Sequence (Delay Line DMA)
Address Register Value
EPCP[18:0] EPII (Write Index)
EPCP[18:0] – 0x1 EPIM
EPCP[18:0] – 0x2 EPIC (Write Count)
EPCP[18:0] – 0x3 EPEI
EPCP[18:0] – 0x4 EPEM
EPCP[18:0] – 0x5 EPEB
PCI bit
EPCP[18:0] – 0x6 EPEL
EPCP[18:0] – 0x7 EPRI
EPCP[18:0] – 0x8 EPRC
EPCP[18:0] – 0x9 EPTP
EPCP[18:0] – 0xA EPCP
Serial Port DMA
The serial ports support standard as well as chained DMA.

Setting Up and Starting Chained DMA

To set up and initiate a chain of DMA operations, use these steps:
1. Set up all TCBs in internal memory.
2-40 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
2. Write to the appropriate DMA control register, setting the DMA enable bit to one and the chaining enable bit to one.
3. Write the address containing the index register value of the first TCB to the chain pointer register, which starts the chain.
The I/O processor responds by autoinitializing the first DMA parameter registers with the values from the first TCB, and then starts the first data transfer.

Inserting a TCB in an Active Chain

It is possible to insert a single DMA operation or another DMA chain within an active DMA chain. Programs may need to perform insertion when a high priority DMA requires service and cannot wait for the cur­rent chain to finish.
When DMA on a channel is disabled and chaining on the channel is enabled, the DMA channel is in chain insertion mode. This mode lets a program insert a new DMA or DMA chain within the current chain with­out effecting the current DMA transfer. Use the following sequence to insert a DMA subchain for the serial port 0A channel while another chain is active:
1. Enter chain insertion mode by setting SCHEN_A = 1 and SDEN_A = 0 in the channel’s DMA control register,
SPCTL0. The DMA inter-
rupt indicates when the current DMA sequence is complete.
2. Copy the address currently held in the chain pointer register to the chain pointer position of the last TCB in the chain that is being inserted.
3. Write the start address of the first TCB of the new chain into the chain pointer register.
4. Resume chained DMA mode by setting SCHEN_A = 1 and
SDEN_A = 1.
ADSP-21368 SHARC Processor Hardware Reference 2-41

Serial Peripheral Interface DMA

Chain insertion mode operates the same as non-chained DMA mode. When the current DMA transfer ends, an interrupt request occurs and no TCBs are loaded. This interrupt request is independent of the
PCI bit
state.
Chain insertion should not be set up as an initial mode of operation. This mode should only be used to insert one or more TCBs into an active DMA chaining sequence.
Serial Peripheral Interface DMA
The serial peripheral interface supports both standard and chained DMA. However, unlike the serial ports, programs cannot insert a TCB in an active chain using the SPI.

Setting Up and Starting Chained DMA over the SPI

Configuring and starting chained DMA transfers over the SPI port is the same as for the serial port, with one exception. Contrary to SPORT DMA chaining, (where the first DMA in the chain is configured by the first TCB), for SPI DMA chaining, the first DMA is not initialized by a TCB. Instead, the first DMA in the chain must be loaded into the SPI parameter registers (IISPI, IMSPI, CSPI), and the chain pointer register (CPSPI) points to a TCB that describes the second DMA in the sequence.
Table 2-12 shows the order of register loading.
Table 2-12. DMA Chaining Sequence
Address Register Description
CPSPI DMA Start Address Address in memory
CPSPI – 1 DMA Address Modifier Address increment
CPSPI – 2 DMA Word Count Number of words to transfer
CPSPI – 3 DMA Next TCB Pointer to address of next TCB
2-42 ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
L
DMA sequence unless the IISPI, IMSPI, and CSPI registers are ini­tialized, SPI DMA is enabled, the SPI port is enabled, and SPI DMA chaining is enabled.
The sequence for setting up and starting a chained DMA is outlined in the following steps and can also be seen in Listing 6-3 on page 6-43.
1. Configure the TCB associated with each DMA in the chain except for the first DMA in the chain.
2. Write the first three parameters for the initial DMA to the IISPI,
Writing an address to the CPSPI register does not begin a chained
IMSPI, and CSPI registers directly.
3. Select a baud rate using the SPIBAUD register.
4. Select which flag to use as the SPI slave select signal in the SPIFLG register.
5. Configure and enable the SPI port with the SPICTL register.
6. Configure the DMA settings for the entire sequence, enabling DMA and DMA chaining in the SPIDMAC register.
7. Begin the DMA by writing the address of a TCB (describing the second DMA in the chain) to the CPSPI register.
The address field of the chain pointer registers is only 19 bits wide. If a program writes a symbolic address to bit 19 of the chain pointer, there may be a conflict with the
PCI bit. Programs should clear the upper bits of
the address, then AND the PCI bit separately, if needed. For example:
R0 = next_TCB+3; /* addr of next chain */ R1 = 0x7FFFF; /* mask 19 bits */ R0 = R0 or R1; CPSPI = R0;
ADSP-21368 SHARC Processor Hardware Reference 2-43

UART DMA

UART DMA
In the UART, separate receive and transmit DMA channels move data between the UART and memory. The software does not have to move data, it just has to set up the appropriate transfers either through the descriptor mechanism or through auto buffer mode. See also “DMA Con-
troller Operation” on page 2-13.
To perform DMA transfers, the UART has a special set of receive and transmit registers. These registers are listed in Table 2-14.
Table 2-13. UART DMA Registers
Register Description
UARTxRXCTL (3 bits) DMA Config/Control register for UART Rx
IIUARTxRX (19 bits) Address for DMA
IMUARTxRX (16 bits) Modifier
CUARTxRX (16 bits) Count
CPUARTxRX (20 bits) Chain Pointer
UARTxRXSTAT (3 bits) DMA Status register
UARTxTXCTL (3 bits) DMA Config/Control register for UART Tx
IIUARTxTX (19 bits) Address for DMA
IMUARTxTX (16 bits) Modifier
CUARTxTX (16 bits) Count
CPUARTxTX (20 bits) Chain Pointer
UARTxTXSTAT (3 bits) DMA Status register
No additional buffering is provided in the UART DMA channel, so the latency requirements are the same as in non-DMA mode. However, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities.
2-44 ADSP-21368 SHARC Processor Hardware Reference
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