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CONTENTS
PREFACE
Purpose of This Manual ............................................................... xxxi
Thank you for purchasing and developing systems using the
ADSP-21367/8/9 and ADSP-2137x SHARC® processors from Analog
Devices.
Purpose of This Manual
The ADSP-21368 SHARC Processor Hardware Reference contains informa-
tion about the architecture and assembly language for ADSP-21367/8/9
and ADSP-2137x. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing,
communications, and consumer applications.
The manual provides information on the processor’s I/O architecture and
the operation of the peripherals associated with each model.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the appropriate hardware reference manuals and data sheets) that
describe your target architecture.
•Chapter 1, “Introduction”
Provides an architectural overview of the ADSP-21367/8/9 and
ADSP-2137x SHARC processors.
•Chapter 2, “I/O Processor”
Describes ADSP-21367/8/9 and ADSP-2137x processors
input/output processor architecture and direct memory accesses
(DMA) for the peripherals that have this feature.
•Chapter 3, “External Port”
Describes the operation of the asynchronous memory interface
(AMI).
•Chapter 4, “Digital Audio/Digital Peripheral Interfaces”
Provides information about the digital applications interface (DAI)
which allows you to attach an arbitrary number and a variety of
peripherals to the ADSP-21367/8/9 and ADSP-2137x processors
while retaining high levels of compatibility.
•Chapter 5, “Serial Ports”
Describes the up to eight dual data line serial ports. Each SPORT
contains a clock, a frame sync, and two data lines that can be configured as either a receiver or transmitter pair.
•Chapter 6, “Serial Peripheral Interface Ports”
Describes the operation of the SPI port. SPI devices communicate
using a master-slave relationship and can achieve high data transfer
rates because they can operate in full-duplex mode.
•Chapter 7, “Input Data Port”
Discusses the function of the input data port (IDP) which provides
a low overhead method of routing signal routing unit (SRU) signals back to the core’s memory.
•Chapter 8, “Pulse Width Modulation”
Describes the implementation and use of the pulse width modulation module which provides a technique for controlling analog
circuits with the microprocessor’s digital outputs.
•Chapter 9, “S/PDIF Transmitter/Receiver”
Provides information on the use of the Sony/Philips Digital Interface which is a standard audio file transfer format that allows the
transfer of digital audio signals from one device to another without
having to be converted to an analog signal.
•Chapter 10, “Asynchronous Sample Rate Converter”
Provides information on the sample rate converter module. This
module performs synchronous or asynchronous sample rate conversions across independent stereo channels, without using any
internal processor resources.
•Chapter 11, “UART Port Controller”
Describes the operation of the Universal Asynchronous
Receiver/Transmitter (UART) which is a full-duplex peripheral
compatible with PC-style industry-standard UART.
•Chapter 12, “Two Wire Interface Controller”
The two wire interface is fully compatible with the widely used I
2
C
bus standard. It is designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations.
•Chapter 13, “Precision Clock Generators”
Details the precision clock generators (PCG) each of which generates a pair of signals derived from a clock input signal.
•Chapter 14, “System Design”
Describes system design features of the ADSP-21367/8/9 and
ADSP-2137x processors. These include power, reset, clock, JTAG,
and booting, as well as pin descriptions and other system level
information.
•Appendix A, “Register Reference”
Provides a graphical presentation of all registers and describes the
bit usage in each register.
•Appendix B, “Interrupts”
Provides a complete listing of the registers that are used to configure and control interrupts.
L
This hardware reference is a companion document to the
ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference. The programming reference provides information relating to
the processor core, such as processing elements, internal memory,
and program sequencing. It also provides programming specific
information, such as complete descriptions of the ADSP-21xxx
instruction set and the compute operations, including their assembly language syntax and opcode fields.
What’s New in This Manual
Revision 1.0 of the ADSP-21368 SHARC Processor Hardware Reference is
the first general release of this manual. The following changes should be
noted.
•In the preliminary version this manual was titled ADSP-2136x
SHARC Processor Hardware reference for the ADSP-21367/8/9 Processors. The title change to ADSP-21368 SHARC Processor
Hardware Reference was done to reflect the fact that the
ADSP-21368 processor contains the super set of features of the
ADSP-21367 and ADSP-21369 models as well as the new
ADSP-21371 and ADSP-21375 models.
•This version of the manual contains information about the
ADSP-21371 and ADSP-21375 SHARC processors. These new
models contain the same core as the ADSP-21367/8/9 processors
and as such are completely code compatible. The primary differences in these new models is the ability to execute programs from
external memory and a running reset feature.
For more information on these topics, see “Direct Execution of
Instructions From External Memory” on page 3-3 and “Running
Reset (ADSP-2137x)” on page 14-22.
Technical or Customer Support
You can reach Analog Devices, Inc. Customer Support in the following
ways:
•Visit the Embedded Processing and DSP products Web site at
The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.
Blackfin® (ADSP-BFxxx) Processors
The name Blackfin refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin families:
ADSP-BF53x, ADSP-BF54x, and ADSP-BF56x.
SHARC (ADSP-21xxx) Processors
The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x,
ADSP-2136x, and ADSP-2137x.
TigerSHARC® (ADSP-TSxxx) Processors
The name TigerSHARC refers to a family of floating-point and fixed-point
(8-bit, 16-bit, and 32-bit) processors. VisualDSP++ currently supports the
following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at
mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as a means to select the
information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publica-
tions, data sheets, application notes, product overviews, and product
announcements.
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
1-781-461-3010 (North America)
+49-89-76903-157 (Europe)
•Access the FTP Web site at
ftp ftp.analog.com or ftp://137.71.25.69
ftp://ftp.analog.com
Related Documents
The following publications that describe the ADSP-2136x SHARC processors (and related processors) can be ordered from any Analog Devices
sales office:
•ADSP-21362 SHARC Processor Data Sheet
•ADSP-21363 SHARC Processor Data Sheet
•ADSP-21364 SHARC Processor Data Sheet
•ADSP-21365 SHARC Processor Data Sheet
•ADSP-21366 SHARC Processor Data Sheet
•ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data
Sheet
•ADSP-21371 SHARC Processor Preliminary Data Sheet
•ADSP-21375 SHARC Processor Preliminary Data Sheet
For information on product related development software and Analog
Devices processors, see these publications:
•VisualDSP++ User’s Guide
•VisualDSP++ C/C++ Compiler and Library Manual for SHARC
Processors
•VisualDSP++ Assembler and Preprocessor Manual
•VisualDSP++ Linker and Utilities Manual
•VisualDSP++ Kernel (VDK) User’s Guide
Visit the Technical Library Web site to access all processor and tools
manuals and data sheets:
http://www.analog.com/processors/manuals
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary
Each documentation file type is described as follows.
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD-ROM at any time
by running the Tools installation. Access the online documentation from
the VisualDSP++ environment, Windows® Explorer, or the Analog
Devices Web site.
.PDFVisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the
Internet Explorer 4.0 (or higher).
Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
.HTML files requires a browser, such as
Accessing Documentation From VisualDSP++
From the VisualDSP++ environment:
•Access VisualDSP++ online Help from the Help menu’s Contents, Search, and Index commands.
•Open online Help from context-sensitive user interface items (toolbar buttons, menu commands, and windows).
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are
located in the
Docs folder also contains the Dinkum Abridged C++ library and the
The
Docs folder of your VisualDSP++ installation CD-ROM.
Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
ADSP-21368 SHARC Processor Hardware Reference xli
Product Information
Hardware Tools Manuals
To purchase EZ-KIT Lite® and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xliiADSP-21368 SHARC Processor Hardware Reference
Conventions
Text conventions used in this manual are identified and described as
follows.
ExampleDescription
Preface
Close command
(File menu)
{this | that}Alternative items in syntax descriptions appear within curly brackets
[this | that]Optional items in syntax descriptions appear within brackets and sepa-
[this,…]Optional item lists in syntax descriptions appear within brackets
.SECTIONCommands, directives, keywords, and feature names are in text with
filenameNon-keyword placeholders appear in text with italic style format.
L
a
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system. For example, the Close
command appears on the File menu.
and separated by vertical bars; read the example as this or that. One
or the other is required.
rated by vertical bars; read the example as an optional
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of this.
letter gothic font.
Note: For correct operation, ...
A Note: provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution: identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
this or that.
Warn in g: Injury to device users may result if ...
A Warning: identifies conditions or inappropriate usage of the product
[
that could lead to conditions that are potentially hazardous for devices
users. In the online version of this book, the word Wa rnin g appears
instead of this symbol.
Additional conventions, which apply only to specific chapters, may
appear throughout this document.
xlivADSP-21368 SHARC Processor Hardware Reference
1INTRODUCTION
The ADSP-21367/8/9 and ADSP-2137x SHARC processors are high performance, 32-bit processors used for high quality audio, medical imaging,
communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding on-chip
SRAM, integrated I/O peripherals, and an additional processing element
for single-instruction, multiple-data (SIMD) support, this processor
builds on the ADSP-21000 family DSP core to form a complete
system-on-a-chip.
Design Advantages
A digital signal processor’s data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios.
Because floating-point DSP math reduces the need for scaling and the
probability of overflow, using a floating-point processor can simplify algorithm and software development. The extent to which this is true depends
on the floating-point processor’s architecture. Consistency with IEEE
workstation simulations and the elimination of scaling are clearly two
ease-of-use advantages. High level language programmability, large
address spaces, and wide dynamic range allow system development time to
be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and/or error handling. The processors
are highly integrated, 32-bit floating-point processors which provide all of
these design advantages.
The SHARC processor architecture balances a high performance processor
core with high performance program memory (PM), data memory (DM),
ADSP-21368 SHARC Processor Hardware Reference 1-1
Design Advantages
and input/output (I/O) buses. In the core, every instruction can execute in
a single cycle. The buses and instruction cache provide rapid, unimpeded
data flow to the core to maintain the execution rate.
Figure 1-1 shows a detailed block diagram of the processor core and the
I/O processor (IOP). This figures illustrates the following architectural
features:
•Two processing elements (PEx and PEy), each containing 32-bit,
IEEE, floating-point computation units—multiplier, arithmetic
logic unit (ALU), shifter, and data register file
•Program sequencer with related instruction cache, interval timer,
and data address generators (DAG1 and DAG2)
•An SDRAM controller that provides an interface up to four separate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to
f
SCLK
•Up to 2M bits of SRAM and 6M bits of on-chip, mask-programmable ROM
•IOP with integrated direct memory access (DMA) controller, serial
peripheral interface (SPI) compatible port, and serial ports
(SPORTs) for point-to-point multiprocessor communications
•A variety of audio centric peripheral modules including a
Sony/Philips Digital Interface (S/PDIF), sample rate converter
(SRC) and pulse width modulation (PWM). Table 1-1 on page 1-5
provides details on these and other features for the current members of the ADSP-21367/8/9 and ADSP-2137x processors families.
•JTAG test access port for emulation
Figure 1-1 also shows the three on-chip buses: the PM bus, DM bus, and
I/O bus. The PM bus provides access to either instructions or data. During a single cycle, these buses let the processor access two data operands
1-2ADSP-21368 SHARC Processor Hardware Reference
Introduction
from memory, access an instruction (from the cache), and perform a
DMA transfer.
Figure 1-1 also shows the asychronous memory interface available on the
ADSP-21368 processor.
INST RUCT ION
CACHE
32X 48-BIT
2DAGS
8X4X32
2PROCESSING
ELEMENTS
(PEX , PEY)
PROGR AM
SEQ UEN CER
TIMER
S
4
GPIO FLAGS/
IRQ/ TIME XP
*THEADSP-21368 PROCESSOR INCLUDES A CUSTOMER-DEFINABLE ROM BLOCK.
PLEAS E CON TACT YO UR ANAL OG DEVIC ES SAL ES REPR ESENT ATIVE FO R ADDIT IONAL D ETAILS
PX R EGISTER
CORE PR OCESS OR
PRE CISION CL OCK
GEN ERATORS (4)
SRC (8 CH ANNELS )
SPDIF(RX/TX)
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
DAI ROUTING UNIT
DIGITAL AUDIO INTERFACE
32PM ADDRESSBUS
32
64
64
ON-CHIP MEM ORY
ADD RDA T A
IOA( 24)
IOP R EGISTER (M EMORY M APPED)
CONTROL,STATUS, &DATA BUFFERS
SERIAL PORTS(8)
INPU T DAT A PORT /
PDAP
DAI PINS
20
IOD( 32)
CONTROLLER
AS YNC HR ON O US
SHA RED MEM ORY
INT ERFA CE
SPI PO RT (2)
TWO WIRE
INTERFACE
DP I PI NS
DIGITAL PERIPHERAL INTERFACE
14
EXTE RNA L PORT
SDR AM
MEMORY
INTERFACE
DMA
CONTROLLER
34 CHANNELS
FLAGS
4-15
PWM
8
3
8
MEMO RY DMA (2)
DPIROUTING UNIT
I/O PROCESSOR
Figure 1-1. ADSP-21368 Block Diagram
The ADSP-21367/8/9 and ADSP-2137x processors address the five central requirements for signal processing:
S
N
I
18
P
L
O
R
CONTROL
T
N
O
C
ADDRESS
ME MORY -TO -
UART(2 )
TIMERS (3)
32
DATA
24
Fast, Flexible Arithmetic. The ADSP-21000 family processors execute all
instructions in a single cycle. They provide fast cycle times and a complete
set of arithmetic operations. The processor is IEEE floating-point compatible and allows either interrupt on arithmetic exception or latched status
exception handling.
ADSP-21368 SHARC Processor Hardware Reference 1-3
Design Advantages
Unconstrained Data Flow. The ADSP-21367/8/9 and ADSP-2137x processors have a Super Harvard Architecture combined with a ten-port data
register file. In every cycle, the processor can write or read two operands to
or from the register file, supply two operands to the ALU, supply two
operands to the multiplier, and receive three results from the ALU and
multiplier. The processor’s 48-bit orthogonal instruction word supports
parallel data transfers and arithmetic operations in the same instruction.
40-Bit Extended Precision. The processor handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-complement
and unsigned), and extended-precision, 40-bit floating-point format. The
processors carry extended precision throughout their computation units,
limiting intermediate data truncation errors (up to 80 bits of precision are
maintained during multiply-accumulate operations).
Dual Address Generators. The processor has two data address generators
(DAGs) that provide immediate or indirect (pre- and post-modify)
addressing. Modulus, bit-reverse, and broadcast operations are supported
with no constraints on data buffer placement.
Efficient Program Sequencing. In addition to zero-overhead loops, the
processor supports single-cycle setup and exit for loops. Loops are both
nestable (six levels in hardware) and interruptable. The processors support
both delayed and non-delayed branches.
The ADSP-21367/8/9 and ADSP-2137x processors also provide the following features which increase the variety processor applications.
High Bandwidth I/O. The processors contain a dedicated, 6M bits
on-chip ROM, an external port, an SPI port, serial ports, digital audio
interface (DAI), and JTAG. The DAI incorporates a precision clock generator, input data port, and a signal routing unit.
Serial Ports. Provides an inexpensive interface to a wide variety of digital
and mixed-signal peripheral devices. The serial ports can operate at up to
half the processor core clock (
CCLK) rate.
1-4ADSP-21368 SHARC Processor Hardware Reference
Introduction
Input Data Port (IDP). The IDP provides an additional input path to the
processor core, configurable as eight channels of serial data or seven channels of serial data and a single channel of up to 20-bit wide parallel data.
Two Serial Peripheral Interfaces (SPI). The primary SPI has dedicated
pins and the secondary is controlled through the DAI. The SPI provides
master or slave serial boot through the SPI, full-duplex operation, master-slave mode, multimaster support, open drain outputs, programmable
baud rates, clock polarities, and phases.
Digital Audio Interface and Digital Peripheral Interface. The digital
audio interface (DAI) and the digital peripheral interface (DPI) are comprised of groups of peripherals and their signal routing units (SRU1 and
SRU2 respectively). This allows peripherals to be interconnected to suit a
wide variety of systems. It also allows the processors to include an arbitrary number and variety of peripherals while retaining high levels of
compatibility without increasing pin count.
Signal Routing Units (SRU1/SRU2). The SRUs provide configuration
flexibility by allowing software-programmable connections to be made
between the DAI/DPI components and the 20 DAI pins and 14 DPI pins.
I/O Processor (IOP). The IOP manages the SHARC processor’s off-chip
data I/O to alleviate the core of this burden. This unit manages the other
processor peripherals such as the SPI, DAI, and IDP as well as direct
memory accesses (DMA).
1 The ADSP-21367 processor include a customer-definable ROM block. Please contact your Analog
Devices sales representative for additional details.
2 Audio decoding algorithms include PCM, Dolby Digital EX, PCM, Dolby Digital EX, Dolby Pro-
logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MPEG2 2channel, MP3, and functions like
bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support will vary depending upon the chip version and the system configurations. Please visit www.analog.com/SHARC for complete information.
3 Analog Devices offers these packages in lead-free (Pb) versions.
YesYesYe sYesNo
NoYesNoNoNo
128dB140dB128dB128dBN/A
3
256-ball
SBGA
208 Lead
MQFP
256-ball
SBGA
256-ball
SBGA
208 Lead
MQFP
208-lead
MQFP
208-lead
MQFP
Architectural Overview
The ADSP-21367/8/9 and ADSP-2137x processors form a complete system-on-a-chip, integrating a large, high speed SRAM and I/O peripherals
supported by a dedicated I/O bus. The following sections summarize the
features of each functional block in the processor architecture, which
appears in Figure 1-1.
1-6ADSP-21368 SHARC Processor Hardware Reference
Introduction
Processor Core
The processor core of the ADSP-21367/8/9 and ADSP-2137x processors
contain two processing elements (each with three computation units and
data register file), a program sequencer, two data address generators, a
timer, and an instruction cache. All digital signal processing occurs in the
processor core. For complete information, see the ADSP-21367/8/9 and
ADSP-2137x SHARC processors.
Processor Peripherals
The term processor peripherals refers to the multiple on-chip functional
blocks used to communicate with off-chip devices. The peripherals
include the JTAG, UART, serial ports, SPI ports, DAI/DPI components
(PCG, timers, and IDP are a few), and any external devices that connect
to the processor.
I/O Processor
The ADSP-21367/8/9 and ADSP-2137x processors input/output processor (IOP) manages the off-chip data I/O to alleviate the core of this
burden. Up to thirty-four channels of DMA are available on the
ADSP-21367/8/9 and ADSP-2137x processors—sixteen via the serial
ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface,
2 for the external port, and 2 for memory-to-memory transfers. The I/O
processor can perform DMA transfers between the peripherals and internal memory at the full core clock speed. The architecture of the internal
memory allows the IOP and the core to access internal memory simultaneously with no reduction in throughput.
Serial Ports. The processors feature up to eight synchronous serial ports
that provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at up to half
of the processor core clock rate with maximum of 50M bits per second.
Each serial port features two data pins that function as a pair based on the
ADSP-21368 SHARC Processor Hardware Reference 1-7
Architectural Overview
same serial clock and frame sync. Accordingly, each serial port has two
DMA channels and serial data buffers associated with it to service the dual
serial data pins. Programmable data direction provides greater flexibility
for serial communications. Serial port data can automatically transfer to
and from on-chip memory using DMA. Each of the serial ports offers a
TDM multichannel mode (up to 128 channels) and supports μ-law or
A-law companding. I
2
S support is also provided with the
ADSP-21367/8/9 and ADSP-2137x processors.
The serial ports can operate with least significant bit first (LSBF) or most
significant bit first (MSBF) transmission order, with word lengths from 3
to 32 bits. The serial ports offer selectable synchronization and transmit
modes. Serial port clocks and frame syncs can be internally or externally
generated.
Serial Peripheral (Compatible) Interface (SPI). The SPI is an industry
standard synchronous serial link that enables the SPI-compatible port to
communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a
full-duplex synchronous serial interface, supporting both master and slave
modes. It can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a master or slave
device.
The SPI-compatible peripheral implementation also supports programmable baud rate and clock phase/polarities, as well as the use of open drain
drivers to support the multimaster scenario to avoid data contention.
SDRAM Controller. The SDRAM controller provides an interface of up
to four separate banks of industry-standard SDRAM devices or DIMMs,
f
at speeds up to
bank has it’s own memory select line (
. Fully compliant with the SDRAM standard, each
SCLK
MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
1-8ADSP-21368 SHARC Processor Hardware Reference
Introduction
ROM-Based Security. For those processors with application code in the
on-chip ROM, an optional ROM security feature is included. This feature
provides hardware support for securing user software code by preventing
unauthorized reading from the enabled code. The processor does not
boot-load any external code, executing exclusively from internal ROM.
Also, the processor is not freely accessible via the JTAG port. Instead, a
64-bit key is assigned to the user. This key must be scanned in through the
JTAG or Test Access Port. The device ignores a wrong key. Emulation
features and external boot modes are only available after the correct key is
scanned.
Digital Audio Interface (DAI)
The digital audio interface (DAI) unit is a new addition to the SHARC
processor peripherals. This set of audio peripherals consists of an interrupt
controller, an interface data port, and a signal routing unit, four precision
clock generators (PCGs) and three timers. Some family members have an
S/PDIF receiver/transmitter and eight channels asynchronous sample rate
converters (SRC).
Interrupt Controller. The DAI contains its own interrupt controller that
indicates to the core when DAI audio events have occurred. This interrupt
controller offer 32 independently configurable channels.
Input Data Port (IDP). The input data port provides the DAI with a way
to transmit data from within the DAI to the core. The IDP provides a
means for up to eight additional DMA paths from the DAI into on-chip
memory. All eight channels support 24-bit wide data and share a 16-deep
FIFO.
Signal Routing Unit One (SRU1). Conceptually similar to a “patch-bay”
or multiplexer, the SRU provides a group of registers that define the interconnection of the serial ports, the input data port, the DAI pins, and the
precision clock generators.
ADSP-21368 SHARC Processor Hardware Reference 1-9
Development Tools
Digital Peripheral Interface (DPI)
The digital peripheral interface (DPI) unit is a new addition to the
SHARC processor peripherals. This set of audio peripherals consists of an
interrupt controller, a two wire interface port (TWI), and a signal routing
unit, three timers and a Universal Asynchronous Receiver/Transmitter
(UART).
Interrupt Controller. The DPI contains its own interrupt controller that
indicates to the core when DPI audio events have occurred. This interrupt
controller offer 32 independently configurable channels.
Two Wire Interface (TWI). The two wire interface (TWI) controller
allows a device to interface to an Inter IC bus as specified by the Philips
2
I
C Bus Specification version 2.1 dated January 2000.
Universal Asynchronous Receiver/Transmitter (UART). A full-duplex
peripheral compatible with PC-style, industry-standard UARTs. The
UART converts data between serial and parallel formats. The UART
includes interrupt handling hardware. Interrupts can be generated from
12 different events.
Signal Routing Unit Two (SRU2). Conceptually similar to a “patch-bay”
or multiplexer, SRU2 provides a group of registers that define the interconnection of the DPI’s peripherals, the DPI pins, and the timers.
Development Tools
The ADSP-21367/8/9 and ADSP-2137x processors are supported by
VisualDSP++, an easy-to-use integrated development and debugging environment (IDDE). VisualDSP++ allows you to manage projects from start
to finish from within a single, integrated interface. Because the project
development and debug environments are integrated, you can move easily
between editing, building, and debugging activities.
1-10ADSP-21368 SHARC Processor Hardware Reference
Introduction
Differences From Previous Processors
This section identifies differences between the ADSP-21367/8/9 and
ADSP-2137x processors and previous SHARC processors: ADSP-21161,
ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and
ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC
processor family is based on the original ADSP-2106x SHARC family.
The ADSP-21367/8/9 and ADSP-2137x processors preserve much of the
ADSP-2106x architecture and is code compatible to the ADSP-21160,
while extending performance and functionality. For background information on SHARC processors and the ADSP-2106x family DSPs, see the
ADSP-2106x SHARC User’s Manual or the ADSP-21065L SHARC DSP
Technical Reference.
I/O Architecture Enhancements
The I/O processor provides much greater throughput than that on the
ADSP-2106x processors.
The DMA controller supports up to 34 channels compared to 14 channels
on the ADSP-21161 processor. DMA transfers occur at clock speed in
parallel with full speed processor execution. The ADSP-21367/8/9 and
ADSP-2137x processors also provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers (and hence
to external memory) with limited core interaction.
In addition to the above, the ADSP-21367/8/9 and ADSP-2137x processors have up to eight serial ports (SPORTs), a 32-bit external memory
interface, a universal asynchronous transmitter/receiver (UART) and an
2
C compatible interface called the TWI (two wire interface).
The ADSP-21367/8/9 and ADSP-2137x processors provide source code
compatibility with the previous SHARC processor family members to the
application assembly source code level. All instructions, control registers,
and system resources available in the ADSP-2106x core programming
model are also available in the ADSP-21367/8/9 and ADSP-2137x processors. Instructions, control registers, or other facilities required to support
the new feature set of the ADSP-2116x core include:
•Code compatibility to the ADSP-21160 SIMD core
•Supersets of the ADSP-2106x programming model
•Reserved facilities in the ADSP-2106x programming model
•Symbol name changes from the ADSP-2106x programming models
These name changes can be managed through reassembly by using the
development tools to apply the ADSP-21367/8/9 and ADSP-2137x processor symbol definitions header file and linker description file. While
these changes have no direct impact on existing core applications, system
and I/O processor initialization code and control code do require
modifications.
Although the porting of source code written for the ADSP-2106x family
to the ADSP-21367/8/9 and ADSP-2137x processors has been simplified,
code changes are required to take full advantage of the new features. For
more information, see the ADSP-2136x SHARC Processor Programming Reference.
1-12ADSP-21368 SHARC Processor Hardware Reference
2I/O PROCESSOR
In applications that use extensive off-chip data I/O, programs may find it
beneficial to use a processor resource other than the processor core to perform data transfers. The ADSP-21367/8/9 and ADSP-2137x processors
contain an I/O processor (IOP) that supports a variety of DMA (direct
memory access) operations. Each DMA operation transfers an entire block
of data. These operations include the transfer types listed below and
shown in Figure 2-2 on page 2-25.
•Internal memory ↔ external memory devices (through the external
port)
•Internal memory ← digital audio/digital peripheral interfaces
(DAI/DPI)
•Internal memory ↔ serial port I/O
•Internal memory ↔ serial peripheral interface I/O
•Internal memory ↔ UART I/O
•Internal memory
By managing DMA, the I/O processor frees the processor core, allowing it
to perform other operations while off-chip data I/O occurs as a background task. The multibank architecture of the internal memory allows
the core and IOP to simultaneously access the internal memory if the
accesses are to different memory banks. This means that DMA transfers to
internal memory do not impact core performance. The processor core
continues to perform computations without penalty.
ADSP-21368 SHARC Processor Hardware Reference 2-1
↔ internal memory
General Procedure for Configuring DMA
To further increase off-chip I/O, multiple DMAs can occur at the same
time. The IOP accomplishes this by managing DMAs of processor memory through the TWI, UART, SPI, input data port (IDP), and serial ports.
[
Accesses to IOP spaces (from the processor core) should not use
Type 1 (dual access) or LW instructions.
General Procedure for Configuring DMA
To configure the ADSP-21367/8/9 and ADSP-2137x processors to use
DMA, use the following general procedure.
1. Determine which DMA options you want to use:
•IOP/core interaction method – interrupt-driven or status-driven (polling)
•DMA transfer method – chained, non-chained, or delay line
•Channel priority scheme – fixed or rotating
2. Determine how you want the DMA to operate:
•Set up the data’s source and/or destination addresses
(INDEX)
•Set up the word COUNT (data buffer size)
•Configure the MODIFY values (step size)
3. Configure the peripheral(s):
•External port (includes AMI, SDRAM)
•Serial ports (SPORTs)
•Universal asynchronous receive/transmit (UART)
2-2ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
•Serial peripheral interface ports (SPI)
•Input data port (IDP)
4. Enable DMA
•Set the applicable bits in the appropriate control registers
For peripheral specific DMA information, see the following sections.
•“External Port DMA” on page 2-35
•“Serial Port DMA” on page 2-40
•“Serial Peripheral Interface DMA” on page 2-42
•“UART DMA” on page 2-44
•“Memory-to-Memory DMA” on page 2-48
Core Access to IOP Registers
In certain cases, extra core cycles are needed to process register accesses.
The access cycles are shown in Table 2-1 and the registers are shown in
In addition to the above, the following situations incur additional stall
cycles.
1. An aborted conditional I/O processor register read can cause one or
two extra core-clock stall cycles if it immediately follows a write.
Such a read is expected to take three core cycles, but it takes four or
five.
2. In case of a full write FIFO, the held-off I/O processor register read
or write access incurs one extra core-clock cycle.
3. Interrupted reads and writes, if preceded by another write, creates
an additional one core cycle stall.
Inside of an interrupt service routine (ISR), a write into an IOP register
that clears the interrupt has some latency. During this delay, the interrupt
may be generated a second time if the program executes an
RTI
instruction.
For example, in the following code the interrupt isn’t cleared instantaneously. During the delay, if the program comes out of the ISR, the
interrupt is generated again.
/*.... code .....*/
dm(TXSPI) = R0; /* Write to TXSPI FIFO; disable spi;
clears the interrupt */
rti;
ADSP-21368 SHARC Processor Hardware Reference 2-5
Configuring IOP/Core Interaction
In order to resolve this issue, use one of the following methods.
1. Read an IOP register from the same peripheral block before executing the RTI. This read forces the write to occur first.
dm(TXSPI) = R0; /* Write to TXSPI FIFO */
R0 = dm(SPICTL); /* Dummy read. This read happens only
after write */
rti;
2. Add sufficient NOP instructions after a write. In all cases, ten NOP
instructions after a write is sufficient to properly update the status.
There are two methods the processor uses to monitor the progress of
DMA operations—interrupts, which are the primary method, and status
polling. The same program can use either method for each DMA channel.
The following sections describe both methods in detail.
Interrupt-Driven I/O
Interrupts are generated at the end of a DMA transfer. This happens when
the count register for a particular channel decrements to zero. The default
interrupt vector locations for each of the channels are listed in Table 2-3
on page 2-9. The interrupt register diagrams and bit descriptions are given
in Appendix B, Interrupts and “DAI Interrupt Controller Registers” on
page A-112.
2-6ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
L
Programs can check the appropriate status or configuration register to
determine which channels are performing a DMA or chained DMA.
All DMA channels can be active or inactive. If a channel is active, a DMA
is in progress on that channel. The I/O processor indicates the active status by setting the channel’s bit in the status register. The only exception to
this is the IDP_DMAx_STAT bits of the DAI_STAT register can become active
even if DMA, through some IDP channel, is not intended.
The following are some other I/O processor interrupt attributes.
The processors also have programmable interrupts using the
peripheral interrupt priority control registers, PICRx. For more
information, see “Peripheral Interrupt Priority Control Registers”
on page A-164.
•When an unchained (single block) DMA process reaches completion (as the count decrements to zero) on any DMA channel, the
I/O processor latches that DMA channel’s interrupt. It does this by
setting the DMA channel’s interrupt latch bit in the IRPTL, LIRPTL,
DAI_IRPTL_H, or DAI_IRPTL_L registers.
•For chained DMA, the I/O processor generates interrupts in one of
two ways:
If PCI = 1, bit 19 of the chain pointer register is the program controlled interrupts bit and an interrupt occurs for each DMA in the
chain.
If PCI = 0, an interrupt occurs at the end of a complete chain. (For
more information on DMA chaining, see “DMA Controller Oper-
ation” on page 2-13.)
•When a DMA channel’s buffer is not being used for a DMA process, the I/O processor can generate an interrupt on single word
writes or reads of the buffer. This interrupt service differs slightly
for each port. For more information on single-word interrupt-driven transfers, see “Serial Port Control Registers (SPCTLx)”
on page 5-59.
ADSP-21368 SHARC Processor Hardware Reference 2-7
Configuring IOP/Core Interaction
During interrupt-driven DMA, programs use the interrupt mask bits in
the
IMASK, LIRPTL, DAI_IRPTL_PRI, DAI_IRPTL_RE, and DAI_IRPTL_FE reg-
isters to selectively mask DMA channel interrupts that the I/O processor
latches into the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L registers.
L
A channel interrupt mask in the IMASK, LIRPTL, DAI_IRPTL_PRI,
DAI_IRPTL_RE, and DAI_IRPTL_FE registers determines whether a latched
interrupt is to be serviced or not. When an interrupt is masked, it is
latched but not serviced. For more information on the IMASK and LIRPTL
registers, see “Interrupt Registers” on page B-6.
L
The I/O processor can also generate interrupts for I/O port operations
that do not use DMA. In this case, the I/O processor generates an interrupt when data becomes available at the receive buffer or when the
transmit buffer is not full (when there is room for the core to write to the
buffer). Generating interrupts in this manner lets programs implement
interrupt-driven I/O under control of the processor core. Care is needed
because multiple interrupts can occur if several I/O ports transmit or
receive data in the same cycle.
The I/O processor only generates a DMA complete interrupt when
the channel’s count register decrements to zero as a result of actual
DMA transfers. Writing zero to a count register does not generate
the interrupt. To stop a DMA preemptively, write a one to the
count register. This causes one more word to be transferred or
received and an interrupt is then generated.
By clearing a channel’s PCI bit during chained DMA, programs
mask the DMA complete interrupt for a DMA process within a
chained DMA sequence.
The digital audio interface (DAI) has two interrupts—the lower priority
option (
rupts to have priorities that are higher and lower than serial ports.
2-8ADSP-21368 SHARC Processor Hardware Reference
DAILI) and higher priority option (DAIHI). This allows two inter-
For more information, see the program sequencer “Interrupts and
Sequencing” section of Chapter 3 in the ADSP-2136x SHARC Processor Programming Reference and Appendix B, Interrupts.
Interrupt Latency in Interrupt-Driven Transfers
During an interrupt-driven I/O transfer from any peripheral that uses an
IOP interrupt service routine, a write into an IOP register to clear the
interrupt causes a certain amount of latency. If the program comes out of
the interrupt service routine during that period of latency, the interrupt is
generated again.
To avoid the interrupt from being regenerated, use one of the following
solutions.
1. Read an IOP register from the same peripheral block before the
return from interrupt (
3. Read a status register from the same peripheral block to check
whether the interrupt has cleared.
Polling/Status-Driven I/O
The second method of controlling I/O is through status polling. The I/O
processor monitors the status of data transfers on DMA channels and indicates interrupt status in the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L
registers. Note that because polling uses processor resources it is not as
efficient as an interrupt-driven system. Also note that polling the DMA
status registers reduces I/O bandwidth. The following provide more information on the registers that control and monitor I/O processes.
•All the bits in the
IRPTL and LIRPTL registers are shown in “Inter-
rupt Latch Register (IRPTL)” on page B-13 and “Interrupt
Register (LIRPTL)” on page B-6.
•Figure A-44 on page A-114 lists all the bits in the
DAI_IRPTL_L registers.
DAI_IRPTL_H and
The DMA controller in the ADSP-21367/8/9 and ADSP-2137x processors maintains the status information of the channels in each of the
peripherals registers, SPMCTLx, EPDMACTL, DAI_STAT, DPI_PIN_STAT,
RXSTAT_UACx, TXSTAT_UACx and SPIDMAC. More information on these regis-
ters can be found at the following locations.
2-12ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
•Bit definitions for the
Status (SPISTAT, SPISTATB) Registers” on page A-56.
•Bit definitions for the SPMCTLx register are illustrated in “SPORT
Multichannel Control Registers (SPMCTLx)” on page A-40.
•Bit definitions for the DAI_STAT register are illustrated in
Figure A-41 on page A-110.
Note that there is a one-cycle latency between a change in DMA channel
status and the status update in the corresponding register.
SPIDMAC register are illustrated in “SPI Port
DMA Controller Operation
There are two methods you can use to start DMA sequences: chaining and
non-chaining.
Non-chained DMA. To start a new DMA sequence after the current one
is finished, a program must first clear the DMA enable bit, write new
parameters to the index, modify, and count registers, then set the DMA
enable bit to re-enable DMA.
Chained DMA. Chained DMA sequences are a set of multiple DMA
operations, each autoinitializing the next in line. To start a new DMA
sequence after the current one is finished, the IOP automatically loads
new index, modify, and count values from an internal memory location
pointed to by that channel’s chain pointer register. Using chaining, programs can set up consecutive DMA operations and each operation can
have different attributes.
Chaining is only supported on the SPI and SPORT DMA channels. The IDP port does not support chaining.
Configuring IOP/Core Interaction
In general, a DMA sequence starts when one of the following occurs:
•Chaining is disabled, and the DMA enable bit transitions from low
to high.
•Chaining is enabled, DMA is enabled, and the chain pointer register address field is written with a nonzero value. In this case, TCB
chain loading of the channel parameter registers occurs first.
•Chaining is enabled, the chain pointer register address field is nonzero, and the current DMA sequence finishes. Again, TCB chain
loading occurs.
A DMA sequence ends when one of the following occurs:
•The count register decrements to zero, and the chain pointer register is zero.
•Chaining is disabled and the channel’s DMA enable bit transitions
from high to low. If the DMA enable bit goes low (=0) and chaining is enabled, the channel enters chain insertion mode and the
DMA sequence continues. For more information, see “Inserting a
TCB in an Active Chain” on page 2-41.
Once a program starts a DMA process, the process is influenced by two
external controls—DMA channel priority and DMA chaining. For more
information, see “Managing DMA Channel Priority” on page 2-19 or
“Chaining DMA Processes” below.
Chaining DMA Processes
The location of the DMA parameters for the next sequence comes from
the chain pointer register. In chained DMA operations, the processor
automatically initializes and then begins another DMA transfer when the
current DMA transfer is complete. In addition to the standard DMA
parameter registers, each DMA channel (SPORT, eternal port, UART and
SPI) also has a chain pointer register that points to the next set of DMA
2-14ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
parameters stored in the processor’s internal memory. These are the
CPSPxy registers for the SPORTs, the CPEP register for the external port,
the RXCP_UACx registers for the UART, and the CPSPI register for the SPI.
Each new set of parameters is stored in a four-word, user-initialized buffer
in internal memory known as a transfer control block (TCB).
The structure of a TCB is conceptually the same as that of a traditional
linked list. Each TCB has several data values and a pointer to the next
TCB. Further, the chain pointer of a TCB may point to itself to constantly reiterate the same DMA.
A DMA sequence is defined as the sum of the DMA transfers for a single
channel, from when the parameter registers initialize to when the count
register decrements to zero. Each DMA channel has a chaining enable bit
(CHEN) in the corresponding control register. This bit must be set to one to
enable chaining. When chaining is enabled, DMA transfers are initiated
by writing a memory address to the chain pointer register. This is also an
easy way to start a single DMA sequence, with no subsequent chained
DMAs.
The chain pointer register can be loaded at any time during the DMA
sequence. This allows a DMA channel to have chaining disabled (chain
pointer register address field = 0x0000) until some event occurs that loads
the chain pointer register with a nonzero value. Writing all zeros to the
address field of the chain pointer register also disables chaining.
If chaining is enabled on a DMA channel, programs should not use polling to determine channel status as it can provide inaccurate information.
In this case, the DMA appears inactive if it is sampled while the next
transfer control block (TCB) is loading.
L
The chain pointer register is 20 bits wide. The lower 19 bits are the memory address field. Like other I/O processor address registers, the chain
pointer register’s value is offset to match the starting address of the
Chained DMA operations may only occur within the same channel. The processor does not support cross-channel chaining.
Configuring IOP/Core Interaction
processor’s internal memory before it is used by the I/O processor. On the
ADSP-21367/8/9 and ADSP-2137x processors, this offset value is
0x0008 0000.
Bit 19 of the chain pointer register is the program-controlled interrupts
(
PCI) bit. This bit controls whether an interrupt is latched after every
DMA in the chain (when set), or whether the interrupt is latched after the
entire DMA sequence completes (if cleared).
L
Because the PCI bit is not part of the memory address in the chain pointer
register, programs must use care when writing and reading addresses to
and from the register. To prevent errors, programs should mask out the
PCI bit (bit 19) when copying the address in a chain pointer register to
another address register.
The DMA registers are shown in Figure 2-1.
Transfer Control Block Chain Loading (TCB)
During TCB chain loading, the I/O processor loads the DMA channel
parameter registers with values retrieved from internal memory. The
address in the chain pointer register points to the highest address of the
TCB (containing the index parameter). This means that if a program
declares an array to hold the TCB, the chain pointer register should not
point to the first location of the array.
Table 2-4 shows the TCB-to-register loading sequence for the serial port
and SPI port DMA channels. The I/O processor reads each word of the
TCB and loads it into the corresponding register. Programs must set up
the TCB in memory in the order shown in Table 2-4, placing the index
parameter at the address pointed to by the chain pointer register of the
The PCI bit only effects DMA channels that have chaining enabled.
Also, interrupt requests enabled by the PCI bit are maskable with
the IMASK register.
Program – Controlled Interrupt Bit
If this bit is set, theI/O processor generates a
DMA interrupt after every DMA in the chain.
PCI Bit
I/O Processor
Figure 2-1. DMA Parameter Registers
previous DMA operation of the chain. The end of the chain (no further
TCBs are loaded) is indicated by a TCB with a chain pointer register value
of zero.
1 Chaining is not available using the IDP port.
2 An “x” denotes the DMA channel used. While the TCB is eight locations in length, SPI and serial
ports only use the first four locations.
1
IISPxIISPI
A TCB chain load request is prioritized like all other DMA operations.
The I/O processor latches a TCB loading request and holds it until the
load request has the highest priority. If multiple chaining requests are
present, the I/O processor services the
TCB registers for the highest priority
DMA channel first. A channel that is in the process of chain loading cannot be interrupted by a higher priority channel. For a list of DMA
channels in priority order, see Table 2-7 on page 2-32.
Setting Up DMA Channel Allocation and Priorities
There are between 24 and 34 channels of DMA available on the
ADSP-21367/8/9 and ADSP-2137x processors, depending on the processor model. The maximum number is configured as—16 via the serial
ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface,
2 for the external port, and 2 for memory-to-memory transfers. Each
channel has a set of parameter registers which are used to set up DMA
2-18ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
transfers. Table 2-5 shows the DMA channel allocation and parameter
register assignments for the ADSP-21367/8/9 and ADSP-2137x
processors.
L
Managing DMA Channel Priority
The DMA channel prioritization scheme ranks channel 0 as highest priority and channel 34 as the lowest priority. Table 2-7 on page 2-32 lists the
DMA channels in priority order. When a channel becomes the highest
priority requester, the I/O processor services the channel’s request. In the
next clock cycle, the I/O processor starts the DMA transfer.
The I/O data (IOD) bus is 32 bits wide and is the only path that the IOP
uses to transfer data between internal memory and the peripherals. When
there are two or more peripherals with active DMAs in progress, they may
all require data to be moved to or from memory in the same cycle. For
example, the input data port may fill its RXPP buffer just as a SPORT shifts
a word into its RXn buffer. To determine which word is transferred first,
the DMA channels for each of the processor’s I/O ports negotiate channel
priority with the I/O processor using an internal DMA request/grant
handshake.
DMA channels vary by processor model. For a breakdown of DMA
channels for a particular model, see the processor specific data
sheet.
Each I/O port has one or more DMA channels, and each channel has a
single request and a single grant. When a particular channel needs to read
or write data to internal memory, the channel asserts an internal DMA
request. The I/O processor prioritizes the request with all other valid
DMA requests. When a channel becomes the highest priority requester,
the I/O processor asserts the channel’s internal DMA grant. In the next
clock cycle, the DMA transfer starts. Figure 2-3 on page 2-30 shows the
paths for internal DMA requests within the I/O processor.
The default DMA channel priority is fixed prioritization by DMA channel
group (serial ports, TWI, UART, IDP, or SPI port). Table 2-7 on
page 2-32 lists the DMA channels in descending order of priority.
For information on programming serial port priority modes, see
Table 5-11 on page 5-74.
The I/O processor determines which DMA channel has the highest priority internal DMA request during every cycle between each data transfer.
Processor core accesses of I/O processor registers and TCB chain loading
(both of which occur after the IOD transfer) are subject to the same prioritization scheme as the DMA channels. Applying this scheme uniformly
prevents I/O bus contention, because these accesses are also performed
over the internal I/O bus. For more information, see “Chaining DMA
Processes” on page 2-14.
DMA Bus Arbitration
If a DMA channel is disabled (EPDEN, SPIDEN, SDEN, or IDP_DMA_EN
bits =0), the I/O processor does not issue internal DMA grants to
that channel (whether or not the channel has data to transfer).
DMA channel arbitration is the method that the IOP uses to determine
how groups rotate priority with other channels. This feature is enabled by
setting the
DMA-capable peripherals execute DMA data transfers to and from internal memory over the IOD bus. When more than one of these peripherals
requests access to the IOD bus in a clock cycle, the bus arbiter, which is
attached to the IOD bus, determines which master should have access to
the bus and grants the bus to that master.
2-20ADSP-21368 SHARC Processor Hardware Reference
DCPR bit in the IOP’s SYSCTL register.
I/O Processor
IOP channel arbitration can be set to use either a fixed or rotating algorithm by setting or clearing bit 7 (
DCPR) in the SYSCTL register:
•fixed SYSCTL[7] cleared (0)
•rotating SYSCTL[7] set (1)
In the fixed priority scheme, the lower indexed peripheral has the highest
priority.
In the rotating priority scheme, the default priorities at reset are the same
as that of the fixed priority. However, the peripheral priority is determined by group, not individually. Peripheral groups are shown in
Table 2-5.
Initially, group A has the highest priority and group F the lowest. As one
group completes its DMA operation, it is assigned the lowest priority
(moves to the back of the line) and the next group is given the highest
priority.
When none of the peripherals request bus access, the highest priority
peripheral, for example, peripheral#0, is granted the bus. However, this
does not change the currently assigned priorities to various peripherals.
Within a peripheral group the priority is highest for the higher indexed
peripheral (see Table 2-5). For example, in SP01 (which is in group A),
SP1 has the highest priority.
Table 2-5. DMA Channel Allocation and Parameter Register
Assignments
Once you have determined and configured the DMA options, you can
configure the DMA parameter registers. The parameter registers control
the source and destination of the data, the size of the data buffer, and the
step size used. These topics are described in detail in the following
sections.
DMA Transfer Direction
DMA transfers between internal memory and external memory devices use
the processor’s external port. For these types of transfers, a program provides the DMA controller with the internal memory buffer size, address,
and address modifier, as well as the external memory buffer size, address
and address modifier and the direction of transfer. After setup, the DMA
transfers begin when the program enables the channel and continues until
the I/O processor transfers the entire buffer to processor memory.
Table 2-6 on page 2-29 shows the parameter registers for each DMA
channel.
Similarly, DMA transfers between internal memory and serial, IDP or SPI
ports have DMA parameters. When the I/O processor performs DMA
between internal memory and one of these ports, the program sets up the
parameters, and the I/O uses the port instead of the external bus.
Additionally, the ADSP-21367/8/9 and ADSP-2137x processors can use
DMA to transfer 64-bit blocks of data between internal memory locations.
The direction (receive or transmit) of the peripheral determines the direction of data transfer. When the port receives data, the I/O processor
automatically transfers the data to internal memory. When the port needs
to transmit a word, the I/O processor automatically fetches the data from
internal memory. Figure 2-2 shows the processor’s I/O processor, related
ports, and buses. Figure 2-3 on page 2-30 shows more detail on DMA
channel data paths.
2-24ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
IOA BUS
SPORT
IISP 7A -0A,
IISP 7B -0B,
IMS P7 A-0A ,
IMS P7B -0B
CSP7A-0A,
CSP7B-0B,
CPSP7A-0A,
CPSP7B-0B
SPI
IISP I, IM SPI,
CSPI,CPSPI
IDP
IDP_DMA_Ix
IDP_DMA_Mx
IDP_DMA_Cx
UART
UARTxRXCTL, IIUARTxRX
IMUARTxRX, CUARTxRX
CPUARTxRX,UARTxRXSTAT
UARTxTXCTL,IIUARTxTX
IMUARTxTX, CUARTxTX
CPUARTxTX,UART xTXSTAT
EXTERNAL
PORT
EIEPx, EMEPx
ECEPx,IIEPx
IMEPx, ICEPx
CEPx, CPEPx
EBEPx, TPEPx
ELEPx
MUX
PRIORITIZER
I/O PROCESSOR
INTERNAL
DMA
IOD BUS
MUX
(4 DEEP )
SPI
DMA
FIFO
DMD, PMD
BUSES(TO C ORE )
TXSP5A-0A,
TXSP5B-0B,
RXSP5A-0A,
RXSP5B-0B
RXSPI, TXSPI
(1 DEEP EACH)
EXTERNEL
EXTERNAL
GENERATOR
DFEP0 (DATA FIFO)
TFEP0 (TAP LIST FIFO)
SPORT S
(2 DEEP )
SPI PORT
PORT
ADDRESS
IDP
IDP F IFO
8DEEP
Figure 2-2. I/O Processor Block Diagram
Data Buffer Registers
Figure 2-2 shows the data buffer registers for each port. These registers
include:
•Serial port receive buffers (RXSPx). These receive buffers for the
serial ports have two-position FIFOs for receiving data when connected to another serial device.
serial ports have two-position FIFOs for transmitting data when
connected to another serial device.
•SPI receive buffers (RXSPI, RXSPIB). These receive buffers for the
SPI ports have a single-position buffer for receiving data when connected to another serial device.
•SPI transmit buffers (TXSPI, TXSPIB). These transmit buffers for
the SPI ports have a single-position buffer for transmitting data
when connected to another serial device.
•Input data port buffers (IDP_FIFO). This receive buffer for the
input data port has eight-position buffers for receiving data when
connected to another device.
Port, Buffer, and DMA Control Registers
The port, buffer, and DMA control registers in Figure 2-2 shows the control registers for the ports and DMA channels. These registers include:
•External port control registers (DMACx). These are the control regis-
ters for the external port DMA channels.
•Input data port control register (IDP_CTL). This is the control reg-
ister for the input data ports.
•Serial port control registers (
SPCTLx, SPMCTLx). These control reg-
isters select the receive or transmit format, monitor FIFO status,
enable chaining, and start DMA for each serial port.
•SPI port control registers (
SPICTL, SPICTLB). These control regis-
ters configure and enable the two SPI interfaces, selecting the
devices as masters or slaves, and determine the data transfer and
word size. The SPIDMAC and SPIDMACB registers also control SPI
DMA and FIFO status.
RXC_UAC/TXC_UAC). Count registers indicate the number of words
remaining to be transferred to or from internal memory on the corresponding DMA channel.
•Chain pointer registers (
RXCP_UAC/TXCP_UAC). Chain pointer registers hold the starting
CPSPx, CPSPI, CPSPIB, CPEP,
address of the TCB (parameter register values) for the next DMA
operation on the corresponding channel. These registers also control whether the I/O processor generates an interrupt when the
current DMA process ends.
•External index registers (
EIEPx). Index registers provide an exter-
nal memory address, acting as a pointer to the next external
memory DMA read or write location.
the number of words remaining to be transferred to or from external memory on the corresponding DMA channel.
•Memory-to-memory write index register (IIMTMW). This register
provides the base address in memory where DMA writes start.
•Memory-to-memory write modify register (IMMTMW). The MTM
modify register modifies the write index register after each 32-bit
write.
•Memory-to-memory write counter register (CMTMW). The MTM
counter register indicates the quantity of 32-bit data to be transferred to memory. The counter is decremented by one after each
data write.
•Memory-to-memory read index register (IIMTMR). This register
provides the base address in memory where DMA reads start.
•Memory-to-memory read modify register (IMMTMR). The MTM
modify register modifies the write index register after each 32-bit
read.
•Memory-to-memory read counter register (
CMTMR). The MTM
counter register indicates the quantity of 32-bit data to be read
from memory. The counter is decremented by one after each data
write.
2-28ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-6. DMA Parameter Registers
RegisterFunctionWidthDescription
IIyInternal Index Register19 bitsAddress of buffer in internal
memory
IMxyInternal Modify Register16 bits
CxyInternal Count Register16 bitsLength of internal buffer
CPxyChain Pointer Register20 bitsChain pointer for DMA
EIEPExternal Index Register19 bitsAddress of buffer in external
EMEPExternal Modify Register16 bitsStride for external buffer
ECEPExternal Count Register16 bitsLength of external buffer
1 IDP_DMA_Mx registers are 6 bits wide only.
1
Stride for internal buffer
chaining
memory
Addressing
Figure 2-3 shows a block diagram of the I/O processor’s address generator
(DMA controller). Table 2-6 lists the parameter registers for each DMA
channel. The parameter registers are uninitialized following a processor
reset.
The I/O processor generates addresses for DMA channels much the same
way that the data address generators (DAGs) generate addresses for data
memory accesses. Each channel has a set of parameter registers including
an index register and modify register that the I/O processor uses to address
a data buffer in internal memory. The index register must be initialized
with a starting address for the data buffer. As part of the DMA operation,
the I/O processor outputs the address in the index register onto the processor’s I/O address bus and applies the address to internal memory
during each DMA cycle—a clock cycle in which a DMA transfer is taking
place.
All addresses in the index registers are offset by a value that matches the
processor’s first internal normal word addressed RAM location (before the
I/O processor uses the addresses). For the ADSP-21367/8/9 and
ADSP-2137x processors, this offset value is 0x0008 0000.
DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)
LOCAL BUS
INTER NAL
MEMORY
ADDRESS
IIX
INDEX (ADDRESS)
IMX
MODIFIER
+/-
POST-M ODIFY
DMAWORDCOUNTER
–1
CX
COUNT
CPX
CHAIN POINTER
+
WORKING REGISTER
MUX
DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)
LOCAL BUS
EXTERNAL
MEMORY
ADDRESS
EIPP
EXT. INDEX (ADDRESS)
EMPP
EXT. MODIFIER
LOCAL BUS
ECPP
EXT. COUNT
+
–1
POST-MODIFY
+
Figure 2-3. DMA Address Generator
2-30ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
The following rules for data transfers must be followed.
•DMA addresses must always be normal word (32-bit) memory.
•Internal memory data transfer sizes are 32 bits, while external data
transfer sizes may be 32, 16, or 8 bits.
•The I/O processor can transfer short word data (16-bit) using the
packing capability of the serial port and SPI port DMA channels.
After transferring each data word to or from internal memory, the I/O
processor adds the modify value to the index register to generate the
address for the next DMA transfer and writes the modified index value to
the index register. The modify value in the modify register is a signed integer, which allows both increment and decrement modifies. The modify
value can have any positive or negative integer value. Note that:
•If the I/O processor modifies the index register past the maximum
18-bit value to indicate an address out of internal memory, the
index wraps around to zero. With the offset for the ADSP-2136x
SHARC processor processors, the wraparound address is
0x0008 0000.
•If a DMA channel is disabled, the I/O processor does not service
requests for that channel, (whether or not the channel has data to
transfer).
[
The processor’s 34 DMA channels are numbered as shown in Table 2-7.
This table also shows the control, parameter, and data buffer registers that
correspond to each channel.
If a program loads the count register with zero, the I/O processor
does not disable DMA transfers on that channel. The I/O processor interprets the zero as a request for 216 transfers. This count
occurs because the I/O processor starts the first transfer before testing the count value. The only way to disable a DMA channel is to
clear its DMA enable bit.
Setting Up DMA Parameter Registers
In the serial port pair SP0/1, SP1 has a higher priority. For multichannel
pairs, the odd numbered channels have a higher priority (for example SP3,
SP5).
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers
DMA
Channel
Number
0SPCTL1IISP1A, IMSP1A, CSP1A,
1SPCTL1IISP1B, IMSP1B, CSP1B,
2SPCTL0IISP0A, IMSP0A, CSP0A,
3SPCTL0IISP0B, IMSP0B, CSP0B,
4SPCTL3IISP3A, IMSP3A, CSP3A,
5SPCTL3IISP3B, IMSP3B, CSP3B,
6SPCTL2IISP2A, IMSP2A, CSP2A,
7SPCTL2IISP2B, IMSP2B, CSP2B,
8SPCTL5 IISP5A, IMSP5A, CSP5A,
Control RegistersParameter RegistersBuffer Registers Description
CPSP1A
CPSP1B
CPSP0A
CPSP0B
CPSP3A
CPSP3B
CPSP2A
CPSP2B
CPSP5A
RXSP1A,
TXSP1A
RXSP1B,
TXSP1B
RXSP0A,
TXSP0A
RXSP0B,
TXSP0B
RXSP3A,
TXSP3A
RXSP3B,
TXSP3B
RXSP2A,
TXSP2A
RXSP2B,
TXSP2B
RXSP5A,
TXSP5A
Serial Port
1A Data
Serial Port
1B Data
Serial Port
0A Data
Serial Port
0B Data
Serial Port
3A Data
Serial Port
3B Data
Serial Port
2A Data
Serial Port
2B Data
Serial Port
5A Data
9SPCTL5IISP5B, IMSP5B, CSP5B,
CPSP5B
10SPCTL4IISP4A, IMSP4A, CSP4A,
CPSP4A
11SPCTL4IISP4B, IMSP4B, CSP4B,
CPSP4B
RXSP5B,
TXSP5B
RXSP4A,
TXSP4A
RXSP4B,
TXSP4B
Serial Port
5B Data
Serial Port
4A Data
Serial Port
4B Data
2-32ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont’d)
DMA
Channel
Number
12SPCTL7 IISP7A, IM7P5A, CSP7A,
13SPCTL7IISP7B, IMSP7B, CSP7B,
14SPCTL6IISP6A, IMSP6A, CSP6A,
15SPCTL6IISP6B, IMSP6B, CSP6B,
16IDP_CTLIDP_DMA_I0,
17IDP_CTLIDP_DMA_I1,
18IDP_CTLIDP_DMA_I2,
19IDP_CTLIDP_DMA_I3,
Control RegistersParameter RegistersBuffer Registers Description
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont’d)
DMA
Channel
Number
32TXCTL_UAC0TXI_UAC0, TXM_UAC0,
33TXCTL_UAC1TXI_UAC1, TXM_UAC1,
Control RegistersParameter RegistersBuffer Registers Description
THR0UART0 Tx
TXC_UAC0, TXCP_UAC0,
TXSTAT_UAC0
THR1UART1 Tx
TXC_UAC1, TXCP_UAC1,
TXSTAT_UAC1
All of the I/O processor’s registers are memory-mapped, ranging from
address 0x0000 0000 to 0x0003 FFFF. For more information on these
registers, see “I/O Processor Registers” on page A-2.
External Port DMA
The external port has two DMA channels that can use either the SDRAM
controller (SDC) or the asynchronous memory interface (AMI). The
DMA chooses the correct interface (AMI or SDC) based on the external
address as determined by bits 0–3 in the external port global control regis-
EPCTL, Table A-3 on page A-11). The DMA controllers support
ter (
conventional DMA, chained and circular DMA, and delay line DMA. The
priority of the two DMA channels is fixed with external port 0 having priority over external port 1.
The DMA controllers have two FIFOs, a four deep data FIFO for
received/transmitted data and a four deep tap list FIFO for the tap list
entries for the delay line DMA.
The registers that control external port DMA are described in Table 2-8.
EBEP1–0 External Base Address Register0x1827, 0x1837
Setting Up and Starting Chained DMA
Use the following procedure to set up and run a chained DMA on the
external port.
1. Configure the AMICTLx registers to enable the AMI, set the desired
wait states, set the data bus width, and so on. Configure the
register to enable the SDRAM, set the desired clock and timing settings, set the data bus width, and so on.
2. Initialize the CPEP register—set the PCI bit if interrupts are needed
after the end of each DMA block.
2-36ADSP-21368 SHARC Processor Hardware Reference
SDCTL
I/O Processor
3. If circular buffering is needed, then program additional writes to
the
ELEP and EBEP registers. Note that for normal chained DMA,
the ELEP and EBEP registers are not part of the TCB. So if circular
buffering is used with the normal chained DMA, all the DMA
blocks will have same ELEP and EBEP values.l
4. Enable DMA (DEN), chaining (CHEN), and circular buffering (CBEN)
if needed, in the DMACx registers. It is advised that the DMA FIFOs
are flushed (DFLSH) when DMA is enabled.
Once the DMA control register is initialized, the DMA controller fetches
the DMA descriptors from the address pointed to by the external port
chain pointer register (CPEP). The order the descriptors are fetched is
shown in Table 2-9.
Once the DMA descriptors are fetched, the normal DMA process starts.
Upon completion, new DMA descriptors are loaded and the process is
repeated until
CPEP = 0x00000. A DMA completion interrupt is generated
at the end of each DMA block or at the end of an entire chained DMA,
depending on the PCI bit setting.
Delay Line DMA
Delay line DMA is used to support reads and writes to external delay line
buffers with limited core interaction. In this sense, delay line DMA is basically a quantity of integrated writes followed by reads from external
memory—called a delay line DMA access. The delay line DMA access consists of the following accesses in the order listed.
1. Writes to external memory. The number of writes are determined
by the external port internal count ICEP register. The data is
fetched from the external port internal index register (
the external port internal modify register (IMEP) is used as the internal modifier. The external port external index register (
2-38ADSP-21368 SHARC Processor Hardware Reference
IIEP) and
EIEP) serves
I/O Processor
as the external index and is incremented by the external modifier
register (
circular buffering is enabled.
2. In chained DMA, when the writes are complete, (ICEP = zero) the
EPEI register, which serves as the write pointer of the delay line, is
written back to the internal memory location from where it was
fetched.
3. Reads from external memory. For reads, the tap list (TL) modifiers
are used and the number of reads is determined by the external port
read count register (RCEP). The write pointer in the external port
external index register (EIEP) serves as the index address for these
reads (reads start from where writes end). The EIEP register, along
with tap list modifiers, are used in a pre-modify addressing mode
to create the external address for the writes. For each 32-bit read
the external index is:
EMEP) after each write. These writes are circular buffered if
•EIEP – TL[0] is the first read address (where TL[0] is the
first tap list entry in internal memory as pointed to by the
external port tap list pointer register TPEP).
•EIEP – TL[1] is the second address, and so on.
Therefore, for each read, the DMA controller fetches the external
modifier from the tap list and the reads are circular buffered (if
enabled).
The external address generation follows pre-modify addressing for
reads in delay line DMA and therefore EIEP values are not modified. Also the
line reads.
EMEP register does not have any effect during delay
Serial Port DMA
4. Once the read count completes, the delay line DMA access is complete and the DMA complete interrupt is generated. Note that if
chaining is enabled, the interrupt is generated based on the
setting. For more information on the PCI bit, see “Interrupt-Driven
I/O” on page 2-6.
Table 2-11. Chain Pointer Loading Sequence (Delay Line DMA)
AddressRegister Value
EPCP[18:0]EPII (Write Index)
EPCP[18:0] – 0x1EPIM
EPCP[18:0] – 0x2EPIC (Write Count)
EPCP[18:0] – 0x3EPEI
EPCP[18:0] – 0x4EPEM
EPCP[18:0] – 0x5EPEB
PCI bit
EPCP[18:0] – 0x6EPEL
EPCP[18:0] – 0x7EPRI
EPCP[18:0] – 0x8EPRC
EPCP[18:0] – 0x9EPTP
EPCP[18:0] – 0xAEPCP
Serial Port DMA
The serial ports support standard as well as chained DMA.
Setting Up and Starting Chained DMA
To set up and initiate a chain of DMA operations, use these steps:
1. Set up all TCBs in internal memory.
2-40ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
2. Write to the appropriate DMA control register, setting the DMA
enable bit to one and the chaining enable bit to one.
3. Write the address containing the index register value of the first
TCB to the chain pointer register, which starts the chain.
The I/O processor responds by autoinitializing the first DMA parameter
registers with the values from the first TCB, and then starts the first data
transfer.
Inserting a TCB in an Active Chain
It is possible to insert a single DMA operation or another DMA chain
within an active DMA chain. Programs may need to perform insertion
when a high priority DMA requires service and cannot wait for the current chain to finish.
When DMA on a channel is disabled and chaining on the channel is
enabled, the DMA channel is in chain insertion mode. This mode lets a
program insert a new DMA or DMA chain within the current chain without effecting the current DMA transfer. Use the following sequence to
insert a DMA subchain for the serial port 0A channel while another chain
is active:
1. Enter chain insertion mode by setting SCHEN_A = 1 and SDEN_A = 0
in the channel’s DMA control register,
SPCTL0. The DMA inter-
rupt indicates when the current DMA sequence is complete.
2. Copy the address currently held in the chain pointer register to the
chain pointer position of the last TCB in the chain that is being
inserted.
3. Write the start address of the first TCB of the new chain into the
chain pointer register.
4. Resume chained DMA mode by setting SCHEN_A = 1 and
Chain insertion mode operates the same as non-chained DMA mode.
When the current DMA transfer ends, an interrupt request occurs and no
TCBs are loaded. This interrupt request is independent of the
PCI bit
state.
Chain insertion should not be set up as an initial mode of operation. This
mode should only be used to insert one or more TCBs into an active
DMA chaining sequence.
Serial Peripheral Interface DMA
The serial peripheral interface supports both standard and chained DMA.
However, unlike the serial ports, programs cannot insert a TCB in an
active chain using the SPI.
Setting Up and Starting Chained DMA over the SPI
Configuring and starting chained DMA transfers over the SPI port is the
same as for the serial port, with one exception. Contrary to SPORT DMA
chaining, (where the first DMA in the chain is configured by the first
TCB), for SPI DMA chaining, the first DMA is not initialized by a TCB.
Instead, the first DMA in the chain must be loaded into the SPI parameter
registers (IISPI, IMSPI, CSPI), and the chain pointer register (CPSPI)
points to a TCB that describes the second DMA in the sequence.
Table 2-12 shows the order of register loading.
Table 2-12. DMA Chaining Sequence
AddressRegisterDescription
CPSPIDMA Start AddressAddress in memory
CPSPI – 1DMA Address ModifierAddress increment
CPSPI – 2DMA Word CountNumber of words to transfer
CPSPI – 3DMA Next TCBPointer to address of next TCB
2-42ADSP-21368 SHARC Processor Hardware Reference
I/O Processor
L
DMA sequence unless the IISPI, IMSPI, and CSPI registers are initialized, SPI DMA is enabled, the SPI port is enabled, and SPI
DMA chaining is enabled.
The sequence for setting up and starting a chained DMA is outlined in the
following steps and can also be seen in Listing 6-3 on page 6-43.
1. Configure the TCB associated with each DMA in the chain except
for the first DMA in the chain.
2. Write the first three parameters for the initial DMA to the IISPI,
Writing an address to the CPSPI register does not begin a chained
IMSPI, and CSPI registers directly.
3. Select a baud rate using the SPIBAUD register.
4. Select which flag to use as the SPI slave select signal in the SPIFLG
register.
5. Configure and enable the SPI port with the SPICTL register.
6. Configure the DMA settings for the entire sequence, enabling
DMA and DMA chaining in the SPIDMAC register.
7. Begin the DMA by writing the address of a TCB (describing the
second DMA in the chain) to the CPSPI register.
The address field of the chain pointer registers is only 19 bits wide. If a
program writes a symbolic address to bit 19 of the chain pointer, there
may be a conflict with the
PCI bit. Programs should clear the upper bits of
the address, then AND the PCI bit separately, if needed. For example:
R0 = next_TCB+3; /* addr of next chain */
R1 = 0x7FFFF; /* mask 19 bits */
R0 = R0 or R1;
CPSPI = R0;
In the UART, separate receive and transmit DMA channels move data
between the UART and memory. The software does not have to move
data, it just has to set up the appropriate transfers either through the
descriptor mechanism or through auto buffer mode. See also “DMA Con-
troller Operation” on page 2-13.
To perform DMA transfers, the UART has a special set of receive and
transmit registers. These registers are listed in Table 2-14.
Table 2-13. UART DMA Registers
RegisterDescription
UARTxRXCTL (3 bits) DMA Config/Control register for UART Rx
IIUARTxRX (19 bits)Address for DMA
IMUARTxRX (16 bits) Modifier
CUARTxRX (16 bits) Count
CPUARTxRX (20 bits) Chain Pointer
UARTxRXSTAT (3 bits) DMA Status register
UARTxTXCTL (3 bits) DMA Config/Control register for UART Tx
IIUARTxTX (19 bits)Address for DMA
IMUARTxTX (16 bits)Modifier
CUARTxTX (16 bits) Count
CPUARTxTX (20 bits)Chain Pointer
UARTxTXSTAT (3 bits)DMA Status register
No additional buffering is provided in the UART DMA channel, so the
latency requirements are the same as in non-DMA mode. However, the
latency is determined by the bus activity and arbitration mechanism and
not by the processor loading and interrupt priorities.
2-44ADSP-21368 SHARC Processor Hardware Reference
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