Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 Datasheet (ANALOG DEVICES)

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SHARC Processors

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD 64-BIT

Core Bus

Cross Bar

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

DAG1/2 Timer

IOD BUS

MTM/ DTCP

PERIPHERAL BUS

32-BIT

Internal Memory

DMD 64-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DAI Peripherals

Peripherals

SIMD Core

Core Flags

SPI

PWM 3

PP Pin MUX

PDAP/ IDP7-0

ASRC 3

TIMER 2-0

CORE

FLAGS

S/PDIF Tx/Rx

PCG A-B

SPI B

SPORT

DAI Routing/Pins

IOD 32-BIT

FLAGx/IRQx/ TMREXP

JTAG

PMD 64-BIT

DMD 64-BIT

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—3M bits of on-chip SRAM

Code compatible with all other members of the SHARC family The ADSP-2136x processors are available with up to 333 MHz

core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more. For complete ordering information, see Ordering

Guide on Page 54.

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include:

JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Available in 136-ball CSP_BGA and 144-lead LQFP_EP

packages

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Functional Block Diagram

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Summary ............................................................... 1

Dedicated Audio Components .................................... 1

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ........................................... 8

System Design ...................................................... 8

Development Tools ............................................... 9

Additional Information ........................................ 10

Related Signal Chains .......................................... 10

Pin Function Descriptions ....................................... 11

Specifications ........................................................ 14

Operating Conditions .......................................... 14

Electrical Characteristics ....................................... 14

Package Information ........................................... 15

REVISION HISTORY

7/12—Revision H to Revision I

Revised PLL Divider input in Core Clock and System Clock

Relationship to CLKIN .............................................16

Replaced the timing diagram Write Cycle for 16-Bit Memory

Timing ................................................................. 27

Changed the t

External Clock ....................................................... 28

(SCLK Width) parameter in Serial Ports—

SCLKW

ESD Caution ...................................................... 15

Maximum Power Dissipation ................................. 15

Absolute Maximum Ratings ................................... 15

Timing Specifications ........................................... 15

Output Drive Currents ......................................... 44

Test Conditions .................................................. 44

Capacitive Loading .............................................. 44

Thermal Characteristics ........................................ 45

144-Lead LQFP_EP Pin Configurations ....................... 46

136-Ball BGA Pin Configurations ............................... 48

Package Dimensions ............................................... 51

Surface-Mount Design .......................................... 52

Automotive Products .............................................. 53

Ordering Guide ..................................................... 54

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GENERAL DESCRIPTION

The ADSP-2136x SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super

Table 1 shows performance benchmarks for these devices.

Table 2 shows the features of the individual product offerings.

Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).

As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz.

Table 1. Benchmarks (at 333 MHz)

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs FIR Filter (per tap) IIR Filter (per biquad) Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1] Divide (y/x) 10.5 ns Inverse Square Root 16.3 ns

Assumes two files in multichannel SIMD mode.

(at 333 MHz)

1.5 ns

6.0 ns

13.5 ns

23.9 ns

Table 2. ADSP-2136x Family Features

Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366

RAM ROM

Audio Decoders in ROM Pulse-Width Modulation Yes Yes Yes Yes Yes S/PDIF Yes No Yes Yes Yes

DTCP SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB

Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,

speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information.

The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices

sales office for more information.

3M bit 4M bit

No No No Yes Yes

Ye s N o N o Ye s N o

3M bit 4M bit

The diagram on Page 1 shows the two clock domains that make up the ADSP-2136x processors. The core clock domain contains the following features:

• Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle

• One periodic interval timer with pinout

•On-chip SRAM (3M bit)

• On-chip mask-programmable ROM (4M bit)

• JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allow flexible exception handling.

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The diagram on Page 1 also shows the following architectural features:

• I/O processor that handles 32-bit DMA for the peripherals

• Six full duplex serial ports

• Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins

• 8-bit or 16-bit parallel port that supports interfaces to offchip memory peripherals

• Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, 8-channel asynchronous sample rate converter, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1 16x32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4x32-BIT

64-BIT

DAG2 16x32

ALU

MULTIPLIER

SHIFTER

DATA SWAP

PM ADDRESS 24

SHARC FAMILY CORE ARCHITECTURE

The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in

Figure 2 and detailed in the following sections.

SIMD Computational Engine

The processor contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms.

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats.

Figure 2. SHARC Core Block Diagram

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Data Register File

Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Universal Registers

The universal registers are general purpose registers. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core.

The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference.

Timer

A core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal.

Single-Cycle Fetch of Instruction and Four Operands

The processor features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With the its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.

On-Chip Memory

The processor contains 3M bits of internal SRAM and 4M bits of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle.

The SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 3M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

On-Chip Memory Bandwidth

The internal memory architecture allows three accesses at the same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses (2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK).

ROM-Based Security

The processor has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 3. ADSP-2136x Internal Memory Space

IOP Registers 0x0000 0000–0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 BFFF

Block 0 SRAM 0x0004 C000–0x0004 FFFF

Block 1 ROM 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 BFFF

Block 1 SRAM 0x0005 C000–0x0005 FFFF

Block 2 SRAM 0x0006 0000–0x0006 1FFF

Reserved 0x0006 2000–0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 1FFF

Reserved 0x0007 2000–0x0007 FFFF

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM 0x0008 0000–0x0008 AAA9

Block 0 SRAM 0x0009 0000–0x0009 5554

Block 1 ROM 0x000A 0000–0x000A AAA9

Block 1 SRAM 0x000B 0000–0x000B 5554

Block 2 SRAM 0x000C 0000–0x000C 2AA9

Block 3 SRAM 0x000E 0000–0x000E 2AA9

Block 0 ROM 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 7FFF

Block 0 SRAM 0x0009 8000–0x0009 FFFF

Block 1 ROM 0x000A 0000–0x000A FFFF

Reserved 0x000B 0000–0x000B 7FFF

Block 1 SRAM 0x000B 8000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 3FFF

Reserved 0x000C 4000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 3FFF

Reserved 0x000E 4000–0x000F FFFF

Block 0 ROM 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 FFFF

Block 0 SRAM 0x0013 0000–0x0013 FFFF

Block 1 ROM 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 FFFF

Block 1 SRAM 0x0017 0000–0x0017 FFFF

Block 2 SRAM 0x0018 0000–0x0018 7FFF

Reserved 0x0018 8000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C 7FFF

Reserved 0x001C 8000–0x001F FFFF

Reserved 0x0020 0000–0xFFFF FFFF

or test access port, is assigned to each customer. The device ignores a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2136x family contains a rich set of peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8-bit or 16-bit, the maximum data transfer rate is 55 Mbps.

DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD (address latch enable) pins are the control pins for the parallel port.

, WR, and ALE

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the processor’s SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes and can operate at a maximum baud rate of f

PCLK

/4.

The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPIcompatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.

Pulse-Width Modulation

The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs.

The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms).

The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters.

Digital Audio Interface (DAI)

The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU, shown in Figure 1).

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI-associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths.

The DAI includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2136x core, configurable as either eight channels of I

S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports.

Serial Ports

The processor features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixedsignal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and a frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

S mode

•I

• Left-justified sample pair mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I

S, or right-justified with

word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers.

Digital Transmission Content Protection (DTCP)

The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. This feature is available on the ADSP-21362 and ADSP-21365 processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information.

Memory-to-Memory (MTM)

If the DTCP module is not used, the memory-to-memory DMA module allows internal memory copies for a standard DMA.

Synchronous/Asynchronous Sample Rate Converter (SRC)

The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 140 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver.

The S/PDIF and SRC are not available on the ADSP-21363 models.

Input Data Port (IDP)

The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit

S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit

I right-justified formats.

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of two units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A and B, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

Peripheral Timers

The following three general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently.

I/O PROCESSOR FEATURES

The processor’s I/O provides many channels of DMA and controls the extensive set of peripherals described in the previous sections.

DMA Controller

The processor’s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4.

Table 4. DMA Channels

Peripheral ADSP-2136x

SPORTs 12 IDP/PDAP 8 SPI 2 MTM/DTCP 2 Parallel Port 1 Total DMA Channels 25

SYSTEM DESIGN

The following sections provide an introduction to system design options and power supply issues.

Program Booting

The internal memory of the processor boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins in Table 5. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.

Table 5. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot 01 SPI Master Boot 10 Parallel Port Boot via EPROM 11 No booting occurs. Processor executes

from internal ROM after reset.

Phase-Locked Loop

The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1. After booting, numerous other ratios can be selected via software control.

The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8.

Power Supplies

The processor has a separate power supply connection for the internal (V power supplies. The internal and analog supplies must meet the

1.2 V requirement for K, B, and Y grade models, and the 1.0 V requirement for Y models. (For information on the temperature ranges offered for this product, see Operating Conditions on

Page 14, Package Information on Page 15, and Ordering Guide on Page 54.) The external supply must meet the 3.3 V require-

ment. All external supply pins must be connected to the same power supply.

Note that the analog supply pin (A internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the A

pin. Place the filter components as close as possible to the

VDD

VDD/AVSS

recommended ferrite chip is the muRata BLM18AG102SN1D.) To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for V to connect the bypass capacitors to the analog power (A and ground (A specified in Figure 3 are inputs to the processor and not the analog ground plane on the board—the A directly to digital ground (GND) at the chip.

DDINT

), external (V

), and analog (A

DDEXT

VDD

VDD/AVSS

) powers the processor’s

pins. For an example circuit, see Figure 3. (A

and GND. Use wide traces

DDINT

) pins. Note that the A

VSS

and A

VDD

pin should connect

VSS

pins

VDD

)

Rev. I | Page 8 of 56 | July 2012

HIGH-Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS

CLOSE TO A

VDD

AND A

VSS

PINS

VDD

VSS

100nF 10nF 1nF

ADSP-213xx

DDINT

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Figure 3. Analog Power (A

Target Board JTAG Emulator Connector

Analog Devices’ DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices’ DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator does not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, refer to the appropriate emulator user’s guide.

DEVELOPMENT TOOLS

The processor is supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2136x processors.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler (based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and

software and hardware development tools,

) Filter Circuit

VDD

devel-

efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Through debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK is designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Rev. I | Page 9 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface. (The emulator does not affect target system loading or timing.) The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, refer to the Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices website, www.ana-

log.com. (Perform a site search on “EE-68.”) This document is

updated regularly to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite platform includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, a power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices’ JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the processor’s architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor

Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab (http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

site

Rev. I | Page 10 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PIN FUNCTION DESCRIPTIONS

The processor’s pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI).

Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST inputs to V

or GND, except for the following:

DDEXT

DAI_Px, SPICLK, MISO, MOSI, EMU

). Tie or pull unused

, TMS, TRST, TDI, and

AD15–0. Note: These pins have pull-up resistors.

Table 6. Pin Descriptions

State During and

Pin Type

AD15–0 I/O/T

(pu)

ALE O

FLAG[0]/IRQ0/SPI FLG[0]

FLAG[1]/IRQ1 FLG[1]

FLAG[2]/IRQ2 FLG[2]

FLAG[3]/TMREXP/ SPIFLG[3]

DAI_P20–1 I/O/T

The following symbols appear in the Type column of Tab le 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

O (pu)

(pd)

I/O FLAG[0] INPUT FLAG0/Interrupt Request0/SPI0 Slave Select.

/SPI

I/O FLAG[1] INPUT FLAG1/Interrupt Request1/SPI1 Slave Select.

/SPI

I/O FLAG[2] INPUT FLAG2/Interrupt Request 2/SPI2 Slave Select.

I/O FLAG[3] INPUT FLAG3/Timer Expired/SPI3 Slave Select.

(pu)

After Reset Function

Three-state with pull-up enabled

Three-state, driven

high

Three-state, driven

high

Three-state, driven

low

Three-state with programmable pull-up

Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin operation, refer to the ADSP-2136x SHARC Processor Hardware Reference.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, ADDR23–8; ALE is used in conjunction with an external latch to retain the values of the ADDR23–8.

For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x SHARC Processor Hardware Reference.

Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. RD has a 22.5 kΩ internal pull-up resistor.

Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted. WR

Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors that are enabled on reset. These pull-ups can be disabled using the DAI_PIN_PULLUP register.

has a 22.5 kΩ internal pull-up resistor.

Rev. I | Page 11 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 6. Pin Descriptions (Continued)

State During and

Pin Type

SPICLK I/O

(pu)

SPIDS

MOSI I/O (O/D)

MISO I/O (O/D)

CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It

XTAL O Output only CLK_CFG1–0 I Input only Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the

I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the

(pu)

After Reset Function

Three-state with pull-up enabled, driven high in SPImaster boot mode

Three-state with pull-up enabled, driven low in SPImaster boot mode

Three-state with pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a varie ty of bau d rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.

processor as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the processor’s

signal can be driven by a slave device to signal to the processor (as SPI master)

SPIDS that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to V action, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device.

SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pullup resistor.

SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting Bit 5 (DMISO) of the SPICTL register equal to 1.

configures the ADSP-2136x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below the specified frequency.

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external cr ystal.

operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are:

00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved.

on the master device. For processor to processor SPI inter-

DDEXT

Rev. I | Page 12 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 6. Pin Descriptions (Continued)

State During and

Pin Type

BOOT_CFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.

RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device. RESET

I/A Input only Processor Reset. Resets the ADSP-2136 x to a k nown state. Upon deass ertion, there is a

TCK I Input only

TMS I/S

(pu)

TDI I/S

(pu) TDO O Three-state TRST

I/A

(pu)

EMU

O (O/D)

(pu) V

DDINT

DDEXT

VDD

VSS

P Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the

P I/O Power Supply. Nominally +3.3 V dc.

P Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for

G Analog Power Supply Return. GND G Power Supply Return. The following symbols appear in the Type column of Tab le 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,

S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output path and pull-up disabled.

Three-state is a three-state driver with pull-up disabled.

After Reset Function

The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot mode, refer to the ADSP-2136x SHARC Processor Hardware Reference.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the processors.

Three-state with pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-2136x. TRST internal pull-up resistor.

Three-state with pull-up enabled

Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU

Y grade models, and supplies the processor’s core.

the Y grade models, and supplies the processor’s internal PLL (clock generator). This pin has the same specifications as V

more information, see Power Supplies on Page 8.

has a 22.5 kΩ internal pull-up resistor.

, except that added filtering circuitry is required. For

DDINT

has a 22.5 kΩ

Rev. I | Page 13 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS

K Grade B Grade Y Grade

Parameter Description Min Max Min Max Min Max Unit

DDINT

VDD

DDEXT

IH_CLKIN

IL_CLKIN

3, 4

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST.

Applies to input pin CLKIN.

See Thermal Characteristics on Page 45 for information on thermal specifications.

See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.

Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V

Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V

External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V

High Level Input Voltage @ V

Low Level Input Voltage @ V

High Level Input Voltage @ V

Low Level Input Voltage @ V

= Max 2.0 V

DDEXT

= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

DDEXT

= Max 1.74 V

DDEXT

= Min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 1.74 V

DDEXT

Junction Temperature 136-Ball CSP_BGA 0 +110 –40 +125 –40 +125 °C

Junction Temperature 144-Lead LQFP_EP 0 +110 –40 +125 –40 +125 °C

+ 0.5 V

ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Max Unit

3, 4

ILPU

5, 6

OZH

OZL

OZLPU

7, 8

DD-INTYP

AVD D

10, 11

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL.

See Output Drive Currents on Page 44 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-stateable pins: FLAG3–0.

Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI.

Typical internal current data reflects nominal operating conditions.

See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

High Level Output Voltage @ V

Low Level Output Voltage @ V

High Level Input Current @ V

Low Level Input Current @ V

Low Level Input Current Pull-Up @ V

Three-State Leakage Current @ V

Three-State Leakage Current Pull-Up @ V

Supply Current (Internal) t

Supply Current (Analog) A

Input Capacitance f

CCLK

VDD

= Min, IOH = –1.0 mA

DDEXT

= Min, IOL = 1.0 mA

DDEXT

= Max, VIN = V

DDEXT

= Max, VIN = 0 V 10 μA

DDEXT

= Max, VIN = 0 V 200 μA

DDEXT

= Max, VIN = V

DDEXT

= Max, VIN = 0 V 10 μA

DDEXT

= Max, VIN = 0 V 200 μA

DDEXT

= Min, V

= Nom 800 mA

DDINT

= Max 10 mA

= 1 MHz, T

= 25°C, VIN = 1.2 V 4.7 pF

CASE

Max 10 μA

DDEXT

Max 10 μA

DDEXT

2.4 V

0.4 V

Rev. I | Page 14 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

tppZ-cc

ADSP-2136x

#yyww country_of_origin

vvvvvv.x n.n

ESD

(electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 4 provides details about the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Ordering Guide on

Page 54.

Figure 4. Typical Package Brand

Table 7. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z RoHS Compliant Designation cc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision # RoHS Compliant Designation yyww Date Code

ESD CAUTION

Table 8. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V Analog (PLL) Supply Voltage (A External (I/O) Supply Voltage (V Input Voltage –0.5 V to +3.8 V Output Voltage Swing –0.5 V to V Load Capacitance 200 pF Storage Temperature Range –65°C to +150°C Junction Temperature While Biased 125°C

)–0.3 V to +1.5 V

DDINT

)–0.3 V to +1.5 V

VDD

)–0.3 V to +4.6 V

DDEXT

+ 0.5 V

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. For voltage reference levels, see Figure 39 on Page 44 under Test

Conditions.

Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

MAXIMUM POWER DISSIPATION

See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for detailed thermal and power information regarding

maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 45.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 8 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. I | Page 15 of 56 | July 2012

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 5). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds f

specified in Table 11.

VCO

• The product of CLKIN and PLLM must never exceed 1/2 f

(max) in Table 11 if the input divider is not enabled

VCO

(INDIV = 0).

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

CLKOUT (TEST ONLY)*

LOOP

FILTER

PLL

VCO

÷ (2 × PLLM)

VCO

PLL

DIVIDER

PMCTL

(2 × PLLN)

VCO

CCLK

CLK_CFGx/

PMCTL (2 × PLLM)

CLKIN

PCLK

XTAL

CLKIN

DIVIDER

RESETOUT

DELAY OF

4096 C LKIN

CYCLES

RESET

BUF

PMCTL (INDIV)

PMCTL

(PLLBP)

BYPASS

MUX

PIN MUX

DIVIDE

BY 2

RESETOUT

PMCTL (CLKOUTEN)

CCLK

CORERST

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f

INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

INPUT

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 11 if the input divider is enabled (INDIV = 1).

The VCO frequency is calculated as follows:

= 2 × PLLM × f

VCO

= (2 × PLLM × f

CCLK

INPUT

) ÷ (2 × PLLN)

where:

= VCO output

VCO

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware.

PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1.

= Input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN ÷ 2 when the input divider is enabled

INPUT

Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 9. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to t

. Refer to the peripheral specific sec-

PCLK

tion for each peripheral’s timing information.

Table 9. Clock Periods

Timing Requirements Description

t t t

CCLK

PCLK

CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × t

CCLK

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference.

Figure 5. Core Clock and System Clock Relationship to CLKIN

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

RSTVDD

CLKVDD

CLKRST

CORERST

PLLRST

DDEXT

DDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

IVDDEVDD

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10. Note that during power-up, when the V

supply comes up after V

, a leakage current of the order of

DDEXT

DDINT

power

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

IVDDEVDD

CLKVDD

CLKRST

PLLRST

RESET Low Before V V

On Before V

DDINT

CLKIN Valid After V

DDINT/VDDEXT

DDEXT

DDINT/VDDEXT

On 0 ns

Valid 0 200 ms CLKIN Valid Before RESET Deasserted 10 PLL Control Setup Before RESET Deasserted 20 μs

Switching Characteristic

CORERST

Valid V

DDINT/VDDEXT

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate

default states at all I/O pins.

The 4096 cycle count depends on t

maximum.

Core Reset Deasserted After RESET Deasserted 4096tCK + 2 t

assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,

specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles

SRST

three-state leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example the RESET pin) until the V

rail has powered up.

DDINT

–50 +200 ms

CCLK

μs

Figure 6. Power-Up Sequencing

Rev. I | Page 17 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

CLKIN

CKL

CKH

CKJ

22pF

R1 1M *

XTAL

CLKIN

22pF

24.576MHz

ADSP-2136x

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS.

*TYPICAL VALUES

47Ω

Clock Input

Table 11. Clock Input

200 MHz

Parameter

Min Max Min Max

Timing Requirements

CKL

CKH

CKRF

CCLK

VCO

6, 7

CKJ

Applies to all 200 MHz models. See Ordering Guide on Page 54.

Applies to all 333 MHz models. See Ordering Guide on Page 54.

Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

See Figure 5 on Page 16 for VCO diagram.

Actual input jitter should be combined with AC specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Period 30 CLKIN Width Low 12.5 7.5 ns CLKIN Width High 12.5 7.5 ns CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns CCLK Period 5.0 10 3.0 10 ns VCO Frequency 200 600 200 800 MHz CLKIN Jitter Tolerance –250 +250 –250 +250 ps

100 18 100 ns

CCLK

333 MHz

Unit

Clock Signals

The processor can use an external clock or a crystal. Refer to the CLKIN pin description in Table 6 on Page 11. The user application program can configure the processor to use its internal clock generator by connecting the necessary components to the CLKIN and XTAL pins. Figure 8 shows the component connections used for a fundamental frequency crystal operating in parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock speed of 266.72 MHz.) To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register.

Figure 7. Clock Input

Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation

Rev. I | Page 18 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

CLKIN

RESET

SRST

WRST

DAI_P20–1

FLAG2–0

(IRQ2–0)

IPW

Reset

Table 12. Reset

Parameter Min Unit

Timing Requirements

WRST

SRST

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

Interrupts

The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0 IRQ1

, and IRQ2 interrupts.

RESET Pulse Width Low 4 × t

RESET Setup Before CLKIN Low 8 ns

Figure 9. Reset

Table 13. Interrupts

Parameter Min Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

Figure 10. Interrupts

+2 ns

PCLK

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

FLAG3

(TMREXP)

WCTIM

DAI_P20–1

(TIMER2–0)

PWMO

Core Timer

The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin).

Table 14. Core Timer

Parameter Min Unit

Switching Characteristic

WCTIM

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

TMREXP Pulse Width 2 × t

Figure 11. Core Timer

– 1 ns

PCLK

Table 15. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

Figure 12. Timer PWM_OUT Timing

– 1 2 × (231 – 1) × t

PCLK

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_P20–1

(TIMER2–0)

PWI

DAI_Pn

DAI_Pm

DPIO

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins.

Table 16. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O).

Timer Pulse Width 2 × t

Figure 13. Timer Width Capture Timing

PCLK

2 × (231– 1) × t

PCLK

Table 17. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

Figure 14. DAI Pin to Pin Direct Routing

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

DTRIGFS

DTRIGCLK

DPCGIO

STRIG

HTRIG

PCGOP

DPCGIO

PCGIP

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs

inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 through DAI_P20).

directly to the DAI pins. For the other cases, where the PCG’s

Table 18. Precision Clock Generator (Direct Pin Routing)

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements t

PCGIP

STRIG

Input Clock Period t PCG Trigger Setup Before Falling

× 4 ns

PCLK

4.5 ns

Edge of PCG Input Clock

HTRIG

PCG Trigger Hold After Falling

3 ns

Edge of PCG Input Clock

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input

2.5 10 10 ns

Clock

DTRIG CLK

PCG Output Clock Delay After PCG

2.5 + (2.5 × t

) 10 + (2.5 × t

PCGIP

) 12 + (2.5 × t

PCGIP

)ns

PCGIP

Trigger

DTRIG FS

PCG Frame Sync Delay After PCG

2.5 + ((2.5 + D – PH) × t

) 10 + ((2.5 + D – PH) × t

PCGIP

) 12 + ((2.5 + D – PH) × t

PCGIP

)ns

Trigger

PCGOP

D = FSxDIV, PH = FSxPHASE. For more information, refer to the

Output Clock Period 2 × t

– 1 ns

PCGIP

ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Gener-

ators” chapter.

In normal mode, t

PCGOP

(min) = 2 × t

PCGIP

Figure 15. Precision Clock Generator (Direct Pin Routing)

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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_P20–1

(FLAG3–0

)

(AD15–0)

DAI_P20–1

(FLAG3–0

OUT

)

(AD15–0)

FOPW

FIPW

Flags

The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use.

Table 19. Flags

Parameter Min Unit

Timing Requirement

FIPW

Switching Characteristic

FOPW

FLAG3–0 IN Pulse Width 2 × t

FLAG3–0 OUT Pulse Width 2 × t

+ 3 ns

PCLK

– 1 ns

PCLK

Figure 16. Flags

Rev. I | Page 23 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ALE

AD15–8

AD7–0

ALEW

ALERW

RWALE

RRH

RDDRV

DAWH

ADAS

ADAH

VALID ADDRESSVALID ADDRESS

VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID DATA

VALID

DATA

ADRH

DADtDRS

DRH

ALEHZ

NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION.

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space.

Table 20. 8-Bit Memory Read Cycle

K and B Grade Y Grade

Parameter

Timing Requirements

t t t

DRS

DRH

DAD

AD7–0 Data Setup Before RD High 3.3 4.5 ns AD7–0 Data Hold After RD High 0 0 ns AD15–8 Address to AD7–0 Data Valid D + t

Switching Characteristics

ALEW

ADAS

RRH

ALE Pulse Width 2 × t AD15–0 Address Setup Before ALE Deasserted t Delay Between RD Rising Edge to Next

Falling Edge

ALERW

RWALE

ADAH

ALEHZ

RDDRV

ADRH

DAWH

ALE Deasserted to Read Asserted 2 × t Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns AD15–0 Address Hold After ALE Deasserted t ALE Deasserted to AD7–0 Address in High-Z t RD Pulse Width D – 2.0 D – 2.0 ns AD7–0 ALE Address Drive After Read High F + H + t AD15–8 Address Hold After RD High H H ns AD15–8 Address to RD High D + t

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t F = 7 × t

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

(if a hold cycle is specified, else H = 0)

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

Min Max Min Max Unit

– 5.0 D + t

PCLK

– 2.0 2 × t

PCLK

– 2.5 t

PCLK

H + t

– 1.4 H + t

PCLK

– 3.8 2 × t

PCLK

– 2.3 t

PCLK

– 2.3 F + H + t

PCLK

– 4.0 D + t

PCLK

+ 3.0 t

PCLK

– 2.5 ns

PCLK

– 2.3 ns

PCLK

– 5.0 ns

PCLK

– 2.0 ns

– 1.4 ns

– 3.8 ns

+ 3.8 ns

PCLK

– 2.3 ns

PCLK

– 4.0 ns

Figure 17. Read Cycle for 8-Bit Memory Timing

Rev. I | Page 24 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

RWALE

RDDRV

VALID

ADDRESS

VALID DATAVALID DATAVALID ADDRESS

ALE

AD15–0

ADAS

ADAH

ALEHZ

DRStDRH

ALEW

ALERW

RRH

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⬆ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.

Table 21. 16-Bit Memory Read Cycle

Parameter

Timing Requirements

t t

DRS

DRH

AD15–0 Data Setup Before RD High 3.3 4.5 ns AD15–0 Data Hold After RD High 0 0 ns

Switching Characteristics

ALEW

ADAS

ALERW

RRH

ALE Pulse Width 2 × t AD15–0 Address Setup Before ALE Deasserted t ALE Deasserted to Read Asserted 2 × t Delay Between RD Rising Edge to Next Falling

Edge

RWALE

RDDRV

ADAH

ALEHZ1

Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns ALE Address Drive After Read High F + H + t AD15–0 Address Hold After ALE Deasserted t ALE Deasserted to Address/Data15–0 in High-Z t RD Pulse Width D – 2.0 D – 2.0 ns

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t F = 7 × t

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

(if a hold cycle is specified, else H = 0)

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

Min Max Min Max Unit

PCLK

– 2.5 t

PCLK

H + t

PCLK

– 2.3 t

PCLK

K and B Grade Y Grade

– 2.0 2 × t

– 3.8 2 × t

– 1.4 H + t

– 2.3 F + H + t

PCLK

+ 3.0 t

PCLK

– 2.0 ns

PCLK

– 2.5 ns

PCLK

– 3.8 ns

PCLK

– 1.4 ns

PCLK

– 2.3 ns

PCLK

– 2.3 ns

PCLK

+ 3.8 ns

PCLK

Figure 18. Read Cycle for 16-Bit Memory Timing

Rev. I | Page 25 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

AD15-8

VALID

ADDRESS

VALID ADDRESS

ADAS

AD7-0

ALE

ADAH

ADWH

ADWL

VALID DATA

DAWH

WRH

RWALE

VALID

ADDRESS

VALID DATA

ALEW

ALERW

DWS

DWH

VALID ADDRESS

NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space.

Table 22. 8-Bit Memory Write Cycle

K and B Grade Y Grade

Parameter

Switching Characteristics

ALEW

ADAS

ALERW

RWALE

WRH

ADAH

ADWL

ADWH

DWS

AD7–0 Data Hold After WR High H H ns

DWH

DAWH

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t F = 7 × t

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

(if a hold cycle is specified, else H = 0)

PCLK

ALE Pulse Width 2 × t AD15–0 Address Setup Before ALE Deasserted t ALE Deasserted to Write Asserted 2 × t Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns Delay Between WR Rising Edge to Next WR Falling Edge F + H + t AD15–0 Address Hold After ALE Deasserted t WR Pulse Width D – F – 2.0 D – F – 2.0 ns AD15–8 Address to WR Low t AD15–8 Address Hold After WR High H H ns AD7–0 Data Setup Before WR High D – F + t

AD15–8 Address to WR High D – F + t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t

Min Min Unit

– 2.0 2 × t

PCLK

– 2.8 t

PCLK

– 3.8 2 × t

PCLK

– 2.3 F + H + t

PCLK

– 0.5 t

PCLK

– 2.8 t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 2.0 ns

PCLK

– 2.8 ns

PCLK

– 3.8 ns

PCLK

– 2.3 ns

PCLK

– 0.5 ns

PCLK

– 3.5 ns

PCLK

– 4.0 ns

PCLK

– 4.0 ns

PCLK

Figure 19. Write Cycle for 8-Bit Memory Timing

Rev. I | Page 26 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

AD15-0

VALID

ADDRESS

VALID DATA

ADAS

ALE

ADAH

WRH

RWALE

ALEW

ALERW

DWS

DWH

VALID DATA

VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP  0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE WR PUL SES OCCUR BETWEEN ALE C YCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWA RE REFERENCE.

Table 23. 16-Bit Memory Write Cycle

Parameter

Switching Characteristics

ALEW

ADAS

ALERW

RWALE

WRH

ADAH

DWS

DWH

D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × t H = t F = 7 × t t

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

(if a hold cycle is specified, else H = 0)

PCLK

= (peripheral) clock period = 2 × t

PCLK

ALE Pulse Width 2 × t AD15–0 Address Setup Before ALE Deasserted t ALE Deasserted to Write Asserted 2 × t Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns Delay Between WR Rising Edge to Next WR Falling Edge F + H + t AD15–0 Address Hold After ALE Deasserted t WR Pulse Width D – F – 2.0 D – F – 2.0 ns AD15–0 Data Setup Before WR High D – F + t AD15–0 Data Hold After WR High H H ns

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t

CCLK

K and B Grade Y Grade

Min Min Unit

– 2.0 2 × t

PCLK

– 2.5 t

PCLK

– 3.8 2 × t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 t

PCLK

– 4.0 D – F + t

PCLK

– 2.0 ns

PCLK

– 2.5 ns

PCLK

– 3.8 ns

PCLK

– 2.3 ns

PCLK

– 2.3 ns

PCLK

– 4.0 ns

PCLK

Figure 20. Write Cycle for 16-Bit Memory Timing

Rev. I | Page 27 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width.

Table 24. Serial Ports—External Clock

Parameter Min Max Max Unit

Timing Requirements

SFSE

Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

HFSE

Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

SDRE

HDRE

SCLKW

SCLK

Receive Data Setup Before Receive SCLK 2.5 ns

Receive Data Hold After SCLK 2.5 ns SCLK Width (t SCLK Period t

Switching Characteristics

DFSE

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 9.5 11 ns

HOFSE

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 ns

DDTE

HDTE

Referenced to sample edge.

Referenced to drive edge.

Transmit Data Delay After Transmit SCLK 9.5 11 ns

Transmit Data Hold After Transmit SCLK 2 ns

Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

K and B Grade Y Grade

× 4) ÷ 2 – 2 ns

PCLK

× 4 ns

PCLK

Table 25. Serial Ports—Internal Clock

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SFSI

Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 7 ns

HFSI

Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

t t

SDRI

HDRI

Receive Data Setup Before SCLK 7 ns

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

HOFSI

DFSIR

HOFSIR

DDTI

HDTI

SCLKIW

Referenced to the sample edge.

Referenced to drive edge.

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 3 3.5 ns

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 8 9.5 ns

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns

Transmit Data Delay After SCLK 3 4.0 ns

Transmit Data Hold After SCLK –1.0 ns Transmit or Receive SCLK Width 2 × t

– 2 2 × t

PCLK

+ 2 2 × t

PCLK

+ 2 ns

Rev. I | Page 28 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(SCLK)

HOFSIR

HFSI

HDRI

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

HFSI

DDTI

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(SCLK)

HOFSE

HOFSI

HDTI

HFSE

HDTE

DDTE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(SCLK)

HOFSE

HFSE

HDRE

DATA RECEIVE—EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

SCLKIW

DFSIR

SFSI

SDRI

SCLKW

DFSE

SFSE

SDRE

DFSE

SFSE

SFSI

DFSI

SCLKIW

SCLKW

Figure 21. Serial Ports

Rev. I | Page 29 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DRIVE SAMPLE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

DDTE/I

HDTE/I

DDTLFSE

DDTENFS

SFSE/I

DRIVE SAMPLE

LATE EXTERNAL TRANSMIT FS

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

DDTE/I

HDTE/I

DDTLFSE

DDTENFS

SFSE/I

HFSE/I

NOTES: THIS FIGURE REFLECTS CHANGES MADE TO SUPPORT LEFT-JUSTIFIED SAMPLE PAIR MODE. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.

Table 26. Serial Ports—External Late Frame Sync

K and B Grade Y Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTLFSE

DDTENFS

The t

DDTLFSE

Data Delay from Late External Transmit Frame Sync or External Receive FS with MCE = 1, MFD = 0 9 10.5 ns

Data Enable for MCE = 1, MFD = 0 0.5 ns

and t

parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.

DDTENFS

Figure 22. External Late Frame Sync

Rev. I | Page 30 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DRIVE EDGE

DDTIN

DDTEN

DDTTE

DAI_P20–1

(SCLK, INT)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(DATA

CHANNEL A/B)

Table 27. Serial Ports—Enable and Three-State

K and B Grade Y Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTEN

DDTTE

DDTIN

Referenced to drive edge.

Data Enable from External Transmit SCLK 2 ns Data Disable from External Transmit SCLK 7 8.5 ns Data Enable from Internal Transmit SCLK –1 ns

Figure 23. Enable and Three-State

Rev. I | Page 31 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_P20–1

(SERIAL CLOCK)

SAMPLE EDGE

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA)

IPDCLK

IPDCLKW

SISFS

SIHFS

SIHD

SISD

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 28. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 28. IDP

Parameter Min Unit

Timing Requirements

SISFS

SIHFS

SISD

SIHD

IDPCLKW

IDPCLK

The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either

CLKIN or any of the DAI pins.

Frame Sync Setup Before Clock Rising Edge 3 ns Frame Sync Hold After Clock Rising Edge 3 ns Data Setup Before Clock Rising Edge 3 ns Data Hold After Clock Rising Edge 3 ns Clock Width (t Clock Period t

× 4) ÷ 2 – 1 ns

PCLK

× 4 ns

PCLK

Figure 24. IDP Master Timing

Rev. I | Page 32 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DATA

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_CLKEN)

DAI_P20–1

(PDAP_STROBE)

PDSTRB

PDHLDD

PDHD

PDSD

SPCLKEN

HPCLKEN

PDCLK

PDCLKW

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Input Data Port” chapter.

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter Min Unit

Timing Requirements

SPCLKEN

HPCLKEN

PDSD

PDHD

PDCLKW

PDCLK

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns Clock Width (t Clock Period t

Switching Characteristics

PDHLDD

PDSTRB

Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins.

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t PDAP Strobe Pulse Width 2 × t

Note that the most significant 16 bits of external 20-bit PDAP data can be provided through either the parallel port AD15–0 pins or the DAI_P20–5 pins. The remaining 4 bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins.

× 4) ÷ 2 – 3 ns

PCLK

× 4 ns

PCLK

– 1 ns

PCLK

– 1.5 ns

PCLK

Figure 25. PDAP Timing

Rev. I | Page 33 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PWM

OUTPUTS

PWMW

PWMP

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

SRCCLK

SRCCLKW

SRCSFS

SRCHFS

SRCHD

SRCSD

Pulse-Width Modulation Generators

Table 30. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWMP

Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).

PWM Output Pulse Width t

PCLK

PWM Output Period 2 × t

Figure 26. PWM Timing

– 2 (216 – 2) × t

– 1.5 (216 – 1) × t

PCLK

– 2 ns

PCLK

Sample Rate Converter—Serial Input Port

The SRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in

Table 31 are valid at the DAI_P20–1 pins. This feature is not

available on the ADSP-21363 models.

Table 31. SRC, Serial Input Port

Parameter Min Unit

Timing Requirements

SRCSFS

SRCHFS

SRCSD

SRCHD

SRCCLKW

SRCCLK

The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s

input can be either CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge 3 ns Frame Sync Hold After Serial Clock Rising Edge 3 ns SDATA Setup Before Serial Clock Rising Edge 3 ns SDATA Hold After Serial Clock Rising Edge 3 ns Clock Width 36 ns Clock Period 80 ns

Figure 27. SRC Serial Input Port Timing

Rev. I | Page 34 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_P20–1

(SERIAL CLOCK)

SAMPLE EDGE

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA)

SRCCLK

SRCCLKW

SRCSFS

SRCHFS

SRCTDD

SRCTDH

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay

Table 32. SRC, Serial Output Port

Parameter Min Max Max Unit

Timing Requirements

SRCSFS

SRCHFS

Frame Sync Setup Before Serial Clock Rising Edge 3 ns Frame Sync Hold After Serial Clock Rising Edge 3 ns

Switching Characteristics

SRCTDD

SRCTDH

The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be

either CLKIN or any of the DAI pins.

Transmit Data Delay After Serial Clock Falling Edge 10.5 12.5 ns Transmit Data Hold After Serial Clock Falling Edge 2 ns

specification with regard to serial clock. Note that the serial clock rising edge is the sampling edge and the falling edge is the drive edge.

K and B Grade Y Grade

Figure 28. SRC Serial Output Port Timing

Rev. I | Page 35 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

MSB

LEFT/RIGHT CHANNEL

LSB LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

RJD

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as left justified, I 20-, or 24-bits. The following sections provide timing for the transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition.

Table 33. S/PDIF Transmitter Right-Justified Mode

Parameter Nominal Unit

Timing Requirement

RJD

S, or right justified with word widths of 16-, 18-,

FS to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode

16 14 12 8

SCLK SCLK SCLK SCLK

Figure 29. Right-Justified Mode

Rev. I | Page 36 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

I2SD

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

LJD

Figure 30 shows the default I2S-justified mode. The frame sync

is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay.

Table 34. S/PDIF Transmitter I

Parameter Nominal Unit

Timing Requirement

I2SD

S Mode

FS to MSB Delay in I2S Mode 1 SCLK

Figure 30. I2S-Justified Mode

Figure 31 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay.

Table 35. S/PDIF Transmitter Left-Justified Mode

Parameter Nominal Unit

Timing Requirement

LJD

FS to MSB Delay in Left-Justified Mode 0 SCLK

Figure 31. Left-Justified Mode

Rev. I | Page 37 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

SITXCLKW

SITXCLK

SISCLKW

SISCLK

SISFS

SIHFS

SISD

SIHD

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 36. S/PDIF Transmitter Input Data Timing

K Grade Y Grade

Parameter Min Max Min Max Unit

Timing Requirements

SISFS

SIHFS

SISD

SIHD

SITXCLKW

SITXCLK

SISCLKW

SISCLK

The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge 3 3 ns Frame Sync Hold After Serial Clock Rising Edge 3 3 ns Data Setup Before Serial Clock Rising Edge 3 3 ns Data Hold After Serial Clock Rising Edge 3 3 ns Transmit Clock Width 9 9.5 ns Transmit Clock Period 20 20 ns Clock Width 36 36 ns Clock Period 80 80 ns

Figure 32. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock.

Table 37. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit

Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/t Frequency for TxCLK = 256 × Frame Sync 49.2 MHz

SITXCLK

MHz

Frame Rate (FS) 192.0 kHz

Rev. I | Page 38 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DAI_P20–1

(SERIAL CLOCK)

SAMPLE EDGE

DAI_P20–1

(FRAME SYNC)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

SCLKIW

DFSI

HOFSI

DDTI

HDTI

S/PDIF Receiver

The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock.

Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter Min Max Unit

Switching Characteristics

DFSI

HOFSI

DDTI

HDTI

SCLKIW

Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.

Frame Sync Delay After Serial Clock 5 ns Frame Sync Hold After Serial Clock –2 ns Transmit Data Delay After Serial Clock 5 ns Transmit Data Hold After Serial Clock –2 ns Transmit Serial Clock Width 38 ns

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. I | Page 39 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPICHM

SDSCIM

SPICLM

SPICLKM

HDSM

SPITDM

SPICLM

SPICHM

MSB

VALID

LSB VALIDMSB VALID

LSB

LSBMSB

MSB

DDSPIDM

HSPIDM

SSPIDM

LSB VALID

FLAG3–0

(OUTPUT)

SPICLK (CP = 0)

(OUTPUT)

SPICLK (CP = 1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

HDSPIDM

HSPIDM

SSPIDM

DDSPIDM

HDSPIDM

SPI Interface—Master

The processor contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 applies to both ports.

Table 39. SPI Interface Protocol—Master Switching and Timing Specifications

K and B Grade Y Grade

Parameter

Timing Requirements

SSPIDM

HSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2 6.2 ns Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) 8.2 9.5 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns

Switching Characteristics

SPICLKM

SPICHM

SPICLM

DDSPIDM

HDSPIDM

SDSCIM

HDSM

SPITDM

Serial Clock Cycle 8 × t Serial Clock High Period 4 × t Serial Clock Low Period 4 × t SPICLK Edge to Data Out Valid (Data Out Delay Time) 3.0 3.0 ns SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) 8.0 9.5 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × t FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × t Last SPICLK Edge to FLAG3–0IN High 4 × t Sequential Transfer Delay 4 × t

Min Max Min Max Unit

– 2 8 × t

PCLK

– 2 4 × t

PCLK

– 2 4 × t

PCLK

– 2 4 × t

PCLK

– 2.5 4 × t

PCLK

– 2.5 4 × t

PCLK

– 2 4 × t

PCLK

– 1 4 × t

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

– 3.0 ns

PCLK

– 3.0 ns

PCLK

– 2 ns

PCLK

– 1 ns

PCLK

Figure 34. SPI Master Timing

Rev. I | Page 40 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPI Interface—Slave

Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications

K and B Grade Y Grade

Parameter Min Max Max Unit

Timing Requirements

SPICLKS

SPICHS

SPICLS

SDSCO

HDS

SSPIDS

HSPIDS

SDPPW

Switching Characteristics

DSOE

DSDHI

DDSPIDS

HDSPIDS

DSOV

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware

Reference, “Serial Peripheral Interface Port” chapter.

Serial Clock Cycle 4 × t Serial Clock High Period 2 × t Serial Clock Low Period 2 × t

– 2 ns

PCLK

– 2 ns

PCLK

– 2 ns

PCLK

SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

2 × t 2 × t

PCLK

ns ns

ns Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns SPICLK Last Sampling Edge to Data Input Not Valid 2 ns SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

SPIDS Assertion to Data Out Active 0 5 5 ns SPIDS Assertion to Data Out Active (SPI2) 0 8 9 ns SPIDS Deassertion to Data High Impedance 0 5 5.5 ns SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 10 ns SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 11.0 ns SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

5 × t

PCLK

Rev. I | Page 41 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPICHS

SPICLS

SPICLKS

HDS

SDPPW

SDSCO

SPICLS

SPICHS

DSOE

DDSPIDS

DSDHI

HDSPIDS

HSPIDS

SSPIDS

MSB VALID

LSB VALIDMSB VALID

SSPIDS

LSB

MSB

DSDHI

DDSPIDS

DSOV

HSPIDS

SSPIDS

HDSPIDS

LSB VALID

SPIDS

(INPUT)

SPICLK (CP = 0) (INPUT)

SPICLK (CP = 1) (INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

Figure 35. SPI Slave Timing

Rev. I | Page 42 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

STAP

HTAP

DTDO

SSYS

HSYS

DSYS

JTAG Test Access Port and Emulation

Table 41. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

STAP

HTAP

SSYS

HSYS

TRSTW

Switching Characteristics

DTDO

DSYS

System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.

TCK Period t

ns TDI, TMS Setup Before TCK High 5 ns TDI, TMS Hold After TCK High 6 ns System Inputs Setup Before TCK High 7 ns System Inputs Hold After TCK High 18 ns TRST Pulse Width 4 × t

TDO Delay from TCK Low 7 ns System Outputs Delay After TCK Low tCK ÷ 2 + 7 ns

Figure 36. IEEE 1149.1 JTAG Test Access Port

Rev. I | Page 43 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SWEEP (V

DDEXT

) VOLTAGE (V)

0 3.50.5 1.5 2.5

3.11V, +125°C

3.3V, +25°C

3.47V,-45°C

3.11V, +125°C

3.3V, +25°C

3.47V,-45°C

1.0 2.0 3.0

OUTPUT

ȍ

LOAD

30pF

1.5V

INPUT

OUTPUT

1.5V

LOAD CAPACITANCE (pF)

100 250

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISE

FALL

y = 0.049x + 1.5105

y=0.0482x + 1.4604

OUTPUT DRIVE CURRENTS

Figure 37 shows typical I-V characteristics for the output driv-

ers of the processor. The curves represent the current drive capability of the output drivers as a function of output voltage.

) A m

( T N

E R R U C )

( E

C R U O

Figure 37. ADSP-2136x Typical Drive

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 12 on Page 19 through Table 41 on Page 43. These include

output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 38.

Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.

Figure 38. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 40, Figure 41, and Figure 42 may not be linear outside the ranges shown for Typical Output Delay versus Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) versus Load Capacitance.

)

(

E M

I T

L L A F

D N A

I R

Figure 40. Typical Output Rise/Fall Time

(20% to 80%, V

)

(

E M

I T

L L A F

D N A E

I R

DDEXT

= Max)

Figure 39. Voltage Reference Levels for AC Measurements

Rev. I | Page 44 of 56 | July 2012

Figure 41. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

LOAD CAPACITANCE (pF)

0 20050 100 150

y=0.0488 x-1.5923

TJTTΨJTPD×()+=

)

( D

L O H

R O

Y A L E D T U P T U O

Figure 42. Typical Output Delay or Hold versus Load Capacitance

(at Ambient Temperature)

THERMAL CHARACTERISTICS

The processor is rated for performance over the temperature range specified in Operating Conditions on Page 14.

Table 42 through Table 44 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board and thermal via design comply with JEDEC standards JESD51-9 (BGA) and JESD51-5 (LQFP_EP). The junction-to-case measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board.

Industrial applications using the BGA package require thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-9 for printed circuit board thermal ball land and thermal via design information.

Industrial applications using the LQFP_EP package require thermal trace squares and thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-5 for more information.

To determine the junction temperature of the device while on the application PCB, use:

Values of θ

are provided for package comparison and PCB

design considerations when an exposed pad is required. Note that the thermal characteristics values provided in Table 42 through Table 44 are modeled values.

Table 42. Thermal Characteristics for BGA (No Thermal vias in PCB)

Parameter Condition Typical Unit

JMA

JMT

Airflow = 0 m/s 25.40 °C/W Airflow = 1 m/s 21.90 °C/W Airflow = 2 m/s 20.90 °C/W

5.07 °C/W Airflow = 0 m/s 0.140 °C/W Airflow = 1 m/s 0.330 °C/W Airflow = 2 m/s 0.410 °C/W

Table 43. Thermal Characteristics for BGA (Thermal vias in PCB)

Parameter Condition Typical Unit

JMA

JMT

Airflow = 0 m/s 23.40 °C/W Airflow = 1 m/s 20.00 °C/W Airflow = 2 m/s 19.20 °C/W

5.00 °C/W Airflow = 0 m/s 0.130 °C/W Airflow = 1 m/s 0.300 °C/W Airflow = 2 m/s 0.360 °C/W

Table 44. Thermal Characteristics for LQFP_EP (with Exposed Pad Soldered to PCB)

Parameter Condition Typical Unit

JMA

JMT

Airflow = 0 m/s 16.80 °C/W Airflow = 1 m/s 14.20 °C/W Airflow = 2 m/s 13.50 °C/W

7.25 °C/W Airflow = 0 m/s 0.51 °C/W Airflow = 1 m/s 0.72 °C/W Airflow = 2 m/s 0.80 °C/W

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter

is the typical value from Table 42 through Table 44.

= power dissipation. See Estimating Power for the

ADSP-21362 SHARC Processors (EE-277) for more information.

Values of θ

are provided for package comparison and PCB

design considerations.

Rev. I | Page 45 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

144-LEAD LQFP_EP PIN CONFIGURATIONS

The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses.

Table 45. LQFP_EP Pin Assignments

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

DDINT

CLK_CFG0 2 GND 38 GND 74 V CLK_CFG1 3 RD BOOT_CFG0 4 ALE 40 GND 76 V BOOT_CFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113 GND 6 AD14 42 DAI_P11 (SD3A) 78 V V

DDEXT

GND 8 GND 44 DAI_P13 (SCLK3) 80 V V

DDINT

GND 10 AD12 46 DAI_P15 (SD4A) 82 V V

DDINT

GND 12 GND 48 GND 84 V V

DDINT

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123 FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK5) 89 SPICLK 125 GND 18 V V

DDINT

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128 V

DDEXT

GND 22 GND 58 DAI_P20 (SFS5) 94 V V

DDINT

AD6 24 V AD5 25 GND 61 FLAG2 97 GND 133 AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 RESETOUT V

DDINT

GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136 AD3 29 DAI_P7 (SCLK1) 65 V AD2 30 V V

DDEXT

GND 32 V AD1 33 GND 69 V AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142 WR V

DDINT

*The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional. For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias.

DDINT

37 V

39 V

DDEXT

DDINT

73 GND 109

DDINT

110

75 GND 111

DDINT

112

114

7 AD13 43 DAI_P12 (SD3B) 79 GND 115

116

118

120

11 V

DDEXT

DDINT

DDEXT

45 DAI_P14 (SFS3) 81 GND 117

DDINT

47 V

DDINT

83 GND 119

DDINT

13 AD11 49 GND 85 RESET 121

122

124

DDINT

54 V

DDINT

90 MISO 126

19 GND 55 GND 91 MOSI 127

21 DAI_P3 (SCLK0) 57 V

23 V

DDEXT

DDINT

59 GND 95 A 60 V

DDEXT

DDINT

93 V

96 A

DDINT

DDEXT

vdd

vss

129 130 131 132

134

27 DAI_P5 (SD1A) 63 V

DDINT

66 GND 102 TRST 138

31 GND 67 V

DDINT

68 GND 104 TMS 140

35 DAI_P9 (SD2A) 71 V 36 V

DDINT

72 V

DDINT

99 EMU 135

101 TDI 137

103 TCK 139

105 GND 141

107 XTAL 143 108 V

DDEXT

144

GND 145*

Rev. I | Page 46 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

LEAD 1

LEAD 36

LEAD 108

LEAD 73

LEAD 144 LEAD 109

LEAD 37 LEAD 72

LEAD 1 INDICATOR

ADSP-2136x

144-LEAD LQFP_EP

TOP VIEW

LEAD 108

LEAD 73

LEAD 1

LEAD 36

LEAD 109 LEAD 144

LEAD 72 LEAD 37

LEAD 1 INDICATOR

GND PAD

(LEAD 145)

ADSP-2136x

144-LEAD LQFP_EP

BOTTOM VIEW

Figure 43 shows the top view of the 144-lead LQFP_EP pin con-

figuration. Figure 44 shows the bottom view of the 144-lead LQFP_EP lead configuration.

Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View)

Figure 44. 144-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. I | Page 47 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

136-BALL BGA PIN CONFIGURATIONS

The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses.

Table 46. BGA Pin Assignments

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

CLK_CFG0 A01 CLK_CFG1 B01 BOOT_CFG1 C01 V

DDINT

XTAL A02 GND B02 BOOT_CFG0 C02 GND D02 TMS A03 V

DDEXT

B03 GND C03 GND D04 TCK A04 CLKIN B04 GND C12 GND D05 TDI A05 TRST RESETOUT TDO A07 A EMU

A06 A

A08 V

VSS

VDD

DDEXT

B05 GND C13 GND D06

B06 V

DDINT

C14 GND D09 B07 GND D10 B08 GND D11

MOSI A09 SPICLK B09 GND D13 MISO A10 RESET SPIDS V

DDINT

A11 V

DDINT

A12 GND B12

B10 V B11

DDINT

GND A13 GND B13 GND A14 GND B14 V

DDINT

GND E02 FLAG0 F02 V GND E04 GND F04 V

E01 FLAG1 F01 AD7 G01 AD6 H01

DDINT

DDEXT

G02 V

DDEXT

G13 DAI_P18 (SD5B) H13

GND E05 GND F05 DAI_P19 (SCLK5) G14 DAI_P17 (SD5A) H14 GND E06 GND F06 GND E09 GND F09 GND E10 GND F10 GND E11 GND F11 GND E13 FLAG2 F13 FLAG3 E14 DAI_P20 (SFS5) F14

D01

D14

H02

Rev. I | Page 48 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 46. BGA Pin Assignments (Continued)

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

AD5 J01 AD3 K01 AD2 L01 AD0 M01 AD4 J02 V

DDINT

GND J04 GND K04 GND L04 GND M03 GND J05 GND K05 GND L05 GND M12 GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13 GND J09 GND K09 GND L09 DAI_P13 (SCLK3) M14 GND J10 GND K10 GND L10 GND J11 GND K11 GND L11 V

DDINT

J13 GND K13 GND L13 DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS3) L14 AD15 N01 AD14 P01 ALE N02 AD13 P02 RD V

DDINT

DDEXT

N03 AD12 P03

N04 AD11 P04

N05 AD10 P05 AD8 N06 AD9 P06 V

DDINT

N07 DAI_P1 (SD0A) P07 DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08 V

DDEXT

N09 DAI_P5 (SD1A) P09 DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10 V

DDINT

N11 DAI_P7 (SCLK1) P11

N12 DAI_P8 (SFS1) P12 GND N13 DAI_P9 (SD2A) P13 DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

K02 AD1 L02 WR M02

Figure 45 and Figure 46 show BGA pin assignments from the

bottom and top, respectively.

Note: Use the center block of ground pins to provide thermal pathways to your printed circuit board’s ground plane.

Rev. I | Page 49 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

VSS

DDINT

DDEXT

I/O SIGNALS

VDD

GND

KEY

12345678910111214 13

VSS

DDINT

DDEXT

I/O SIGNALS

VDD

GND

KEY

123456789101112 1413

Figure 45. BGA Pin Assignments (Bottom View, Summary)

Figure 46. BGA Pin Assignments (Top View, Summary)

Rev. I | Page 50 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD

0.27

0.22

0.17

0.75

0.60

0.45

0.50 BSC

LEAD PITCH

20.20

20.00 SQ

19.80

22.20

22.00 SQ

21.80

EXPOSED*

PAD

10873108

144

109

144

109

PIN 1

1.60 MAX

SEATING

PLANE

EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND

DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED.

8.80 SQ

0.15

0.10

0.05

0.08

COPLANARITY

0.20

0.15

0.09

1.45

1.40

1.35

7°

3.5° 0°

VIEW A

ROTATED 90° CCW

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

VIEW A

PACKAGE DIMENSIONS

The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages.

For information relating to the exposed pad on the SW-144-1 package, see the table endnote on Page 46.

Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1]

(SW-144-1)

Dimensions shown in millimeters

Rev. I | Page 51 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

0.25 MIN

0.50

0.45

0.40

1.31

1.21

1.10

1.70 MAX

A B C D E F G

K L M

131411

876

N P

12.10

12.00 SQ

11.90

10.40

BSC SQ

COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1

WITH EXCEPTION TO BALL DIAMETER.

COPLANARITY

0.12

BALL DIAMETER

0.80

BSC

DETAIL A

A1 BALL CORNER

A1 BALL

CORNER

DETAIL A

BOTTOM VIEW

TOP VIEW

SEATING

PLANE

Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-136-1)

Dimensions shown in millimeters

SURFACE-MOUNT DESIGN

Table 47 is provided as an aid to PCB design. For industry stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern Standard.

Table 47. BGA Data for Use with Surface-Mount Design

Package Solder Mask

Package Package Ball Attach Type

136-Ball CSP_BGA (BC-136-1) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter

Opening Package Ball Pad Size

Rev. I | Page 52 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

AUTOMOTIVE PRODUCTS

Some ADSP-2136x models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models.

Table 48. Automotive Products

The automotive grade products shown in Table 48 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant.

Model Notes

AD21362WBBCZ1xx

AD21362WBSWZ1xx

AD21362WYSWZ2xx

Temperature

Range

–40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

–40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

–40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

Instruction Rate

On-Chip SRAM ROM Package Description

Package Option

AD21363WBBCZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21363WBSWZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21363WYSWZ2xx –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21364WBBCZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

AD21364WBSWZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21364WYSWZ2xx –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

AD21365WBSWZ1xxA

AD21365WBSWZ1xxF

AD21365WYSWZ2xxA

AD21366WBBCZ1xxA

AD21366WBSWZ1xxA

AD21366WYSWZ2xxA

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ)

specification which is the only temperature specification.

License from DTLA required for these products.

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.

3, 4

–40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

–40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

–40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

–40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

–40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

Rev. I | Page 53 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ORDERING GUIDE

Model1

ADSP-21362BBCZ-1AA ADSP-21362BSWZ-1AA ADSP-21362YSWZ-2AA

Notes

Temperature

Range

–40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

Instruction Rate

On-Chip SRAM ROM

Package Description

Package Option

ADSP-21363KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21363YSWZ-2AA

–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21364KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21364BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364YSWZ-2AA –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21365BBCZ-1AA ADSP-21365BSWZ-1AA ADSP-21365YSWZ-2AA ADSP-21365YSWZ-2CA ADSP-21366KBC-1AA ADSP-21366KBCZ-1AR ADSP-21366KBCZ-1AA ADSP-21366KSWZ-1AA ADSP-21366BBC–1AA ADSP-21366BBCZ-1AA ADSP-21366BSWZ-1AA ADSP-21366YSWZ-2AA

Z = RoHS compliant part.

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ)

specification which is the only temperature specification.

License from DTLA required for these products.

License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

R = Tape and reel.

3, 4, 5

4, 5

4, 5, 6

4, 5

–40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

–40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1

0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1

Rev. I | Page 54 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. I | Page 55 of 56 | July 2012

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

D06359-0-7/12(I)

Rev. I | Page 56 of 56 | July 2012

Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

DEDICATED AUDIO COMPONENTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SHARC FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Data Register File

Context Switch

Universal Registers

Timer

Single-Cycle Fetch of Instruction and Four Operands

Instruction Cache

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

On-Chip Memory

On-Chip Memory Bandwidth

ROM-Based Security

FAMILY PERIPHERAL ARCHITECTURE

Parallel Port

Serial Peripheral (Compatible) Interface

Pulse-Width Modulation

Digital Audio Interface (DAI)

Serial Ports

S/PDIF-Compatible Digital Audio Receiver/Transmitter

Digital Transmission Content Protection (DTCP)

Memory-to-Memory (MTM)

Synchronous/Asynchronous Sample Rate Converter (SRC)

Input Data Port (IDP)

Precision Clock Generator (PCG)

Peripheral Timers

I/O PROCESSOR FEATURES

DMA Controller

SYSTEM DESIGN

Program Booting

Phase-Locked Loop

Power Supplies

Target Board JTAG Emulator Connector

DEVELOPMENT TOOLS

Designing an Emulator-Compatible DSP Board (Target)

Evaluation Kit

ADDITIONAL INFORMATION

RELATED SIGNAL CHAINS

PIN FUNCTION DESCRIPTIONS

SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PACKAGE INFORMATION

ESD CAUTION

TIMING SPECIFICATIONS

MAXIMUM POWER DISSIPATION

ABSOLUTE MAXIMUM RATINGS

Core Clock Requirements

Voltage Controlled Oscillator

Power-Up Sequencing

Clock Input

Clock Signals

RESET

Interrupts

Core Timer

Timer PWM_OUT Cycle Timing

Timer WDTH_CAP Timing

DAI Pin to Pin Direct Routing

Precision Clock Generator (Direct Pin Routing)

Flags

Memory Read—Parallel Port

Memory Write—Parallel Port

Serial Ports

Input Data Port (IDP)

Parallel Data Acquisition Port (PDAP)

Pulse-Width Modulation Generators

Sample Rate Converter—Serial Input Port

Sample Rate Converter—Serial Output Port

S/PDIF Transmitter

S/PDIF Transmitter-Serial Input Waveforms