ANALOG DEVICES ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 Service Manual
SHARC Processors
Internal Memory I/F
Block 0
RAM/ROM
B0D
64-BIT
Instruction
Cache
5 stage
Sequencer
PEx PEy
PMD 64-BIT
Core Bus
Cross Bar
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DAG1/2 Timer
IOD BUS
MTM/
DTCP
PERIPHERAL BUS
32-BIT
Internal Memory
DMD 64-BIT
PERIPHERAL BUS
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DAI Peripherals
Peripherals
SIMD Core
S
Core
Flags
SPI
PWM
3
-
0
PP
PP Pin MUX
PDAP/
IDP7-0
ASRC
3
-
0
TIMER
2-0
CORE
FLAGS
S/PDIF
Tx/Rx
PCG
A-B
SPI B
SPORT
5
-
0
DAI Routing/Pins
IOD 32-BIT
FLAGx/IRQx/
TMREXP
JTAG
PMD 64-BIT
DMD 64-BIT
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bits of on-chip SRAM
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with up to 333 MHz
core instruction rate with unique audiocentric peripherals
such as the digital applications interface, S/PDIF transceiver, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 54.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
8 channels of asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 136-ball CSP_BGA and 144-lead LQFP_EP
packages
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Figure 1. Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2012 All rights reserved.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components .................................... 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ........................................... 8
System Design ...................................................... 8
Development Tools ............................................... 9
Additional Information ........................................ 10
Related Signal Chains .......................................... 10
Pin Function Descriptions ....................................... 11
Specifications ........................................................ 14
Operating Conditions .......................................... 14
Electrical Characteristics ....................................... 14
Package Information ........................................... 15
REVISION HISTORY
7/12—Revision H to Revision I
Revised PLL Divider input in Core Clock and System Clock
Relationship to CLKIN .............................................16
Replaced the timing diagram Write Cycle for 16-Bit Memory
Timing ................................................................. 27
Changed the t
External Clock ....................................................... 28
(SCLK Width) parameter in Serial Ports—
SCLKW
ESD Caution ...................................................... 15
Maximum Power Dissipation ................................. 15
Absolute Maximum Ratings ................................... 15
Timing Specifications ........................................... 15
Output Drive Currents ......................................... 44
Test Conditions .................................................. 44
Capacitive Loading .............................................. 44
Thermal Characteristics ........................................ 45
144-Lead LQFP_EP Pin Configurations ....................... 46
136-Ball BGA Pin Configurations ............................... 48
Package Dimensions ............................................... 51
Surface-Mount Design .......................................... 52
Automotive Products .............................................. 53
Ordering Guide ..................................................... 54
Rev. I | Page 2 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
GENERAL DESCRIPTION
The ADSP-2136x SHARC® processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices, Inc., Super
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Harvard Architecture. The processor is source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2136x are
32-/40-bit floating-point processors optimized for high
performance automotive audio applications. They contain a
large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface
(DAI).
As shown in the functional block diagram on Page 1, the
ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors
on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two
GFLOPS running at 333 MHz.
Table 1. Benchmarks (at 333 MHz)
Speed
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/x) 10.5 ns
Inverse Square Root 16.3 ns
1
Assumes two files in multichannel SIMD mode.
1
1
(at 333 MHz)
1.5 ns
6.0 ns
13.5 ns
23.9 ns
Table 2. ADSP-2136x Family Features
Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366
RAM
ROM
Audio Decoders in ROM
Pulse-Width Modulation Yes Yes Yes Yes Yes
S/PDIF Yes No Yes Yes Yes
2
DTCP
SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB
1
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,
speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system
configurations. Please visit www.analog.com for complete information.
2
The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices
sales office for more information.
1
3M bit
4M bit
No No No Yes Yes
Ye s N o N o Ye s N o
3M bit
4M bit
3M bit
4M bit
3M bit
4M bit
3M bit
4M bit
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2136x processors. The core clock domain contains
the following features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• One periodic interval timer with pinout
•On-chip SRAM (3M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user breakpoints, which allow flexible exception handling.
Rev. I | Page 3 of 56 | July 2012
The diagram on Page 1 also shows the following architectural
features:
• I/O processor that handles 32-bit DMA for the peripherals
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins
• 8-bit or 16-bit parallel port that supports interfaces to offchip memory peripherals
• Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, 8-channel asynchronous sample rate
converter, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU)
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S
SIMD Core
CACHEINTERRUPT
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 32
DM ADDRESS 32
DM DATA 64
PM DATA 64
DAG1
16x32
MRF
80-BIT
ALU
MULTIPLIER
SHIFTER
RF
Rx/Fx
PEx
16x40-BIT
JTAG
DMD/PMD 64
PM DATA 48
ASTATx
STYKx
ASTATy
STYKy
TIMER
RF
Sx/SFx
PEy
16x40-BIT
MRB
80-BIT
MSB
80-BIT
MSF
80-BIT
FLAG
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
DAG2
16x32
ALU
MULTIPLIER
SHIFTER
DATA
SWAP
PM ADDRESS 24
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2136x is code-compatible at the assembly level with
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x
and ADSP-2116x SIMD SHARC processors, as shown in
Figure 2 and detailed in the following sections.
SIMD Computational Engine
The processor contains two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal
processing algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or
the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit,
single-precision floating-point, 40-bit extended-precision
floating-point, and 32-bit fixed-point data formats.
Figure 2. SHARC Core Block Diagram
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Data Register File
Each processing element contains a general-purpose data register file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) files, combined
with the ADSP-2136x enhanced Harvard architecture, allow
unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and
in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
The universal registers are general purpose registers. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data bus. These
registers contain hardware to handle the data width difference.
Timer
A core timer that can generate periodic software interrupts. The
core timer can be configured to use FLAG3 as a timer expired
signal.
Single-Cycle Fetch of Instruction and Four Operands
The processor features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 2). With the its separate program and data memory
buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.
Instruction Cache
The processor includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
The processor’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
processor can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single
instruction.
On-Chip Memory
The processor contains 3M bits of internal SRAM and 4M bits
of internal ROM. Each block can be configured for different
combinations of code and data storage (see Table 3). Each
memory block supports single-cycle, independent accesses by
the core processor and I/O processor. The processor’s memory
architecture, in combination with its separate on-chip buses,
allows two data transfers from the core and one from the I/O
processor, in a single cycle.
The SRAM can be configured as a maximum of 96K words of
32-bit data, 192K words of 16-bit data, 64K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to 3M bits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage
format is supported that effectively doubles the amount of data
that can be stored on-chip. Conversion between the 32-bit
floating-point and 16-bit floating-point formats is performed in
a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one
block stores data using the DM bus for transfers, and the other
block stores instructions and data using the PM bus for
transfers.
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows three accesses at the
same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses
(2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK).
ROM-Based Security
The processor has a ROM security feature that provides hardware support for securing user software code by preventing
unauthorized reading from the internal code. When using this
feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the
processor is not freely accessible via the JTAG port. Instead, a
unique 64-bit key, which must be scanned in through the JTAG
Rev. I | Page 5 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 3. ADSP-2136x Internal Memory Space
IOP Registers 0x0000 0000–0003 FFFF
Extended Precision Normal or
Long Word (64 Bits)
Block 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
Block 0 SRAM
0x0004 C000–0x0004 FFFF
Block 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
Block 1 SRAM
0x0005 C000–0x0005 FFFF
Block 2 SRAM
0x0006 0000–0x0006 1FFF
Reserved
0x0006 2000–0x0006 FFFF
Block 3 SRAM
0x0007 0000–0x0007 1FFF
Reserved
0x0007 2000–0x0007 FFFF
Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM
0x0008 0000–0x0008 AAA9
Block 0 SRAM
0x0009 0000–0x0009 5554
Block 1 ROM
0x000A 0000–0x000A AAA9
Block 1 SRAM
0x000B 0000–0x000B 5554
Block 2 SRAM
0x000C 0000–0x000C 2AA9
Block 3 SRAM
0x000E 0000–0x000E 2AA9
Block 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Block 0 SRAM
0x0009 8000–0x0009 FFFF
Block 1 ROM
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
Block 1 SRAM
0x000B 8000–0x000B FFFF
Block 2 SRAM
0x000C 0000–0x000C 3FFF
Reserved
0x000C 4000–0x000D FFFF
Block 3 SRAM
0x000E 0000–0x000E 3FFF
Reserved
0x000E 4000–0x000F FFFF
Block 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
Block 0 SRAM
0x0013 0000–0x0013 FFFF
Block 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
Block 1 SRAM
0x0017 0000–0x0017 FFFF
Block 2 SRAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
Block 3 SRAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
or test access port, is assigned to each customer. The device
ignores a wrong key. Emulation features and external boot
modes are only available after the correct key is scanned.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-2136x family contains a rich set of peripherals that
support a wide variety of applications, including high quality
audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, monitor control,
imaging, and other applications.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8-bit or
16-bit, the maximum data transfer rate is 55 Mbps.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD
(address latch enable) pins are the control pins for the
parallel port.
, WR, and ALE
Serial Peripheral (Compatible) Interface
The processors contain two serial peripheral interface ports
(SPIs). The SPI is an industry-standard synchronous serial link,
enabling the processor’s SPI-compatible port to communicate
with other SPI-compatible devices. The SPI consists of two data
pins, one device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes and can operate at a maximum baud rate of f
PCLK
/4.
The SPI port can operate in a multimaster environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The ADSP-2136x SPIcompatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
Pulse-Width Modulation
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
Rev. I | Page 6 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM
waveforms).
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode,
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
about the midpoint of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in 3-phase PWM inverters.
Digital Audio Interface (DAI)
The digital audio interface (DAI) provides the ability to connect
various peripherals to any of the DSP’s DAI pins (DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU, shown in Figure 1).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the
DAI-associated peripherals for a wider variety of applications by
using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and
three timers. The IDP provides an additional input path to the
ADSP-2136x core, configurable as either eight channels of I
2
S
serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has
its own DMA channel that is independent from the processor’s
serial ports.
Serial Ports
The processor features six synchronous serial ports that provide
an inexpensive interface to a wide variety of digital and mixedsignal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made
up of two data lines, a clock, and a frame sync. The data lines
can be programmed to either transmit or receive and each data
line has a dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in four modes:
• Standard DSP serial mode
•Multichannel (TDM) mode
2
S mode
•I
• Left-justified sample pair mode
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left-justified, I
2
S, or right-justified with
word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the signal routing unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.
Digital Transmission Content Protection (DTCP)
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) is protected by this copy protection system.
This feature is available on the ADSP-21362 and
ADSP-21365 processors only. Licensing through DTLA is
required for these products. Visit www.dtcp.com for more
information.
Memory-to-Memory (MTM)
If the DTCP module is not used, the memory-to-memory DMA
module allows internal memory copies for a standard DMA.
Synchronous/Asynchronous Sample Rate Converter (SRC)
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 140 dB
SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.
The S/PDIF and SRC are not available on the ADSP-21363
models.
Input Data Port (IDP)
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
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audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right
pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit
2
S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
I
right-justified formats.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of two units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A and B, are identical in functionality and operate independently of each other.
The two signals generated by each unit are normally used as a
serial bit clock/frame sync pair.
Peripheral Timers
The following three general-purpose timers can generate periodic interrupts and be independently set to operate in one of
three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables all three general-purpose timers
independently.
I/O PROCESSOR FEATURES
The processor’s I/O provides many channels of DMA and controls the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controllers allow data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the parallel port (PP). See Table 4.
Table 4. DMA Channels
Peripheral ADSP-2136x
SPORTs 12
IDP/PDAP 8
SPI 2
MTM/DTCP 2
Parallel Port 1
Total DMA Channels 25
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the parallel port, an SPI master, an
SPI slave, or an internal boot. Booting is determined by the boot
configuration (BOOT_CFG1–0) pins in Table 5. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Table 5. Boot Mode Selection
BOOT_CFG1–0 Booting Mode
00 SPI Slave Boot
01 SPI Master Boot
10 Parallel Port Boot via EPROM
11 No booting occurs. Processor executes
from internal ROM after reset.
Phase-Locked Loop
The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the
CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and
6:1. After booting, numerous other ratios can be selected via
software control.
The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
Power Supplies
The processor has a separate power supply connection for the
internal (V
power supplies. The internal and analog supplies must meet the
1.2 V requirement for K, B, and Y grade models, and the 1.0 V
requirement for Y models. (For information on the temperature
ranges offered for this product, see Operating Conditions on
Page 14, Package Information on Page 15, and Ordering Guide
on Page 54.) The external supply must meet the 3.3 V require-
ment. All external supply pins must be connected to the same
power supply.
Note that the analog supply pin (A
internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the
A
pin. Place the filter components as close as possible to the
VDD
A
VDD/AVSS
recommended ferrite chip is the muRata BLM18AG102SN1D.)
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
to connect the bypass capacitors to the analog power (A
and ground (A
specified in Figure 3 are inputs to the processor and not the analog ground plane on the board—the A
directly to digital ground (GND) at the chip.
DDINT
), external (V
), and analog (A
DDEXT
VDD
VDD/AVSS
) powers the processor’s
pins. For an example circuit, see Figure 3. (A
and GND. Use wide traces
DDINT
) pins. Note that the A
VSS
and A
VDD
pin should connect
VSS
VSS
pins
VDD
)
)
Rev. I | Page 8 of 56 | July 2012
HIGH-Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO A
VDD
AND A
VSS
PINS
A
VDD
A
VSS
100nF 10nF 1nF
ADSP-213xx
V
DDINT
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Figure 3. Analog Power (A
Target Board JTAG Emulator Connector
Analog Devices’ DSP Tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processor to
monitor and control the target board processor during emulation. Analog Devices’ DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the
emulator does not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, refer to the
appropriate emulator user’s guide.
DEVELOPMENT TOOLS
The processor is supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2136x processors.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy-to-use assembler (based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a
cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
®
software and hardware development tools,
) Filter Circuit
VDD
®
devel-
efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Through debugging both C/C++ and assembly programs with
the VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP
software development. Its dialog boxes and property pages let
programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK is designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with a
drag of the mouse and examine runtime stack and heap usage.
The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the
graphical and textual environments.
Rev. I | Page 9 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG
interface. (The emulator does not affect target system loading or
timing.) The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, refer to the Analog Devices JTAG Emulation Technical
Reference (EE-68) on the Analog Devices website, www.ana-
log.com. (Perform a site search on “EE-68.”) This document is
updated regularly to keep pace with improvements to emulator
support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
platform includes an evaluation board along with an evaluation
suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also
included are sample application programs, a power supply, and
a USB cable. All evaluation versions of the software tools are
limited for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices’ JTAG
emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
processor’s architecture and functionality. For detailed information on the ADSP-2136x family core architecture and
instruction set, refer to the ADSP-2136x SHARC Processor
Hardware Reference and the ADSP-2136x SHARC Processor
Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Circuits from the Lab
(http://www.analog.com/signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
TM
site
Rev. I | Page 10 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
PIN FUNCTION DESCRIPTIONS
The processor’s pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS and TDI).
Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST
inputs to V
or GND, except for the following:
DDEXT
DAI_Px, SPICLK, MISO, MOSI, EMU
). Tie or pull unused
, TMS, TRST, TDI, and
AD15–0. Note: These pins have pull-up resistors.
Table 6. Pin Descriptions
State During and
Pin Type
AD15–0 I/O/T
(pu)
RD
WR
ALE O
FLAG[0]/IRQ0/SPI
FLG[0]
FLAG[1]/IRQ1
FLG[1]
FLAG[2]/IRQ2
FLG[2]
FLAG[3]/TMREXP/
SPIFLG[3]
DAI_P20–1 I/O/T
The following symbols appear in the Type column of Tab le 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
O
(pu)
O
(pu)
(pd)
I/O FLAG[0] INPUT FLAG0/Interrupt Request0/SPI0 Slave Select.
/SPI
I/O FLAG[1] INPUT FLAG1/Interrupt Request1/SPI1 Slave Select.
/SPI
I/O FLAG[2] INPUT FLAG2/Interrupt Request 2/SPI2 Slave Select.
I/O FLAG[3] INPUT FLAG3/Timer Expired/SPI3 Slave Select.
(pu)
After Reset Function
Three-state with
pull-up enabled
Three-state, driven
1
high
Three-state, driven
1
high
Three-state, driven
1
low
Three-state with
programmable
pull-up
Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA
unit output addresses and data for peripherals on these multiplexed pins. The multiplex
state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit
mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin
operation, refer to the ADSP-2136x SHARC Processor Hardware Reference.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16
external address bits, ADDR23–8; ALE is used in conjunction with an external latch to
retain the values of the ADDR23–8.
For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x
SHARC Processor Hardware Reference.
Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pull-up resistor.
Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR
Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a
new address on the parallel port address pins. On reset, ALE is active high. However, it
can be reconfigured using software to be active low. When AD15–0 are flags, this pin
remains deasserted. ALE has a 20 kΩ internal pull-down resistor.
Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The
SRU configuration registers define the combination of on-chip peripheral inputs or
outputs connected to the pin and to the pin’s output enable. The configuration registers
of these peripherals then determine the exact behavior of the pin. Any input or output
signal present in the SRU can be routed to any of these pins. The SRU provides the
connection from the serial ports, input data port, precision clock generators and timers,
sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ
pull-up resistors that are enabled on reset. These pull-ups can be disabled using the
DAI_PIN_PULLUP register.
has a 22.5 kΩ internal pull-up resistor.
Rev. I | Page 11 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 6. Pin Descriptions (Continued)
State During and
Pin Type
SPICLK I/O
(pu)
SPIDS
MOSI I/O (O/D)
MISO I/O (O/D)
CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It
XTAL O Output only
CLK_CFG1–0 I Input only Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the
The following symbols appear in the Type column of Tab le 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the
(pu)
(pu)
After Reset Function
Three-state with
pull-up enabled,
driven high in SPImaster boot mode
Three-state with
pull-up enabled,
driven low in SPImaster boot mode
Three-state with
pull-up enabled
2
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the
rate at which data is transferred. The master can transmit data at a varie ty of bau d rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data
transfers, only for the length of the transferred word. Slave devices ignore the serial clock
if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in
the data driven on the MISO and MOSI lines. The data is always shifted out on one clock
edge and sampled on the opposite edge of the clock. Clock polarity and clock phase
relative to data are programmable into the SPICTL control register and define the transfer
format. SPICLK has a 22.5 kΩ internal pull-up resistor.
processor as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the processor’s
signal can be driven by a slave device to signal to the processor (as SPI master)
SPIDS
that an error has occurred, as some other device is also trying to be the master device. If
asserted low when the device is in master mode, it is considered a multimaster error. For
a single-master, multiple-slave configuration where flag pins are used, this pin must be
tied or pulled high to V
action, any of the master processor’s flag pins can be used to drive the SPIDS signal on
the SPI slave device.
SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the processor is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the
master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pullup resistor.
SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the processor is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data.
In an SPI interconnection, the data is shifted out from the MISO output pin of the slave
and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up
resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting
Bit 5 (DMISO) of the SPICTL register equal to 1.
configures the ADSP-2136x to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external
clock oscillator. The core is clocked either by the PLL output or this clock input depending
on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated
below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external cr ystal.
operating frequency can be changed by programming the PLL multiplier and divider in
the PMCTL register at any time after the core comes out of reset. The allowed values are:
00 = 6:1
01 = 32:1
10 = 16:1
11 = reserved.
on the master device. For processor to processor SPI inter-
DDEXT
Rev. I | Page 12 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 6. Pin Descriptions (Continued)
State During and
Pin Type
BOOT_CFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.
RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device.
RESET
I/A Input only Processor Reset. Resets the ADSP-2136 x to a k nown state. Upon deass ertion, there is a
TCK I Input only
TMS I/S
(pu)
TDI I/S
(pu)
TDO O Three-state
TRST
I/A
(pu)
EMU
O (O/D)
(pu)
V
DDINT
V
DDEXT
A
VDD
A
VSS
P Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the
P I/O Power Supply. Nominally +3.3 V dc.
P Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for
G Analog Power Supply Return.
GND G Power Supply Return.
The following symbols appear in the Type column of Tab le 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pull-up disabled.
4
Three-state is a three-state driver with pull-up disabled.
After Reset Function
The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot
mode, refer to the ADSP-2136x SHARC Processor Hardware Reference.
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
Three-state with
pull-up enabled
Three-state with
pull-up enabled
4
Three-state with
pull-up enabled
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-2136x. TRST
internal pull-up resistor.
Three-state with
pull-up enabled
Emulation Status. Must be connected to the processor’s JTAG emulators target board
connector only. EMU
Y grade models, and supplies the processor’s core.
the Y grade models, and supplies the processor’s internal PLL (clock generator). This pin
has the same specifications as V
more information, see Power Supplies on Page 8.
has a 22.5 kΩ internal pull-up resistor.
, except that added filtering circuitry is required. For
DDINT
has a 22.5 kΩ
Rev. I | Page 13 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPECIFICATIONS
Specifications are subject to change without notice.
OPERATING CONDITIONS
K Grade B Grade Y Grade
Parameter Description Min Max Min Max Min Max Unit
V
DDINT
A
VDD
V
DDEXT
1
V
IH
1
V
IL
V
IH_CLKIN
V
IL_CLKIN
3, 4
T
J
3, 4
T
J
1
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST.
2
Applies to input pin CLKIN.
3
See Thermal Characteristics on Page 45 for information on thermal specifications.
4
See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.
Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V
Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V
High Level Input Voltage @ V
Low Level Input Voltage @ V
2
High Level Input Voltage @ V
Low Level Input Voltage @ V
= Max 2.0 V
DDEXT
= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V
DDEXT
= Max 1.74 V
DDEXT
= Min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 1.74 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 1.74 V
DDEXT
DDEXT
DDEXT
Junction Temperature 136-Ball CSP_BGA 0 +110 –40 +125 –40 +125 °C
Junction Temperature 144-Lead LQFP_EP 0 +110 –40 +125 –40 +125 °C
+ 0.5 V
+ 0.5 V
ELECTRICAL CHARACTERISTICS
Parameter Description Test Conditions Min Max Unit
1
V
OH
1
V
OL
3, 4
I
IH
3
I
IL
4
I
ILPU
5, 6
I
OZH
5
I
OZL
6
I
OZLPU
7, 8
I
DD-INTYP
9
I
AVD D
10, 11
C
IN
1
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL.
2
See Output Drive Currents on Page 44 for typical drive current capabilities.
3
Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN.
4
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
5
Applies to three-stateable pins: FLAG3–0.
6
Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI.
7
Typical internal current data reflects nominal operating conditions.
8
See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.
9
Characterized, but not tested.
10
Applies to all signal pins.
11
Guaranteed, but not tested.
High Level Output Voltage @ V
Low Level Output Voltage @ V
High Level Input Current @ V
Low Level Input Current @ V
Low Level Input Current Pull-Up @ V
Three-State Leakage Current @ V
Three-State Leakage Current @ V
Three-State Leakage Current Pull-Up @ V
Supply Current (Internal) t
Supply Current (Analog) A
Input Capacitance f
CCLK
VDD
IN
= Min, IOH = –1.0 mA
DDEXT
= Min, IOL = 1.0 mA
DDEXT
= Max, VIN = V
DDEXT
= Max, VIN = 0 V 10 μA
DDEXT
= Max, VIN = 0 V 200 μA
DDEXT
= Max, VIN = V
DDEXT
= Max, VIN = 0 V 10 μA
DDEXT
= Max, VIN = 0 V 200 μA
DDEXT
= Min, V
= Nom 800 mA
DDINT
= Max 10 mA
= 1 MHz, T
= 25°C, VIN = 1.2 V 4.7 pF
CASE
2
2
Max 10 μA
DDEXT
Max 10 μA
DDEXT
2.4 V
0.4 V
Rev. I | Page 14 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
tppZ-cc
S
ADSP-2136x
a
#yyww country_of_origin
vvvvvv.x n.n
ESD
(electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
PACKAGE INFORMATION
The information presented in Figure 4 provides details about
the package branding for the ADSP-2136x processor. For a
complete listing of product availability, see Ordering Guide on
Page 54.
Figure 4. Typical Package Brand
Table 7. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Designation
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code
ESD CAUTION
Table 8. Absolute Maximum Ratings
Parameter Rating
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage –0.5 V to +3.8 V
Output Voltage Swing –0.5 V to V
Load Capacitance 200 pF
Storage Temperature Range –65°C to +150°C
Junction Temperature While Biased 125°C
)–0.3 V to +1.5 V
DDINT
)–0.3 V to +1.5 V
VDD
)–0.3 V to +4.6 V
DDEXT
DDEXT
+ 0.5 V
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. For
voltage reference levels, see Figure 39 on Page 44 under Test
Conditions.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
MAXIMUM POWER DISSIPATION
See Estimating Power for the ADSP-21362 SHARC Processors
(EE-277) for detailed thermal and power information regarding
maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 45.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 8 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Rev. I | Page 15 of 56 | July 2012
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
specified in Table 11.
VCO
• The product of CLKIN and PLLM must never exceed 1/2
f
(max) in Table 11 if the input divider is not enabled
VCO
(INDIV = 0).
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
CLKOUT (TEST ONLY)*
LOOP
FILTER
PLL
f
VCO
÷ (2 × PLLM)
VCO
PLL
DIVIDER
PMCTL
(2 × PLLN)
f
VCO
f
CCLK
CLK_CFGx/
PMCTL (2 × PLLM)
CLKIN
PCLK
XTAL
CLKIN
DIVIDER
RESETOUT
DELAY OF
4096 C LKIN
CYCLES
RESET
BUF
BUF
PMCTL
(INDIV)
PMCTL
(PLLBP)
BYPASS
MUX
PIN MUX
DIVIDE
BY 2
RESETOUT
PMCTL (CLKOUTEN)
CCLK
CORERST
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f
INPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
f
INPUT
• The product of CLKIN and PLLM must never exceed f
VCO
(max) in Table 11 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
= 2 × PLLM × f
f
VCO
f
= (2 × PLLM × f
CCLK
INPUT
INPUT
) ÷ (2 × PLLN)
where:
= VCO output
f
VCO
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
= Input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled or
f
INPUT
= CLKIN ÷ 2 when the input divider is enabled
f
INPUT
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 9. All
of the timing specifications for the ADSP-2136x peripherals are
defined in relation to t
. Refer to the peripheral specific sec-
PCLK
tion for each peripheral’s timing information.
Table 9. Clock Periods
Timing
Requirements Description
t
t
t
CK
CCLK
PCLK
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t
CCLK
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, refer to the ADSP-2136x SHARC Processor
Hardware Reference.
Figure 5. Core Clock and System Clock Relationship to CLKIN
Rev. I | Page 16 of 56 | July 2012
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
t
RSTVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
V
DDEXT
V
DDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
t
IVDDEVDD
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 10. Note that during power-up, when the V
supply comes up after V
, a leakage current of the order of
DDEXT
DDINT
power
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
1
RESET Low Before V
V
On Before V
DDINT
CLKIN Valid After V
DDINT/VDDEXT
DDEXT
DDINT/VDDEXT
On 0 ns
Valid 0 200 ms
CLKIN Valid Before RESET Deasserted 10
PLL Control Setup Before RESET Deasserted 20 μs
Switching Characteristic
t
CORERST
1
Valid V
DDINT/VDDEXT
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate
default states at all I/O pins.
4
The 4096 cycle count depends on t
maximum.
Core Reset Deasserted After RESET Deasserted 4096tCK + 2 t
assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,
specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles
SRST
three-state leakage current pull-up, pull-down, may be observed
on any pin, even if that is an input only (for example the RESET
pin) until the V
rail has powered up.
DDINT
–50 +200 ms
2
4
3,
CCLK
μs
Figure 6. Power-Up Sequencing
Rev. I | Page 17 of 56 | July 2012
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