ANALOG DEVICES ADSP-2126x Service Manual

a

ADSP-2126x SHARC® Processor

Peripherals Manual

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Revision 3.0, December 2005

Part Number

82-002002-01

Copyright Information

© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC
logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog
Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xxi

Intended Audience ......................................................................... xxi

Manual Contents .......................................................................... xxii

What’s New in This Manual ........................................................ xxiii

Technical or Customer Support ................................................... xxiii

Supported Processors .................................................................... xxiv

Product Information ..................................................................... xxv

MyAnalog.com ........................................................................ xxv

Processor Product Information ................................................. xxv

Related Documents ................................................................ xxvi

Online Technical Documentation .......................................... xxvii

Accessing Documentation From VisualDSP++ .................. xxviii

Accessing Documentation From Windows ........................ xxviii

Accessing Documentation From the Web ............................ xxix

Printed Manuals ..................................................................... xxix

VisualDSP++ Documentation Set ........................................ xxx

Hardware Tools Manuals ..................................................... xxx

Processor Manuals ............................................................... xxx

ADSP-2126x SHARC Processor Peripherals Manual iii

CONTENTS

Data Sheets ........................................................................ xxx

Conventions ................................................................................ xxxi

INTRODUCTION

ADSP-2126x Processor Design Advantages .................................... 1-1

Architectural Overview ................................................................. 1-6

Processor Core ........................................................................ 1-6

Processor Peripherals ............................................................... 1-7

Dual-Ported Internal Memory (SRAM) ............................... 1-7

I/O Processor ..................................................................... 1-8

Digital Audio Interface (DAI) ........................................... 1-10

Development Tools ..................................................................... 1-10

Differences From Previous SHARCs ............................................ 1-11

Processor Core Enhancements ............................................... 1-11

Processor Internal Bus Enhancements .................................... 1-12

Memory Organization Enhancements .................................... 1-12

Parallel Port Enhancements ................................................... 1-12

I/O Architecture Enhancements ............................................ 1-13

Instruction Set Enhancements ............................................... 1-13

I/O PROCESSOR

General Procedure for Configuring DMA ...................................... 2-2

IOP/Core Interaction Options ...................................................... 2-3

Interrupt Driven I/O ............................................................... 2-3

Polling/Status Driven I/O ....................................................... 2-7

iv ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

DMA Controller Operation ..................................................... 2-8

Chaining DMA Processes .................................................. 2-10

Transfer Control Block Chain Loading (TCB) ................... 2-12

Setting Up and Starting the Chain ..................................... 2-14

Setting Up and Starting Chained DMA over the SPI .......... 2-14

Inserting a TCB in an Active Chain ................................... 2-15

Setting Up DMA Channel Allocation and Priorities ............... 2-16

Managing DMA Channel Priority ..................................... 2-17

DMA Bus Arbitration ....................................................... 2-18

Setting Up DMA Parameter Registers .......................................... 2-20

DMA Transfer Direction ....................................................... 2-21

Data Buffer Registers ............................................................. 2-23

Port, Buffer, and DMA Control Registers ............................... 2-24

Addressing ............................................................................ 2-26

Setting Up DMA ........................................................................ 2-30

PARALLEL PORT

Parallel Port Pins ........................................................................... 3-3

Alternate Pin Functions ........................................................... 3-4

Parallel Ports as FLAG Pins ................................................. 3-4

Parallel Data Acquisition Port as Address Pins ...................... 3-5

Parallel Port Operation .................................................................. 3-5

Basic Parallel Port External Transaction .................................... 3-5

Reading From an External Device or Memory .......................... 3-6

Writing to an External Device or Memory ................................ 3-7

ADSP-2126x SHARC Processor Peripherals Manual v

CONTENTS

Transfer Protocol ..................................................................... 3-8

8-Bit Mode ......................................................................... 3-9

16-Bit Mode ..................................................................... 3-10

Comparison of 16-Bit and 8-Bit SRAM Modes ...................... 3-11

Parallel Port Interrupt ................................................................. 3-12

Parallel Port Throughput ............................................................ 3-12

8-Bit Access .......................................................................... 3-14

16-Bit Access ........................................................................ 3-14

Conclusion ........................................................................... 3-15

Parallel Port Registers ................................................................. 3-15

Parallel Port Control Register (PPCTL) ................................. 3-16

Parallel Port DMA Registers .................................................. 3-16

Parallel Port External Setup Registers ..................................... 3-19

Using the Parallel Port ................................................................ 3-19

DMA Transfers ..................................................................... 3-20

Core Driven Transfers ........................................................... 3-21

Known Duration Accesses ................................................. 3-23

Status Driven Transfers (Polling) ....................................... 3-24

Core-Stall Driven Transfers ............................................... 3-24

Interrupt Driven Accesses ................................................. 3-24

Parallel Port Programming Examples ........................................... 3-25

SERIAL PORTS

Serial Port Signals ......................................................................... 4-5

SPORT Operation Modes ............................................................. 4-9

vi ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

Standard DSP Serial Mode ..................................................... 4-11

Standard DSP Serial Mode Control Bits ............................ 4-11

Clocking Options ............................................................. 4-11

Frame Sync Options .......................................................... 4-12

Data Formatting ............................................................... 4-13

Data Transfers ................................................................... 4-13

Status Information ............................................................ 4-14

Left-Justified Sample Pair Mode ............................................. 4-14

Setting the Internal Serial Clock and Frame Sync Rates ...... 4-15

Left-Justified Sample Pair Mode Control Bits ..................... 4-15

Setting Word Length (SLEN) ............................................ 4-15

Enabling SPORT Master Mode (MSTR) ........................... 4-16

Selecting Transmit and Receive Channel Order (FRFS) ...... 4-16

Selecting Frame Sync Options (DIFS) ............................... 4-16

Enabling SPORT DMA (SDEN) ....................................... 4-17

Interrupt-Driven Data Transfer Mode ............................ 4-17

DMA-Driven Data Transfer Mode ................................. 4-17

I2S Mode .............................................................................. 4-18

I2S Mode Control Bits ...................................................... 4-19

Setting the Internal Serial Clock and Frame Sync Rates ...... 4-20

I2S Control Bits ................................................................ 4-20

Setting Word Length (SLEN) ............................................ 4-20

Enabling SPORT Master Mode (MSTR) ........................... 4-21

Selecting Transmit and Receive Channel Order (FRFS) ...... 4-21

ADSP-2126x SHARC Processor Peripherals Manual vii

CONTENTS

Selecting Frame Sync Options (DIFS) ............................... 4-21

Enabling SPORT DMA (SDEN) ...................................... 4-22

Interrupt-Driven Data Transfer Mode ........................... 4-22

DMA-Driven Data Transfer Mode ................................ 4-23

Multichannel Operation ........................................................ 4-24

Frame Syncs in Multichannel Mode .................................. 4-26

Active State Multichannel Receive Frame Sync Select ..... 4-27

Multichannel Mode Control Bits ...................................... 4-27

Receive Multichannel Frame Sync Source ...................... 4-29

Active State Transmit Data Valid ................................... 4-29

Multichannel Status Bits ............................................... 4-29

Channel Selection Registers .......................................... 4-30

SPORT Loopback ............................................................ 4-31

Clock Signal Options .................................................................. 4-33

Frame Sync Options ................................................................... 4-33

Framed Versus Unframed Frame Syncs ................................... 4-34

Internal Versus External Frame Syncs ..................................... 4-35

Active Low Versus Active High Frame Syncs .......................... 4-35

Sampling Edge for Data and Frame Syncs .............................. 4-36

Early Versus Late Frame Syncs ............................................... 4-36

Data-Independent Frame Sync .............................................. 4-37

Data Word Formats .................................................................... 4-39

Word Length ........................................................................ 4-39

Endian Format ...................................................................... 4-40

viii ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

Data Packing and Unpacking ................................................. 4-40

Data Type ......................................................................... 4-41

Companding ..................................................................... 4-42

SPORT Control Registers and Data Buffers ................................. 4-44

Register Writes and Effect Latency ......................................... 4-50

Serial Port Control Registers (SPCTLx) .................................. 4-50

Transmit and Receive Data Buffers ......................................... 4-59

Clock and Frame Sync Frequencies (DIV) .............................. 4-62

SPORT Reset ........................................................................ 4-65

SPORT Interrupts ................................................................. 4-65

Moving Data Between SPORTS and Internal Memory ................. 4-66

DMA Block Transfers ............................................................ 4-66

Setting Up DMA on SPORT Channels .............................. 4-68

SPORT DMA Parameter Registers ......................................... 4-69

SPORT DMA Chaining .................................................... 4-73

Single Word Transfers ............................................................ 4-74

SPORT Programming Examples .................................................. 4-75

SERIAL PERIPHERAL INTERFACE PORT

Functional Description ................................................................. 5-2

SPI Interface Signals ..................................................................... 5-3

SPI Clock Signal (SPICLK) ..................................................... 5-4

SPICLK Timing .................................................................. 5-5

SPI Slave Select Outputs (SPIDS0-3) ................................... 5-5

SPI Device Select Signal .......................................................... 5-5

ADSP-2126x SHARC Processor Peripherals Manual ix

CONTENTS

Master Out Slave In (MOSI) ................................................... 5-6

Master In Slave Out (MISO) ................................................... 5-6

SPI General Operations ................................................................ 5-8

SPI Enable .............................................................................. 5-8

Open Drain Mode (OPD) ....................................................... 5-9

Master Mode Operation .......................................................... 5-9

Slave Mode Operation ........................................................... 5-11

Multimaster Conditions ........................................................ 5-12

SPI Data Transfer Operations ..................................................... 5-12

Core Transmit and Receive Operations .................................. 5-12

SPI DMA ............................................................................. 5-13

Master Mode DMA Operation .......................................... 5-14

Master Transfer Preparation .......................................... 5-16

Slave Mode DMA Operation ............................................ 5-17

Slave Transfer Preparation ............................................. 5-18

Changing SPI Configuration ............................................. 5-20

Switching From Transmit To Receive DMA ....................... 5-21

Switching From Receive to Transmit DMA ....................... 5-23

DMA Error Interrupts ...................................................... 5-24

DMA Chaining ................................................................ 5-25

SPI Transfer Formats .................................................................. 5-26

Beginning and Ending an SPI Transfer .................................. 5-27

SPI Word Lengths ...................................................................... 5-30

8-Bit Word Lengths .............................................................. 5-30

x ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

16-Bit Word Lengths ............................................................. 5-31

32-Bit Word Lengths ............................................................. 5-31

Packing ................................................................................. 5-31

SPI Interrupts ............................................................................. 5-32

SPI Registers ............................................................................... 5-34

Control and Status Registers .................................................. 5-35

SPI Baud Setup Register (SPIBAUD) ................................. 5-36

SPI Control Register (SPICTL) ......................................... 5-37

SPI Flag Register (SPIFLG) ............................................... 5-40

Use of DSxEN Bits in SPIFLG for Multiple Slave

SPI Systems .................................................................... 5-42

SPI Device Select Input Pin ............................................... 5-43

SPI Status Register (SPISTAT) .......................................... 5-44

Buffering and Transmit/Receive Registers ............................... 5-46

SPI Transmit Data Buffer Register (TXSPI) ....................... 5-47

SPI Receive Data Buffer Register (RXSPI) ......................... 5-48

DMA Registers ...................................................................... 5-48

SPI DMA Configuration (SPIDMAC) Register .................. 5-48

SPI DMA Internal Index Register (IISPI) .......................... 5-50

SPI DMA Address Modifier Register (IMSPI) .................... 5-50

SPI DMA Word Count Register (CSPI) ............................. 5-51

SPI DMA Chain Pointer Register (CPSPI) ......................... 5-51

Shift Registers ....................................................................... 5-52

Receive Shift Register (RXSR) ........................................... 5-52

Transmit Shift Register (TXSR) ......................................... 5-52

ADSP-2126x SHARC Processor Peripherals Manual xi

CONTENTS

SPI Receive Data Buffer Shadow Register

(RXSPI_SHADOW) ...................................................... 5-53

Error Signals and Flags ............................................................... 5-53

Mode Fault Error (MME) ..................................................... 5-53

Transmission Error Bit (TUNF) ............................................ 5-55

Reception Error Bit (ROVF) ................................................. 5-55

Transmit Collision Error Bit (TXCOL) ................................. 5-55

SPI Programming Examples ........................................................ 5-56

INPUT DATA PORT

Serial Inputs ................................................................................. 6-3

Parallel Data Acquisition Port (PDAP) .......................................... 6-6

Masking .................................................................................. 6-7

Packing Unit ........................................................................... 6-8

Packing Mode 11 ................................................................ 6-8

Packing Mode 10 ................................................................ 6-9

Packing Mode 01 ................................................................ 6-9

Packing Mode 00 .............................................................. 6-10

Clocking Edge Selection ........................................................ 6-10

Hold Input ........................................................................... 6-10

PDAP Strobe ........................................................................ 6-12

FIFO Control and Status ............................................................ 6-13

FIFO to Memory Data Transfer .................................................. 6-14

Interrupt-Driven Transfers .................................................... 6-15

Starting an Interrupt-Driven Transfer ................................ 6-16

xii ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

Interrupt-Driven Transfer Notes ............................................ 6-17

DMA Transfers ...................................................................... 6-18

Starting DMA Transfers .................................................... 6-18

DMA Transfer Notes ......................................................... 6-19

DMA Channel Parameter Registers ........................................ 6-21

IDP (DAI) Interrupt Service Routines for DMAs ................... 6-22

Input Data Port Programming Example ....................................... 6-23

DIGITAL AUDIO INTERFACE

Structure of the DAI ..................................................................... 7-1

DAI System Design ....................................................................... 7-2

Signal Routing Unit ...................................................................... 7-3

Connecting Peripherals ............................................................ 7-3

Pins Interface .......................................................................... 7-7

Pin Buffers as Signal Output Pins ............................................ 7-9

Pin Buffers as Signal Input Pins ............................................. 7-10

Bidirectional Pin Buffers ........................................................ 7-11

Making Connections in the SRU ................................................. 7-14

SRU Connection Groups ....................................................... 7-15

Group A Connections – Clock Signals ............................... 7-16

Group B Connections – Data Signals ................................. 7-18

Group C Connections – Frame Sync Signals ...................... 7-19

Group D Connections – Pin Signal Assignments ................ 7-20

Group E Connections – Miscellaneous Signals ................... 7-22

Group F – Pin Enable Signals ............................................ 7-24

ADSP-2126x SHARC Processor Peripherals Manual xiii

CONTENTS

General-Purpose (GPIO) and Flags ............................................. 7-25

Miscellaneous Signals .................................................................. 7-25

DAI Interrupt Controller ............................................................ 7-25

Relationship to the Core ....................................................... 7-25

DAI Interrupts ...................................................................... 7-27

High and Low Priority Latches .............................................. 7-28

Rising and Falling Edge Masks .............................................. 7-29

Using the SRU() Macro .............................................................. 7-30

PRECISION CLOCK GENERATOR

Clock Outputs ............................................................................. 8-2

Frame Sync Outputs ..................................................................... 8-4

Frame Sync ............................................................................. 8-4

Frame Sync Output Synchronization with External Clock ........ 8-5

Phase Shift ................................................................................... 8-6

Phase Shift Settings ................................................................. 8-7

Pulse Width ............................................................................ 8-9

Bypass Mode ........................................................................... 8-9

Bypass as a Pass Through .................................................. 8-10

Bypass as a One Shot ........................................................ 8-10

PCG Programming Examples ...................................................... 8-12

SYSTEM DESIGN

Pin Descriptions ........................................................................... 9-2

Pin Multiplexing ..................................................................... 9-5

xiv ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

Address/Data Pins as FLAGs ............................................... 9-7

Input Synchronization Delay ................................................... 9-7

Clock Derivation ..................................................................... 9-8

Power Management Control Register ................................... 9-8

Timing Specifications ........................................................ 9-11

RESET and CLKIN .............................................................. 9-13

Reset Generators ................................................................... 9-16

Interrupt and Timer Pins ....................................................... 9-17

Core-Based Flag Pins ............................................................. 9-18

JTAG Interface Pins .............................................................. 9-19

Phase-Locked Loop Startup ................................................... 9-20

Conditioning Input Signals ......................................................... 9-21

RESET Input Hysteresis ........................................................ 9-21

Designing for High Frequency Operation .................................... 9-22

Clock Specifications and Jitter ............................................... 9-22

Other Recommendations and Suggestions .............................. 9-23

Decoupling Capacitors and Ground Planes ............................ 9-23

Oscilloscope Probes ............................................................... 9-24

Recommended Reading ......................................................... 9-24

Booting ...................................................................................... 9-26

Parallel Port Booting .............................................................. 9-27

SPI Port Booting ................................................................... 9-29

32-bit SPI Host Boot ........................................................ 9-31

16-bit SPI Host Boot ........................................................ 9-32

ADSP-2126x SHARC Processor Peripherals Manual xv

CONTENTS

8-bit SPI Host Boot .......................................................... 9-33

Slave Boot Mode .............................................................. 9-35

Master Boot ..................................................................... 9-36

Booting From an SPI Flash ............................................... 9-39

Booting From an SPI PROM (16-bit address) ................... 9-39

Booting From an SPI Host Processor ................................. 9-40

Data Delays, Latencies, and Throughput ..................................... 9-40

Execution Stalls ..................................................................... 9-41

DAG Stalls ........................................................................... 9-42

Memory Stalls ....................................................................... 9-42

IOP Register Stalls ................................................................ 9-42

DMA Stalls ........................................................................... 9-42

IOP Buffer Stalls ................................................................... 9-43

REGISTERS REFERENCE

I/O Processor Registers ................................................................. A-2

Flag Value Register (FLAGS) ................................................... A-6

System Control Register (SYSCTL) ....................................... A-11

Hardware Breakpoint Control Register (BRKCTL) ................ A-13

Serial Port Registers .................................................................... A-19

SPORT Serial Control Registers (SPCTLx) ............................ A-19

SPORT Multichannel Control Registers (SPMCTLxy) ........... A-28

SPORT Transmit Buffer Registers (TXSPx) ........................... A-34

SPORT Receive Buffer Registers (RXSPx) .............................. A-34

SPORT Divisor Registers (DIVx) .......................................... A-35

xvi ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

SPORT Count Registers (SPCNTx) ...................................... A-36

SPORT Transmit Select Registers (MTxCSy) ........................ A-36

SPORT Transmit Compand Registers (MTxCCSy) ............... A-37

SPORT Receive Select Registers (MRxCSx) .......................... A-37

SPORT Receive Compand Registers (MRxCCSx) ................. A-38

SPORT DMA Index Registers (IISPx) ................................... A-39

SPORT DMA Modifier Registers (IMSPx) ............................ A-39

SPORT DMA Count Registers (CSPx) ................................. A-40

SPORT Chain Pointer Registers (CPSP) ............................... A-40

SPI Registers .............................................................................. A-41

SPI Port Status Register (SPISTAT) ....................................... A-41

SPI Port Flags Register (SPIFLG) .......................................... A-43

SPI Control Register (SPICTL) ............................................. A-44

SPI Receive Buffer Register (RXSPI) ..................................... A-45

RXSPI Shadow Register (RXSPI_SHADOW) ....................... A-48

SPI Transmit Buffer Register (TXSPI) ................................... A-48

SPI Baud Rate Register (SPIBAUD) ...................................... A-49

SPI DMA Registers .................................................................... A-50

SPI DMA Configuration Register (SPIDMAC) ..................... A-50

SPI DMA Start Address Register (IISPI) ................................ A-53

SPI DMA Address Modify Register (IMSPI) .......................... A-53

SPI DMA Word Count Register (CSPI) ................................ A-54

SPI DMA Chain Pointer Register (CPSPI) ............................ A-54

Parallel Port Registers ................................................................. A-54

ADSP-2126x SHARC Processor Peripherals Manual xvii

CONTENTS

Parallel Port Control Register (PPCTL) ................................. A-55

Parallel Port DMA Transmit Register (TXPP) ........................ A-56

Parallel Port DMA Receive Register (RXPP) .......................... A-58

Parallel Port DMA Start Internal Index Address Register

(IIPP) ................................................................................ A-59

Parallel Port DMA Internal Modifier Address Register

(IMPP) .............................................................................. A-59

Parallel Port DMA Internal Word Count Register (ICPP) ....... A-59

Parallel Port DMA Start External Index Address Register

(EIPP) ............................................................................... A-59

Parallel Port DMA External Modifier Address Register

(EMPP) ............................................................................. A-59

Parallel Port DMA External Word Count Register

(ECPP) .............................................................................. A-60

Signal Routing Unit Registers ..................................................... A-60

Clock Routing Control Registers (Group A) .......................... A-61

Serial Data Routing Registers (SRU_DATx, Group B) ........... A-65

Frame Sync Routing Control Registers

(SRU_FSx, Group C) ......................................................... A-70

Pin Signal Assignment Registers

(SRU_PINx, Group D) ...................................................... A-73

Miscellaneous SRU Registers (SRU_EXT_MISCx,

Group E) ........................................................................... A-79

DAI Pin Buffer Enable Registers (Group F) ........................... A-83

Precision Clock Generator Registers ............................................ A-88

Input Data Port Registers ............................................................ A-95

Input Data Port Control Registers (IDP_CTL) ...................... A-95

xviii ADSP-2126x SHARC Processor Peripherals Manual

Input Data Port FIFO Register (IDP_FIFO) ......................... A-97

Input Data Port DMA Control Registers ............................... A-99

Parallel Data Acquisition Port Control Register

(IDP_PDAP_CTL) ......................................................... A-100

Digital Audio Interface Status Register (DAI_STAT) ........... A-104

DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) A-106

DAI Pin Status Register (DAI_PIN_STAT) ......................... A-109

DAI Interrupt Controller Registers ..................................... A-110

INDEX

ADSP-2126x SHARC Processor Peripherals Manual xix

xx ADSP-2126x SHARC Processor Peripherals Manual

PREFACE

Thank you for purchasing and developing systems using SHARC®
processors from Analog Devices.

Purpose of This Manual

The ADSP-2126x SHARC Processor Peripherals Manual contains informa­tion about the DSP architecture and DSP assembly language for SHARC
processors. These are 32-bit, fixed- and floating-point digital signal pro­cessors from Analog Devices for use in computing, communications, and
consumer applications.

The manual provides information on how assembly instructions execute
on the SHARC processor’s architecture along with reference information
about DSP operations.

Intended Audience

The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual, but should supplement it with other texts
(such as the appropriate hardware reference manuals and data sheets) that
describe your target architecture.

ADSP-2126x SHARC Processor Peripherals Manual xxi

Manual Contents

Manual Contents

The manual consists of:

• Chapter 1, “Introduction”
Provides an architectural overview of the ADSP-2126x processor.

• Chapter 2, “I/O Processor”
Describes ADSP-2126x input/output processor architecture.

• Chapter 3, “Parallel Port”
Describes the processor’s on-chip DMA controller as a mechanism
for transferring data without core interruption.

• Chapter 4, “Serial Ports”
Describes the six dual data line serial ports. Each SPORT contains
a clock, a frame sync, and two data lines that can be configured as
either a receiver or transmitter pair.

• Chapter 5, “Serial Peripheral Interface Port”
Describes the operation of the SPI port. SPI devices communicate
using a master-slave relationship and can achieve high data transfer
rate because they can operate in full-duplex mode.

• Chapter 6, “Input Data Port”
Discusses the function of the input data port (IDP) which provides
a low overhead method of routing signal routing unit (SRU) sig­nals back to the core’s memory.

• Chapter 7, “Digital Audio Interface”
Provides information about the digital audio interface (DAI) which
allows you to attach an arbitrary number and variety of peripherals
to the ADSP-2126x while retaining high levels of compatibility.

• Chapter 8, “Precision Clock Generator”
Details the precision clock generators (PCG) each of which gener­ates a pair of signals derived from a clock input signal.

xxii ADSP-2126x SHARC Processor Peripherals Manual

• Chapter 9, “System Design”
Describes system features of the ADSP-2126x processor. These
include power, reset, clock, JTAG, and booting, as well as pin
descriptions and other system level information.

• Appendix A, “Registers Reference”
Provides ‘at-a-glance’ register figures and bit descriptions.

Preface

L

This hardware reference is a companion document to the
ADSP-2126x SHARC Processor Core Manual.

What’s New in This Manual

Revision 3.0 of the ADSP-2126x SHARC Processor Peripherals Manual dif­fers in a number of ways from the revision 2.0 book. In revision 3.0 all
errata reports against the previous revision have been corrected.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

ADSP-2126x SHARC Processor Peripherals Manual xxiii

Supported Processors

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and
fixed-point (8-bit, 16-bit, and 32-bit) processors. VisualDSP++ currently
supports the following TigerSHARC families: ADSP-TS101 and
ADSP-TS20x.

SHARC (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, and
ADSP-2136x.

Blackfin® (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin families:
ADSP-BF53x and ADSP-BF56x.

xxiv ADSP-2126x SHARC Processor Peripherals Manual

Preface

Product Information

You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at www.analog.com. Our Web site provides infor­mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

the customizing of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.

Registration

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as a means to select the
information you want to receive.

If you are already a registered user, just log on. Your user name is your
e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product
announcements.

ADSP-2126x SHARC Processor Peripherals Manual xxv

Product Information

You may also obtain additional information about Analog Devices and its
products in any of the following ways.

• E-mail questions or requests for information to

[e-mail] (World wide support)
[e-mail] (Europe support)
[e-mail] (China support)

• Fax questions or requests for information to

1-781-461-3010 (North America)
[phone] (Europe)

• Access the FTP Web site at

ftp ftp.analog.com (or ftp 137.71.25.69)
ftp://ftp.analog.com

Related Documents

The following publications that describe the ADSP-2126x processor (and
related processors) can be ordered from any Analog Devices sales office:

• ADSP-21261 SHARC Processor Data Sheet

• ADSP-21262 SHARC Processor Data Sheet

• ADSP-21266 SHARC Processor Data Sheet

• ADSP-21267 SHARC Processor Data Sheet

• ADSP-2126x SHARC Processor Core Manual

• ADSP-21160 SHARC DSP Instruction Set Reference

xxvi ADSP-2126x SHARC Processor Peripherals Manual

Preface

For information on product related development software and Analog
Devices processors, see these publications:

• VisualDSP++ User's Guide for SHARC Processors

• VisualDSP++ C/C++ Compiler and Library Manual for SHARC

Processors

• VisualDSP++ Assembler and Preprocessor Manual for SHARC
Processors

• VisualDSP++ Linker and Utilities Manual for SHARC Processors

• VisualDSP++ Kernel (VDK) User's Guide

Visit the Technical Library Web site to access all processor and tools
manuals and data sheets:

http://www.analog.com/processors/technical_library

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are also provided.

ADSP-2126x SHARC Processor Peripherals Manual xxvii

Product Information

Each documentation file type is described as follows.

File Description

.CHM Help system files and manuals in Help format

.HTM or
.HTML

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Dinkum Abridged C++ library and FlexLM network license manager software doc­umentation. Viewing and printing the HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).

Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).

If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD-ROM at any time
by running the Tools installation. Access the online documentation from
the VisualDSP++ environment, Windows® Explorer, or the Analog
Devices Web site.

Accessing Documentation From VisualDSP++

From the VisualDSP++ environment:

• Access VisualDSP++ online Help from the Help menu’s Contents,
Search, and Index commands.

• Open online Help from context-sensitive user interface items (tool­bar buttons, menu commands, and windows).

Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documenta­tion from Windows.

xxviii ADSP-2126x SHARC Processor Peripherals Manual

Preface

Help system files (.

CHM) are located in the Help folder, and .PDF files are

located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.

Using Windows Explorer

• Double-click the vdsp-help.chm file, which is the master Help sys­tem, to access all the other .CHM files.

• Double-click any file that is part of the VisualDSP++ documenta­tion set.

Using the Windows Start Button

• Access VisualDSP++ online Help by clicking the Start button and
choosing Programs, Analog Devices, VisualDSP++, and
VisualDSP++ Documentation.

• Access the .PDF files by clicking the Start button and choosing

Programs, Analog Devices, VisualDSP++, Documentation for
Printing, and the name of the book.

Accessing Documentation From the Web

Download manuals at the following Web site:

http://www.analog.com/processors/technical_library

Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.

Printed Manuals

For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.

ADSP-2126x SHARC Processor Peripherals Manual xxix

Product Information

VisualDSP++ Documentation Set

To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.

If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto

http://www.analog.com/salesdir.

Hardware Tools Manuals

To purchase EZ-KIT Lite® and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.

Processor Manuals

Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.

Data Sheets

All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.

To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.

xxx ADSP-2126x SHARC Processor Peripherals Manual