Datasheet ADSP-2126x Datasheet (ANALOG DEVICES)

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ADSP-2126x SHARC® Processor

Peripherals Manual

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Revision 3.0, December 2005

Part Number

82-002002-01

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

PREFACE

Purpose of This Manual ................................................................. xxi

Intended Audience ......................................................................... xxi

Manual Contents .......................................................................... xxii

What’s New in This Manual ........................................................ xxiii

Technical or Customer Support ................................................... xxiii

Supported Processors .................................................................... xxiv

Product Information ..................................................................... xxv

MyAnalog.com ........................................................................ xxv

Processor Product Information ................................................. xxv

Related Documents ................................................................ xxvi

Online Technical Documentation .......................................... xxvii

Accessing Documentation From VisualDSP++ .................. xxviii

Accessing Documentation From Windows ........................ xxviii

Accessing Documentation From the Web ............................ xxix

Printed Manuals ..................................................................... xxix

VisualDSP++ Documentation Set ........................................ xxx

Hardware Tools Manuals ..................................................... xxx

Processor Manuals ............................................................... xxx

ADSP-2126x SHARC Processor Peripherals Manual iii

CONTENTS

Data Sheets ........................................................................ xxx

Conventions ................................................................................ xxxi

INTRODUCTION

ADSP-2126x Processor Design Advantages .................................... 1-1

Architectural Overview ................................................................. 1-6

Processor Core ........................................................................ 1-6

Processor Peripherals ............................................................... 1-7

Dual-Ported Internal Memory (SRAM) ............................... 1-7

I/O Processor ..................................................................... 1-8

Digital Audio Interface (DAI) ........................................... 1-10

Development Tools ..................................................................... 1-10

Differences From Previous SHARCs ............................................ 1-11

Processor Core Enhancements ............................................... 1-11

Processor Internal Bus Enhancements .................................... 1-12

Memory Organization Enhancements .................................... 1-12

Parallel Port Enhancements ................................................... 1-12

I/O Architecture Enhancements ............................................ 1-13

Instruction Set Enhancements ............................................... 1-13

I/O PROCESSOR

General Procedure for Configuring DMA ...................................... 2-2

IOP/Core Interaction Options ...................................................... 2-3

Interrupt Driven I/O ............................................................... 2-3

Polling/Status Driven I/O ....................................................... 2-7

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CONTENTS

DMA Controller Operation ..................................................... 2-8

Chaining DMA Processes .................................................. 2-10

Transfer Control Block Chain Loading (TCB) ................... 2-12

Setting Up and Starting the Chain ..................................... 2-14

Setting Up and Starting Chained DMA over the SPI .......... 2-14

Inserting a TCB in an Active Chain ................................... 2-15

Setting Up DMA Channel Allocation and Priorities ............... 2-16

Managing DMA Channel Priority ..................................... 2-17

DMA Bus Arbitration ....................................................... 2-18

Setting Up DMA Parameter Registers .......................................... 2-20

DMA Transfer Direction ....................................................... 2-21

Data Buffer Registers ............................................................. 2-23

Port, Buffer, and DMA Control Registers ............................... 2-24

Addressing ............................................................................ 2-26

Setting Up DMA ........................................................................ 2-30

PARALLEL PORT

Parallel Port Pins ........................................................................... 3-3

Alternate Pin Functions ........................................................... 3-4

Parallel Ports as FLAG Pins ................................................. 3-4

Parallel Data Acquisition Port as Address Pins ...................... 3-5

Parallel Port Operation .................................................................. 3-5

Basic Parallel Port External Transaction .................................... 3-5

Reading From an External Device or Memory .......................... 3-6

Writing to an External Device or Memory ................................ 3-7

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CONTENTS

Transfer Protocol ..................................................................... 3-8

8-Bit Mode ......................................................................... 3-9

16-Bit Mode ..................................................................... 3-10

Comparison of 16-Bit and 8-Bit SRAM Modes ...................... 3-11

Parallel Port Interrupt ................................................................. 3-12

Parallel Port Throughput ............................................................ 3-12

8-Bit Access .......................................................................... 3-14

16-Bit Access ........................................................................ 3-14

Conclusion ........................................................................... 3-15

Parallel Port Registers ................................................................. 3-15

Parallel Port Control Register (PPCTL) ................................. 3-16

Parallel Port DMA Registers .................................................. 3-16

Parallel Port External Setup Registers ..................................... 3-19

Using the Parallel Port ................................................................ 3-19

DMA Transfers ..................................................................... 3-20

Core Driven Transfers ........................................................... 3-21

Known Duration Accesses ................................................. 3-23

Status Driven Transfers (Polling) ....................................... 3-24

Core-Stall Driven Transfers ............................................... 3-24

Interrupt Driven Accesses ................................................. 3-24

Parallel Port Programming Examples ........................................... 3-25

SERIAL PORTS

Serial Port Signals ......................................................................... 4-5

SPORT Operation Modes ............................................................. 4-9

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CONTENTS

Standard DSP Serial Mode ..................................................... 4-11

Standard DSP Serial Mode Control Bits ............................ 4-11

Clocking Options ............................................................. 4-11

Frame Sync Options .......................................................... 4-12

Data Formatting ............................................................... 4-13

Data Transfers ................................................................... 4-13

Status Information ............................................................ 4-14

Left-Justified Sample Pair Mode ............................................. 4-14

Setting the Internal Serial Clock and Frame Sync Rates ...... 4-15

Left-Justified Sample Pair Mode Control Bits ..................... 4-15

Setting Word Length (SLEN) ............................................ 4-15

Enabling SPORT Master Mode (MSTR) ........................... 4-16

Selecting Transmit and Receive Channel Order (FRFS) ...... 4-16

Selecting Frame Sync Options (DIFS) ............................... 4-16

Enabling SPORT DMA (SDEN) ....................................... 4-17

Interrupt-Driven Data Transfer Mode ............................ 4-17

DMA-Driven Data Transfer Mode ................................. 4-17

I2S Mode .............................................................................. 4-18

I2S Mode Control Bits ...................................................... 4-19

Setting the Internal Serial Clock and Frame Sync Rates ...... 4-20

I2S Control Bits ................................................................ 4-20

Setting Word Length (SLEN) ............................................ 4-20

Enabling SPORT Master Mode (MSTR) ........................... 4-21

Selecting Transmit and Receive Channel Order (FRFS) ...... 4-21

ADSP-2126x SHARC Processor Peripherals Manual vii

CONTENTS

Selecting Frame Sync Options (DIFS) ............................... 4-21

Enabling SPORT DMA (SDEN) ...................................... 4-22

Interrupt-Driven Data Transfer Mode ........................... 4-22

DMA-Driven Data Transfer Mode ................................ 4-23

Multichannel Operation ........................................................ 4-24

Frame Syncs in Multichannel Mode .................................. 4-26

Active State Multichannel Receive Frame Sync Select ..... 4-27

Multichannel Mode Control Bits ...................................... 4-27

Receive Multichannel Frame Sync Source ...................... 4-29

Active State Transmit Data Valid ................................... 4-29

Multichannel Status Bits ............................................... 4-29

Channel Selection Registers .......................................... 4-30

SPORT Loopback ............................................................ 4-31

Clock Signal Options .................................................................. 4-33

Frame Sync Options ................................................................... 4-33

Framed Versus Unframed Frame Syncs ................................... 4-34

Internal Versus External Frame Syncs ..................................... 4-35

Active Low Versus Active High Frame Syncs .......................... 4-35

Sampling Edge for Data and Frame Syncs .............................. 4-36

Early Versus Late Frame Syncs ............................................... 4-36

Data-Independent Frame Sync .............................................. 4-37

Data Word Formats .................................................................... 4-39

Word Length ........................................................................ 4-39

Endian Format ...................................................................... 4-40

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CONTENTS

Data Packing and Unpacking ................................................. 4-40

Data Type ......................................................................... 4-41

Companding ..................................................................... 4-42

SPORT Control Registers and Data Buffers ................................. 4-44

Serial Port Control Registers (SPCTLx) .................................. 4-50

Transmit and Receive Data Buffers ......................................... 4-59

Clock and Frame Sync Frequencies (DIV) .............................. 4-62

SPORT Reset ........................................................................ 4-65

SPORT Interrupts ................................................................. 4-65

Moving Data Between SPORTS and Internal Memory ................. 4-66

DMA Block Transfers ............................................................ 4-66

Setting Up DMA on SPORT Channels .............................. 4-68

SPORT DMA Parameter Registers ......................................... 4-69

SPORT DMA Chaining .................................................... 4-73

Single Word Transfers ............................................................ 4-74

SPORT Programming Examples .................................................. 4-75

SERIAL PERIPHERAL INTERFACE PORT

Functional Description ................................................................. 5-2

SPI Interface Signals ..................................................................... 5-3

SPI Clock Signal (SPICLK) ..................................................... 5-4

SPICLK Timing .................................................................. 5-5

SPI Slave Select Outputs (SPIDS0-3) ................................... 5-5

SPI Device Select Signal .......................................................... 5-5

ADSP-2126x SHARC Processor Peripherals Manual ix

CONTENTS

Master Out Slave In (MOSI) ................................................... 5-6

Master In Slave Out (MISO) ................................................... 5-6

SPI General Operations ................................................................ 5-8

SPI Enable .............................................................................. 5-8

Open Drain Mode (OPD) ....................................................... 5-9

Master Mode Operation .......................................................... 5-9

Slave Mode Operation ........................................................... 5-11

Multimaster Conditions ........................................................ 5-12

SPI Data Transfer Operations ..................................................... 5-12

Core Transmit and Receive Operations .................................. 5-12

SPI DMA ............................................................................. 5-13

Master Mode DMA Operation .......................................... 5-14

Master Transfer Preparation .......................................... 5-16

Slave Mode DMA Operation ............................................ 5-17

Slave Transfer Preparation ............................................. 5-18

Changing SPI Configuration ............................................. 5-20

Switching From Transmit To Receive DMA ....................... 5-21

Switching From Receive to Transmit DMA ....................... 5-23

DMA Error Interrupts ...................................................... 5-24

DMA Chaining ................................................................ 5-25

SPI Transfer Formats .................................................................. 5-26

Beginning and Ending an SPI Transfer .................................. 5-27

SPI Word Lengths ...................................................................... 5-30

8-Bit Word Lengths .............................................................. 5-30

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CONTENTS

16-Bit Word Lengths ............................................................. 5-31

32-Bit Word Lengths ............................................................. 5-31

Packing ................................................................................. 5-31

SPI Interrupts ............................................................................. 5-32

SPI Registers ............................................................................... 5-34

Control and Status Registers .................................................. 5-35

SPI Baud Setup Register (SPIBAUD) ................................. 5-36

SPI Control Register (SPICTL) ......................................... 5-37

SPI Flag Register (SPIFLG) ............................................... 5-40

Use of DSxEN Bits in SPIFLG for Multiple Slave

SPI Systems .................................................................... 5-42

SPI Device Select Input Pin ............................................... 5-43

SPI Status Register (SPISTAT) .......................................... 5-44

Buffering and Transmit/Receive Registers ............................... 5-46

SPI Transmit Data Buffer Register (TXSPI) ....................... 5-47

SPI Receive Data Buffer Register (RXSPI) ......................... 5-48

DMA Registers ...................................................................... 5-48

SPI DMA Configuration (SPIDMAC) Register .................. 5-48

SPI DMA Internal Index Register (IISPI) .......................... 5-50

SPI DMA Address Modifier Register (IMSPI) .................... 5-50

SPI DMA Word Count Register (CSPI) ............................. 5-51

SPI DMA Chain Pointer Register (CPSPI) ......................... 5-51

Shift Registers ....................................................................... 5-52

Receive Shift Register (RXSR) ........................................... 5-52

Transmit Shift Register (TXSR) ......................................... 5-52

ADSP-2126x SHARC Processor Peripherals Manual xi

CONTENTS

SPI Receive Data Buffer Shadow Register

(RXSPI_SHADOW) ...................................................... 5-53

Error Signals and Flags ............................................................... 5-53

Mode Fault Error (MME) ..................................................... 5-53

Transmission Error Bit (TUNF) ............................................ 5-55

Reception Error Bit (ROVF) ................................................. 5-55

Transmit Collision Error Bit (TXCOL) ................................. 5-55

SPI Programming Examples ........................................................ 5-56

INPUT DATA PORT

Serial Inputs ................................................................................. 6-3

Parallel Data Acquisition Port (PDAP) .......................................... 6-6

Masking .................................................................................. 6-7

Packing Unit ........................................................................... 6-8

Packing Mode 11 ................................................................ 6-8

Packing Mode 10 ................................................................ 6-9

Packing Mode 01 ................................................................ 6-9

Packing Mode 00 .............................................................. 6-10

Clocking Edge Selection ........................................................ 6-10

Hold Input ........................................................................... 6-10

PDAP Strobe ........................................................................ 6-12

FIFO Control and Status ............................................................ 6-13

FIFO to Memory Data Transfer .................................................. 6-14

Interrupt-Driven Transfers .................................................... 6-15

Starting an Interrupt-Driven Transfer ................................ 6-16

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CONTENTS

Interrupt-Driven Transfer Notes ............................................ 6-17

DMA Transfers ...................................................................... 6-18

Starting DMA Transfers .................................................... 6-18

DMA Transfer Notes ......................................................... 6-19

DMA Channel Parameter Registers ........................................ 6-21

IDP (DAI) Interrupt Service Routines for DMAs ................... 6-22

Input Data Port Programming Example ....................................... 6-23

DIGITAL AUDIO INTERFACE

Structure of the DAI ..................................................................... 7-1

DAI System Design ....................................................................... 7-2

Signal Routing Unit ...................................................................... 7-3

Connecting Peripherals ............................................................ 7-3

Pins Interface .......................................................................... 7-7

Pin Buffers as Signal Output Pins ............................................ 7-9

Pin Buffers as Signal Input Pins ............................................. 7-10

Bidirectional Pin Buffers ........................................................ 7-11

Making Connections in the SRU ................................................. 7-14

SRU Connection Groups ....................................................... 7-15

Group A Connections – Clock Signals ............................... 7-16

Group B Connections – Data Signals ................................. 7-18

Group C Connections – Frame Sync Signals ...................... 7-19

Group D Connections – Pin Signal Assignments ................ 7-20

Group E Connections – Miscellaneous Signals ................... 7-22

Group F – Pin Enable Signals ............................................ 7-24

ADSP-2126x SHARC Processor Peripherals Manual xiii

CONTENTS

General-Purpose (GPIO) and Flags ............................................. 7-25

Miscellaneous Signals .................................................................. 7-25

DAI Interrupt Controller ............................................................ 7-25

Relationship to the Core ....................................................... 7-25

DAI Interrupts ...................................................................... 7-27

High and Low Priority Latches .............................................. 7-28

Rising and Falling Edge Masks .............................................. 7-29

Using the SRU() Macro .............................................................. 7-30

PRECISION CLOCK GENERATOR

Clock Outputs ............................................................................. 8-2

Frame Sync Outputs ..................................................................... 8-4

Frame Sync ............................................................................. 8-4

Frame Sync Output Synchronization with External Clock ........ 8-5

Phase Shift ................................................................................... 8-6

Phase Shift Settings ................................................................. 8-7

Pulse Width ............................................................................ 8-9

Bypass Mode ........................................................................... 8-9

Bypass as a Pass Through .................................................. 8-10

Bypass as a One Shot ........................................................ 8-10

PCG Programming Examples ...................................................... 8-12

SYSTEM DESIGN

Pin Descriptions ........................................................................... 9-2

Pin Multiplexing ..................................................................... 9-5

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CONTENTS

Address/Data Pins as FLAGs ............................................... 9-7

Input Synchronization Delay ................................................... 9-7

Clock Derivation ..................................................................... 9-8

Power Management Control Register ................................... 9-8

Timing Specifications ........................................................ 9-11

RESET and CLKIN .............................................................. 9-13

Reset Generators ................................................................... 9-16

Interrupt and Timer Pins ....................................................... 9-17

Core-Based Flag Pins ............................................................. 9-18

JTAG Interface Pins .............................................................. 9-19

Phase-Locked Loop Startup ................................................... 9-20

Conditioning Input Signals ......................................................... 9-21

RESET Input Hysteresis ........................................................ 9-21

Designing for High Frequency Operation .................................... 9-22

Clock Specifications and Jitter ............................................... 9-22

Other Recommendations and Suggestions .............................. 9-23

Decoupling Capacitors and Ground Planes ............................ 9-23

Oscilloscope Probes ............................................................... 9-24

Recommended Reading ......................................................... 9-24

Booting ...................................................................................... 9-26

Parallel Port Booting .............................................................. 9-27

SPI Port Booting ................................................................... 9-29

32-bit SPI Host Boot ........................................................ 9-31

16-bit SPI Host Boot ........................................................ 9-32

ADSP-2126x SHARC Processor Peripherals Manual xv

CONTENTS

8-bit SPI Host Boot .......................................................... 9-33

Slave Boot Mode .............................................................. 9-35

Master Boot ..................................................................... 9-36

Booting From an SPI Flash ............................................... 9-39

Booting From an SPI PROM (16-bit address) ................... 9-39

Booting From an SPI Host Processor ................................. 9-40

Data Delays, Latencies, and Throughput ..................................... 9-40

Execution Stalls ..................................................................... 9-41

DAG Stalls ........................................................................... 9-42

Memory Stalls ....................................................................... 9-42

IOP Register Stalls ................................................................ 9-42

DMA Stalls ........................................................................... 9-42

IOP Buffer Stalls ................................................................... 9-43

REGISTERS REFERENCE

I/O Processor Registers ................................................................. A-2

Flag Value Register (FLAGS) ................................................... A-6

System Control Register (SYSCTL) ....................................... A-11

Hardware Breakpoint Control Register (BRKCTL) ................ A-13

Serial Port Registers .................................................................... A-19

SPORT Serial Control Registers (SPCTLx) ............................ A-19

SPORT Multichannel Control Registers (SPMCTLxy) ........... A-28

SPORT Transmit Buffer Registers (TXSPx) ........................... A-34

SPORT Receive Buffer Registers (RXSPx) .............................. A-34

SPORT Divisor Registers (DIVx) .......................................... A-35

xvi ADSP-2126x SHARC Processor Peripherals Manual

CONTENTS

SPORT Count Registers (SPCNTx) ...................................... A-36

SPORT Transmit Select Registers (MTxCSy) ........................ A-36

SPORT Transmit Compand Registers (MTxCCSy) ............... A-37

SPORT Receive Select Registers (MRxCSx) .......................... A-37

SPORT Receive Compand Registers (MRxCCSx) ................. A-38

SPORT DMA Index Registers (IISPx) ................................... A-39

SPORT DMA Modifier Registers (IMSPx) ............................ A-39

SPORT DMA Count Registers (CSPx) ................................. A-40

SPORT Chain Pointer Registers (CPSP) ............................... A-40

SPI Registers .............................................................................. A-41

SPI Port Status Register (SPISTAT) ....................................... A-41

SPI Port Flags Register (SPIFLG) .......................................... A-43

SPI Control Register (SPICTL) ............................................. A-44

SPI Receive Buffer Register (RXSPI) ..................................... A-45

RXSPI Shadow Register (RXSPI_SHADOW) ....................... A-48

SPI Transmit Buffer Register (TXSPI) ................................... A-48

SPI Baud Rate Register (SPIBAUD) ...................................... A-49

SPI DMA Registers .................................................................... A-50

SPI DMA Configuration Register (SPIDMAC) ..................... A-50

SPI DMA Start Address Register (IISPI) ................................ A-53

SPI DMA Address Modify Register (IMSPI) .......................... A-53

SPI DMA Word Count Register (CSPI) ................................ A-54

SPI DMA Chain Pointer Register (CPSPI) ............................ A-54

Parallel Port Registers ................................................................. A-54

ADSP-2126x SHARC Processor Peripherals Manual xvii

CONTENTS

Parallel Port Control Register (PPCTL) ................................. A-55

Parallel Port DMA Transmit Register (TXPP) ........................ A-56

Parallel Port DMA Receive Register (RXPP) .......................... A-58

Parallel Port DMA Start Internal Index Address Register

(IIPP) ................................................................................ A-59

Parallel Port DMA Internal Modifier Address Register

(IMPP) .............................................................................. A-59

Parallel Port DMA Internal Word Count Register (ICPP) ....... A-59

Parallel Port DMA Start External Index Address Register

(EIPP) ............................................................................... A-59

Parallel Port DMA External Modifier Address Register

(EMPP) ............................................................................. A-59

Parallel Port DMA External Word Count Register

(ECPP) .............................................................................. A-60

Signal Routing Unit Registers ..................................................... A-60

Clock Routing Control Registers (Group A) .......................... A-61

Serial Data Routing Registers (SRU_DATx, Group B) ........... A-65

Frame Sync Routing Control Registers

(SRU_FSx, Group C) ......................................................... A-70

Pin Signal Assignment Registers

(SRU_PINx, Group D) ...................................................... A-73

Miscellaneous SRU Registers (SRU_EXT_MISCx,

Group E) ........................................................................... A-79

DAI Pin Buffer Enable Registers (Group F) ........................... A-83

Precision Clock Generator Registers ............................................ A-88

Input Data Port Registers ............................................................ A-95

Input Data Port Control Registers (IDP_CTL) ...................... A-95

xviii ADSP-2126x SHARC Processor Peripherals Manual

Input Data Port FIFO Register (IDP_FIFO) ......................... A-97

Input Data Port DMA Control Registers ............................... A-99

Parallel Data Acquisition Port Control Register

(IDP_PDAP_CTL) ......................................................... A-100

Digital Audio Interface Status Register (DAI_STAT) ........... A-104

DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) A-106

DAI Pin Status Register (DAI_PIN_STAT) ......................... A-109

DAI Interrupt Controller Registers ..................................... A-110

INDEX

ADSP-2126x SHARC Processor Peripherals Manual xix

xx ADSP-2126x SHARC Processor Peripherals Manual

PREFACE

Thank you for purchasing and developing systems using SHARC® processors from Analog Devices.

Purpose of This Manual

The ADSP-2126x SHARC Processor Peripherals Manual contains information about the DSP architecture and DSP assembly language for SHARC processors. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing, communications, and consumer applications.

The manual provides information on how assembly instructions execute on the SHARC processor’s architecture along with reference information about DSP operations.

Intended Audience

The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate hardware reference manuals and data sheets) that describe your target architecture.

ADSP-2126x SHARC Processor Peripherals Manual xxi

Manual Contents

The manual consists of:

• Chapter 1, “Introduction” Provides an architectural overview of the ADSP-2126x processor.

• Chapter 2, “I/O Processor” Describes ADSP-2126x input/output processor architecture.

• Chapter 3, “Parallel Port” Describes the processor’s on-chip DMA controller as a mechanism for transferring data without core interruption.

• Chapter 4, “Serial Ports” Describes the six dual data line serial ports. Each SPORT contains a clock, a frame sync, and two data lines that can be configured as either a receiver or transmitter pair.

• Chapter 5, “Serial Peripheral Interface Port” Describes the operation of the SPI port. SPI devices communicate using a master-slave relationship and can achieve high data transfer rate because they can operate in full-duplex mode.

• Chapter 6, “Input Data Port” Discusses the function of the input data port (IDP) which provides a low overhead method of routing signal routing unit (SRU) signals back to the core’s memory.

• Chapter 7, “Digital Audio Interface” Provides information about the digital audio interface (DAI) which allows you to attach an arbitrary number and variety of peripherals to the ADSP-2126x while retaining high levels of compatibility.

• Chapter 8, “Precision Clock Generator” Details the precision clock generators (PCG) each of which generates a pair of signals derived from a clock input signal.

xxii ADSP-2126x SHARC Processor Peripherals Manual

• Chapter 9, “System Design” Describes system features of the ADSP-2126x processor. These include power, reset, clock, JTAG, and booting, as well as pin descriptions and other system level information.

• Appendix A, “Registers Reference” Provides ‘at-a-glance’ register figures and bit descriptions.

Preface

This hardware reference is a companion document to the ADSP-2126x SHARC Processor Core Manual.

What’s New in This Manual

Revision 3.0 of the ADSP-2126x SHARC Processor Peripherals Manual differs in a number of ways from the revision 2.0 book. In revision 3.0 all errata reports against the previous revision have been corrected.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

processor.tools.support@analog.com

• E-mail processor questions to

processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support)

• Phone questions to 1-800-ANALOGD

ADSP-2126x SHARC Processor Peripherals Manual xxiii

Supported Processors

• Contact your Analog Devices, Inc. local sales office or authorized distributor

• Send questions by mail to:

Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and fixed-point (8-bit, 16-bit, and 32-bit) processors. VisualDSP++ currently supports the following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

SHARC (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP++ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, and ADSP-2136x.

Blackfin® (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin families: ADSP-BF53x and ADSP-BF56x.

xxiv ADSP-2126x SHARC Processor Peripherals Manual

Preface

Product Information

You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

the customizing of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

Registration

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as a means to select the information you want to receive.

If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product announcements.

ADSP-2126x SHARC Processor Peripherals Manual xxv

Product Information

You may also obtain additional information about Analog Devices and its products in any of the following ways.

• E-mail questions or requests for information to

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ADSP-2126x SHARC Processor Peripherals Manual xxvii

Product Information

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xxviii ADSP-2126x SHARC Processor Peripherals Manual

Preface

Help system files (.

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ADSP-2126x SHARC Processor Peripherals Manual xxix

Product Information

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xxx ADSP-2126x SHARC Processor Peripherals Manual

Conventions

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Preface

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this or that.

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[

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ADSP-2126x SHARC Processor Peripherals Manual xxxi

Conventions

Additional conventions, which apply only to specific chapters, may appear throughout this document.

xxxii ADSP-2126x SHARC Processor Peripherals Manual

1 INTRODUCTION

A digital signal processor’s data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and probability of overflow, using a floating-point DSP can ease algorithm and software development. The extent to which this is true depends on the floating-point processor’s architecture. Consistency with IEEE workstation simulations and the elimination of scaling are clearly two ease-of-use advantages. High level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and error handling. The ADSP-2126x processors are highly integrated, lower cost 32-bit floating-point DSPs which provide many of these design advantages.

For brevity, the ADSP-21262, ADSP-21266 and ADSP-21267 SHARC processors will be referred to as the ADAP-2126x. For instances where functionality applies to one or the other processor specifically, it will be noted in the text.

ADSP-2126x Processor Design Advantages

The ADSP-2126x processor is a high performance 32-bit processor used for medical imaging, communications, military, audio, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding a dual-ported on-chip SRAM, integrated I/O

ADSP-2126x SHARC Processor Peripherals Manual 1-1

ADSP-2126x Processor Design Advantages

peripherals, and an additional processing element for Single-Instruction Multiple-Data (SIMD) support, this processor builds on the ADSP-21000 Family processor core to form a complete system-on-a-chip.

The SHARC processor architecture balances a high performance processor core with high performance buses (PM, DM, I/O). In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate.

Figure 1-1 shows a detailed block diagram of the processor, illustrating the

following architectural features:

• Two processing elements (PEx and PEy), each containing 32-bit IEEE floating-point computation units—multiplier, ALU, shifter, and data register file

• Program sequencer with related instruction cache, interval timer, and Data Address Generators (DAG1 and DAG2)

• Dual-ported SRAM

• Input/Output (I/O) processor with integrated DMA controller, SPI-compatible port, and serial ports for point-to-point multiprocessor communications

• JTAG Test Access Port for emulation

• Parallel port for interfacing to off-chip memory and peripherals

Figure 1-1 also shows the three on-chip buses of the ADSP-2126x proces-

sor: the Program Memory (PM) bus, Data Memory (DM) bus, and Input/Output (I/O) bus. The PM bus provides access to either instructions or data. During a single cycle, these buses let the processor access two data operands from memory, access an instruction (from the cache), and perform a DMA transfer.

1-2 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

DUAL-PORTED SRAM

TWO INDEPENDENT

BLOCKS

MULT

DAT A AD DRADDR DATA

IOD

RE GIS TE R S

(MEMORY MAPPED)

CONTRO L, STAT US, &

DATAB UFFERS

IOP

ADDR DATA DATA ADDR

DATA

FILE

(PE Y)

16 X 40-B IT

) T

)

(

O L

(

IOA

JTAG TEST& E MULATION

GPIO FLAGS/IRQ/TIM EXP

DMA CONTROLLER

22 CHANNELS

ADDRESS/DATA BUS/GPIO

PARAL LEL PORT

SERIALPORTS (6)

PRECI SION CLOCK

GENERAT OR (1)

MULT

DAG1

8X4X 32

PX R EGIST ER

16 X 40-B IT

CORE PROC ESSOR

DAG2

8X4X 32

PM ADDRESS BUS

DM ADDRESS BUS

PM D ATA BUS

DM DATABUS

DATA

FI LE

(PEX)

ALU

TIMER

BARREL SHIFTER

INSTRUCTIO N

32 X48-BIT

PROGRAM

SEQU ENCER

CACHE

32 64

BARREL SHIFTER

ALU

I/O PROC ESSOR

Figure 1-1. ADSP-2126x SHARC Processor Block Diagram

DUAL-PORTEDROM

TWO I NDEPE NDENT

BLOCKS

ADDR DATA

CO NT RO L /G PI O

SPI PO RT (1)

INPUT

DAT A PO RT (8 )

DAI

TIMERS(3)

16 3

0 K

C O L B

SIGNAL

ROUTING

UNIT

) T I B

)

(

O L

2 (

Further, the ADSP-2126x processor addresses the five central requirements for DSPs:

• Fast, flexible arithmetic computation units

• Unconstrained data flow to and from the computation units

• Extended precision and dynamic range in the computation units

• Dual address generators with circular buffering support

• Efficient program sequencing

ADSP-2126x SHARC Processor Peripherals Manual 1-3

ADSP-2126x Processor Design Advantages

CLOCK

ADC

(OPTIONAL)

CLK

SDAT

DAC

(OPTIONAL)

CLK

SDAT

ADSP-2126x

CLKIN XTAL

CLK_CFG1-0

BOOTCFG1-0

FLAG 3-1

DAI_P1

DAI_P2 DAI_P3

SRU

DAI_P18 DAI _P 19 DA I_P20

CLK FS

DAI

RESET JTAG

PCGA

PCGB

SCLK 0 SFS 0 SD0 A SD0 B

SPORT0

SP ORT1

SPORT 2

SPORT3

SPORT4

SPORT5

CLKOUT

ALE

AD15-0

Figure 1-2. Typical Single Processor System

CO NTR O L

LATCH

AD DR

PARALLEL

PO RT

DA TA

RAM ROM

BOOT ROM

I/O D EVICE

CSFL AG 0

DATA

ADDRESS

Fast, Flexible Arithmetic. The ADSP-21000 family processors execute all instructions in a single cycle. They provide fast cycle times and a complete set of arithmetic operations. The processor is IEEE floating-point compatible and allows either interrupt on arithmetic exception or latched status exception handling.

Unconstrained Data Flow. The ADSP-2126x processor has a Super Harvard Architecture combined with a ten-port data register file. In every cycle, the processor can write or read two operands to or from the register file, supply two operands to the ALU, supply two operands to the

1-4 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

multiplier, and receive three results from the ALU and multiplier. The processor’s 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction.

40-Bit Extended-Precision. The processor handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-complement and unsigned), and extended-precision 40-bit floating-point format. The processors carry extended precision throughout their computation units, limiting intermediate data truncation errors (up to 80 bits of precision are maintained during multiply-accumulate operations).

Dual Address Generators. The processor has two Data Address Generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus, bit-reverse, and broadcast operations are supported with no constraints on data buffer placement.

Efficient Program Sequencing. In addition to zero-overhead loops, the processor supports single-cycle setup and exit for loops. Loops are both nestable (six levels in hardware) and interruptable. The processors support both delayed and non-delayed branches.

High Bandwidth I/O. The processors contain up to a dedicated, 4M bits on-chip ROM, a parallel port, an SPI port, serial ports, Digital Audio Interface (DAI), and JTAG. The DAI incorporates a precision clock generator, input data port, and a signal routing unit.

Serial Ports. Provides an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half the processor core clock (

CCLK) rate.

Digital Audio Interface (DAI). The DAI includes a precision clock generator, an input data port and a signal routing unit.

Input Data Port (IDP). The IDP provides an additional input path to the processor core configurable as eight channels of serial data or seven channels of serial data and a single channel of up to 20-bit wide parallel data.

ADSP-2126x SHARC Processor Peripherals Manual 1-5

Architectural Overview

Signal Routing Unit (SRU). Provides configuration flexibility by allowing software-programmable connections to be made between the DAI components, serial ports, three pulse-width modulation (PWM) timers, and 20 DAI pins.

Serial Peripheral Interface (SPI). The SPI provides master or slave serial boot through SPI, full-duplex operation, master-slave mode multi-master support, open drain outputs, Programmable baud rates, clock polarities, and phases.

I/O Processor (IOP). The IOP manages the SHARC processor’s off-chip data I/O to alleviate the core of this burden. This unit manages the other processor peripherals such as the SPI, DAI, and IDP as well as direct memory accesses (DMA).

Architectural Overview

The ADSP-2126x processor forms a complete system-on-a-chip, integrating a large, high speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the ADSP-2126x processor architecture, which appears in Figure 1-1.

Processor Core

The processor core of the ADSP-2126x processor consists of two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core. For complete information, see the ADSP-2126x SHARC Processor Core Manual.

1-6 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

Processor Peripherals

The term processor peripherals refers to the multiple on-chip functional blocks used to communicate with off-chip devices. The ADSP-2126x processor peripherals include the JTAG, Parallel, Serial, SPI ports, DAI components (PCG, Timers, and IDP), and any external devices that connect to the processor.

Dual-Ported Internal Memory (SRAM)

The individual ADSP-2126x processor products contain varying amounts of memory. For example, the ADSP-21262 processor provides 2M bits of internal SRAM and 2M bits of internal ROM, each of which is organized as two blocks of 1M bit. Each memory block of SRAM is dual-ported for single cycle, independent accesses by the core processor and I/O processor. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle.

All of the memory can be accessed as 16-, 32-, 48-, or 64-bit words. The amount of memory for each word size changes, based on the part number. On the ADSP-2126x processor, the memory can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (and 40-bit data), or combinations of different word sizes up to 2M bits.

The processor also supports a 16-bit floating-point storage format, which effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats completes in a single instruction.

While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, (using the DM bus for transfers), and the other block stores instructions and data, (using the PM bus for transfers). Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the

ADSP-2126x SHARC Processor Peripherals Manual 1-7

Architectural Overview

cache. The processor also maintains single-cycle execution when one of the data operands is transferred to or from off-chip, using the processor parallel port.

I/O Processor

The ADSP-2126x processor Input/Output Processor (IOP) manages the SHARC processor’s off-chip data I/O to alleviate the core of this burden. Up to 22 simultaneous DMA transfers (22 DMA channels) are supported for transfers between internal memory and serial ports (12), the input data port (IDP) (8), SPI port (1), and the parallel port. The I/O processor can perform DMA transfers between the peripherals and internal memory at the full core clock speed. The dual-ported architecture of the internal memory allows the IOP and the core to access internal memory simultaneously with no reduction in throughput.

Serial Ports. The ADSP-2126x processor features up to six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to up to half of the processor core clock rate with maximum of 50M bits per second. Each serial port features two data pins that function as a pair based on the same serial clock and frame sync. Accordingly, each serial port has two DMA channels and serial data buffers associated with it to service the dual serial data pins. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA. Each of the serial ports offers a TDM multichannel mode (up to 128 channels) and supports μ-law or A-law companding. I

S support is also provided.

The serial ports can operate with least significant bit first (LSBF) or most significant bit first (MSBF) transmission order, with word lengths from three to 32 bits. The serial ports offer selectable synchronization and transmit modes. Serial port clocks and frame syncs can be internally or externally generated.

1-8 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

Parallel Port. The ADSP-2126x processor parallel port provides the processor interface to asynchronous 8-bit memory. The parallel port supports a 66M bytes per second transfer rate and 256 word page boundaries. The on-chip DMA controller automatically packs external data into the appropriate word width during transfers.

The parallel port supports packing of 32-bit words into 8-bit or 16-bit external memory and programmable external data access duration from 3 to 32 clock cycles.

Serial Peripheral (Compatible) Interface (SPI). The ADSP-2126x processor SPI is an industry standard synchronous serial link that enables the SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. It can operate in a multi master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device.

The SPI-compatible peripheral implementation also supports programmable baud rate and clock phase/polarities, as well as the use of open drain drivers to support the multi master scenario to avoid data contention.

ROM Based Security. For ADSP-2126x processors with application code in the on-chip ROM, an optional ROM security feature is included. This feature provides hardware support for securing user software code by preventing unauthorized reading from the enabled code. The processor does not boot-load any external code, executing exclusively from internal ROM. The processor also is not freely accessible via the JTAG port. Instead, a 64-bit key is assigned to the user. This key must be scanned in through the JTAG or Test Access Port. The device ignores a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.

ADSP-2126x SHARC Processor Peripherals Manual 1-9

Development Tools

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, an interface data port, and a signal routing unit.

Interrupt Controller. The DAI contains its own interrupt controller that indicates to the core when DAI audio events have occurred. This interrupt controller offers up to 32 independently configurable channels.

Input Data Port (IDP). The input data port provides the DAI with a way to transmit data from within the DAI to the core. The IDP provides a means for up to eight additional DMA paths from the DAI into on-chip memory. All eight channels support 24-bit wide data and share a 16-deep FIFO.

Signal Routing Unit (SRU). Conceptually similar to a “patch-bay” or multiplexer, the SRU provides a group of registers that define the interconnection of the serial ports, the interface data port, the DAI pins, and the precision clock generators.

Development Tools

The ADSP-2126x processor is supported by VisualDSP++, an easy to use Integrated Development & Debugging Environment (IDDE). VisualDSP++ allows you to manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities.

1-10 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

Differences From Previous SHARCs

This section identifies differences between the ADSP-2126x processor and previous SHARCs: ADSP-21161, ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L. Like the ADSP-2116x family, the ADSP-2126x processor family is based on the original ADSP-2106x SHARC family. The ADSP-2126x processor preserves much of the ADSP-2106x architecture and is code compatible to the ADSP-21160, while extending performance and functionality. For background information on SHARC processors and the ADSP-2106x Family processors, see the ADSP-2106x SHARC User’s Manual or the ADSP-21065L SHARC DSP Technical Reference.

Processor Core Enhancements

Computational bandwidth on the ADSP-2126x processor is significantly greater than that on the ADSP-2106x processors. The increase comes from raising the operational frequency and adding another processing element: ALU, shifter, multiplier, and register file. The new processing element lets the processor process multiple data streams in parallel (SIMD mode). The processor operates at 200 MHz using a three stage pipeline.

Like the ADSP-21160 processor, the program sequencer on the ADSP-2126x processor differs from the ADSP-2106x processor family, having several enhancements: new interrupt vector table definitions, SIMD mode stack and conditional execution model, and instruction decodes associated with new instructions. Interrupt vectors have been added that detect illegal memory accesses. Also, mode stack and mode mask support have been added to improve context switch time.

As with the ADSP-21160 processor, the DAGs on the ADSP-2126x processor differ from the ADSP-2106x processors in that DAG2 (for the PM bus) has the same addressing capability as DAG1 (for the DM bus). The DAG registers move 64 bits per cycle. Additionally, the DAGs support the new memory map and long word transfer capability. Circular buffering on

ADSP-2126x SHARC Processor Peripherals Manual 1-11

Differences From Previous SHARCs

the ADSP-2126x processor can be quickly disabled on interrupts and restored on the return. Data “broadcast”, from one memory location to both data register files, is determined by appropriate index register usage.

Processor Internal Bus Enhancements

The PM, DM, and I/O data buses have increased from 32 bits on the ADSP-2106x DSPs to 64 bits. Additional multiplexing and control logic enable 16-, 32-, or 64-bit wide moves between both register files and memory. The processor is capable of broadcasting a single memory location to each of the register files in parallel. Also, the processor permits register contents to be exchanged between the two processing elements’ register files in a single cycle.

Memory Organization Enhancements

The ADSP-2126x processor memory map differs from that of the ADSP-2106x DSPs. The system memory map supports double-word transfers each cycle, reflects extended internal memory capacity for derivative designs, and works with an updated control register for SIMD support. The ADSP-2126x processor family provides enough on-chip memory for several audio decoders.

Parallel Port Enhancements

The parallel port differs from that of the ADSP-2106x DSPs. A new packing mode permits DMA for instructions and data to and from 8-bit external memory. The parallel port supports SRAM, EPROM, and flash memory. There are two modes supported for transfers. In one mode, 8-bit data and 8-bit address can be transferred. In another mode, data and address lines are multiplexed to transfer 16 bits of address/data.

1-12 ADSP-2126x SHARC Processor Peripherals Manual

Introduction

I/O Architecture Enhancements

The I/O processor on the provides much greater throughput than that on the ADSP-2106x DSPs.

The ADSP-2126x processor DMA controller supports up to 22 channels compared to 14 channels on the ADSP-21161 processor. DMA transfers occur at clock speed in parallel with full speed processor execution.

Instruction Set Enhancements

The ADSP-2126x processor provides source code compatibility with the previous SHARC processor family members, to the application assembly source code level. All instructions, control registers, and system resources available in the ADSP-2106x core programming model are also available in the ADSP-2126x processor. Instructions, control registers, or other facilities, required to support the new feature set of the ADSP-2116x core include:

• Code compatibility to the ADSP-21160 SIMD core

• Supersets of the ADSP-2106x programming model

• Reserved facilities in the ADSP-2106x programming model

• Symbol name changes from the ADSP-2106x programming models

These name changes can be managed through reassembly by using the development tools to apply the ADSP-2126x processor symbol definitions header file and linker description file. While these changes have no direct impact on existing core applications, system and I/O processor initialization code and control code do require modifications.

ADSP-2126x SHARC Processor Peripherals Manual 1-13

Differences From Previous SHARCs

Although the porting of source code written for the ADSP-2106x family to the ADSP-2126x processor has been simplified, code changes will be required to take full advantage of the new ADSP-2126x processor features. For more information, see the ADSP-21160 SHARC DSP Instruction Set Reference.

1-14 ADSP-2126x SHARC Processor Peripherals Manual

2 I/O PROCESSOR

In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to perform data transfers. The ADSP-2126x processor contains an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data. These operations include the transfer types listed below and shown in Figure 2-3 on

page 2-22:

• Internal memory ↔ external memory devices

• Internal memory ↔ serial port I/O

• Internal memory ↔ SPI I/O

• Internal memory ← Digital Audio Interface (DAI)

By managing DMA, the I/O processor frees the processor core, allowing it to perform other processor operations while off-chip data I/O occurs as a background task. The dual-ported internal memory allows the core and IOP to simultaneously access the same block of internal memory. This means that DMA transfers to internal memory do not impact core performance. The processor core continues to perform computations without penalty.

To further increase off-chip I/O, multiple DMAs can occur at the same time. The IOP accomplishes this by managing DMAs of processor memory through the parallel, SPI, input data port (IDP) and serial ports.

Each DMA is referred to as a channel, and each channel is configured independently.

ADSP-2126x SHARC Processor Peripherals Manual 2-1

General Procedure for Configuring DMA

There are 22 channels of DMA available on the ADSP-2126x processor— one channel for the SPI interface, one channel for the parallel port interface, 12 channels via the serial ports, and eight channels for the input data port (IDP). Another DMA feature is interrupt generation upon completion of a DMA transfer or upon completion of a chain of DMAs.

General Procedure for Configuring DMA

To configure the ADSP-2126x processor to use DMA, use the following general procedure.

1. Determine which DMA options you want to use:

• IOP/Core interaction method – Interrupt driven or status driven (polling)

• DMA transfer method – Chained or Non chained

• Channel priority scheme – fixed or rotating

2. Determine how you want the DMA to operate:

• Determine and set up the data’s source and/or destination addresses (INDEX)

• Set up the word COUNT (data buffer size)

• Configure the MODIFY values (step size)

3. Configure the peripheral(s):

• Serial ports (SPORTs)

• Parallel port (PP)

• Input data port (IDP)

2-2 ADSP-2126x SHARC Processor Peripherals Manual

I/O Processor

4. Enable DMA

• Set the applicable bits in the appropriate registers: –parallel port–

PPDEN in PPCTL

–serial port–SDEN_x (SCHEN_x for chaining) in SPCTLx –SPI–SPIDEN (SPICHEN for chaining) in SPIDMAC –IDP–IDP_DMA_EN in the IDP_CTL

IOP/Core Interaction Options

There are two methods the processor uses to monitor the progress of DMA operations—interrupts, which are the primary method, and status polling. The same program can use either method for each DMA channel. The following sections describe both methods in detail.

Interrupt Driven I/O

Interrupts on the ADSP-2126x processor are generated at the end of a DMA transfer. This happens when the count register for a particular channel decrements to zero. The interrupt vector locations for each of the channels are listed in Table 2-1. The interrupt register diagram and bit descriptions are given in the ADSP-2126x SHARC Processor Core Manual and “DAI Interrupt Controller Registers” on page A-110.

Programs can check the appropriate status register (for example

PPCTL for

the parallel port) to determine which channels are performing a DMA or chained DMA.

All DMA channels can be active or inactive. If a channel is active, a DMA is in progress on that channel. The I/O processor indicates the active status by setting the channel’s bit in the status register. The only exception to this is the

IDP_DMAx_STAT bits of the DAI_STAT register can become active

even if DMA, through some IDP channel, is not intended.

ADSP-2126x SHARC Processor Peripherals Manual 2-3

IOP/Core Interaction Options

The following are some other I/O processor interrupt attributes.

• When an unchained (single block) DMA process reaches completion (as the count decrements to zero) on any DMA channel, the I/O processor latches that DMA channel’s interrupt. It does this by setting the DMA channel’s interrupt latch bit in the

DAI_IRPTL_H, or DAI_IRPTL_L registers.

• For chained DMA, the I/O processor generates interrupts in one of two ways: If PCI = 1, an interrupt occurs for each DMA in the chain; if PCI = 0, an interrupt occurs at the end of a complete chain. (For more information on DMA chaining, see “DMA Con-

troller Operation” on page 2-8).

• When a DMA channel’s buffer is not being used for a DMA process, the I/O processor can generate an interrupt on single word writes or reads of the buffer. This interrupt service differs slightly for each port. For more information on single word interrupt-driven transfers, see “Parallel Port Control Register (PPCTL)”

on page A-55, and SPCTL register in Table 4-6 on page 4-51.

IRPTL, LIRPTL,

During interrupt-driven DMA, programs use the interrupt mask bits in the IMASK, LIRPTL, DAI_IRPTL_PRI, DAI_IRPTL_RE, and DAI_IRPTL_FE registers to selectively mask DMA channel interrupts that the I/O processor latches into the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L registers.

2-4 ADSP-2126x SHARC Processor Peripherals Manual

The I/O processor only generates a DMA complete interrupt when the channel’s count register decrements to zero as a result of actual DMA transfers. Writing zero to a count register does not generate the interrupt. To stop a DMA preemptively, write a one to the count register. This causes one more word to be transferred or received and an interrupt is then generated.

I/O Processor

A channel interrupt mask in the

DAI_IRPTL_RE, and DAI_IRPTL_FE registers determines whether a latched

IMASK, LIRPTL, DAI_IRPTL_PRI,

interrupt is to be serviced or not. When an interrupt is masked, it is latched but not serviced.

By clearing a channel’s PCI bit during chained DMA, programs

mask the DMA complete interrupt for a DMA process within a chained DMA sequence.

The I/O processor can also generate interrupts for I/O port operations that do not use DMA. In this case, the I/O processor generates an interrupt when data becomes available at the receive buffer or when the transmit buffer is not full (when there is room for the core to write to the buffer). Generating interrupts in this manner lets programs implement interrupt-driven I/O under control of the processor core. Care is needed because multiple interrupts can occur if several I/O ports transmit or receive data in the same cycle.

Table 2-1. DMA Interrupt Vector Locations

Associated Register(s) Bits Vector

Address

Interrupt Name

DMA Channel

Data Buffer

IRPTL/IMASK 14 0x38 SP1I 0 RXSP1A, TXSP1A

LIRPTL 0 0x44 SP0I 2 RXSP0A, TXSP0A

IRPTL/IMASK 15 0x3C SP3I 4 RXSP3A, TXSP3A

LIRPTL 1 0x48 SP2I 6 RXSP2A, TXSP2A

IRPTL/IMASK 16 0x40 SP5I 8 RXSP5A, TXSP5A

LIRPTL 2 0x4C SP4I 10 RXSP4A, TXSP4A

IRPTL/IMASK 14 0x38 SP1I 1 RXSP1B, TXSP1B

LIRPTL 0 0x44 SP0I 3 RXSP0B, TXSP0B

IRPTL/IMASK 15 0x3C SP3I 5 RXSP3B, TXSP3B

LIRPTL 1 0x48 SP2I 7 RXSP2B, TXSP2B

ADSP-2126x SHARC Processor Peripherals Manual 2-5

IOP/Core Interaction Options

Table 2-1. DMA Interrupt Vector Locations (Cont’d)

Associated Register(s) Bits Vector

Address

IRPTL/IMASK 16 0x40 SP5I 9 RXSP5B, TXSP5B

LIRPTL 2 0x4C SP4I 11 RXSP4B, TXSP4B

IRPTL/IMASK (high priority option) LIRPTL (low priority option)

LIRPTL 3 0x50 PPI 21 RXPP, TXPP

IRPTL/IMASK (high priority option) LIRPTL (low priority option)

0x30

0x74

0x2C

0x5C

0x2C

0x5C

0x2C

0x5C

0x2C

0x5C

Interrupt Name

SPIHI

SPILI

DAIHI

DAILI

DAIHI

DAILI

DAIHI

DAILI

DAIHI

DAILI

DMA Channel

20 RXSPI, TXSPI

12 IDP_FIF0

13 IDP_FIF0

14 IDP_FIF0

15 IDP_FIF0

Data Buffer

IRPTL/IMASK (high priority option) LIRPTL (low priority option)

0x2C

0x5C

0x2C

0x5C

DAIHI

DAILI

DAIHI

DAILI

16 IDP_FIF0

17 IDP_FIF0

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Table 2-1. DMA Interrupt Vector Locations (Cont’d)

I/O Processor

Associated Register(s) Bits Vector

Address

IRPTL/IMASK (high priority option) LIRPTL (low priority option)

0x2C

0x5C

0x2C

0x5C

The SPI has two interrupts—a lower priority option (

Interrupt Name

DAIHI

DAILI

DAIHI

DAILI

DMA Channel

18 IDP_FIF0

19 IDP_FIF0

Data Buffer

SPILI) and a higher

priority option (SPIHI). This allows two interrupts to have priorities that are higher and lower than serial ports.

The DAI also has two interrupts—the lower priority option (DAILI) and higher priority option (DAIHI). This allows two interrupts to have priorities that are higher and lower than serial ports.

Polling/Status Driven I/O

The second method of controlling I/O is through status polling. The I/O processor monitors the status of data transfers on DMA channels and indicates interrupt status in the registers. Note that because polling uses processor resources it is not as efficient as an interrupt-driven system. Also note that polling the DMA status registers reduces I/O bandwidth. The following provide more information on the registers that control and monitor I/O processes.

IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L

• All the bits in

IRPTL and LIRPTL registers are shown in the

ADSP-2126x SHARC Processor Core Manual.

• Figure A-59 on page A-112 lists all the bits in DAI_IRPTL_H.

• Figure A-60 on page A-113 lists all the bits in DAI_IRPTL_L.

ADSP-2126x SHARC Processor Peripherals Manual 2-7

IOP/Core Interaction Options

The DMA controller in the ADSP-2126x processor maintains the status information of the channels in each of the peripherals registers,

PPCTL, DAI_STAT, and SPIDMAC. More information on these registers can be

found at the following locations.

• Bit definitions for the SPIDMAC register are illustrated in “SPI DMA

Configuration Register (SPIDMAC)” on page A-50.

• Bit definitions for the SPMCTLxy register are illustrated in “SPORT

Multichannel Control Registers (SPMCTLxy)” on page A-28.

• Bit definitions for the PPCTL register are illustrated in “Parallel Port

Control Register (PPCTL)” on page A-55.

• Bit definitions for the DAI_STAT register are illustrated in

Figure A-56 on page A-105.

SPMCTLxy,

L L

There is a one cycle latency between a change in DMA channel status and the status update in the corresponding register.

If chaining is enabled on a DMA channel, programs should not use polling to determine channel status as it can provide inaccurate information. In this case, the DMA appears inactive if it is sampled while the next transfer control block (TCB) is loading.

DMA Controller Operation

There are two methods you can use to start DMA sequences: chaining and non-chaining.

Non-chained DMA. To start a new DMA sequence after the current one is finished, a program must first clear the DMA enable bit, write new parameters to the index, modify, and count registers, then set the DMA enable bit to re-enable DMA.

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I/O Processor

Chained DMA. Chained DMA sequences are a set of multiple DMA operations, each autoinitializing the next in line. To start a new DMA sequence after the current one is finished, the IOP automatically loads new index, modify, and count values from an internal memory location pointed to by that channel’s chain pointer ( programs can set up consecutive DMA operations and each operation can have different attributes.

CP) register. Using chaining,

In general, a DMA sequence starts when one of the following occurs:

A DMA sequence ends when one of the following occurs:

Chaining is only supported on the SPI and SPORT DMA channels. The parallel port, and IDP port do not support chaining.

• Chaining is disabled, and the DMA enable bit transitions from low to high.

• Chaining is enabled, DMA is enabled, and the chain pointer register address field is written with a nonzero value. In this case, TCB chain loading of the channel parameter registers occurs first.

• Chaining is enabled, the chain pointer register address field is nonzero, and the current DMA sequence finishes. Again, TCB chain loading occurs.

• The count register decrements to zero, and the CP register is zero.

• Chaining is disabled and the channel’s DMA enable bit transitions from high to low. If the DMA enable bit goes low (=0) and chaining is enabled, the channel enters chain insertion mode and the DMA sequence continues. For more information, see “Inserting a

TCB in an Active Chain” on page 2-15.

Once a program starts a DMA process, the process is influenced by two external controls—DMA channel priority and DMA chaining. For more information, see “Managing DMA Channel Priority” on page 2-17 or

“Chaining DMA Processes” below.

ADSP-2126x SHARC Processor Peripherals Manual 2-9

IOP/Core Interaction Options

Chaining DMA Processes

The location of the DMA parameters for the next sequence comes from the chain pointer (

CP) register. In chained DMA operations, the

ADSP-2126x processor automatically initializes and then begins another DMA transfer when the current DMA transfer is complete. In addition to the standard DMA parameter registers, each DMA channel (SP and SPI) also has a CP register that points to the next set of DMA parameters stored in the processor’s internal memory. In the SPI this is the CPSPI and in the SPORT it is CPSPxy. Each new set of parameters is stored in a four-word, user initialized buffer in internal memory known as a transfer control block (TCB). In TCB chain loading, the ADSP-2126x processor’s IOP automatically reads the TCB from internal memory and then loads the values into the channel parameter registers to set up the next DMA sequence.

The structure of a TCB is conceptually the same as that of a traditional linked-list. Each TCB has several data values and a pointer to the next TCB. Further, the chain pointer of a TCB may point to itself to constantly reiterate the same DMA.

A DMA sequence is defined as the sum of the DMA transfers for a single channel, from when the parameter registers initialize to when the count register decrements to zero. Each DMA channel has a chaining enable bit (CHEN) in the corresponding control register. This bit must be set to one to enable chaining. When chaining is enabled, DMA transfers are initiated by writing a memory address to the

CP register. This is also an easy way to

start a single DMA sequence, with no subsequent chained DMAs.

The CP register can be loaded at any time during the DMA sequence. This allows a DMA channel to have chaining disabled ( field = 0x0000) until some event occurs that loads the

CP register address

CP register with a

nonzero value. Writing all zeros to the address field of the chain pointer register (

CP) also disables chaining.

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I/O Processor

nel. The processor does not support cross-channel chaining.

The parallel port and IDP port do not support DMA chaining.

Chained DMA operations may only occur within the same chan-

Address pointer to next TCB

Chaining is not available on the IDP or parallel ports. An “x” denotes the DMA channel used.

CPSPx

CSPx

IMSPx

IISPx

Figure 2-1. TCB Chaining

The chain pointer register is 20 bits wide. The lower 19 bits are the memory address field. Like other I/O processor address registers, the chain pointer register’s value is offset to match the starting address of the processor’s internal memory before it is used by the I/O processor. On the ADSP-2126x processor, this offset value is 0x0008 0000.

Lowest Address

Highest Address

Bit 19 of the chain pointer register is the Program Controlled Interrupts (PCI) bit. This bit controls whether an interrupt is latched after each DMA completes or whether the interrupt is latched after the entire DMA sequence completes. If set, the

PCI bit enables a DMA channel interrupt to

occur after every DMA in the chain. If cleared, an interrupt occurs at the completion of the entire DMA sequence.

The PCI bit only effects DMA channels that have chaining enabled.

Also, interrupt requests enabled by the

IMASK register.

the

PCI bit are maskable with

ADSP-2126x SHARC Processor Peripherals Manual 2-11

IOP/Core Interaction Options

Because the

PCI bit is not part of the memory address in the chain pointer

register, programs must use care when writing and reading addresses to and from the register. To prevent errors, programs should mask out the

PCI bit (bit 19) when copying the address in a chain pointer to another

address register.

The DMA registers are shown in Figure 2-2.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IIx

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMx

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EIPP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EMPP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECPP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CPx

PROGRAM – CONTROLLED INTERRUPT BIT

IF THIS BIT IS SET, THE I/O PROCESSOR WILLGENERATE A

DMA INTERRUPT AFTER EVERY DMA IN THE CHAIN.

PCI BIT

Figure 2-2. DMA Parameter Registers

Transfer Control Block Chain Loading (TCB)

During TCB chain loading, the I/O processor loads the DMA channel parameter registers with values retrieved from internal memory. The address in the chain pointer register points to the highest address of the

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I/O Processor

TCB (containing the index parameter). This means that if a program declares an array to hold the TCB, the

CP register should not point to the

first location of the array. Instead the CP register should point to array[3].

Table 2-2 shows the TCB-to-register loading sequence for the serial port

and SPI port DMA channels. The I/O processor reads each word of the TCB and loads it into the corresponding register. Programs must set up the TCB in memory in the order shown in Table 2-2, placing the index parameter at the address pointed to by the CP register of the previous DMA operation of the chain. The end of the chain (no further TCBs are loaded) is indicated by a TCB with a CP value of zero.

Table 2-2. TCB Chain Loading Sequence

Address

CPSPx + 0x0008 0000 IISPx IISPI

CPSPx – 1 + 0x0008 0000 IMSPx IMSPI

CPSPx – 2 + 0x0008 0000 CSPx CSPI

CPSPx – 3 + 0x0008 0000 CPSPx CPSPI

1 Chaining is not available using the IDP or parallel ports. 2 An “x” denotes the DMA channel used. While the TCB is eight locations

in length, SPI and serial ports only use the first four locations.

Serial Ports SPI Port

A TCB chain load request is prioritized like all other DMA operations. The I/O processor latches a TCB loading request and holds it until the load request has the highest priority. If multiple chaining requests are present, the I/O processor services the

TCB registers for the highest priority

DMA channel first. A channel that is in the process of chain loading cannot be interrupted by a higher priority channel. For a list of DMA channels in priority order, see Table 2-5 on page 2-28.

ADSP-2126x SHARC Processor Peripherals Manual 2-13

IOP/Core Interaction Options

Setting Up and Starting the Chain

To set up and initiate a chain of DMA operations, use these steps:

1. Set up all TCBs in internal memory.

2. Write to the appropriate DMA control register, setting the DMA enable bit to one and the chaining enable bit to one.

3. Write the address containing the index register value of the first TCB to the chain pointer register, which starts the chain.

The I/O processor responds by autoinitializing the first DMA parameter registers with the values from the first TCB, and then starts the first data transfer.

Setting Up and Starting Chained DMA over the SPI

Configuring and starting chained DMA transfers over the SPI port is the same as for the serial port, with one exception. Contrary to SPORT DMA chaining, (where the first DMA in the chain is configured by the first TCB), for SPI DMA chaining, the first DMA is not initialized by a TCB. Instead, the first DMA in the chain must be loaded into the SPI parameter registers ( points to a TCB that describes the second DMA in the sequence.

IISPI, IMSPI, CSPI), and the chain pointer register (CPSPI)

The sequence for setting up and starting a chained DMA is outlined in the following steps and can also be seen in Listing 5-3 on page 5-60.

2-14 ADSP-2126x SHARC Processor Peripherals Manual

Writing an address to the CPSPI register does not begin a chained DMA sequence unless IISPI, IMSPI, and CSPI are initialized, SPI DMA is enabled, the SPI port is enabled, and SPI DMA chaining is enabled.

1. Configure the TCB associated with each DMA in the chain except for the first DMA in the chain.

I/O Processor

2. Write the first three parameters for the initial DMA to the

IMSPI, and CSPI registers directly.

IISPI,

3. Select a baud rate using the SPIBAUD register.

4. Select which flag to use as the SPI slave select signal in the SPIFLG register.

5. Configure and enable the SPI port with the SPICTL register.

6. Configure the DMA settings for the entire sequence, enabling DMA and DMA chaining in the SPIDMAC register.

7. Begin the DMA by writing the address of a TCB (describing the second DMA in the chain) to the CPSPI register.

The address field of the chain pointer registers is only 19 bits wide. If a program writes a symbolic address to bit 19 of the chain pointer, there may be a conflict with the PCI bit. Programs should clear the upper bits of the address, then AND the PCI bit separately, if needed. For example:

R0 = next_TCB+3; /* addr of next chain */ R1 = 0x7FFFF; /* mask 19 bits */ R0 = R0 or R1; CPx = R0;

Inserting a TCB in an Active Chain

This is supported by serial ports only. The SPI interface does not

[

support inserting a TCB in an active chain.

It is possible to insert a single DMA operation or another DMA chain within an active DMA chain. Programs may need to perform insertion when a high priority DMA requires service and cannot wait for the current chain to finish.

ADSP-2126x SHARC Processor Peripherals Manual 2-15

IOP/Core Interaction Options

When DMA on a channel is disabled and chaining on the channel is enabled, the DMA channel is in chain insertion mode. This mode lets a program insert a new DMA or DMA chain within the current chain without effecting the current DMA transfer. Use the following sequence to insert a DMA subchain for the serial port 0A channel while another chain is active:

1. Enter chain insertion mode by setting in the channel’s DMA control register, SPCTL0. The DMA interrupt indicates when the current DMA sequence has completed.

2. Copy the address currently held in the chain pointer register to the chain pointer position of the last TCB in the chain that is being inserted.

3. Write the start address of the first TCB of the new chain into the chain pointer register.

4. Resume chained DMA mode by setting SCHEN_A = 1 and

SDEN_A = 1.

Chain insertion mode operates the same as non-chained DMA mode. When the current DMA transfer ends, an interrupt request occurs and no TCBs are loaded. This interrupt request is independent of the PCI bit state.

Chain insertion should not be set up as an initial mode of operation. This mode should only be used to insert one or more TCBs into an active DMA chaining sequence.

SCHEN_A = 1 and SDEN_A = 0

Setting Up DMA Channel Allocation and Priorities

The ADSP-2126x processor has 22 DMA channels including 12 channels accessible via the serial ports, one SPI channel, one parallel port channel, and eight input data port channels. Each channel has a set of parameter registers which are used to set up DMA transfers. Table 2-3 shows the

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I/O Processor

DMA channel allocation and parameter register assignments for the ADSP-2126x processor. DMA channel 0 has the highest priority and DMA channel 21 has the lowest priority.

Managing DMA Channel Priority

The default channel priority is: DMA channel 0 as highest priority and DMA channel 22 as lowest priority. Table 2-5 on page 2-28 lists the DMA channels in priority order. When a channel becomes the highest priority requester, the I/O processor services the channel’s request. In the next clock cycle, the I/O processor starts the DMA transfer.

The I/O data (IOD) bus is 32 bits wide and is the only path that the IOP uses to transfer data between internal memory and the peripherals. When there are two or more peripherals with active DMAs in progress, they may all require data to be moved to or from memory in the same cycle. For example, the parallel port may fill its word into its RXn buffer. To determine which word is transferred first, the DMA channels for each of the processor’s I/O ports negotiate channel priority with the I/O processor using an internal DMA request/grant handshake.

RXPP buffer just as a SPORT shifts a

Each I/O port has one or more DMA channels, and each channel has a single request and a single grant. When a particular channel needs to read or write data to internal memory, the channel asserts an internal DMA request. The I/O processor prioritizes the request with all other valid DMA requests. When a channel becomes the highest priority requester, the I/O processor asserts the channel’s internal DMA grant. In the next clock cycle, the DMA transfer starts. Figure 2-4 on page 2-27 shows the paths for internal DMA requests within the I/O processor.

ADSP-2126x SHARC Processor Peripherals Manual 2-17

If a DMA channel is disabled (PPDEN, SPIDEN, SDEN, or IDP_DMA_EN bits =0), the I/O processor does not issue internal DMA grants to that channel (whether or not the channel has data to transfer).

IOP/Core Interaction Options

The default DMA channel priority is fixed prioritization by DMA channel group (serial ports, parallel port, IDP, or SPI port). Table 2-5 on

page 2-28 lists the DMA channels in descending order of priority.

For information on programming serial port priority modes, see Table 4-7

on page 4-65.

The I/O processor determines which DMA channel has the highest priority internal DMA request during every cycle between each data transfer.

Processor core accesses of I/O processor registers and TCB chain loading (both of which occur after the IOD transfer) are subject to the same prioritization scheme as the DMA channels. Applying this scheme uniformly prevents I/O bus contention, because these accesses are also performed over the internal I/O bus. For more information, see “Chaining DMA

Processes” on page 2-10.

DMA Bus Arbitration

DMA channel arbitration is the method that the IOP uses to determine how groups rotate priority with other channels. This feature is enabled by setting the

DCPR bit in the IOP’s SYSCTL register.

DMA-capable peripherals execute DMA data transfers to and from internal memory over the IOD bus. When more than one of these peripherals requests access to the IOD bus in a clock cycle, the bus arbiter, which is attached to the IOD bus, determines which master should have access to the bus and grants the bus to that master.

IOP channel arbitration can be set to use either a fixed (

SYSCTL[7] = 0) or

rotating (SYSCTL[7] = 1) algorithm.

In the fixed priority scheme, the lower indexed peripheral has the highest priority.

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I/O Processor

In the rotating priority scheme, the default priorities at reset are the same as that of the fixed priority. However, the peripheral priority is determined by group, not individually. Peripheral groups are shown in

Table 2-3.

Initially, Group A has the highest priority and Group F the lowest. As one group completes its DMA operation, it is assigned the lowest priority (moves to the back of the line) and the next group is given the highest priority.

When none of the peripherals request bus access, the highest priority peripheral, for example, peripheral#0, is granted the bus. However, this does not change the currently assigned priorities to various peripherals.

Within a peripheral group the priority is highest for the higher indexed peripheral (see Table 2-3). For example in SP01 (group A), SP1 has the highest priority.

Table 2-3. DMA Channel Allocation and Parameter Register Assignments

DMA Channel Number

0 (highest priority)

1 RXSP1B, TXSP1B A 0xC67, 0xC66 Serial Port 1B Data

2 RXSP0A, TXSP0A A 0xC61, 0xC60 Serial Port 0A Data

3 RXSP0B, TXSP0B A 0xC63, 0xC62 Serial Port 0

4 RXSP3A, TXSP3A B 0x465, 0x464 Serial Port 3A Data

5 RXSP3B, TXSP3B B 0x467, 0x466 Serial Port 3B Data

6 RXSP2A, TXSP2A B 0x461, 0x460 Serial Port 2A Data

7 RXSP2B, TXSP2B B 0x463, 0x462 Serial Port 2B Data

Data Buffer Group IOP Address of Data

Buffers

RXSP1A, TXSP1A A 0xC65, 0xC64 Serial Port 1A Data

Description

B Data

ADSP-2126x SHARC Processor Peripherals Manual 2-19

Setting Up DMA Parameter Registers

Table 2-3. DMA Channel Allocation and Parameter Register Assignments (Cont’d)

DMA Channel Number

8 RXSP5A, TXSP5A C 0x865 or 0x864 Serial Port 5A Data

9 RXSP5B, TXSP5B C 0x867 or 0x866 Serial Port 5B Data

10 RXSP4A, TXSP4A C 0x861 or 0x860 Serial Port 4A Data

11 RXSP4B, TXSP4B C 0x863 or 0x862 Serial Port 4B Data

12 IDP_FIF0 D 0x24D0 DAI IDP Channel 0

13 IDP_FIF0 D 0x24D0 DAI IDP Channel 1

14 IDP_FIF0 D 0x24D0 DAI IDP Channel 2

15 IDP_FIF0 D 0x24D0 DAI IDP Channel 3

16 IDP_FIF0 D 0x24D0 DAI IPD Channel 4

17 IDP_FIF0 D 0x24D0 DAI IDP Channel 5

18 IDP_FIF0 D 0x24D0 DAI IDP Channel 6

19 IDP_FIF0 D 0x24D0 DAI IDP Channel 7

20 RXSPI, TXSPI E 0x1004, 0x1003 SPI Data

21 (lowest priority)

Data Buffer Group IOP Address of Data

Buffers

RXPP, TXPP F 0x1809, 0x1808 Parallel Port Data

Description

Setting Up DMA Parameter Registers

Once you have determined and configured the DMA options, you can configure the DMA parameter registers. The parameter registers control the source and destination of the data, the size of the data buffer, and the step size used. These topics are described in detail in the following sections.

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I/O Processor

DMA Transfer Direction

DMA transfers between internal memory and external memory devices use the processor’s parallel port. For these types of transfers, a program provides the DMA controller with the internal memory buffer size, address, and address modifier, as well as the external memory buffer size, address and address modifier and the direction of transfer. After setup, the DMA transfers begin when the program enables the channel and continues until the I/O processor transfers the entire buffer to processor memory.

Table 2-4 on page 2-25 shows the parameter registers for each DMA

channel.

Similarly, DMA transfers between internal memory and serial, IDP or SPI ports have DMA parameters. When the I/O processor performs DMA between internal memory and one of these ports, the program sets up the parameters, and the I/O uses the port instead of the external bus.

The direction (receive or transmit) of the I/O port determines the direction of data transfer. When the port receives data, the I/O processor automatically transfers the data to internal memory. When the port needs to transmit a word, the I/O processor automatically fetches the data from internal memory. Figure 2-4 on page 2-27 shows more detail on DMA channel data paths. Figure 2-3 shows the processor’s I/O processor, related ports, and buses.

ADSP-2126x SHARC Processor Peripherals Manual 2-21

Setting Up DMA Parameter Registers

IOA BUS

IOD BUS

DMD, PMD

BUSES (TO CORE)

SPORT

IISP5A-0A, IISP5B-0B,

IMSP5A-0A,

IMSP5B-0B CSP5A-0A, CSP5B-0B,

CPSP5A-0A,

CPSP5B-0B

SPI

IISPI, IMSPI,

CSPI, CPSPI

PARALLEL

PORT

EIPP, EMPP,

ECPP, IIPP, IMPP, ICPP

IDP

IDP_DMA_IX IDP_DMA_MX IDP_DMA_CX

MUX

INTERNAL

DMA

PRIORITI ZER

I/O

PROCESSOR

MUX

SPI D MA

FIFO

(4 DEEP)

Figure 2-3. I/O Processor Block Diagram

SPORTS

TXSP5A-0A, TXSP5B-0B, RXSP5A-0A, RXSP5B-0B

(2 DEEP)

SPI PORT

RXSPI, TXSPI

(1 DEEP EACH)

PARAL LEL

PORT

RXPP, TXPP

(2 DEEP EACH)

EXTERNAL

ADDRESS

GENERATOR

IDP

IDP FIFO

8DEEP

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I/O Processor

Data Buffer Registers

The data buffer registers in Figure 2-3 on page 2-22 shows the data buffer registers for each port. These registers include:

• Serial Port Receive Buffer (RXSPx). These receive buffers for the

serial ports have two position FIFOs for receiving data when connected to another serial device.

• Serial Port Transmit Buffer (TXSPx). These transmit buffers for

the serial ports have two position FIFOs for transmitting data when connected to another serial device.

• SPI Receive Buffer (RXSPI). This receive buffer for the SPI port has

a single position buffer for receiving data when connected to another serial device.

• SPI Transmit Buffer (TXSPI). This transmit buffer for the SPI port

has a single position buffer for transmitting data when connected to another serial device.

• Parallel Port Transmit Buffer (TXPP). This transmit buffer for the

parallel port has two-position FIFOs for transmitting data when connected to another device.

• Parallel Port Receive Buffer (RXPP). This receive buffer for the par-

allel port has two position FIFOs for receiving data when connected to another parallel device.

• Input Data Port Buffers (

IDP_FIFO). This receive buffer for the

input data port has eight position buffers for receiving data when connected to another device.

ADSP-2126x SHARC Processor Peripherals Manual 2-23

Setting Up DMA Parameter Registers

Port, Buffer, and DMA Control Registers

The Port, Buffer, and DMA Control Registers in Figure 2-3 shows the control registers for the ports and DMA channels. These registers include:

• Parallel Port Control register (PPCTL). This register enables the

parallel port system, DMA, and external data width. It also configures wait states, bus hold cycles and identifies the status of the parallel port FIFO, internal, and external interfaces.

• Input Data Port Control register (IDP_CTL). This is the control

• Serial Port Control registers (SPCTLx, SPMCTLxy). These control

registers select the receive or transmit format, monitor FIFO status, enable chaining, and start DMA for each serial port.

• SPI Port Control register (SPICTL). This control register config-

ures and enables the SPI interface, selects the device as master or slave, and determines the data transfer and word size. The SPIDMAC register also controls SPI DMA and FIFO status.

Table 2-4 shows the parameter registers for each DMA channel. These

registers function similarly to data address generator registers and include:

• Internal Index registers (IISPx, IISPI, IIPP, IDP_DMA_Ix). Index

registers provide an internal memory address, acting as a pointer to the next internal memory DMA read or write location.

• Internal Modify registers (

IMSPx, IMPP, IMSPI, IDP_DMA_Mx). Mod-

ify registers provide the signed increment by which the DMA controller post-modifies the corresponding internal memory index register after the DMA read or write.

• Count registers (CSPx, ICPP, CSPI, IDP_DMA_Cx). Count registers

indicate the number of words remaining to be transferred to or from internal memory on the corresponding DMA channel.

2-24 ADSP-2126x SHARC Processor Peripherals Manual

I/O Processor

• Chain Pointer registers (

CPSPx, CPSPI). Chain pointer registers

hold the starting address of the TCB (parameter register values) for the next DMA operation on the corresponding channel. These registers also control whether the I/O processor generates an interrupt when the current DMA process ends.

• External Index registers (EIPP). Index registers provide an external

memory address, acting as a pointer to the next external memory DMA read or write location.

• External Modify registers (EMPP). Modify registers provide the

increment by which the DMA controller post-modifies the corresponding external memory index register after the DMA read or write.

• External Count registers (ECPP). External count registers indicate

the number of words remaining to be transferred to or from external memory on the corresponding DMA channel.

Table 2-4. ADSP-2126x Processor DMA Parameter Registers

IIy Internal Index Register 19 bits Address of buffer in internal

memory

IMxy Internal Modify Register 16 bits

Cxy Internal Count Register 16 bits Length of internal buffer

CPxy Chain Pointer Register 20 bits Chain pointer for DMA

EIPP External Index Register 19 bits Address of buffer in external

EMPP External Modify Register 2 bits Stride for external buffer

ECPP External Count Register 16 bits Length of external buffer

1 IDP_DMA_Mx are 6 bits wide only.

Stride for internal buffer

chaining

memory

ADSP-2126x SHARC Processor Peripherals Manual 2-25

Setting Up DMA Parameter Registers

Addressing

Figure 2-4 shows a block diagram of the I/O processor’s address generator

(DMA controller). Table 2-4 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset.

The I/O processor generates addresses for DMA channels much the same way that the Data Address Generators (DAGs) generate addresses for data memory accesses. Each channel has a set of parameter registers including an index register and modify register that the I/O processor uses to address a data buffer in internal memory. The index register must be initialized with a starting address for the data buffer. As part of the DMA operation, the I/O processor outputs the address in the index register onto the processor’s I/O address bus and applies the address to internal memory during each DMA cycle—a clock cycle in which a DMA transfer is taking place.

All addresses in the index registers are offset by a value matching the processor’s first internal normal word addressed RAM location, before the I/O processor uses the addresses. For the ADSP-2126x processor, this offset value is 0x0008 0000.

DMA addresses must always be normal word (32-bit) memory, and internal memory data transfer sizes are 32 bits. External data transfer sizes may be 16 or 8 bits. The I/O processor can transfer short word data (16-bit) using the packing capability of the serial port and SPI port DMA channels.

After transferring each data word to or from internal memory, the I/O processor adds the modify value to the index register to generate the address for the next DMA transfer and writes the modified index value to

2-26 ADSP-2126x SHARC Processor Peripherals Manual

DMA ADDRESS GENERATOR (INTERNAL ADDRESSES)

LOCAL BUS

I/O Processor

INTERNAL

MEMORY ADDRESS

IIX

INDEX (ADDRESS)

IMX

MODIFIER

+/-

POST-MODIFY

DMA WORD COUNTER

LOCAL BUS

–1

COUNT

CPX

CHAIN POINTER

WORKING REGISTER

MUX

DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES)

LOCAL BUS

EXTERNAL

MEMORY

ADDRESS

EIPP

EXT. INDEX (ADDRESS)

EMPP

EXT. MODIFIER

ECPP

EXT. COUNT

–1

POST-MODIFY

Figure 2-4. DMA Address Generator

ADSP-2126x SHARC Processor Peripherals Manual 2-27

Setting Up DMA Parameter Registers

the index register. The modify value in the modify register is a signed integer, which allows both increment and decrement modifies. The modify value can have any positive or negative integer value.

[

The processor’s 22 DMA channels are numbered as shown in Table 2-5. This table also shows the control, parameter, and data buffer registers that correspond to each channel.

Note: In SP01, SP1 has a higher priority. Similarly, for SP23 and SP45, the odd numbered SPs have a higher priority (SP3, SP5).

If the I/O processor modifies the index register past the maximum 18-bit value to indicate an address out of internal memory, the index wraps around to zero. With the offset for the ADSP-2126x processor, the wraparound address is 0x0008 0000.

If a program loads the count register with zero, the I/O processor does not disable DMA transfers on that channel. The I/O processor interprets the zero as a request for 216 transfers. This count occurs because the I/O processor starts the first transfer before testing the count value. The only way to disable a DMA channel is to clear its DMA enable bit.

If a DMA channel is disabled, the I/O processor does not service requests for that channel, whether or not the channel has data to transfer.

Table 2-5. DMA Channel Registers: Controls, Parameters, and Buffers

DMA Channel Number

0 SPCTL1 IISP1A, IMSP1A,

1 SPCTL1 IISP1B, IMSP1B,

2-28 ADSP-2126x SHARC Processor Peripherals Manual

Control Registers

Parameter Registers Buffer Registers Description

RXSP1A, TXSP1A Serial Port 1A Data

CSP1A, CPSP1A

RXSP1B, TXSP1B Serial Port 1B Data

CSP1B, CPSP1B

Table 2-5. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d)

I/O Processor

DMA Channel Number

2 SPCTL0 IISP0A, IMSP0A,

3 SPCTL0 IISP0B, IMSP0B,

4 SPCTL3 IISP3A, IMSP3A,

5 SPCTL3 IISP3B, IMSP3B,

6 SPCTL2 IISP2A, IMSP2A,

7 SPCTL2 IISP2B, IMSP2B,

8 SPCTL5 IISP5A, IMSP5A,

9 SPCTL5 IISP5B, IMSP5B,

10 SPCTL4 IISP4A, IMSP4A,

Control Registers

Parameter Registers Buffer Registers Description

CSP0A, CPSP0A

CSP0B, CPSP0B

CSP3A, CPSP3A

CSP3B, CPSP3B

CSP2A, CPSP2A

CSP2B, CPSP2B

CSP5A, CPSP5A

CSP5B, CPSP5B

CSP4A, CPSP4A

RXSP0A, TXSP0A Serial Port 0A Data

RXSP0B, TXSP0B Serial Port 0B Data

RXSP3A, TXSP3A Serial Port 3A Data

RXSP3B, TXSP3B Serial Port 3B Data

RXSP2A, TXSP2A Serial Port 2A Data

RXSP2B, TXSP2B Serial Port 2B Data

RXSP5A, TXSP5A Serial Port 5A Data

RXSP5B, TXSP5B Serial Port 5B Data

RXSP4A, TXSP4A Serial Port 4A Data

11 SPCTL4 IISP4B, IMSP4B,

CSP4B, CPSP4B

12 IDP_CTL IDP_DMA_I0,

IDP_DMA_M0, IDP_DMA_C0

13 IDP_CTL IDP_DMA_I1,

IDP_DMA_M1, IDP_DMA_C1

14 IDP_CTL IDP_DMA_I2,

IDP_DMA_M2, IDP_DMA_C2

RXSP4B, TXSP4B Serial Port 4B Data

IDP_FIFO DAI IDP Channel 0

IDP_FIFO DAI IDP Channel 1

IDP_FIFO DAI IDP Channel 2

ADSP-2126x SHARC Processor Peripherals Manual 2-29

Setting Up DMA

Table 2-5. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d)

DMA Channel Number

15 IDP_CTL IDP_DMA_I3,

16 IDP_CTL IDP_DMA_I4,

17 IDP_CTL IDP_DMA_I5,

18 IDP_CTL IDP_DMA_I6,

19 IDP_CTL IDP_DMA_I7,

20 SPICTL IISPI, IMSPI, CSPI,

21 PPCTL EIPP, EMPP, ECPP, IIPP,

Control Registers

Parameter Registers Buffer Registers Description

IDP_DMA_M3, IDP_DMA_C3

IDP_DMA_M4, IDP_DMA_C4

IDP_DMA_M5, IDP_DMA_C5

IDP_DMA_M6, IDP_DMA_C6

IDP_DMA_M7, IDP_DMA_C7

CPSPI

IMPP, ICPP

IDP_FIFO DAI IDP Channel 3

IDP_FIFO DAI IPD Channel 4

IDP_FIFO DAI IDP Channel 5

IDP_FIFO DAI IDP Channel 6

IDP_FIFO DAI IDP Channel 7

RXSPI, TXSPI SPI Data

RXPP, TXPP Parallel Port Data

All of the I/O processor’s registers are memory-mapped, ranging from address 0x0000 0000 to 0x0003 FFFF. For more information on these registers, see “I/O Processor Registers” on page A-2.

Setting Up DMA

Because the I/O processor registers are memory-mapped, the processor has access to program DMA operations. A processor sets up a DMA channel by writing the transfer’s parameters to the DMA parameter registers. After

2-30 ADSP-2126x SHARC Processor Peripherals Manual

I/O Processor

the index, modify, and count registers (among others) are loaded with a starting source or destination address, an address modifier, and a word count, the processor is ready to start the DMA.

The SPI port, parallel port, serial ports and input data ports each have a DMA enable bit (

SPIDEN, PPDEN, SDEN or IDP_DMA_EN) in their channel

control register. Setting this bit for a DMA channel with configured DMA parameters starts the DMA on that channel. If the parameters configure the channel to receive, the I/O processor transfers data words received at the buffer to the destination in internal memory. If the parameters configure the channel to transmit, the I/O processor transfers a word automatically from the source memory to the channel’s buffer register. These transfers continue until the I/O processor transfers the selected number of words as determined by the count parameter. DMA through the IDP ports occurs in internal memory only.

ADSP-2126x SHARC Processor Peripherals Manual 2-31

Setting Up DMA

2-32 ADSP-2126x SHARC Processor Peripherals Manual

3 PARALLEL PORT

The ADSP-2126x processor has a parallel port that allows bidirectional transfers between it and external parallel devices. Using the parallel port bus and control lines, the processor can interface to 8-bit or 16-bit wide external memory devices. The parallel port provides a DMA interface between internal and external memory and has the ability to support core driven data transfer modes. Regardless of whether 8-bit or 16-bit external memory devices are used, the internal data word size is always 32 bits (normal word addressing), and the parallel port employs packing to place the data appropriately.

The processor provides two data packing modes, 8/32 and 16/32. For reads, data packing involves shifting multiple successive 8- or 16-bit elements from the parallel port to the ADSP-2126x processor’s Receive register to form each 32-bit word, transferring multiple successive 8-bit or 16-bit elements. For writes, packing involves shifting each 32-bit word out into 8- or 16-bit elements that are placed into the memory device.

This chapter describes the parallel port operation, registers, interrupt function, and transfer protocol. Figure 3-1 shows a block diagram of the parallel port.

ADSP-2126x SHARC Processor Peripherals Manual 3-1

INTERNAL

MEMORY

CORE

ACCESS

RECEIVE REGISTER

DMA

PARALLEL

PORT

IIPP

IMPP

ICPP

EIPP

EMPP

ECPP

RXPP

TRANSMIT REGISTER

PPCTL

EXTERNAL ADDRESS

PPSI

PPSOTXPP

Figure 3-1. Parallel Port Block Diagram

MUX

PARALLEL PORT

CONTROLLER

AD[7-0]

AD[15-8]

ALE

3-2 ADSP-2126x SHARC Processor Peripherals Manual

Parallel Port

Parallel Port Pins

This section describes the pins that the parallel port uses for its operation.

For a complete list of pin descriptions and package pinouts, see the product specific data sheet for your device.

Address/Data (AD15–0) pins. The ADSP-2126x processor provides time multiplexed address/data pins that are used for providing both address and data information. The state of the address/data pins is determined by the 8- or 16-bit operating mode and the state of the ALE, RD, and WR pins.

Read strobe (RD) pin. This output pin is asserted low to indicate a read operation. Data is latched into the processor using the rising edge of this signal.

Write strobe (WR) pin. This output pin is asserted low to indicate a write operation. The rising edge of this signal can be used by memory devices to latch the data from the processor.

Address Latch Enable (ALE) pin. The address latch enable pin is used to strobe an external latch connected to the address/data pins (AD15–0). The external latch holds the most significant bits (MSBs) of the external memory address. An ALE cycle is inserted for the first access after the parallel port is enabled and anytime the upper 16 bits of the address change from a previous cycle.

In 8-bit mode, a maximum of 24 bits of external address are facilitated through latching the upper 16 bits,

EA23–8, from AD15–0 into the external

latch during the ALE phase of the cycle. The remaining 8 bits of address

EA7–0 are provided through AD15–8 during the second half of the cycle

when the

RD or WR signal is asserted.

ADSP-2126x SHARC Processor Peripherals Manual 3-3

Parallel Port Pins

In 16-bit mode, a maximum of 16 bits of external address are facilitated through latching the upper 16 bits of

AD15–0 from AD15–0 into the exter-

nal latch during the ALE phase of the cycle. The AD15–0 represent the external 16 bits of data during the second half of the cycle when the RD or

WR signal is asserted.

The ALE pin is active high by default, but can be set active low via the

PPALEPL bit (bit 13) in the Parallel Port Control (PPCTL) register.

port boot mode must use address latching hardware that can process this active high signal.

Alternate Pin Functions

The following sections describe how to make the parallel port pins function as flag pins and how to make the parallel data acquisition port pins function as address pins. For additional information on pin multiplexing, see “Pin Multiplexing” on page 9-5.

Parallel Ports as FLAG Pins

Setting (= 1) bit 20 in the SYSCTL register, (PPFLGS) causes the 16 address pins to function as FLAG0-FLAG15. To use the parallel port for data access, this bit should be cleared (= 0). For more information, see “System

Design” on page 9-1.

The ADSP-2126x processor supports up to 16 general purpose FLAG pins.

Since ALE polarity is active high by default, systems using parallel

These several different ways. If the parallel port is disabled, then the 16 address and data pins become these same 16 pins. Finally, FLAG0–FLAG3 are available on four separate pins. These pins are shared with

FLAG signals are multiplexed with other signals, and may be used in

FLAG0–FLAG15. If the parallel port is in use, then

FLAG signals can be routed through the SRU, to 16 DAI

IRQ0–2 and TIMEXP.

3-4 ADSP-2126x SHARC Processor Peripherals Manual

Parallel Port

Parallel Data Acquisition Port as Address Pins

PDAP use of AD[15:0] pins. When bit 26 of the IDP_PP_CTL register is set, the Parallel Data Acquisition Port (PDAP) reads from the parallel port’s AD0–15 pins. When this bit is cleared, the PDAP reads data using DAI pins DAIP20–5. To use the parallel port, this bit must be cleared (= 0).

For more information, see “Parallel Data Acquisition Port (PDAP)” on page 6-6.

Configuring the parallel port pins to function as FLAG0–15 also causes these four dedicated pins to change to their alternate role,

IRQ0–2 and TIMEXP.

Parallel Port Operation

This section describes how the parallel port transfers data. The SYSCTL and

PPCTL registers control the parallel port operating mode. The bits in the SYSCTL register are listed in the ADSP-2126x SHARC Processor Core Man-

ual. Table 3-3 on page 3-17 lists all the bits in the PPCTL register.

Basic Parallel Port External Transaction

A parallel port external transaction consists of a combination of an ALE cycle and a data cycle, which is either a read or write cycle. The following section describes parallel port operation as it relates to processor timing. Refer to the data sheet for your processor for detailed timing specifications.

ALE cycle is an address latch cycle. In this cycle the RD and WR signals

An are inactive and onto the

AD15–0 remaining valid slightly after de-assertion to ensure a sufficient

hold time for the external latch. The ALE pin always remains high for 2 x

ADSP-2126x SHARC Processor Peripherals Manual 3-5

AD15–0 lines, and shortly thereafter the ALE pin is strobed, with

CCLK, irrespective of the data cycle duration values that are set in the

ALE is strobed. The upper 16 bits of the address are driven

Parallel Port Operation

PPCTL register. The parallel port runs at 1/3 the CCLK rate, and so the ALE

cycle is 3 x CCLK. An ALE cycle is inserted whenever the upper 16 bits of address differs from a previous access, as well as after the parallel port is enabled.

In a read cycle, the WR and ALE signals are inactive and RD is strobed. If the upper 16 bits of the external address have changed, this cycle is always preceded by an ALE cycle. In 8-bit mode, the lower 8 bits of the address, EA7–

0, are driven on the AD15–8 pins, and data is sampled from the AD7–0 pins

on the rising edge of RD. In 16-bit mode, address bits are not driven in the read cycle, the external address is provided entirely by the external latch, and data is sampled from the AD15–0 pins at the rising edge of RD. Read cycles can be lengthened by configuring the parallel port data cycle duration bits in the PPCTL register.

In a write cycle, RD and ALE are inactive and WR is strobed. If the upper 16 bits of the external address have changed, this cycle is always preceded by an ALE cycle. In 8-bit mode, the lower 8 bits of the address are driven on the AD15–8 pins and data is driven on the AD7–0 pins. In 16-bit mode, address bits are not driven in the write cycle, the external address is provided entirely by the external latch, 16-bit data is driven onto the AD15-0 pins, and data is written to the external device on the rising edge of the WR signal. Address and data are driven before the falling edge of WR and deasserted after the rising edge to ensure enough setup and hold time with respect to the WR signal. Write cycles can be lengthened by configuring the parallel port data cycle duration bits in the

PPCTL register.

Reading From an External Device or Memory

The parallel port has a two stage data FIFO for receiving data (RXPP). In the first stage, a 32-bit register ( data pins and packs the 8- or 16-bit data into 32 bits. Once the 32-bit data is received in

PPSI, the data is transferred into the second 32-bit reg-

3-6 ADSP-2126x SHARC Processor Peripherals Manual

PPSI) provides an interface to the external

Parallel Port

ister (

RXPP). Once the receive FIFO is full, the chip cannot initiate any

more external data transfers. The RXPP register acts as the interface to the core or I/O processor (for DMA).

The PPTRAN bit must be zero in order to be read.

The order of 8 to 32-bit data packing is shown in Table 3-1. The first byte received is [7:0], second [15:8] and so on. The 16- to 32-bit packing scheme is shown in the third column of the table.

Table 3-1. Packing Sequence for 32-Bit Data

Transfer AD7–0, 8-bit to 32-bit

First Word 1; bits 7–0 Word 1; bits 15–0

Second Word 1; bits 15–8 Word 1; bits 31–16

Third Word 1; bits 23–16

Fourth Word 1; bits 31–24

Writing to an External Device or Memory

The parallel port has a two stage data FIFO for transmitting data (TXPP). The first stage (TXPP) is a 32-bit register that receives data from the internal memory via the DMA controller or a core write. The data in TXPP is moved to the second 32-bit register, PPSO. The PPSO register provides an interface to the external pins. Once a full word is transferred out of

TXPP data is moved to PPSO, if TXPP is not empty.

Table 3-1 does not show ALE cycles; it shows only the order of the

data reads and writes.

AD15–0, 16-bit to 32-bit

(8-bit bus, LSW first)

(16-bit bus, LSW first)

PPSO,

ADSP-2126x SHARC Processor Peripherals Manual 3-7

The PPTRAN bit of the PPCTL register must be set to one in order to enable writes to it.

Parallel Port Operation

The order of 32- to 8-bit data unpacking is shown in Table 3-2. The first byte transferred from 32-bit to 16-bit unpacking scheme is shown in column three of the table.

PPSO is [7:0], the second [15:8] and so on. The

Table 3-2. Unpacking Sequence for 32-Bit Data

Transfer AD7–0, 32-bit to 8-bit

First Word 1; bits 7–0 Word 1; bits 15–0

Second Word 1; bits 15–8 Word 1; bits 31–16

Third Word 1; bits 23–16

Fourth Word 1; bits 31–24

Table 3-2 does not show ALE cycles; it shows only the order of the

data reads and writes.

AD15–0, 32-bit to 16-bit

(8-bit bus, LSW first)

Parallel port DMAs can only be performed to 32-bit (normal word) internal memory.

(16-bit bus, LSW first)

Transfer Protocol

The external interface follows the standard asynchronous SRAM access protocol. The programmable Data Cycle Duration (PPDUR) and optional Bus Hold Cycle ( to interface with memories having different access time requirements. The data cycle duration is programmed via the PPDUR bit in the PPCTL register. The hold cycle at the end of the data cycle is programmed via the PPBHC bit in the

PPCTL register.

BHC) addition at the end of each data cycle are provided

For standard asynchronous SRAM there are two transfer modes—8-bit and 16-bit mode. In 8-bit mode, the address range is 0x0 to 0xFFFFFF which is 16M bytes (4M 32-bit words). In 16-bit mode, the address range

3-8 ADSP-2126x SHARC Processor Peripherals Manual

Disabling the parallel port (PPEN bit is cleared) flushes both parallel port FIFOs, RXPP, and TXPP.

Parallel Port

is 0x0 to 0xFFFF which is a 128K bytes (32K 32-bit words). Although programs can initiate reads or writes on one and two byte boundaries, the parallel port always transfers 4 bytes (two 16-bit or four 8-bit words).

8-Bit Mode

ALE cycle always precedes the first transfer of data after the parallel port

is enabled. During ALE cycles for 8-bit mode, the upper 16 bits of the external address (EA23–8) are driven on the 16-bit parallel port bus (pins

AD15–0). In data cycles (reads and writes), the processor drives the lower 8

bits of address EA7–0 on AD15–8. The 8 bits of external data, ED7–0, that are provided by AD7–0, are sampled by the RD/WR signal respectively. The processor continues to receive and or send data with the same ALE cycle until the upper 16 bits of external address differ from the previous access. For consecutive accesses (EMPP = 1), this occurs once every 256 cycles.

Figure 3-2 shows the connection diagram for the 8-bit mode.

Eight-bit mode enables a larger external address range.

180⍀

ADSP-2126x

AD[7-0]

AD[15-8]

ALE

D[7-0]

D[15-8]

ALE

SRAMCE

LATCH

Q[15-0]

FLASHCE

68⍀

DATA[7-0]

ADDR[7-0]

ADDR[23-8]

Figure 3-2. External Transfer—8-bit Mode

ADSP-2126x SHARC Processor Peripherals Manual 3-9

FLASH

DATA[7-0]

SRAM

Parallel Port Operation

16-Bit Mode

In 16-bit mode, the external address range is

EA15–0 (64K addressable

16-bit words). For a nonzero stride value (EMPP = 0), the transfer of data occurs in two cycles. In cycle one, the processor performs an ALE cycle, driving the 16 bits of external address, EA15–0, onto the 16-bit parallel port bus (pins AD15–0), allowing the external latch to hold this address. In the second cycle, the processor either drives or receives the 16 bits of external data (ED15–0) through the 16-bit parallel port bus (pins AD15–0). This pattern repeats until the transfer completes.

However, a special case occurs when the external address modifier is zero, (EMPP = 0). In this case, the external address is latched only once, using the

ALE cycle before the first data transfer. After the address has been latched

externally, the processor continues receiving and sending 16-bit data on

AD15–0 until the transfer completes. This mode can be used with external

FIFOs and high speed A/D and D/A converters and offers the maximum throughput available on the parallel port (132 Mbyte/sec).

Figure 3-3 shows the connection diagram in 16-bit mode.

FLASH

DATA[7-0]

SRAM

ADSP-2126x

AD[15-0]

180⍀

68⍀

DATA[17-0]

ALE

SRAMCE

LATCH

FLASHCE

Q[15-0]

ADDR[23-8]

ALE

Figure 3-3. External Transfer—16-bit Mode

3-10 ADSP-2126x SHARC Processor Peripherals Manual

Parallel Port

Comparison of 16-Bit and 8-Bit SRAM Modes

When considering whether to employ the 16- or 8-bit mode in a particular design, a few key points should be considered.

• The 8-bit mode provides a 24-bit address, and therefore can access 16M bytes of external memory. In contrast, the 16-bit mode can only address 64K x 16 bit words, which is equivalent to 128K bytes. Therefore, the 8-bit mode provides 128 times the storage capacity of the 16-bit mode.

• For sequential accesses, the 8-bit mode requires only one ALE cycle per 256 bytes. With minimum wait states selected, this represents a worst case overhead of: (1 ALE cycle)/(256 accesses + 1 ALE) x 100% = 0.39% overhead for

ALE cycles. In contrast, the 16-bit mode requires one ALE cycle per

external sequential access. Regardless of length (N), this represents a worst case overhead of: (N ALE cycles)/(N accesses + N ALE cycles) x 100% = 50% overhead for ALE cycles. However, the 16-bit mode delivers two bytes per cycle. Therefore, the total data transfer speed for sequential accesses is nearly identical for both 8-bit and 16-bit modes.

The question that arises at this point is: If the total transfer rates are the same for both 8-bit and 16-bit modes, and the 8-bit mode can also address 128 times as much external memory, why would a system use the 16-bit mode?

• Sometimes an external device is only capable of interfacing to a 16-bit bus.

• When the DMA external modifier is set to zero, the address does not change after the first cycle, therefore an ALE cycle is only inserted on the first cycle. In this case, the 16-bit port can run

ADSP-2126x SHARC Processor Peripherals Manual 3-11

Parallel Port Interrupt

twice as fast as the 8-bit port, as the overhead for

ALE cycles is zero.

This is convenient when interfacing to high speed 16-bit FIFO-based devices, including A/D and D/A converters.

• In situations where a majority of address accesses are non-sequential and cross 256 byte boundaries, the overhead of the ALE cycles in the 8-bit mode approaches 20%1. In this particular situation, the 16-bit memory can provide a 40% speed advantage over the 8-bit mode.

Parallel Port Interrupt

The parallel port has one interrupt signal, PPI, (bit 3 in the LIRPTL register). When DMA is enabled, the maskable interrupt PPI occurs when the DMA block transfer has completed (when the DMA Internal Word Count register ICPP decrements to zero). When DMA is disabled, the maskable interrupt is latched in every cycle the receive buffer is not empty or the transmit buffer is not full.

The parallel port receive (RXPP) and transmit (TXPP) buffers are memory mapped IOP registers. The PPI bit is located at vector address 0x50. The latch (PPI), mask (PPIMSK) and mask pointer (PPIMSKP) bits associated with the parallel port interrupt are all located in the LIRPTL register.

Parallel Port Throughput

As described in “Parallel Port Operation”, each 32-bit word transferred through the parallel port takes a specific period of time to complete. This throughput depends on a number of factors, namely parallel port speed

This can be realized by recalling that four bytes must be packed/unpacked into a single 32-bit word. For example when a 32-bit word is written/read, there is a single ALE cycle inserted per four consecutive addresses. This results in: (N/4 ALE cycles)/(N accesses + N/4 ALE cycles) x 100% = 20%.

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Parallel Port

(1/3 core instruction rate), memory width (8 bits or 16 bits), and memory access constraints (occurrence of of data cycles, and/or addition of hold time cycles).

The maximum parallel port speed is 1/3 of the core. The relationship between core clock and parallel port speed is static. For a 200 MHz core clock, the parallel port runs at 66 MHz. Since there is no parallel port clock signal, it is easiest to think of parallel port throughput in terms of core clock cycles.

As described in “Parallel Port Operation”, parallel port accesses require both ALE cycles to latch the external address and additional data cycles to transmit or receive data. Therefore, the throughput on the parallel port is determined by the duration and number of these cycles per word. The duration of each type of cycle is shown below and the frequency is determined by the external memory width.

ALE cycles at page boundaries, duration

The following sections show examples of transfers that demonstrate the expected throughput for a given set of parameters. Each word transfer sequence is made up of a number of data cycles and potentially one additional ALE cycle.

There is one case where the frequency is also determined by the external address modifier register (EMPP).

• ALE cycles are fixed at 3 core cycles (CCLK) and are not affected by the PPDUR or BHC bit settings. In this case, the ALE is high for 2 core clock cycles. Address for ALE is set up a half core clock cycle before

ALE goes HIGH (active) and remains on bus a half cycle after ALE

goes LOW (inactive). Therefore, the total ALE cycles on the bus are 1/2 + 2 + 1/2 = 3 core clock cycles. Please refer to the data sheet for more precise timing characteristics.

• Data cycle duration is programmable with a range of 3 to 31 CCLK cycles. They may range from 4 to 32 cycles if the

BHC bit is set (=1).

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Parallel Port Throughput

8-Bit Access

In 8-bit mode, the first data-access (whether a read or a write) always consists of one ALE cycle followed by four data cycles. As long as the upper 16 bits of address do not change, each subsequent transfer consists of four data cycles. The ALE cycle is inserted only when the parallel port address crosses an 8-bit boundry page, in other words, after every 256 bytes that are transferred.

For example, if PPDUR3, BHC = 0, and the processor is in 8-bit mode. The first byte on a new page takes six core cycles (three for the ALE cycle and three for the data cycle), and the next sequential 255 bytes consume three core cycles each.

Therefore, the average data rate for a 256 byte page is:

(3 CCLK x 255 + 6 CCLK x 1) / 256 = 3.01 core clock cycles per byte.

For a 200 MHz core, this results in:

(200M CCLK /sec) x (1 byte/3.008 CCLK) = 66.4M Bytes/sec

16-Bit Access

In 16-bit mode, every word transfer consists of two ALE cycles and two data cycles. Therefore, for every 32-bit word transferred, at least six cycles are needed to transfer the data plus an additional six CCLK cycles for the two

ALE cycles, for a total of 12 CCLK cycles per 32-bit transfer (four

bytes). For a 200 MHz core clock, this results in a maximum sustained data rate device of:

200 MHz /12 = 16.67 Million 32-bit words/sec = 66.6M Bytes/sec

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CCLK

Parallel Port

There is a specific case which allows this maximum rate to be exceeded. If the external address modifier (

ALE cycle is needed at the very start of the transfer. Subsequent words,

EMPP) is set to a stride of zero, then only one

essentially written to the same address, do not require any ALE cycles, and every parallel port cycle may be a 16-bit data cycle. In this case, the throughput is nearly doubled (except for the very first ALE cycle) to over 132M bytes per second. This mode is particularly useful for interfacing to FPGA’s or other memory-mapped peripherals such as DAC/ADC converters.

Conclusion

For sequential accesses, the average data rates are nearly identical in 8- and 16-bit modes. For help deciding between the two modes, please refer to

“Comparison of 16-Bit and 8-Bit SRAM Modes” on page 3-11.

Parallel Port Registers

The ADSP-2126x processor’s parallel port contains several user-accessible registers. The Parallel Port Control Register, PPCTL, contains control and status bits and is described below. Two additional registers, RXPP and

TXPP, are used for buffering receive and transmit data during DMA opera-

tions and can be accessed by the core. Finally, the following registers are used for every parallel port access (both core-driven and DMA-driven).

• “Parallel Port DMA Start External Index Address Register (EIPP)”

on page A-59

• “Parallel Port DMA External Modifier Address Register (EMPP)”

on page A-59

ADSP-2126x SHARC Processor Peripherals Manual 3-15

Parallel Port Registers

For DMA transfers only, the following registers must also be initialized:

• “Parallel Port DMA Internal Word Count Register (ICPP)” on

page A-59

• “Parallel Port DMA Start Internal Index Address Register (IIPP)”

on page A-59

• “Parallel Port DMA Internal Modifier Address Register (IMPP)”

on page A-59

• “Parallel Port DMA External Word Count Register (ECPP)” on

page A-60

Additional information on Parallel Port registers can be found in “Parallel

Port Registers” on page A-54.

Parallel Port Control Register (PPCTL)

The Parallel Port Control (PPCTL) register is a memory-mapped register located at address 0x1800 and is used to configure and enable the parallel port system. This register also contains status information for the TX/RX FIFO, the state of DMA, and for external bus availability. This read/write register is also used to program the data cycle duration and to determine the data transfer format.

Table 3-3 provides the bit descriptions for the

PPCTL register.

Parallel Port DMA Registers

The following registers require initialization only when performing DMA-driven accesses.

• DMA Start Internal Index Address Register (IIPP)

This 19-bit register contains the offset from the DMA starting address of 32-bit internal memory.

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Parallel Port

Table 3-3. Parallel Port Register (PPCTL) Bit Definitions

Bit Name Definition Default

0PPENParallel Port Enable. Enables (if set, =1) or disables (if

cleared, =0) the parallel port. Clearing this bit clears the FIFO and the parallel status information. If an RD, WR, or ALE cycle has already started, it completes normally before the port is disabled. The parallel port is ready to transmit or receive two cycles after it is enabled. An ALE cycle always occurs before the first read or write cycle after PPEN is enabled.

5–1 PPDUR Parallel Port Duration. The duration of Parallel Port

data cycles is determined by these bits. ALE cycles are not affected by this setting and are fixed at 3 CCLK cycles. 00000 = Reserved 00001 = Reserved 00010 = 3 clock cycles; 66 MHz throughput 00011 = 4 clock cycles; 50 MHz throughput 00100 = 5 clock cycles; 40 MHz throughput 00101 = 6 clock cycles; 33 MHz throughput ... 11111 = 32 clock cycles; 6.25 MHz throughput

6 PPBHC Bus Hold Cycle. If set (=1), this causes every data-cycle

to be prolonged for 1 CCLK period. If cleared (=0) no bus hold cycle occurs, and the duration of data-cycle is exactly the value specified in PPDUR. Bus hold cycles do not apply to ALE cycles which are always 3 CCLK cycles.

7 PP16 Parallel Port External Data Width. Sets the external data

width to 16 bits (if set, =1) or 8 bits (if cleared, =0).

Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 0 Bit 5 = 1

8 PPDEN Parallel Port DMA Enable. Enables (if set, =1) DMA on

the parallel port or disables DMA (if cleared, =0). When PPDEN is cleared, any DMA requests already in the pipeline complete, and no new DMA requests are made. This does not affect FIFO status.

9 PPTRAN Parallel Port Transmit/Receive Select. Indicates whether

the processor is reading from external memory (if cleared, =0) or writing to external memory (if set, =1).

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Parallel Port Registers

Table 3-3. Parallel Port Register (PPCTL) Bit Definitions (Cont’d)

Bit Name Definition Default

11–10 PPS Parallel Port FIFO Status. These read-only bits indicate

the status of the parallel port FIFO: 00 = RXPP/TXPP is empty 01 = RXPP/TXPP is partially full 11 = RXPP/TXPP is full

12 PPBHD Parallel Port Buffer Hang Disable. When this bit is

cleared (=0), core stalls occur normally. The core stall occurs when the core attempts to write to a full transmit buffer or read from the empty receive buffer. This bit prevents a core hang, when set (=1). Old data present in the receive buffer is reread if the core tries to read it. If a write to the transmit buffer is performed, the core overwrites the current data in the buffer.

13 PPALEPL Parallel Port ALE Polarity Level. Asserts ALE active low

(if set, =1) or active high (if cleared, =0).

15–14 Reserved

16 PPDS DMA Status. This read-only bit indicates that the inter-

nal DMA interface is active (if set, =1) or not active (if cleared, =0).

17 PPBS Parallel Port Bus Status. Indicates that the external bus

interface is busy (if set, =1) or available (if cleared, =0). The bus will be “busy” for the duration of the 32-bit transfer, including the ALE cycles. Note: This bit goes high 2 cycles after data is ready to transmit (after a data is written to PPTX, after PPRX is read with PPEN=1, after writing PPCTL to have PPEN=1 and PPDEN=1).

31–18 Reserved

• DMA Internal Modifier Address register (IMPP)

This 16-bit register contains the internal memory DMA address modifier.

• DMA Internal Word Count register (ICPP)

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Parallel Port

This 16-bit register contains the number of words in internal memory to be transferred via DMA.

• Parallel Port DMA External Word Count Register (

This 24-bit register contains the number of words in external memory to be transferred via DMA.

ECPP)

Parallel Port External Setup Registers

The following registers must be initialized for both core-driven and DMA-driven transfers.

• Parallel Port DMA External Index Address Register (EIPP)

This 24-bit register contains the external memory byte address used for core-driven and DMA driven transfers.

• Parallel Port External Address Modifier Register (EMPP)

This 2-bit register contains the external memory DMA address modifier. It supports only +1, 0, –1. After each data cycle, the EIPP register is modified by this value.

Using the Parallel Port

There are a number of considerations to make when interfacing to parallel external devices. This section describes the different the ways that the parallel port can be used to access external devices. Considerations for choosing between an 8-bit and a 16-bit wide interface are discussed in

“Comparison of 16-Bit and 8-Bit SRAM Modes” on page 3-11.

External parallel devices can be accessed in two ways, either using DMA-driven transfers or core-driven transfers. DMA transfers are performed in the background by the I/O Processor and are generally used to move blocks of data. To perform DMA transfers, the address, word-count,

ADSP-2126x SHARC Processor Peripherals Manual 3-19

Using the Parallel Port

and address-modifier are specified for both the source and destination buffers (one internal, one external). Once initiated, (by setting

PPEN = 1

and PPDEN = 1), the IOP performs the specified transfer in the background without further core interaction. The main advantage of DMA transfers over core driven transfers is that the core can continue executing code while sequential data is imported/exported in the background.

Unlike the external port on previous SHARC processors, the ADSP-2126x core cannot directly access the external parallel bus. Instead, the core initializes two registers to indicate the external address and address-modifier and then accesses data through intermediate registers. Then, when the core accesses either the PPTX or PPRX registers, the parallel port writes/fetches data to/from the specified external address. The details of this functionality and the four main techniques to manage each transfer are detailed below. In general, core-driven transfers are most advantageous when performing single-word accesses and/or accesses to non-sequential addresses.

DMA Transfers

To use the parallel port for DMA programs, start by setting up values in the DMA parameter registers. The program then writes to the PPCTL register to enable PPDEN with all of the necessary settings like cycle duration value, transfer direction, and so on. While a parallel port DMA is active, the DMA parameter registers are not writable. Furthermore, only the and DMAEN bits (in the PPCTL register) can be changed. If any other bit is changed, the parallel port will malfunction. It is recommended that both the PPDEN and PPEN bits be set and reset together to ensure proper DMA operation.

To see an example program that sets up a parallel port DMA, see

Listing 3-1 on page 3-25.

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PPEN

Parallel Port

Core Driven Transfers

Core-driven transfers can be managed using four techniques. The transfers can 1) use interrupts, 2) poll status bits in the PPCTL register, 3) predict when each access will complete by calculating the data and ALE cycle durations, or 4) rely on the fact that the core stalls on certain accesses to PPRX and PPTX. For all four of these methods, the core uses the same basic steps to initiate the transfer. However, each method uses a different technique to complete it. The following steps provide the basic procedure for setting up and initiating a data transfer using the core.

1. Write the external byte address to the EIPP register and the external address modifier to the EMPP register.

Before initializing or modifying any of the parallel port parameter registers such as EIPP and EMPP, the parallel port must first be disabled (bit 0, PPEN, of the PPCTL register must be cleared). Only when PPEN=0, can those registers be modified and the port then re-enabled. This sequence is most often used to perform non-sequential, external transfers, such as when accessing taps in a delay line.

For core-driven transfers, the ECPP, IIPP, IMPP, and ICPP are not used. Although these registers are automatically updated by the parallel port (the ECPP register decrements for example), they may be left uninitialized without consequence.

2. Initialize the

These include the parallel port data-cycle duration ( whether the transfer is a receive or transmit operation (

PPCTL register with the appropriate settings.

PPDUR) and

PPTRAN). For

core-driven transfers, be sure to clear the DMA enable bit, PPDEN. In this same write to

PPEN, to 1.

bit 0,

PPCTL, the port may also be enabled by setting

ADSP-2126x SHARC Processor Peripherals Manual 3-21

Using the Parallel Port

When enabling the parallel port (setting

PPEN = 1), the external bus activ-

ity varies, depending on the direction of data transfer (receive or transmit). For transmit operations (PPTRAN = 1), the parallel port does not perform any external accesses until valid data is written to the TXPP register by the core.

For read operations (PPTRAN = 0), two core clock cycles after PPEN is set (=1), the parallel port immediately fetches two 32-bit data words from the external byte address indicated by EIPP. Subsequently, additional data is fetched only when the core reads (empties) RXPP.

The following are guidelines that programs must follow when the processor core accesses parallel port registers.

• While a DMA transfer is active, the core may only write the PPEN and PPDEN bits of PPCTL. Accessing any of the DMA parameter registers or other bits in PPCTL during an active transfer will cause the parallel port to malfunction.

• Core reads of the FIFO register during a DMA operation are allowed but do not affect the status of the FIFO.

If PPEN is cleared while a transfer is underway (whether core or DMA-driven), the current external bus cycle (ALE cycle or data cycle) will complete but no further external bus cycles occur. Disabling the parallel port clears the data in the

RXPP and TXPP

registers.

• Core reads and writes to the

TXPP and RXPP registers update the sta-

tus of the FIFO when DMA is not active. This happens even when the parallel port is disabled.

• The

PPCTL register has a two-cycle effect-latency. This means that if

programs write to this register in cycle N, the new settings will not be in effect until cycle N + 2. Avoid sampling PPBS until at least 2 cycles after the PPEN bit in PPCTL is set.

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Datasheet ADSP-2126x Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

PREFACE

Purpose of This Manual

Intended Audience

Manual Contents

What’s New in This Manual

Technical or Customer Support

Supported Processors

Product Information

MyAnalog.com

Processor Product Information

Related Documents

Online Technical Documentation

Accessing Documentation From VisualDSP++

Accessing Documentation From Windows

Accessing Documentation From the Web

Printed Manuals

VisualDSP++ Documentation Set

Hardware Tools Manuals

Processor Manuals

Data Sheets

Conventions

1 INTRODUCTION

ADSP-2126x Processor Design Advantages

Architectural Overview

Processor Core

Processor Peripherals

Dual-Ported Internal Memory (SRAM)

I/O Processor

Development Tools

Digital Audio Interface (DAI)

Differences From Previous SHARCs

Processor Core Enhancements

Processor Internal Bus Enhancements

Memory Organization Enhancements

Parallel Port Enhancements

I/O Architecture Enhancements

Instruction Set Enhancements

2 I/O PROCESSOR

General Procedure for Configuring DMA

IOP/Core Interaction Options

Interrupt Driven I/O

Polling/Status Driven I/O

DMA Controller Operation

Chaining DMA Processes

Transfer Control Block Chain Loading (TCB)

Setting Up and Starting the Chain

Setting Up and Starting Chained DMA over the SPI

Inserting a TCB in an Active Chain

Setting Up DMA Channel Allocation and Priorities

Managing DMA Channel Priority

DMA Bus Arbitration

Setting Up DMA Parameter Registers

DMA Transfer Direction

Data Buffer Registers

Port, Buffer, and DMA Control Registers

Addressing

Setting Up DMA

3 PARALLEL PORT

Parallel Port Pins

Alternate Pin Functions

Parallel Ports as FLAG Pins

Parallel Data Acquisition Port as Address Pins

Parallel Port Operation

Basic Parallel Port External Transaction

Reading From an External Device or Memory

Writing to an External Device or Memory

Transfer Protocol

8-Bit Mode

16-Bit Mode

Comparison of 16-Bit and 8-Bit SRAM Modes

Parallel Port Interrupt

Parallel Port Throughput

8-Bit Access

16-Bit Access

Conclusion