ANALOG DEVICES ADSP-21262 Service Manual

SUMMARY

ADDR

DATA

PX REGISTER

6

JTAG TEST & EMULATION

20

3

SER IAL PORTS ( 6)

INPUT
DATA PORTS (8)
PARALLEL DATA

ACQUISIT ION POR T

PER IPHERA L

TI ME R S (3 )

SI GNAL

RO UTI NG

UNIT

PRECISI ON CLOCK

GENERATORS (2)

DIGITAL AUDIO INTERFACE

3

16

ADDRESS/

DATA BUS/ GPIO

CONTROL/GPIO

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS,

DATA BUFFERS

4

SPI PORT ( 1)

DMA CONTROLLER

22 CHANNELS

4

GPIO FLAGS/

IRQ /TIM EXP

PROCESSING

ELEMEN T

(PEY)

PROCES SING

ELEM ENT

(PEX)

TIMER

INSTRUCTION

CACHE

32  48-B IT

DAG1

8  4  32

DAG2

8  4  32

32PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

64

64

CORE PROCESS OR

PROGRAM

SEQ UENCE R

ADDR DATA

SRAM
1M BIT ROM

2M BIT

DUAL PORTED MEMORY

BLOCK 0

SRAM
1M BIT ROM

2M B IT

DUAL PORTED MEMORY

BLO C K 1

S

IOD
(32)

IOA
(19)

32

I/O PROCESSOR

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High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Processes high performance audio while enabling low

system costs

Audio decoders and postprocessor algorithms support

nonvolatile memory that can be configured to contain a
combination of PCM 96 kHz, Dolby
Surround EX
DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA­PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6

Various multichannel surround sound decoders are con-

tained in ROM. For configurations of decoder algorithms,
see Table 3 on Page 6.

TM

TM

, DTS-ES

®

TM

Discrete 6.1, DTS-ES Matrix 6.1,

Digital, Dolby Digital

SHARC

Embedded Processor

ADSP-21261/ADSP-21262/ADSP-21266

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, 6 serial

ports, a digital audio interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi­tion port (PDAP), and 3 programmable timers, all under
software control by the signal routing unit (SRU)

On-chip memory—up to 2M bits on-chip SRAM and a dedi-

cated 4M bits on-chip mask-programmable ROM

The ADSP-2126x processors are available with a 150 MHz or a

200 MHz core instruction rate. For complete ordering
information, see Ordering Guide on Page 47.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Figure 1. Functional Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
FAX: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADSP-21261/ADSP-21262/ADSP-21266

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KEY FEATURES

Serial ports offer left-justified sample-pair and I2S support

via 12 programmable and simultaneous receive or trans­mit pins, which support up to 24 transmit or 24 receive I
channels of audio when all 6 serial ports (SPORTs) are
enabled or 6 full duplex TDM streams of up to 128
channels per frame

At 200 MHz (5 ns) core instruction rate, the ADSP-2126x oper-

ates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed- or floating-point
data; 400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—3 independent buses for dual

data fetch, instruction fetch, and nonintrusive, zero-over­head I/O

Up to 2M bits on-chip dual-ported SRAM (1M bit block 0, 1M

Up to 4M bits on-chip dual-ported mask-programmable ROM

Dual data address generators (DAGs) with modulo and bit-

Zero-overhead looping with single-cycle loop setup,

Single instruction multiple data (SIMD) architecture provides

Transfers between memory and core at up to four 32-bit

Accelerated FFT butterfly computation through a multiply

DMA controller supports

IEEE 1149.1 JTAG standard test access port and on-chip

Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages; avail-

Digital audio interface includes 6 serial ports, 2 precision

bit block 1) for simultaneous access by core processor and
DMA

(2M bits in block 0 and 2M bits in block 1)

reverse addressing

providing efficient program sequencing

2 computational processing elements
Concurrent execution—each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows single

cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch

floating- or fixed-point words per cycle, sustained

2.4 GBps bandwidth at 200 MHz core instruction rate;
900 Mbps is available via DMA

with add and subtract instruction

Up to 22 zero-overhead DMA channels for transfers

between the ADSP-2126x internal memory and serial
ports (12), the input data ports (IDP) (8), the SPI-compat­ible port (1), and the parallel port (1)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

emulation

able in RoHS compliant packages

clock generators, an input data port, 3 programmable tim­ers, and a signal routing unit

2

S

Asynchronous parallel/external port provides

Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data
66M byte/sec transfer rate for 200 MHz core rate
50M byte/sec transfer rate for 150 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLKs

Serial ports provide

50M bits/sec for a 200 MHz core and up to 37.5M bits/sec

for a 150 MHz core on each data line—each has a clock,

frame sync, and 2 data lines that can be configured as

either a receiver or transmitter pair
Left-justified sample-pair and I

direction for up to 24 simultaneous receive or transmit

channels (16 channels on the ADSP-21261) using 2 I

compatible stereo devices per serial port
TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110
Up to 12 TDM stream support, each with 128 channels

per frame
Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either 8 channels of I
serial data or as 7 channels plus a single 20-bit wide syn­chronous parallel data acquisition port

Supports receive audio channel data in I

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, 6 serial ports,
two precision clock generators, 3 timers, an input data
port/parallel data acquisition port, 10 interrupts, 6 flag
inputs, 6 flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)

Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open-drain outputs
Programmable baud rates, clock polarities, and phases

3 muxed flag/IRQ lines
1 muxed flag/timer expired line
ROM-based security features:

JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

2

S support, programmable

2

S, left-justified

2

S-

2

S or

Rev. E | Page 2 of 48 | July 2008

TABLE OF CONTENTS

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ADSP-21261/ADSP-21262/ADSP-21266

Summary ............................................................... 1

Key Features ........................................................... 2

Table of Contents .................................................... 3

Revision History ...................................................... 3

General Description ................................................. 4

Family Core Architecture ....................................... 5

Memory and I/O Interface Features ........................... 6

Target Board JTAG Emulator Connector .................... 9

Development Tools ............................................... 9

Evaluation Kit ..................................................... 10

Designing an Emulator-Compatible DSP Board (Target) 11

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Pins as Flags ..................................... 15

Core Instruction Rate to CLKIN Ratio Modes ............. 15

Address Data Modes ............................................. 15

Product Specifications .............................................. 16

Operating Conditions ........................................... 16

Electrical Characteristics ........................................ 16

Package Information ............................................ 17

ESD Caution ...................................................... 17

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

Timing Specifications ........................................... 17

Output Drive Currents .......................................... 39

Test Conditions ................................................... 39

Capacitive Loading ............................................... 39

Environmental Conditions ..................................... 40

Thermal Characteristics ........................................ 40

144-Lead LQFP Pin Configurations ............................. 41

136-Ball BGA Pin Configurations .. ............................. 42

Outline Dimensions ................................................ 45

Surface-Mount Design .......................................... 45

Ordering Guide ...................................................... 47

REVISION HISTORY

7/08—Rev. D to Rev. E

This revision of the data sheet combines the ADSP-21261 and

ADSP-21262 into the ADSP-21266 data sheet.

Corrected all outstanding document errata.

Corrected block diagram............................................. 1

Added Extended Precision Normal or Instruction Word (48

Bits) to Table 4 and Table 5 ......................................... 7

Revised VCO specification in Clock Input .....................20

Rev. E | Page 3 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

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GENERAL DESCRIPTION

The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs
are members of the SIMD SHARC family of DSPs featuring
Analog Devices Inc., Super Harvard Architecture. The
ADSP-2126x is source code compatible with the ADSP-21160
and ADSP-21161 DSPs as well as with first generation ADSP­2106x SHARC processors in SISD (single-instruction, single­data) mode. Like other SHARC DSPs, the ADSP-2126x are
32-bit/40-bit floating-point processors optimized for high per­formance audio applications with dual-ported on-chip SRAM,
mask-programmable ROM, multiple internal buses to eliminate
I/O bottlenecks, and an innovative digital audio interface.

Table 1 shows performance benchmarks for the processors run-

ning at 200 MHz. Table 2 shows the features of the individual
product offerings.

Table 1. Processor Benchmarks (at 200 MHz)

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]
Divide (y/x)
Inverse Square Root

1

Assumes two files in multichannel SIMD mode.

1

1

(at 200 MHz)

61.3 μs

3.3 ns

13.3 ns

30 ns

53.3 ns
20 ns

30 ns

As shown in the functional block diagram in Figure 1 on Page 1,
the ADSP-2126x uses two computational units to deliver a 5 to
10 times performance increase over previous SHARC proces­sors on a range of DSP algorithms. Fabricated in a state-of-the­art, high speed, CMOS process, the ADSP-2126x DSPs achieve
an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at
150 MHz. With its SIMD computational hardware, the
ADSP-2126x can perform 1200 MFLOPS running at 200 MHz,
or 900 MFLOPS running at 150 MHz.

Table 2. ADSP-2126x SHARC Processor Features

Feature ADSP-21261 ADSP-21262 ADSP-21266

RAM 1M bit 2M bit 2M bit

ROM 3M bit 4M bit 4M bit

Audio Decoders

1

in ROM

DMA Channels 18 22 22

SPORTs 4 6 6

Package 136-ball BGA

1

For information on available audio decoding algorithms, see Table 3 on Page 6.

No No Yes

144-lead LQFP

136-ball BGA
144-lead LQFP

136-ball BGA
144-lead LQFP

The ADSP-2126x continues SHARC’s industry-leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2M bit dual-ported SRAM memory, 4M bit
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and digital audio interface.

The block diagram of the ADSP-2126x on Page 1 illustrates the
following architectural features:

• Two processing elements, each containing an ALU, multi­plier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

• Three programmable interval timers with PWM genera­tion, PWM capture/pulse width measurement, and
external event counter capabilities

• On-chip dual-ported SRAM (up to 2M bit)

• On-chip dual-ported, mask-programmable ROM
(up to 4M bit)

• JTAG test access port

• 8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals

• DMA controller

• Six full-duplex serial ports (four on the ADSP-21261)

• SPI-compatible interface

• Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
programmable timers, and a flexible signal routing unit
(SRU)

Figure 2 shows one sample configuration of a SPORT using the

precision clock generator to interface with an I

2

S DAC with a much lower jitter clock than the serial port

I
would generate itself. Many other SRU configurations are

2

S ADC and an

possible.

FAMILY CORE ARCHITECTURE

The ADSP-2126x is code compatible at the assembly level with
the ADSP-2136x and ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-2126x shares architec­tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.

SIMD Computational Engine

The ADSP-2126x contain two computational processing ele­ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY

Rev. E | Page 4 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

DAI

SPORT 5

SPO RT4

SPORT3

SPO RT2

SP ORT 1

SPORT0

SCL K0

SD0A

SFS0

SD0B

SRU

DA I_ P 1
DAI_P2
DAI_P3

DA I_ P1 8

DA I_ P19

DA I_P 20

3

CLOCK

2
2

CLKIN
XTA L

CLK_CFG1–0
BOOTCFG1–0

FLAG 3–1

ADDR

PARALLEL

PO RT

RA M , R O M

BOOT ROM

I/O D EVIC E

OE

DA TA

WE

RD

WR

CLKOUT

ALE

AD15–0

LATCH

RESE T JTAG

ADSP-21266

ADDRESS

DATA

CONTROL

CS

FL A G0

PCGB

PCG A

CLK
FS

ADC

(OPTIONAL)

CLK

FS

SDAT

DAC

(OPTIONAL)

CLK

FS

SDAT

6

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Figure 2. ADSP-21266 System Sample Configuration

and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele­ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive audio
algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing

Rev. E | Page 5 of 48 | July 2008

elements. These computation units support IEEE 32-bit single
precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har­vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2126x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-2126x’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a
single cycle.

ADSP-21261/ADSP-21262/ADSP-21266

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Instruction Cache

The ADSP-2126x includes an on-chip instruction cache that
enables three-bus operation to fetch an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The ADSP-2126x’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program­ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-2126x contain
sufficient registers to allow the creation of up to 32 circular buff­ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over­head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-2126x can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­ing up to four 32-bit values from memory—all in a single
instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-2126x adds the following architectural features to
the SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21262 and ADSP-21266 contain two megabits of
internal SRAM and four megabits of internal mask-program­mable ROM. The ADSP-21261 contain one megabit of internal
SRAM and three megabits of internal mask-programmable
ROM. Each block can be configured for different combinations
of code and data storage (see memory maps, Table 4 and

Table 5). Each memory block is dual-ported for single-cycle,

independent accesses by the core processor and I/O processor.
The dual-ported memory, in combination with three separate
on-chip buses, allows two data transfers from the core and one
from the I/O processor, in a single cycle.

The ADSP-2126x is available with a variety of multichannel
surround sound decoders, preprogrammed in ROM memory.

Table 3 shows the configuration of decoder algorithms.

Table 3. Multichannel Surround Sound Decoder Algorithms
in On-Chip ROM

Algorithms B ROM C ROM D ROM

PCM Yes Yes Yes
AC-3 Yes Yes Yes
DTS 96/24 v2.2 v2.3 v2.3
AAC (LC) Yes Yes Coefficients only
WMAPRO 7.1 96 KHz No No Yes
MPEG2 BC 2ch Yes Yes No
Noise Yes Yes Yes
DPL2x/EX DPL2 Yes Yes
Neo:6/ES (v2.5046) Yes Yes Yes

The ADSP-2126x’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ­ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float­ing-point storage format is supported that effectively doubles
the amount of data that can be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for­mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.

Rev. E | Page 6 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

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Table 4. Internal Memory Space (ADSP-21261)

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Block 0 SRAM
0x0004 0000–0x0004 1FFF

Reserved
0x0004 2000–0x0005 7FFF

Block 0 ROM
0x0005 8000–0x0002 FFFF

Reserved
0x0005 3000–0x0005 FFFF

Block 1 SRAM
0x0006 0000–0x0006 1FFF

Reserved
0x0006 2000–0x0007 7FFF

Block 1 ROM
0x0007 8000–0x0007 DFFF

Reserved
0x0007 E000–0x0007 FFFF

Extended Precision Normal or
Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 SRAM
0x0008 0000–0x0008 2AAA

Reserved Reserved

Block 0 ROM
0x000A 0000–0x000A 7FFF

Reserved Reserved

Block 1 SRAM
0x000C 0000–0x000C 2AAA

Reserved Reserved

Block 1 ROM
0x000E 0000–0x000E 7FFF

Reserved Reserved

Table 5. Internal Memory Space (ADSP-21262/ADSP-21266)

Block 0 SRAM
0x0008 0000–0x0008 3FFF

0x0008 4000–0x000A FFFF

Block 0 ROM
0x000B 0000–0x000B BFFF

0x000B C000–0x000B FFFF

Block 1 SRAM
0x000C 0000–0x000C 3FFF

0x000C 4000–0x000E FFFF

Block 1 ROM
0x000F 0000–0x000F BFFF

0x000F C000–0x000F FFFF

Block 0 SRAM
0x0010 0000–0x0010 7FFF

Reserved
0x0010 8000–0x0015 FFFF

Block 0 ROM
0x0016 0000–0x0017 7FFF

Reserved
0x0017 8FFF–0x0017 FFFF

Block 1 SRAM
0x0018 0000–0x0018 7FFF

Reserved
0x0018 8000–0x001D FFFF

Block 1 ROM
0x001E 0000–0x001F 7FFF

Reserved
0x0000

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Block 0 SRAM
0x0004 0000–0x0004 3FFF

Reserved
0x0004 4000–0x0005 7FFF

Block 0 ROM
0x0005 8000–0x0005 FFFF

Block 1 SRAM
0x0006 0000–0x0006 3FFF

Reserved
0x0006 4000–0x0007 7FFF

Block 1 ROM
0x0007 8000–0x0007 FFFF

Extended Precision Normal or
Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 SRAM
0x0008 0000–0x0008 5555

Reserved Reserved

Block 0 ROM
0x000A 0000–0x000A AAAA

Block 1 SRAM
0x000C 0000–0x000C 5555

Reserved Reserved

Block 1 ROM
0x000E 0000–0x000E AAAA

DMA Controller

The ADSP-2126x’s on-chip DMA controller allows zero-over­head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul­taneously executing its program instructions. DMA transfers
can occur between the ADSP-2126x’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
port, the IDP (input data port), parallel data acquisition port
(PDAP), or the parallel port. Up to 22 channels of DMA are
available on the ADSP-2126x—one for the SPI interface, 12 via

Block 0 SRAM
0x0008 0000–0x0008 7FFF

0x0008 8000–0x000A FFFF

Block 0 ROM
0x000B 0000–0x000B FFFF

Block 1 SRAM
0x000C 0000–0x000C 7FFF

0x000C 8000–0x000E FFFF

Block 1 ROM
0x000F 0000–0x000F FFFF

the serial ports, eight via the input data port, and one via the
processor’s parallel port. Programs can be downloaded to the
ADSP-2126x using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans­fers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The digital audio interface provides the ability to connect vari­ous peripherals to any of the SHARC DSP’s DAI pins
(DAI_P20–1).

Block 0 SRAM
0x0010 0000–0x0010 FFFF

Reserved
0x0011 0000–0x0015 FFFF

Block 0 ROM
0x0016 0000–0x0017 FFFF

Block 1 SRAM
0x0018 0000–0x0018 FFFF

Reserved
0x0019 0000–0x001D FFFF

Block 1 ROM
0x001E 0000–0x001F FFFF

Rev. E | Page 7 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

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Connections are made using the signal routing unit (SRU,
shown in the block diagram on Page 1).

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon­figurable signal paths.

The DAI also includes six serial ports, two precision clock gen­erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the ADSP-2126x core, configurable as either eight
channels of I
20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-2126x’s serial ports.

For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.

2

S or serial data, or as seven channels plus a single

Serial Ports

The ADSP-2126x features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the Analog
Devices AD183x family of audio codecs, ADCs, and DACs. The
serial ports are made up of two data lines, a clock, and frame
sync. The data lines can be programmed to either transmit or
receive and each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/sec for a 200 MHz core and 37.5M bits/sec for a
150 MHz core. Serial port data can be automatically transferred
to and from on-chip memory via a dedicated DMA. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig­nals while the other SPORT provides two receive signals. The
frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

2

• I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle, two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­ious attributes of this mode.

Each of the serial ports supports the left-justified sample-pair
and I
monly used by audio codecs, ADCs, and DACs) with two data
pins, allowing four left-justified sample-pair or I

2

S protocols (I2S is an industry-standard interface com-

2

S channels

(using two stereo devices) per serial port with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.

Serial Peripheral (Compatible) Interface

The serial peripheral interface is an industry-standard synchro­nous serial link, enabling the ADSP-2126x SPI-compatible port
to communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-2126x SPI-compatible peripheral
implementation also features programmable baud rates at up to
50 MHz for a core clock of 200 MHz and up to 37.5 MHz for a
core clock of 150 MHz, clock phases, and polarities. The
ADSP-2126x SPI-compatible port uses open-drain drivers to
support a multimaster configuration and to avoid data
contention.

2

S

Parallel Port

The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16­bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/sec, and a clock rate of 150 MHz is equivalent to
50M byte/sec.

DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral­lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.

Tim er s

The ADSP-2126x has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-pur­pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer
expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,

Rev. E | Page 8 of 48 | July 2008

a 32-bit period register, and a 32-bit pulse width register. A sin-

V

DDINT

HIGH-Z FERRITE

BEAD CHIP

A

VDD

A

VSS

100nF 10 nF 1nF

ADSP-212xx

LOCATE ALL COMPONENTS

CLOSE TO A

VDD

AND A

VSS

PINS

www.BDTIC.com/ADI

gle control and status register enables or disables all three
general-purpose timers independently.

ROM-Based Security

The ADSP-2126x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter­nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or test access port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.

Program Booting

The internal memory of the ADSP-2126x boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOT_CFG1–0) pins.

Phase-Locked Loop

The ADSP-2126x uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power-up, the
CLK_CFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft­ware control. The ratios are made up of software configurable
numerator values from 1 to 64 and software configurable divi­sor values of 2, 4, 8, and 16.

Power Supplies

The ADSP-2126x has separate power supply connections for the
internal (V

), external (V

DDINT

), and analog (A

DDEXT

VDD/AVSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply pin (A

) powers the

VDD

ADSP-2126x’s internal clock generator PLL. To produce a stable
clock, it is recommended that PCB designs use an external filter
circuit for the A
possible to the A

Figure 3. (A recommended ferrite chip is the muRata

pin. Place the filter components as close as

VDD

VDD/AVSS

pins. For an example circuit, see

BLM18AG102SN1D). To reduce noise coupling, the PCB
should use a parallel pair of power and ground planes for

and GND. Use wide traces to connect the bypass capac-

V

DDINT

itors to the analog power (A
that the A

VDD

and A

pins specified in Figure 3 are inputs to

VSS

the processor and not the analog ground plane on the board—
the A

pin should connect directly to digital ground (GND) at

VSS

) and ground (A

VDD

VSS

) pins. Note

the chip.

ADSP-21261/ADSP-21262/ADSP-21266

Figure 3. Analog Power Filter Circuit

emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces­sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The ADSP-2126x is supported by a complete automotive refer­ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
postprocessing algorithms that are factory programmed into the
ROM space of the ADSP-2126x. SIMD optimized libraries con­sume less processing resources, which results in more available
processing power for custom proprietary features.

The nonvolatile memory of the ADSP-2126x can be configured
to contain a combination of Dolby Digital, Dolby Pro Logic,
Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,
and Neo:6. Multiple S/PDIF and analog I/Os are provided to
maximize end system flexibility.

The ADSP-2126x is also supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2126x.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-2126x
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.

®

†

software and hardware development tools,

®

‡

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-2126x pro­cessor to monitor and control the target board processor during

Rev. E | Page 9 of 48 | July 2008

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel­opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to

• Control how the development tools process inputs and
generate outputs

• Maintain a one-to-one correspondence with the tools’
command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre­emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen­eration of various VDK-based objects, and visualizing the
system state when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica­tions. It also is used for downloading components from the
Web, dropping them into the application, and publishing com­ponent archives from within VisualDSP++. VCSE supports
component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphi­cal and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range o
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

f tools supporting the SHARC processor family. Hard-

EVALUATION KIT

®

Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standal­one unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom-defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, nonin­trusive emulation.

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

†

evaluation plat-

Rev. E | Page 10 of 48 | July 2008

DESIGNING AN EMULATOR-COMPATIBLE DSP

www.BDTIC.com/ADI

BOARD (TARGET)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter­face—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys­tem timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.

ADSP-21261/ADSP-21262/ADSP-21266

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2126x
architecture and functionality. For detailed information on the
ADSP-2126x family core architecture and instruction set, refer
to the ADSP-2126x SHARC DSP Core Manual and the
ADSP-21160 SHARC DSP Instruction Set Reference.

Rev. E | Page 11 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

PIN FUNCTION DESCRIPTIONS

The ADSP-2126x pin definitions are listed below. Inputs identi­fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI).
Inputs identified as asynchronous (A) can be asserted asynchro­nously to CLKIN (or to TCK for TRST). Tie or pull unused
inputs to V

or GND, except for the following:

DDEXT

DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI
and AD15–0 (NOTE: These pins have internal pull-up
resistors.)

The following symbols appear in the Type column of Table 6:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive,
(O/D) = open-drain, and T = three-state.

Table 6. Pin Descriptions

State During and

Pin Type

AD15–0 I/O/T Rev. 0.1 silicon—

RD

WR

ALE O Output only, driven

FLAG3–0 I/O/A Three-state Flag Pins. Each FLAG pin is configured via control bits as either an input or output. As an

DAI_P20–1 I/O/T Three-state with

O Output only, driven

O Output only, driven

After Reset Function

Parallel Port Address/Data. The parallel port and its corresponding DMA unit output

AD15–0 pins are
driven low both
during and after
reset.

Rev. 0.2 silicon—
AD15–0 pins are
three-stated and
pulled high both
during and after
reset.

1

high

1

high

1

low

programmable
pull-up

addresses and data for peripherals on these multiplexed pins. The multiplex state is deter­mined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each
AD pin has a 22.5 kΩ internal pull-up resistor. See Address Data Modes on Page 15 for
details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16
external address bits, A23–8; ALE is used in conjunction with an external latch to retain
the values of the A23–8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address
bits, A15–0; ALE is used in conjunction with an external latch to retain the values of the
A15–0. To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the SYSCTL register and
disable the parallel port. See Table 7 on Page 15 for a list of how the AD15–0 pins map to
the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use
these pins for parallel input data.

Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted.

Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or 16-bit
data to an external memory device. When AD15–0 are flags, this pin remains deasserted.

Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a new
address on the parallel port address pin. On reset, ALE is active high. However, it can be
reconfigured using software to be active low. When AD15–0 are flags, this pin remains
deasserted.

input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI
EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set
(= 1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (= 1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When Bit 18 is set (= 1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When Bit 19 is set (= 1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which
indicates that the system timer has expired.

Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The
SRU configuration registers define the combination of on-chip peripheral inputs or
outputs connected to the pin and to the pin’s output enable. The configuration registers
of these peripherals then determine the exact behavior of the pin. Any input or output
signal present in the SRU can be routed to any of these pins. The SRU provides the
connection from the serial ports, input data port, precision clock generators, and timers
to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull up resistors which are
enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register.

and the TIMEXP signals.

Rev. E | Page 12 of 48 | July 2008

Table 6. Pin Descriptions (Continued)

www.BDTIC.com/ADI

State During and

Pin Type

SPICLK

SPIDS

MOSI

MISO

BOOT_CFG1–0

CLKIN

XTAL

I/O

I

I/O (O/D)

I/O (O/D)

I

I

O

After Reset Function

Three-state with
pull-up enabled,
driven high in SPI­master boot mode

Input only

Three-state with
pull-up enabled,
driven low in SPI­master boot mode

Three-state with
pull-up enabled

Input only

Input only

Output only

2

ADSP-21261/ADSP-21262/ADSP-21266

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the
rate at which data is transferred. The master can transmit data at a variety of baud rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during
data transfers, only for the length of the transferred word. Slave devices ignore the serial
clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift
in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock
edge and sampled on the opposite edge of the clock. Clock polarity and clock phase
relative to data are programmable into the SPICTL control register and define the transfer
format. SPICLK has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected,
MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset
in SPI master boot mode.

Serial Peripheral Inter face Slave Device Select. An active low signal used to select the
DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by
the master device for the slave devices. In multimaster mode, the DSP’s SPIDS signal can
be dri ven by a s lav e de vic e to sig nal t o th e DSP (as SPI master) that an error has occurred,
as some other device is also trying to be the master device. If asserted low when the
device is in master mode, it is considered a multimaster error. For a single master,
multiple-slave configuration where flag pins are used, this pin must be tied or pulled high

on the master device. For ADSP-2126x to ADSP-2126x SPI interaction, any of the

to V

DDEXT

master ADSP-2126x’s flag pins can be used to drive the SPIDS signal on the ADSP-2126x
SPI slave device.

SPI Master Out Slave In. If the ADSP-2126x is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-2126x is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an ADSP-2126x SPI interconnection, the data is shifted out from the MOSI output
pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ
internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are
driven during reset. These pins are not three-stated during reset in SPI master boot mode.

SPI Master In Slave Out. If the ADSP-2126x is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-2126x is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data.
In an ADSP-2126x SPI interconnection, the data is shifted out from the MISO output pin
of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal
pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL
register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI slaves, the DSP’s MISO pin can be disabled by setting (=1) Bit
5 (DMISO) of the SPICTL register.

Boot Configuration Select. Selects the boot mode for the DSP. The BOOT_CFG pins must
be valid before reset is asserted. See Table 8 on Page 15 for a description of the boot
modes.

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2126x clock input. It
configures the ADSP-2126x to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-2126x to use the external clock source such as an external clock
oscillator. The core is clocked either by the PLL output or this clock input depending on
the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below
the specified frequency.

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

Rev. E | Page 13 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

Table 6. Pin Descriptions (Continued)

State During and

Pin Type

CLK_CFG1–0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Tabl e 9 for a

RESETOUT/ O Output only Reset Out/Local Clock Out. Drives out the core reset signal to an external device.
CLKOUT CLKOUT can also be configured as a reset out pin (RESETOUT). The functionality can be

RESET I/A Input only Processor Reset. Resets the ADSP-2126x to a known state. Upon deassertion, there is a

TCK I Input only

TMS I/S Three-state with

TDI I/S Three-state with

TDO O Three-state
TRST I/A Three-state with

EMU O (O/D) Three-state with

V

V

A

A

DDINT

DDEXT

VDD

VSS

P Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

P I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP

P Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock

G Analog Power Supply Return.

GND G Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

1

RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

2

Output only is a three-state driver with its output path always enabled.

3

Input only is a three-state driver, with both output path and pull-up disabled.

4

Three-state is a three-state driver, with pull-up disabled.

After Reset Function

description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL
register. The default is reset out.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.

3

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-2126x.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

pull-up enabled

pull-up enabled

4

22.5 kΩ internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5

kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.
Te st R es e t ( J TAG ) . Resets the test state machine. TRST must be asserted (pulsed low) after

pull-up enabled

power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 kΩ internal
pull-up resistor.

Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools

pull-up enabled

product line of JTAG emulators target board connector only. EMU has a

22.5 kΩ internal pull-up resistor.

(13 pins on the BGA package, 32 pins on the LQFP package).

package).

generator). This pin has the same specifications as V
circuitry is required. For more information, see Power Supplies on Page 9.

, except that added filtering

DDINT

Rev. E | Page 14 of 48 | July 2008

ADSP-21261/ADSP-21262/ADSP-21266

www.BDTIC.com/ADI

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the
SYSCTL register and disable the parallel port.

Table 7. AD15–0 to FLAG Pin Mapping

AD Pin Flag Pin

AD0 FLAG8 AD8
AD1 FLAG9 AD9
AD2 FLAG10 AD10
AD3 FLAG11 AD11
AD4 FLAG12 AD12
AD5 FLAG13 AD13
AD6 FLAG14 AD14
AD7 FLAG15 AD15

Boot Modes

Table 8. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 Parallel Port Boot via EPROM
11 Reserved

AD Pin Flag Pin

FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7

ADDRESS DATA MODES

Table 10 shows the functionality of the AD pins for 8-bit and

16-bit transfers to the parallel port. For 8-bit data transfers, ALE
latches address bits A23–A8 when asserted, followed by address
bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit
data transfers, ALE latches address bits A15–A0 when asserted,
followed by data bits D15–D0 when deasserted.

Table 10. Address/Data Mode Selection

EP Data AD7–0 AD15–8
Mode ALE Function Function

8-bit Asserted A15–8 A23–16
8-bit Deasserted D7–0 A7–0
16-bit Asserted A7–0 A15–8
16-bit Deasserted D7–0 D15–8

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 9. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0 Core to CLKIN Ratio

00 3:1
01 16:1
10 8:1
11 Reserved

Rev. E | Page 15 of 48 | July 2008