Analog Devices ADSP-21161N a Datasheet
a
S
DSP Microcomputer
ADSP-21161N
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Wireless Communications,
Graphics, Imaging, Motor-Control, and Telephony
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Code Compatible with All Other SHARC Family DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Serial Ports Offer I
2
S Support Via 8 Programmable and
Simultaneous Receive or Transmit Pins, which
Support up to 16 Transmit or 16 Receive Channels of
Audio
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR
INSTRUCTION
CACHE
32 ⴛ 48-BIT
PROGRAM
SEQUENCER
32
32
64
64
BARREL
SHIFTER
DAG1
8 ⴛ 4 ⴛ 32
BUS
CONNECT
(PX)
MULT
DAG2
8 ⴛ 4 ⴛ 32
DATA
REGISTER
FILE
(PEX)
16 ⴛ 40-BIT
TIMER
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BARREL
SHIFTER
Integrated Peripherals—Integrated I/O Processor,
1M Bit On-Chip Dual-Ported SRAM, SDRAM
Controller, Glueless Multiprocessing Features, and
I/O Ports (Serial, Link, External Bus, SPI, and JTAG)
ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and
40-Bit Floating-Point Formats
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
600 MFLOPs Peak and 400 MFLOPs Sustained
Performance
225-Ball 17 mm
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR DATA ADDR
ADDR DATA DATA
DATA
REGISTER
FILE
(PEY)
16 ⴛ 40-BIT
× 17 mm MBGA Package
I/O PORT
DATA
IOD
64
MULT
ADDR
IOA
18
0
K
1
C
K
O
L
C
B
O
L
B
AND EMULATION
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST PORT
JTAG TEST
GPIO
FLAGS
SDRAM
CONTROLLER
ADDR BUS
MUX
DATA BUS
MUX
6
12
8
24
32
ALU
ALU
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
IOP
REGISTERS
(MEMO RY MAPPED)
CONTROL,
STATUS,&
DATA BUFFERS
I/O PROCESSOR
DMA
CONTROLLER
SERIAL PORTS (4)
LINK PORTS (2)
SPI PORTS (1)
5
16
20
4
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 www.analog.com
Fax:781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADSP-21161N
KEY FEATURES (continued)
1 M Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0,
0.5 M Bit Block 1) for Independent Access by Core
Processor and DMA
200 Million Fixed-Point MACs Sustained Performance
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping with Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and On-Chip
Emulation
Single Instruction Multiple Data (SIMD) Architecture
Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—At Assembly Level, Uses the
Same Instruction Set as Other SHARC DSPs
Parallelism in Buses and Computational Units Enables:
Single-Cycle Execution (with or without SIMD) of: a
Multiply Operation, an ALU Operation, a Dual
Memory Read or Write, and an Instruction Fetch
Transfers Between Memory and Core at Up to Four
32-Bit Floating- or Fixed-Point Words Per Cycle,
Sustained 1.6 Gbytes/s Bandwidth
Accelerated FFT Butterfly Computation through a
Multiply with Add and Subtract
DMA Controller Supports:
14 Zero-Overhead DMA Channels for Transfers between
ADSP-21161N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports,
Link Ports, or Serial Peripheral Interface (SPICompatible)
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
800 M Bytes/s Transfer Rate over IOP Bus
Host Processor Interface to 8-, 16-, and 32-Bit
Microprocessors; the Host Can Directly Read/Write
ADSP-21161N IOP Registers
32-Bit (or up to 48-Bit) Wide Synchronous External Port
Provides:
Glueless Connection to Asynchronous, SBSRAM and
SDRAM External Memories
Memory Interface Supports Programmable Wait State
Generation and Wait Mode for Off-Chip Memory
Up to 50 MHz Operation for Non-SDRAM Accesses
1:2, 1:3, 1:4, 1:6, 1:8 Clock into Core Clock Frequency
Multiply Ratios
24-Bit Address, 32-Bit Data Bus. 16 Additional Data
Lines via Multiplexed Link Port Data Pins Allow
Complete 48-Bit Wide Data Bus for Single-Cycle
External Instruction Execution
Direct Reads and Writes of IOP Registers from Host or
Other 21161N DSPs
62.7 Mega-Word Address Range for Off-Chip SRAM and
SBSRAM Memories
32-48, 16-48, 8-48 Execution Packing for Executing
Instruction Directly from 32-Bit, 16-Bit, or 8-Bit Wide
External Memories
32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data
Packing for DMA Transfers Directly from 32-Bit,
16-Bit, or 8-Bit Wide External Memories to and from
Internal 32-, 48-, or 64-Bit Internal Memory
Can be Configured to have 48-Bit Wide External Data
Bus, if Link Ports are not Used. The Link Port Data
Lines are Multiplexed with the Data Lines D0 to D15
and are Enabled through Control Bits in SYSCON
SDRAM Controller for Glueless Interface to Low Cost
External Memory
Zero Wait State, 100 MHz Operation for Most Accesses
Extended External Memory Banks (64 M Words) for
SDRAM Accesses
Page Sizes up to 2048 Words
An SDRAM Controller Supports SDRAM in Any and All
Memory Banks
Support for Interface to Run at Core Clock and Half the
Core Clock Frequency
Support for 16 M Bits, 64 M Bits, 128 M Bits, and
256 M Bits with SDRAM Data Bus Configurations of
4, 8, 16, and 32
254 Mega-Word Address Range for Off-Chip SDRAM
Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-21161Ns, Global Memory,
and a Host
Two 8-Bit Wide Link Ports for Point-to-Point
Connectivity Between ADSP-21161Ns
400 M Bytes/s Transfer Rate over Parallel Bus
200 M Bytes/s Transfer Rate Over Link Ports
Serial Ports Provide:
Four 50 M Bit/s Synchronous Serial Ports with
Companding Hardware
8 Bidirectional Serial Data Pins, Configurable as Either a
Transmitter or Receiver
2
S Support, Programmable Direction for 8
I
Simultaneous Receive and Transmit Channels, or Up
to Either 16 Transmit Channels or 16 Receive
Channels
128 Channel TDM Support for T1 and E1 Interfaces
Companding Selection on a Per Channel Basis in TDM
Mode
Serial Peripheral Interface (SPI)
Slave Serial Boot through SPI from a Master SPI Device
Full-Duplex Operation
Master-Slave Mode Multimaster Support
Open-Drain Outputs
Programmable Baud Rates, Clock Polarities and Phases
12 Programmable I/O Pins
1 Programmable Timer
–2– REV. A
ADSP-21161N
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3
ADSP-21161N Family Core Architecture . . . . . . . . . 5
SIMD Computational Engine . . . . . . . . . . . . . . . . 5
Independent, Parallel Computation Units . . . . . . . 5
Data Register File . . . . . . . . . . . . . . . . . . . . . . . . . 5
Single-Cycle Fetch of Instruction and
Four Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Address Generators With Hardware Circular
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 5
ADSP-21161N Memory and I/O Interface Features . 5
Dual-Ported On-Chip Memory . . . . . . . . . . . . . . . 5
Off-Chip Memory and Peripherals Interface . . . . . 6
SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Target Board JTAG Emulator Connector . . . . . . . 7
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Peripheral (Compatible) Interface . . . . . . . . 9
Host Processor Interface . . . . . . . . . . . . . . . . . . . . 9
General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . 9
Program Booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Phase-Locked Loop and Crystal Double Enable . . 9
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Designing an Emulator-Compatible
DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . 10
Additional Information . . . . . . . . . . . . . . . . . . . . . . 11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 12
BOOT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 20
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up Sequencing – Silicon
Revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Read – Bus Master . . . . . . . . . . . . . . . . 27
Memory Write – Bus Master . . . . . . . . . . . . . . . . 28
Synchronous Read/Write – Bus Master . . . . . . . . 29
Synchronous Read/Write – Bus Slave . . . . . . . . . . 30
Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . 31
Asynchronous Read/Write –
Host to ADSP-21161N . . . . . . . . . . . . . . . . . . 33
Three-State Timing – Bus Master, Bus Slave . . . . 35
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 37
SDRAM Interface – Bus Master . . . . . . . . . . . . . 39
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SPI Interface Specifications . . . . . . . . . . . . . . . . . 47
JTAG Test Access Port and Emulation . . . . . . . . 50
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 51
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 51
Output Disable Time . . . . . . . . . . . . . . . . . . . . . 51
Example System Hold Time Calculation . . . . . . . 51
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 52
Environmental Conditions . . . . . . . . . . . . . . . . . . . 52
Thermal Characteristics . . . . . . . . . . . . . . . . . . . 52
225-BALL METRIC MBGA
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . 53
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 55
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
GENERAL DESCRIPTION
The ADSP-21161N SHARC DSP is the first low cost derivative
of the ADSP-21160 featuring Analog Devices Super Harvard
Architecture. Easing portability, the ADSP-21161N is source
code compatible with the ADSP-21160 and with first generation
ADSP-2106x SHARCs in SISD (Single Instruction, Single
Data) mode. Like other SHARC DSPs, the ADSP-21161N is a
32-bit processor that is optimized for high performance DSP
applications. The ADSP-21161N includes a 100 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor with
multiprocessing support, and multiple internal buses to eliminate
I/O bottlenecks.
As was first offered in the ADSP-21160, the ADSP-21161N
offers a Single-Instruction-Multiple-Data (SIMD) architecture.
Using two computational units (ADSP-2106x SHARCs have
one), the ADSP-21161N can double cycle performance versus
the ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power CMOS
process, the ADSP-21161N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21161N can perform 600 million math operations per
second. Table 1 shows performance benchmarks for the
ADSP-21161N.
Table 1. Benchmarks (at 100 MHz)
Speed
Benchmark Algorithm
1024 Point Complex FFT
(at 100 MHz)
171 µs
(Radix 4, with reversal)
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
5 ns
40 ns
1
Matrix Multiply (pipelined)
[3 × 3] × [3 × 1] 30 ns
[4 × 4] × [4 × 1] 37 ns
Divide (y/x) 60 ns
Inverse Square Root 40 ns
1
1
DMA Transfers 800 M bytes/s
1
Specified in SISD mode. Using SIMD, the same benchmark applies for
two sets of computations. For example, two sets of biquad operations can
be performed in the same amount of time as the SISD mode benchmark.
–3–REV. A
ADSP-21161N
The ADSP-21161N continues SHARC’s industry-leading
standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include a 1 M bit dual ported SRAM memory, host
processor interface, I/O processor that supports 14 DMA
channels, four serial ports, two link ports, SDRAM controller,
SPI interface, external parallel bus, and glueless multiprocessing.
The block diagram of the ADSP-21161N on Page 1 illustrates
the following architectural features:
• Two processing elements, each ma de u p of an AL U, M ul-
tiplier, Shifter, and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
• Interval timer
ADSP-21161N
CLOCK
LINK
DEVICES
(2 MAX)
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SPI
COMPATIBLE
DEVICE
(HOST OR SLAVE)
(OPTIONAL)
CLKIN
XTAL
2
CLK_CFG1-0
CLKDBL
EBOOT
LBOOT
3
IRQ2-0
12
FLAG11-0
TIMEXP
RPBA
ID2-0
LXCLK
LXACK
LXDAT7-0
SCLK0
FS0
D0A
D0B
SCLK1
FS1
D1A
D1B
SCLK2
FS2
D2A
D2B
SCLK3
FS3
D3A
D3B
SPICLK
SPIDS
MOSI
MISO
RESET JTAG
ADDR23-0
DATA47-16
SDCL K1-0
DMAR2-1
DMAG2-1
RSTOUT
BMS
BRST
RD
WR
ACK
MS3-0
RAS
CAS
DQM
SDWE
SDCKE
SDA10
CLKOUT
CS
HBR
HBG
REDY
BR6-1
PA
SBTS
7
• On-Chip SRAM (1 M bit)
• SDRAM Controller for glueless interface to SDRAMs
• External port that supports:
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six ADSP-
21161N SHARCs
• Host port read/write of IOP registers
• DMA controller
• Four serial ports
• Two lin k p or ts
• SPI compatible interface
• JTAG test access port
• 12 General-Purpose I/O Pins
Figure 1 shows a typical single-processor system. A multiprocess-
ing system appears in Figure 4 on Page 8.
L
S
S
O
E
R
T
R
N
O
C
A
D
T
D
A
A
D
CS
ADDR
DATA
ADDR
DATA
OE
WE
ACK
CS
DATA
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
MEMORY
AND
PERIPHERALS
(OPTIONAL)
DMA DEVICE
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
CS
ADDR
DATA
SDRAM
(OPTIONAL)
Figure 1. System Diagram
–4– REV. A
ADSP-21161N
ADSP-21161N Family Core Architecture
The ADSP-21161N includes the following architectural features
of the ADSP-2116x family core. The ADSP-21161N is code
compatible at the assembly level with the ADSP-21160, ADSP21060, ADSP-21061, ADSP-21062, and ADSP-21065L.
SIMD Computational Engine
The ADSP-21161N contains two computational processing
elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floatingpoint, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2116x enhanced Harvard
architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred
–
to as R0
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 4). With the ADSP-21161N’s separate
program and data memory buses and on-chip instruction cache,
R15 and in PEY as S0–S15.
the processor can simultaneously fetch four operands (two over
each data bus) and an instruction (from the cache), all in a
single cycle.
Instruction Cache
The ADSP-21161N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This cache
enables full-speed execution of core, looped operations such as
digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators With Hardware Circular Buffers
The ADSP-21161N’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming
of delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs of the ADSP-21161N contain sufficient registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wrap-around, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP21161N can conditionally execute a multiply, an add, and a
subtract in both processing elements, while branching, all in a
single instruction.
ADSP-21161N Memory and I/O Interface Features
The ADSP-21161N adds the following architectural features to
the ADSP-2116x family core:
Dual-Ported On-Chip Memory
The ADSP-21161N contains one megabit of on-chip SRAM,
organized as two blocks of 0.5 M bits. Each block can be configured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dualported memory in combination with three separate on-chip buses
allow two data transfers from the core and one from the I/O
processor, in a single cycle. On the ADSP-21161N, the memory
can be configured as a maximum of 32K words of 32-bit data,
64K words of 16-bit data, 21K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to one
megabit. All of the memory can be accessed as 16-bit, 32-bit,
48-bit, or 64-bit words. A 16-bit floating-point storage format is
supported that effectively doubles the amount of data that may
be stored on-chip. Conversion between the 32-bit floating-point
and 16-bit floating-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data using
the DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers. Using the DM bus and
–5–REV. A
ADSP-21161N
PM bus, with one dedicated to each memory block, assures
single-cycle execution with two data transfers. In this case, the
instruction must be available in the cache.
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMORY
SPACE
IOP REGISTERS
LONG WORD ADDRESSING
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
IOP REGISTERS OF ADSP-21161N
WITH ID = 001
IOP REGISTERS OF ADSP-21161N
WITH ID = 010
IOP REGISTERS OF ADSP-21161N
WITH ID = 011
IOP REGISTERS OF ADSP-21161N
WITH ID = 100
IOP REGISTERS OF ADSP-21161N
WITH ID = 101
IOP REGISTERS OF ADSP-21161N
WITH ID = 110
RESERVED
ADDRESS
0x0000 0000 - 0x0001 FFFF
0x0002 0000 - 0x0002 1FFF (BLK 0)
0x0002 8000 - 0x0002 9FFF (BLK 1)
0x0004 0000 - 0x0004 3FFF (BLK 0)
0x0005 0000 - 0x0005 3FFF (BLK 1)
0x0008 0000 - 0x0008 7FFF (BLK 0)
0x000A 0000 - 0x000A 7FFF (BLK 1)
0x0010 0000 - 0x0011 FFFF
0x0012 0000 - 0x0013 FFFF
0x0014 0000 - 0x0015 FFFF
0x0016 0000 - 0x0017 FFFF
0x0018 0000 - 0x0019 FFFF
0x001A 0000 - 0x001B FFFF
0x001C 0000
0x001F FFFF
ADDRESS
0x0020 0000
MS0
BANK 0
0x00FF FFFF (NON-SDRAM)
0x03FF FFFF (SDRAM)
0x0400 0000
MS1
BANK 1
0x04FF FFFF (NON-SDRAM)
0x07FF FFFF (SDRAM)
0x0800 0000
MS2
BANK 2
0x08FF FFFF (NON-SDRAM)
0x0BFF FFFF (SDRAM)
0x0C00 0000
EXTERNAL MEMORY SPACE
Figure 2. Memory Map
Off-Chip Memory and Peripherals Interface
The ADSP-21161N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 62.7-M word
off-chip address space (254.7-M word if all SDRAM) is included
in the ADSP-21161N’s unified address space. The separate onchip buses—for PM addresses, PM data, DM addresses, DM
data, I/O addresses, and I/O data—are multiplexed at the external
port to create an external system bus with a single 24-bit address
bus and a single 32-bit data bus. Every access to external memory
is based on an address that fetches a 32-bit word. When fetching
an instruction from external memory, two 32-bit data locations
are being accessed for packed instructions. Unused link port lines
–
can also be used as additional data lines DATA15
DATA0,
allowing single-cycle execution of instructions from external
memory, at up to 100 MHz. Figure 3 on Page 7 shows the
alignment of various accesses to external memory.
BANK 3
0x0CFF FFFF (NON-SDRAM)
0x0FFF FFFF (SDRAM)
NOTE: BANK SIZES ARE FIXED
MS3
The external port supports asynchronous, synchronous, and synchronous burst accesses. Synchronous burst SRAM can be
interfaced gluelessly. The ADSP-21161N also can interface gluelessly to SDRAM. Addressing of external memory devices is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. The ADSP-21161N
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to memory
and peripherals with variable access, hold, and disable time
requirements.
SDRAM Interface
The SDRAM interface enables the ADSP-21161N to transfer
data to and from synchronous DRAM (SDRAM) at the core
clock frequency or at one-half the core clock frequency. The
–6– REV. A
ADSP-21161N
K1–
0=0
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to 400 M bytes/s
for 32-bit transfers and 600 M bytes/s for 48-bit transfers.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16 Mb, 64 Mb, 128 Mb, and 256 Mb—
and includes options to support additional buffers between the
ADSP-21161N and SDRAM. The SDRAM interface is
extremely flexible and provides capability for connecting
SDRAMs to any one of the ADSP-21161N’s four external
memory banks, with up to all four banks mapped to SDRAM.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21161N supports pipelining of the address and
control signals to enable such buffering between itself and
multiple SDRAM devices.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21161N
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on SHARC Analog Devices DSP
Tools product line of JTAG emulator operation, see the appropriate Emulator Hardware User’s Guide. For detailed information on the interfacing of Analog Devices JTAG emulators
with Analog Devices DSP products with JTAG emulation ports,
please refer to Engineer to Engineer Note
JTAG Emulation Technical Reference
EE-68: Analog Devices
. Both of these documents can
be found on the Analog Devices website:
http://www.analog.com/dsp/tech_docs.html
DMA Controller
The ADSP-21161N’s on-chip DMA controller enables zerooverhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21161N’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP21161N’s internal memory and its serial ports, link ports, or the
SPI-compatible (Serial Peripheral Interface) port. External bus
packing and unpacking of 32-, 48-, or 64-bit words in internal
memory is performed during DMA transfers from either 8-,
16-, or 32-bit wide external memory. Fourteen channels of DMA
are available on the ADSP-21161N—two are shared between the
SPI interface and the link ports, eight via the serial ports, and
four via the processor’s external port (for host processor, other
ADSP-21161Ns, memory, or I/O transfers). Programs can be
downloaded to the ADSP-21161N using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels
using DMA Request/Grant lines (
DMAR2–1, DMAG2–1
).
Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked
DMA transfers.
DATA 47–1 6
47 4 0 39 32 3 1 24 2 3 16
PROM
BO O T
NOTE:
EXTRA DATA LINE S DATA15–0 ARE ONLY ACCESSIBLE IF LINK PORTS
ARE DISABLED. ENABLE THESE ADDITIONAL DATA L INKS BY SELECTING IPAC
1INSYS CON.
15 8 7 0
DATA15-8
DA TA 1 5–0
L1DATA7–0
8-BIT PACKED DMA DATA
8-BIT PACKED INSTRUCTION
EXECUTION
16-BIT PACKED DMA DATA
16-BIT PACKED INSTRUCTION EXE CUTION
FLOAT OR FIXED, D31–D0,
32-BIT PACKED
32-BIT PACKED INSTRUCTION
48-BIT INSTRUCT ION FETCH
(NO PACKING)
L0DATA7–0
DATA7–0
Figure 3. External Data Alignment Options
Multiprocessing
The ADSP-21161N offers powerful features tailored to
multiprocessing DSP systems. The external port and link ports
provide integrated glueless multiprocessing support.
The external port supports a unified address space (see Figure 2
on Page 6) that enables direct interprocessor accesses of each
ADSP-21161N’s internal memory-mapped (I/O processor) registers. All other internal memory can be indirectly accessed via
DMA transfers initiated via the programming of the IOP DMA
parameter and control registers. Distributed bus arbitration logic
is included on-chip for simple, glueless connection of systems
containing up to six ADSP-21161Ns and a host processor.
Master processor change over incurs only one cycle of overhead.
Bus arbitration is selectable as either fixed or rotating priority.
Bus lock enables indivisible read-modify-write sequences for
semaphores. A vector interrupt is provided for interprocessor
commands. Maximum throughput for interprocessor data
transfer is 400 M bytes/s over the external port.
Two link ports provide a second method of multiprocessing communications. Each link port can support communications to
another ADSP-21161N. The ADSP-21161N, running at
100 MHz, has a maximum throughput for interprocessor communications over the links of 200 M bytes/s. The link ports and
cluster multiprocessing can be used concurrently or
independently.
Link Ports
The ADSP-21161N features two 8-bit link ports that provide
additional I/O capabilities. With the capability of running at
100 MHz, each link port can support 100 M bytes/s. Link port
I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate
independently and simultaneously, with a maximum data
throughput of 200 M bytes/s. Link port data is packed into
48- or 32-bit words and can be directly read by the core processor
–7–REV. A
ADSP-21161N
CLOCK
RESET
ADSP-21161N #4
ADSP-21161N #3
CLKIN
RESET
3
ID2-0
ADDR23-0
DATA47-16
CONTROL
L
S
S
O
E
R
T
R
N
O
C
A
D
T
D
A
A
D
ADSP-21161N #2
CLKIN
RESET
2
ID2-0
ADSP-21161N #1
CLKIN
RESET
1
ID2-0
ADDR23-0
DATA47-16
CONTROL
ADDR23-0
DATA47-16
L
O
R
T
N
O
C
SDCLK1-0
SDCKE
BMS
RD
WR
ACK
MS3-0
SBTS
CS
HBR
HBG
REDY
BR6-2
BR1
RAS
CAS
DQM
SDWE
ADDR
DATA
CS
ADDR
DATA
OE
WE
ACK
CS
ADDR
L
S
S
O
E
R
T
R
N
D
O
D
A
C
DATA
A
T
A
D
RAS
CAS
DQM
WE
CLK
CKE
BOOT
EPROM
(OPTIONAL)
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
SDRAM
(OPTIONAL)
Figure 4. Shared Memory Multiprocessing System
or DMA-transferred to on-chip memory. Each link port has its
own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are
programmable as either transmit or receive.
SDA10
A10
CS
ADDR
DATA
Serial Ports
The ADSP-21161N features four synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. Each serial port is made up of
two data lines, a clock and frame sync. The data lines can be
programmed to either transmit or receive.
–8– REV. A
ADSP-21161N
The serial ports operate at up to half the clock rate of the core,
providing each with a maximum data rate of 50 M bit/s. The serial
data pins are programmable as either a transmitter or receiver,
providing greater flexibility for serial communications. Serial port
data can be automatically transferred to and from on-chip
memory via a dedicated DMA. Each of the serial ports features
a Time Division Multiplex (TDM) multichannel mode, where
two serial ports are TDM transmitters and two serial ports are
TDM receivers (SPORT0 Rx paired with SPORT2 Tx,
SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports
also support the I
commonly used by audio codecs, ADCs and DACs), with two
data pins, allowing four I
devices) per serial port, with a maximum of up to 16 I
2
S protocol (an industry standard interface
2
S channels (using two I2S stereo
2
S channels.
The serial ports permit little-endian or big-endian transmission
formats and word lengths selectable from 3 bits to 32 bits. For
2
S mode, data-word lengths are selectable between 8 bits and 32
I
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard synchronous serial link, enabling the ADSP-21161N SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
a 4-wire interface consisting of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with up
to four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21161N SPI-compatible peripheral
implementation also features programmable baud rate and clock
phase/polarities. The ADSP-21161N SPI-compatible port uses
open drain drivers to support a multimaster configuration and to
avoid data contention.
Host Processor Interface
The ADSP-21161N host interface enables easy connection to
standard 8-bit, 16-bit, or 32-bit microprocessor buses with little
additional hardware required. The host interface is accessed
through the ADSP-21161N’s external port. Four channels of
DMA are available for the host interface; code and data transfers
are accomplished with low software overhead. The host processor
requests the ADSP-21161N’s external bus with the host bus
request (
), host bus grant (
HBG
), and chip select (CS)
HBR
signals. The host can directly read and write the internal IOP
registers of the ADSP-21161N, and can access the DMA channel
setup and message registers. DMA setup via a host would allow
it to access any internal memory address via DMA transfers.
Vector interrupt support provides efficient execution of host
commands.
General-Purpose I/O Ports
The ADSP-21161N also contains 12 programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21161N can be booted at
system power-up from either an 8-bit EPROM, a host processor,
the SPI interface, or through one of the link ports. Selection of
BMS
the boot source is controlled by the Boot Memory Select (
),
EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.
8-, 16-, or 32-bit host processors can also be used for booting.
Phase-Locked Loop and Crystal Double Enable
The ADSP-21161N uses an on-chip Phase-Locked Loop (PLL)
–
to generate the internal clock for the core. The CLK_CFG1
0
pins are used to select ratios of 2:1, 3:1, and 4:1. In addition to
the PLL ratios, the
ratio options. The (1
CLKDBL
×/2×
pin can be used for more clock
CLKIN) rate set by the
CLKDBL
pin determines the rate of the PLL input clock and the rate at
which the external port operates. With the combination of
CLK_CFG1
CLKDBL
, ratios of 2:1, 3:1, 4:1, 6:1, and
–
0 and
8:1 between the core and CLKIN are supported. See also
Figure 10 on Page 20.
Power Supplies
The ADSP-21161N has separate power supply connections for
the analog (AV
) power supplies. The internal and analog supplies must
(V
DDEXT
/AGND), internal (V
DD
), and external
DDINT
meet the 1.8 V requirement. The external supply must meet the
3.3 V requirement. All external supply pins must be connected
to the same supply.
Note that the analog supply (AV
) powers the ADSP-21161N’s
DD
clock generator PLL. To produce a stable clock, provide an
external circuit to filter the power input to the AV
pin. Place
DD
the filter as close as possible to the pin. For an example circuit,
see Figure 5. To prevent noise coupling, use a wide trace for the
analog ground (AGND) signal and install a decoupling capacitor
as close as possible to the pin.
V
DDINT
Figure 5. Analog Power (AVDD) Filter Circuit
Development Tools
10
0.1F
AGND
0.01F
AV
DD
The ADSP-21161N is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++
1
development environment. The
same emulator hardware that supports other ADSP-21xxx DSPs,
also fully emulates the ADSP-21161N.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
1
VisualDSP++ is a registered trademark of Analog Devices, Inc.
–9–REV. A
ADSP-21161N
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathematical functions. Two key points for these tools are:
• Compiled ADSP-21161N C/C++ code efficiency—The
compiler has been developed for efficient translation of
C/C++ code to ADSP-21161N assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
• ADSP-2106x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-21161N.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-21xxx
development tools, including the syntax highlighting in the
VisualDSP++ editor. This capability permits:
• Controlling how the development tools process inputs
and generate outputs.
• Maintaining a one-to-one correspondence with the tool’s
command line switches.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-21161N processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-21xxx processor family. Hardware
tools include ADSP-21xxx PC plug-in cards. Third Party
software tools include DSP libraries, real-time operating systems,
and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices DSP Tools family of emulators are tools that
every DSP developer needs to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The emulator
uses the TAP to access the internal features of the DSP, allowing
the developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be halted
to send data and commands, but once an operation has been
completed by the emulator, the DSP system is set running at full
speed with no impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in Figure 6. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
×
square post header, set on 0.1"
0.1" spacing, with a minimum
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
As can be seen in Figure 6, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TRST
, and
EMU
TDO,
used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and
BTRST
that are optionally used for board-
level (boundary scan) testing.
12
GND
KEY (NO PIN)
BTMS
BTCK
BTRST TRST
34
56
78
910
11 12
BTDI
13 14
GND
TOP VIEW
EMU
GND
TMS
TCK
TDI
TDO
Figure 6. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
When the emulator is not connected to this header, place jumpers
across BTMS, BTCK,
BTRST
, and BTDI as shown in Figure 7.
This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.
–10– REV. A
ADSP-21161N
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
12
34
56
78
910
9
11 12
13 14
TOP VIEW
EMU
GND
TMS
TCK
TRST
TDI
TDO
Figure 7. JTAG Target Board Connector with No Local Boundary Scan
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector at the
14-pin target end. Figure 9 displays the keep-out area for a target
board header. The keep-out area enables the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.025" square
post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan chains,
signal buffering, signal termination, and emulator pod logic, see
0.64 "
0.88"
0.24"
Figure 8. JTAG Pod Connector Dimensions
0.10"
0.1 5"
Figure 9. JTAG Pod Connector Keep-Out Area
EE-68: Analog Devices JTAG Emulation Technical Reference
the
on
the Analog Devices website (www.analog.com)—use site search
on “EE-68”. This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-21161N
architecture and functionality. For detailed information on the
ADSP-2116x Family core architecture and instruction set, refer
ADSP-21161 SHARC DSP Hardware Reference
to the
ADSP-21160 SHARC DSP Instruction Set Reference
and the
.
–11–REV. A
ADSP-21161N
PIN FUNCTION DESCRIPTIONS
ADSP-21161N pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
TRST
to CLKIN (or to TCK for
or GND, except for the following:
V
DDEXT
• ADDR23–0, DATA47–0, BRST, CLKOUT (Note:
These pins have a logic-level hold circuit enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)
(Note: These pins have a pull-up enabled on the ADSP21161N DSP with ID2–0 = 00x.)
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note:
See Link Port Buffer Control Register Bit definitions in
the ADSP-21161N SHARC DSP Hardware Reference.)
• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,
TMS,TRST, TDI (Note: These pins have a pull-up.)
Table 2. Pin Function Descriptions
Pin Type Function
ADDR23–0 I/O/T External Bus Address. The ADSP-21161N outputs addresses for external memory and
DATA47
MS3–0 I/O/T Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-
RD I/O/T Memor y Read Strobe. RD is asser ted whenever ADSP-21161N reads a word from external
–16 I/O/T External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these
).Tie or pull unused inputs to
peripherals on these pins. In a multiprocessor system the bus master outputs addresses for
read/writes of the IOP registers of other ADSP-21161Ns while all other internal memory
resources can be accessed indirectly via DMA control (that is, accessing IOP DMA parameter
registers). The ADSP-21161N inputs addresses when a host processor or multiprocessing
bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0
pins maintains the input at the level it was last driven. This latch is only enabled on the
ADSP-21161N with ID2
pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the DSP’s
DATA47
on the ADSP-21161N with ID2
Note: DATA15
the link ports are disabled and will not be used. In addition, DATA7
L0DAT7
execution of 48-bit instructions from external SBSRAM (system clock speed-exter nal port), SRAM
(system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The
IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1
to enable this full instruction Width/No-packing Mode of operation.
sponding banks of external memory. Memory bank sizes are fixed to 16 M words for nonSDRAM and 64 M words for SDRAM. The MS3–0 outputs are decoded memory address
lines. In asynchronous access mode, the MS3–0 outputs transition with the other address
outputs. In synchronous access modes, the MS3–0 outputs assert with the other address
lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted.
In a multiprocessor system, the MSx signals are tracked by slave SHARCs. The internal
addresses 24 and 25 are zeros and 26 and 27 are decoded into MS3–0.
memory or from the IOP registers of other ADSP-21161Ns. External devices, including
other ADSP-21161Ns, must assert RD for reading from a word of the ADSP-21161N IOP
register memory. In a multiprocessing system, RD is driven by the bus master. RD has a
20 kΩ internal pull-up resistor that is enabled for DSPs with ID2
–16 pins maintains the input at the level it was last driven. This latch is only enabled
–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if
–0) can also be used to extend the data bus if the link ports are not used. This enables
–0=00x.
The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
SBTS
Ω
on all
is
(O/D) = Open Drain, and T = Three-State (when
asserted or when the ADSP-21161N is a bus slave).
Unlike previous SHARC processors, the ADSP-21161N
contains internal series resistance equivalent to 50
input/output drivers except the CLKIN and XTAL pins.
Therefore, for traces longer than six inches, external series
resistors on control, data, clock, or frame sync pins are not
required to dampen reflections from transmission line effects for
point-to-point connections. However, for more complex
networks such as a star configuration, series termination is still
recommended.
–0=00x.
–0 pins (multiplexed with
–0=0x1)
–0=00x.
–12– REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin Type Function
WR I/O/T Memor y Write Low Strobe. WR is asser ted when ADSP-21161N writes a word to external
memory or IOP registers of other ADSP-21161Ns. External devices must assert WR for
writing to ADSP-21161N IOP registers. In a multiprocessing system, the bus master drives
WR. WR has a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2
BRST I/O/T Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data
associated with consecutive addresses is being read or written. A slave device samples the
initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-21161N in a multiprocessor
environment can read slave external port buffers (EPBx) using the burst protocol. BRST is
asserted after the initial access of a burst transfer. It is asserted for every cycle after that,
except for the last data request cycle (denoted by RD or WR asserted and BRST negated).
A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven.
This latch is only enabled on the ADSP-21161N with ID2
ACK I/O/S Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21161N deasserts
ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has
a 20 kΩ internal pull-up resistor that is enabled during reset or on DSPs with ID2
SBTS I/S Suspend Bus and Three-State. External devices can assert SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21161N attempts to access external memory while SBTS is asserted, the
processor will halt and the memory access will not be completed until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21161N deadlock.
CAS I/O/T SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx,
and sometimes SDA10, defines the operation for the SDRAM to perform.
RAS I/O/T SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and
sometimes SDA10, defines the operation for the SDRAM to perform.
SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a
precharge command and during SDRAM power-up initialization.
SDCLK0 I/O/S/T SDRAM Clock Output 0. Clock for SDRAM devices.
SDCLK1 O/S/T SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of offchip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data
sheet supplied with the SDRAM device.
SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses or host accesses. This pin replaces the DSP’s A10 pin only during SDRAM
accesses.
IRQ2–0 I/A Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
FLAG11
TIMEXP O Timer Expired. Asserted for four core clock cycles when the timer is enabled and
HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, it
can be tested as a condition. As an output, it can be used to signal external peripherals.
TCOUNT decrements to zero.
21161N’s external bus. When HBR is asserted in a multiprocessing system, the ADSP21161N that is bus master will relinquish the bus and assert HBG. To relinquish the bus,
the ADSP-21161N places the address, data, select, and strobe lines in a high impedance
state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multiprocessing
system.
–0=00x.
–0=00x.
–0=00x.
–13–REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin Type Function
HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor
may take control of the external bus. HBG is asserted (held low) by the ADSP-21161N until
HBR is released. In a multiprocessing system, HBG is output by the ADSP-21161N bus
master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 t
To avoid erroneous grants, HBG should be pulled up with a 20kΩ to 50kΩ external resistor.
CS I/A Chip Select. Asserted by host processor to select the ADSP-21161N.
REDY O (O/D) Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to
a host access of its IOP registers when CS and HBR inputs are asserted.
DMAR1 I/A DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services. DMAR1 has a 20 kΩ internal pull-up resistor that is enabled for DSPs with
–0=00x.
ID2
DMAR2 I/A DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services. DMAR2 has a 20 kΩ internal pull-up resistor that is enabled for DSPs with
–0=00x.
ID2
DMAG1 O/T DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20 kΩ
internal pull-up resistor that is enabled for DSPs with ID2
DMAG2 O/T DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20 kΩ
internal pull-up resistor that is enabled for DSPs with ID2
BR6–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for
bus mastership. An ADSP-21161N only drives its own BRx line (corresponding to the value
of its ID2
ADSP-21161Ns, the unused BRx pins should be pulled high; the processor's own BRx line
must not be pulled high or low because it is an output.
BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is
current bus master of the shared external bus. The ADSP-21161N drives BMSTR high only
while it is the bus master. In a single-processor system (ID=000), the processor drives this
pin high. This pin is used for debugging purposes.
–0IMultiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used
ID2
by ADSP-21161N. ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on.
Use ID=000 or ID =001 in single-processor systems. These lines are a system configuration
selection that should be hardwired or only changed at reset.
RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP21161N. If the value of RPBA is changed during system operation, it must be changed in
the same CLKIN cycle on every ADSP-21161N.
PA I/O/T Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt
background DMA transfers and gain access to the external bus. PA is connected to all ADSP21161Ns in the system. If access priority is not required in a system, the PA pin should be
left unconnected. PA has a 20 kΩ internal pull-up resistor that is enabled for DSPs with
ID2
DxA I/O Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an
internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output
to transmit serial data, or as an input to receive serial data.
DxB I/O Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an
internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output
to transmit serial data, or as an input to receive serial data.
SCLKx I/O Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal
pull-up resistor. This signal can be either internally or externally generated.
–0 inputs) and monitors all others. In a multiprocessor system with less than six
–0=00x.
–0=00x.
–0=00x.
(1 CLKIN cycle).
CK
–14– REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin Type Function
FSx I/O Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates
shifting of serial data. This signal is either generated internally or externally. It can be active
high or low or an early or a late frame sync, in reference to the shifting of serial data.
SPICLK I/O Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the
rate at which data is transferred. The master may transmit data at a variety of baud rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during
data transfers, only for the length of the transferred word. Slave devices ignore the serial
clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and
shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one
clock edge of the clock and sampled on the opposite edge of the clock. Clock polarity and
clock phase relative to data are programmable into the SPICTL control register and define
the transfer format. SPICLK has a 50 kΩ internal pull-up resistor.
SPIDS I Serial Peripheral Interface Slave Device Select. An active low signal used to enable
slave devices. This input signal behaves like a chip select, and is provided by the master device
for the slave devices. In multimaster mode SPIDS signal can be asserted to a master device
to signal that an error has occurred, as some other device is also trying to be the master
device. If asserted low when the device is in master mode, it is considered a multimaster
error. For a single-master, multiple-slave configuration where FLAG3
must be tied or pulled high to V
21161N SPI interaction, any of the master ADSP-21161N’s FLAG3
drive the SPIDS signal on the ADSP-21161N SPI slave device.
MOSI I/O (o/d) SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21161N is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data.
In an ADSP-21161N SPI interconnection, the data is shifted out from the MOSI output pin
of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal pullup resistor.
MISO I/O (o/d) SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21161N is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In
an ADSP-21161N SPI interconnection, the data is shifted out from the MISO output pin
of the slave and shifted into the MISO input pin of the master. MISO has an internal pullup resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time.
LxDAT7
[DATA15
LxCLK I/O Link Port Clock (Link Ports 0
LxACK I/O Link Port Acknowledge (Link Ports 0
EBOOT I EPROM Boot Select. For a description of how this pin operates, see the table in the BMS
LBOOT I Link Boot. For a description of how this pin operates, see the table in the BMS pin
–0
–0]
I/O
[I/O/T]
Link Port Data (Link Ports 0
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when
used as a data pin; or a 20 kΩ internal pull-down resistor that is enabled or disabled by the
LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LxPDRDE bit of the LCTL register.
Note: L1DAT7
DATA7
data lines for executing instructions at up to the full clock rate from external memory. See
DATA47
resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
50 kΩ resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
pin description. This signal is a system configuration selection that should be hardwired.
description. This signal is a system configuration selection that should be hardwired.
–0 pins. If link ports are disabled and are not used, these pins can be used as additional
–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the
–16 for more information.
–1).
on the master device. For ADSP-21161N to ADSP-
DDEXT
–1). Each LxCLK pin has an internal pull-down 50 kΩ
–1). Each LxACK pin has an internal pull-down
–0 are used, this pin
–0 pins can be used to
–15–REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin Type Function
BMS I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins (see Table 4). This input is a system configuration selection that should be
hardwired. For Host and PROM boot, DMA channel 10 (EPB0) is used. For Link boot and
SPI boot, DMA channel 8 is used.
Three-state only in EPROM boot mode (when BMS is an output).
CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input.
It configures the ADSP-21161N to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-21161N to use the external clock source such as an external clock
oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The
instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at powerup via the CLK_CFG1
specified frequency.
XTAL O Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-
21161N’s internal clock oscillator or to disable it to use an external clock source. See CLKIN.
CLK_CFG1-0 I Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal
to n × PLLICLK where n is user selectable to 2, 3, or 4, using the CLK_CFG1
These pins can also be used in combination with the CLKDBL pin to generate additional
core clock rates of 6 × CLKIN and 8 × CLKIN (see the Clock Rate Ratios table in the
CLKDBL description).
CLKDBL I Crystal Double Mode Enable. This pin is used to enable the 2× clock double circuitry,
where CLKOUT can be configured as either 1× or 2× the rate of CLKIN. This CLKIN
double circuit is primarily intended to be used for an external crystal in conjunction with
the internal clock generator and the XTAL pin. The internal clock generator when used in
conjunction with the XTAL pin and an external crystal is designed to support up to a
maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to
generate a 50 MHz input into the PLL. The 2× clock mode is enabled (during RESET low)
by tying CLKDBL to GND, otherwise it is connected to V
example, this enables the use of a 25 MHz crystal to enable 100 MHz core clock rates and
a 50 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1 =0 and CLKDBL=0.
This pin can also be used to generate different clock rate ratios for external clock oscillators
as well. The possible clock rate ratio options (up to 100 MHz) for either CLKIN (external
clock oscillator) or XTAL (crystal input) are shown in Table 3 on Page 17. An 8:1 ratio
enables the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate
and a 25 MHz CLKOUT (external port) clock rate. See also Figure 10 on Page 20.
Note: When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz.
For all other external clock sources, the maximum CLKIN frequency is 50 MHz.
CLKOUT O/T Local Clock Out. CLKOUT is 1× or 2× and is driven at either 1× or 2× the frequency of
CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL
pin. This output is three-stated when the ADSP-21161N is not the bus master or when the
host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT pin maintains
the output at the level it was last driven. This latch is only enabled on the ADSP-21161N
with ID2
If CLKDBL enabled, CLKOUT=2 × CLKIN
If CLKDBL disabled, CLKOUT= 1 × CLKIN
Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 × CLKIN or
2 × CLKIN.
Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.
RESET I/A Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the
program memory location specified by the hardware reset vector address. The RESET input
must be asserted (low) at power-up.
–0=00x.
–0 pins. CLKIN may not be halted, changed, or operated below the
–0 inputs.
for 1× clock mode. For
DDEXT
–16– REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued)
Pin Type Function
RSTOUT
TCK I Tes t Cl o ck ( J TA G). Provides a clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
EMU O (O/D) Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools
V
DDINT
V
DDEXT
AVD D P Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock
AGND G Analog Power Supply Return.
GND G Power Supply Return. (26 pins).
NC Do Not Connect. Reserved pins that must be left open and unconnected. (5 pins
1
RSTOUT exists only for silicon revision 1.2.
2
Four NC pins for silicon revision 1.2, because RSTOUT has been added.
1
O Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in
reset. It is deasserted 4080 cycles after RESET is deasserted indicating that the PLL is stable
and locked.
pull-up resistor.
internal pull-up resistor.
after power-up or held low for proper operation of the ADSP-21161N. TRST has a 20 kΩ
internal pull-up resistor.
product line of JTAG emulators target board connector only. EMU has a 50 kΩ internal
pull-up resistor.
P Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).
P I/O Power Supply. Nominally +3.3 V dc. (13 pins).
generator). This pin has the same specifications as V
, except that added filtering
DDINT
circuitry is required. See Power Supplies on Page 9.
2
).
Table 3. Clock Rate Ratios
CLKDBL CLK_CFG1 CLK_CFG0 Core:CLKIN CLKIN:CLKOUT
10 0 2:1 1:1
10 1 3:1 1:1
11 0 4:1 1:1
00 0 4:1 1:2
00 1 6:1 1:2
01 0 8:1 1:2
BOOT MODES
Table 4. Boot Mode Selection
EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS to EPROM chip select.)
0 0 1 (Input) Host Processor
0 1 0 (Input) Serial Boot via SPI
0 1 1 (Input) Link Port
0 0 0 (Input) No Booting. Processor executes from external memory.
1 1 x (Input) Reserved
–17–REV. A
ADSP-21161N
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
C Grade K Grade
Parameter
V
DDINT
AV
DD
V
DDEXT
V
IH
V
IL
T
CASE
Specifications subject to change without notice.
1
Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1,
DMAR2, BR6–1, ID2–0, RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI,
MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.
2
See Thermal Characteristics on Page 52 for information on thermal specifications.
Internal (Core) Supply Voltage 1.71 1.89 1.71 1.89 V
Analog (PLL) Supply Voltage 1.71 1.89 1.71 1.89 V
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
High Level Input Voltage1
Low Level Input Voltage1 @ V
Case Operating Temperature
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Max Unit
V
OH
V
OL
I
IH
I
IL
I
IHC
I
ILC
I
IKH
I
IKL
I
IKH-OD
I
IKL-OD
I
ILPU
I
OZH
I
OZL
I
OZLPU1
I
OZLPU2
I
OZHPD1
I
OZHPD2
I
DD-INPEAK
I
DD-INHIGH
I
DD-INLOW
I
DD-IDLE
AI
DD
C
IN
Specifications subject to change without notice.
1
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS,
SDCLKx, SDCKE, EMU, XTAL, TDO, CLKOUT, TIMEXP, RSTOUT.
2
See Output Drive Currents on Page 51 for typical drive current capabilities.
3
Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB,
SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx,
CLKDBL, TCK, RESET, CLKIN.
4
Applies to input pins with 20 kΩ internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5
Applies to CLKIN only.
6
Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7
Current required to switch from kept high to low or from kept low to high.
8
Characterized, but not tested.
High Level Output Voltage
Low Level Output Voltage
High Level Input Current3,
Low Level Input Current
CLKIN High Level Input Current
CLKIN Low Level Input Current
Keeper High Load Current
Keeper Low Load Current
Keeper High Overdrive Current6, 7,
Keeper Low Overdrive Current6, 7,
Low Level Input Current Pull-Up
Three-State Leakage Current9,
Three-State Leakage Current
Three-State Leakage Current Pull-Up1
Three-State Leakage Current Pull-Up2
Three-State Leakage Current Pull-Down1
Three-State Leakage Current Pull-Down2
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Idle)
Supply Current (Analog)
Input Capacitance
20, 21
1
1
4
3
6
6
14, 15
15, 16
15, 17
15, 18
19
Test Conditions Min Max Min Max Unit
@ V
2
5
5
8
8
4
10, 11
9, 12, 13
= max 2.0 V
DDEXT
= min –0.5 +0.8 –0.5 +0.8 V
DDEXT
+0.5 2.0 V
DDEXT
DDEXT
–40 +105 0 +85 °C
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
@ V
10
11
@ V
@ V
12
@ V
13
@ V
t
CCLK
t
CCLK
t
CCLK
t
CCLK
= min, IOH = –2.0 mA
DDEXT
= min, IOL = 4.0 mA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = 0 V 10 µA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = 0 V 35 µA
DDEXT
= max, VIN = 2.0 V –250 –100 µA
DDEXT
= max, VIN = 0.8 V 50 200 µA
DDEXT
= max –300 µA
DDEXT
= max 300 µA
DDEXT
= max, VIN = 0 V 350 µA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = 0 V 10 µA
DDEXT
= max, VIN = 0 V 500 µA
DDEXT
= max, VIN = 0 V 350 µA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = V
DDEXT
= 10.0 ns, V
= 10.0 ns, V
= 10.0 ns, V
= 10.0 ns, V
= max 900 mA
DDINT
= max 650 mA
DDINT
= max 500 mA
DDINT
= max 400 mA
DDINT
2
2
max 10 µA
DDEXT
max 35 µA
DDEXT
max 10 µA
DDEXT
max 350 µA
DDEXT
max 500 µA
DDEXT
2.4 V
+0.5 V
@ AVDD = max 10 mA
fIN = 1 MHz, T
= 25°C, VIN = 1.8 V 4.7 pF
CASE
0.4 V
–18– REV. A
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