ANALOG DEVICES ADSP-21161 Service Manual
ADSP-21161 SHARC® Processor
Hardware Reference
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
Revision 4.0, February 2005
Part Number
82-001944-01
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, EZ–Kit Lite, SHARC, the SHARC logo and
VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
CONTENTS
INTRODUCTION
Design Advantages ........................................................................ 1-1
Architecture Overview ................................................................... 1-5
Processor Core ......................................................................... 1-5
Processing Elements ............................................................ 1-6
Program Sequence Control .................................................. 1-7
Processor Internal Buses .................................................... 1-10
Processor Peripherals .............................................................. 1-11
Dual-Ported Internal Memory (SRAM) ............................. 1-11
External Port ..................................................................... 1-12
I/O Processor .................................................................... 1-14
JTAG Port ............................................................................. 1-16
Differences From Previous SHARC Processors ............................. 1-16
Processor Core Enhancements ................................................ 1-17
Processor Internal Bus Enhancements ..................................... 1-17
Memory Organization Enhancements .................................... 1-18
External Port Enhancements .................................................. 1-18
Host Interface Enhancements ............................................ 1-18
Multiprocessor Interface Enhancements ............................. 1-19
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IO Architecture Enhancements .............................................. 1-19
DMA Controller Enhancements ........................................ 1-19
Link Port Enhancements ................................................... 1-19
Instruction Set Enhancements ............................................... 1-20
For More Information About Analog Products ............................. 1-21
For Technical or Customer Support ............................................. 1-22
What’s New in This Manual ....................................................... 1-22
Related Documents .................................................................... 1-23
Conventions ............................................................................... 1-24
PROCESSING ELEMENTS
Setting Computational Modes ...................................................... 2-4
32-Bit (Normal Word) Floating-Point Format .......................... 2-4
40-Bit Floating-Point Format .................................................. 2-5
16-Bit (Short Word) Floating-Point Format ............................. 2-6
32-Bit Fixed-Point Format ....................................................... 2-6
Rounding Mode ...................................................................... 2-7
Using Computational Status ......................................................... 2-8
Arithmetic Logic Unit (ALU) ........................................................ 2-9
ALU Operation ....................................................................... 2-9
ALU Saturation ..................................................................... 2-10
ALU Status Flags ................................................................... 2-11
ALU Instruction Summary .................................................... 2-12
Multiply—Accumulator (Multiplier) ........................................... 2-15
Multiplier Operation ............................................................. 2-15
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Multiplier (Fixed-Point) Result Register ................................. 2-16
Multiplier Status Flags ........................................................... 2-19
Multiplier Instruction Summary ............................................ 2-20
Barrel-Shifter (Shifter) ................................................................. 2-23
Shifter Operation .................................................................. 2-23
Shifter Status Flags ................................................................ 2-27
Shifter Instruction Summary .................................................. 2-28
Data Register File ........................................................................ 2-30
Alternate (Secondary) Data Registers ........................................... 2-32
Multifunction Computations ...................................................... 2-34
Secondary Processing Element (PEy) ............................................ 2-37
Dual Compute Units Sets ...................................................... 2-39
Dual Register Files ................................................................. 2-42
Dual Alternate Registers ........................................................ 2-43
SIMD (Computational) Operations ....................................... 2-43
SIMD And Status Flags ......................................................... 2-46
PROGRAM SEQUENCER
Instruction Pipeline ...................................................................... 3-7
Instruction Cache ......................................................................... 3-8
Using the Cache .................................................................... 3-11
Optimizing Cache Usage ....................................................... 3-11
Branches and Sequencing ............................................................ 3-13
Conditional Branches ............................................................ 3-15
Delayed Branches .................................................................. 3-15
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Restrictions and Limitations When Using
Delayed Branches .......................................................... 3-19
Loops and Sequencing ................................................................ 3-22
Restrictions on Ending Loops ................................................ 3-25
Restrictions on Short Loops .................................................. 3-26
Loop Address Stack ............................................................... 3-29
Loop Counter Stack .............................................................. 3-30
Interrupts and Sequencing .......................................................... 3-34
Sensing Interrupts ................................................................. 3-40
Masking Interrupts ............................................................... 3-41
Latching Interrupts ............................................................... 3-42
Stacking Status During Interrupts .......................................... 3-44
Nesting Interrupts ................................................................. 3-45
Reusing Interrupts ................................................................ 3-47
Interrupting IDLE ................................................................ 3-48
Multiprocessing Interrupts .................................................... 3-49
Timer and Sequencing ................................................................ 3-50
Stacks and Sequencing ................................................................ 3-52
Conditional Sequencing .............................................................. 3-53
SIMD Mode and Sequencing ...................................................... 3-57
Conditional Compute Operations ......................................... 3-58
Conditional Branches and Loops ........................................... 3-59
Conditional Data Moves ....................................................... 3-59
Case 1: Complementary Register Pair Data Move .............. 3-60
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Case 2: Uncomplemented–to–Complementary
Register Move ................................................................ 3-63
Case 3: Complementary Register => Uncomplimentary
Register .......................................................................... 3-64
Case 4: Data Move Involves External Memory or
IOP Memory Space ........................................................ 3-65
Conditional DAG Operations ................................................ 3-66
DATA ADDRESS GENERATOR
Setting DAG Modes ...................................................................... 4-2
Circular Buffering Mode .......................................................... 4-4
Broadcast Loading Mode ......................................................... 4-5
Alternate (Secondary) DAG Registers ....................................... 4-6
Bit-reverse Addressing Mode .................................................... 4-8
Using DAG Status ........................................................................ 4-8
DAG Operations ........................................................................... 4-9
Addressing With DAGs ......................................................... 4-10
Addressing Circular Buffers ................................................... 4-12
Modifying DAG Registers ...................................................... 4-17
Addressing in SISD and SIMD Modes ................................... 4-18
DAGs, Registers, and Memory .................................................... 4-18
DAG Register-to-Bus Alignment ............................................ 4-19
DAG Register Transfer Restrictions ........................................ 4-21
DAG Instruction Summary ......................................................... 4-23
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CONTENTS
MEMORY
Internal Memory .......................................................................... 5-2
External Memory .......................................................................... 5-2
Processor Architecture .................................................................. 5-4
Off-Chip Memory and Peripherals Interface .................................. 5-6
Buses ............................................................................................ 5-7
Internal Address and Data Buses .............................................. 5-7
Internal Data Bus Exchange .................................................. 5-10
ADSP-21161 Memory Map ........................................................ 5-16
Internal Memory ................................................................... 5-16
Multiprocessor Memory ........................................................ 5-19
External Memory .................................................................. 5-22
Shadow Write FIFO .............................................................. 5-24
Memory Organization and Word Size .................................... 5-25
Placing 32-Bit Words and 48-Bit Words ............................ 5-25
Mixing 32-Bit and 48-Bit Words ....................................... 5-26
Restrictions on Mixing 32-Bit and 48-Bit Words ............... 5-28
48-Bit Word Allocation .................................................... 5-31
Setting Data Access Modes .......................................................... 5-32
SYSCON Register Control Bits ............................................. 5-32
Mode 1 Register Control Bits ................................................ 5-34
Mode 2 Register Control Bits ................................................ 5-34
Wait Register Control Bits ..................................................... 5-34
Using Boot Memory .............................................................. 5-35
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Reading From Boot Memory ............................................. 5-35
Writing to Boot Memory ................................................... 5-36
Internal Interrupt Vector Table .............................................. 5-37
Internal Memory Data Width ................................................ 5-37
Memory Bank Size ................................................................ 5-38
External Bus Priority ............................................................. 5-39
Secondary Processor Element (PEy) ........................................ 5-39
Broadcast Register Loads ....................................................... 5-40
Illegal I/O Processor Register Access ....................................... 5-41
Unaligned 64-Bit Memory Access .......................................... 5-41
External Bank X Access Mode ................................................ 5-42
External Bank X Waitstates .................................................... 5-45
Using Memory Access Status ....................................................... 5-46
Accessing Memory ...................................................................... 5-46
Access Word Size ................................................................... 5-47
Long Word (64-Bit) Accesses ............................................. 5-48
Instruction Word (48-Bit) and Extended-Precision
Normal Word (40-Bit) Accesses ...................................... 5-50
Normal Word (32-Bit) Accesses ......................................... 5-50
Short Word (16-Bit) Accesses ............................................ 5-51
SISD, SIMD, and Broadcast Load Modes ............................... 5-51
Single and Dual Data Accesses ............................................... 5-52
Data Access Options .............................................................. 5-52
Short Word Addressing of Single Data in SISD Mode ........ 5-54
Short Word Addressing of Single Data in SIMD Mode ....... 5-56
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Short Word Addressing of Dual-Data in SISD Mode ......... 5-58
Short Word Addressing of Dual-Data in SIMD Mode ....... 5-60
32-Bit Normal Word Addressing of Single Data in
SISD Mode ................................................................... 5-62
32-Bit Normal Word Addressing of Single Data in
SIMD Mode .................................................................. 5-64
32-Bit Normal Word Addressing of Dual Data in
SISD Mode ................................................................... 5-66
32-Bit Normal Word Addressing of Dual Data in
SIMD Mode .................................................................. 5-68
Extended Precision Normal Word Addressing of
Single Data .................................................................... 5-70
Extended Precision Normal Word Addressing of Dual
Data in SISD Mode ....................................................... 5-72
Extended-Precision Normal Word Addressing of Dual
Data in SIMD Mode ..................................................... 5-74
Long Word Addressing of Single Data ............................... 5-76
Long Word Addressing of Dual Data in SISD Mode .......... 5-78
Long Word Addressing of Dual Data in SIMD Mode ........ 5-80
Mixed Word Width Addressing of Dual Data in
SISD Mode ................................................................... 5-82
Mixed Word Width Addressing of Dual Data in
SIMD Mode .................................................................. 5-84
Broadcast Load Access ...................................................... 5-86
Shadow Write FIFO Considerations in SIMD Mode .............. 5-95
Arranging Data in Memory ....................................................... 5-100
Executing Instructions From External Memory .......................... 5-101
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32- to 48-Bit Packing Address Generation Scheme ............... 5-109
Total Program Size (32- to 48-Bit Packing) ...................... 5-110
16- to 48-Bit Packing Address Generation Scheme ............... 5-111
Total Program Size (16- to 48-Bit Packing) ...................... 5-111
8- to 48-Bit Packing Address Generation Scheme ................. 5-112
Total Program Size (8- to 48-Bit Packing) ........................ 5-113
No Packing (48- to 48-Bit) Address Generation Scheme ....... 5-113
I/O PROCESSOR
DMA Channel Allocation and Priorities ...................................... 6-16
DMA Interrupt Vector Locations ................................................. 6-18
Booting Modes ........................................................................... 6-20
DMA Controller Operation ........................................................ 6-20
Managing DMA Channel Priority .......................................... 6-22
Chaining DMA Processes ...................................................... 6-25
Transfer Control Block (TCB) Chain Loading ................... 6-26
Setting Up and Starting the Chain ..................................... 6-28
Inserting a TCB in an Active Chain ................................... 6-28
External Port DMA ..................................................................... 6-29
External Port Registers ........................................................... 6-30
External Port FIFO Buffers .................................................... 6-33
External Port DMA Data Packing .......................................... 6-34
32-Bit Bus Downloading ................................................... 6-37
16-Bit Bus Downloading ................................................... 6-38
8-Bit Bus Downloading ..................................................... 6-39
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Boot Memory DMA Mode .................................................... 6-42
External Port Buffer Modes ................................................... 6-42
External Port Channel Priority Modes ................................... 6-43
External Port Channel Transfer Modes ................................... 6-46
External Port Channel Handshake Modes .............................. 6-47
Master Mode .................................................................... 6-50
Paced Master Mode .......................................................... 6-54
Slave Mode ....................................................................... 6-55
Handshake Mode ............................................................. 6-57
DMA Handshake Idle Cycle .................................................. 6-64
External-Handshake Mode ................................................ 6-66
Setting Up External Port DMA .............................................. 6-68
Bootloading Through The External Port ................................ 6-70
Host Processor Booting ..................................................... 6-72
PROM Booting ................................................................ 6-74
External Port DMA Programming Examples .......................... 6-76
Link Port DMA .......................................................................... 6-81
Link Port Registers ................................................................ 6-81
Link Port Buffer Modes ......................................................... 6-83
Link Port Channel Priority Modes ......................................... 6-83
Link Port Channel Transfer Modes ........................................ 6-85
Setting Up Link Port DMA ................................................... 6-86
Bootloading Through The Link Port ..................................... 6-88
Link Port DMA Programming Examples ................................ 6-90
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Serial Port DMA ......................................................................... 6-95
Serial Port Registers ............................................................... 6-96
Serial Port Buffer Modes ........................................................ 6-97
Serial Port Channel Priority Modes ........................................ 6-99
Serial Port Channel Transfer Modes ....................................... 6-99
Setting Up Serial Port DMA ................................................ 6-100
SPORT DMA Programming Examples ................................. 6-102
SPI Port DMA .......................................................................... 6-108
SPI Port Registers ................................................................ 6-108
SPI Port Buffer .................................................................... 6-109
SPI DMA Channel Priority .................................................. 6-112
Setting up SPl Port DMA .................................................... 6-112
Bootloading Through the SPI Port ....................................... 6-113
SPI Port DMA Programming Examples ................................ 6-116
Using I/O Processor Status ........................................................ 6-121
External Port Status ............................................................. 6-127
Link Port Status .................................................................. 6-131
Serial Port Status ................................................................. 6-135
SPI Port Status .................................................................... 6-137
Optimizing DMA Throughput .................................................. 6-139
Internal Memory DMA ....................................................... 6-139
External Memory DMA ....................................................... 6-140
System-Level Considerations ................................................ 6-144
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EXTERNAL PORT
Setting External Port Modes .......................................................... 7-3
External Memory Interface ........................................................... 7-3
Banked External Memory ........................................................ 7-9
Boot Memory ....................................................................... 7-10
Idle Cycle ......................................................................... 7-10
Data Hold Cycle ............................................................... 7-12
Multiprocessor Memory Space Waitstates and
Acknowledge ................................................................. 7-12
Timing External Memory Accesses ......................................... 7-13
Asynchronous Mode Interface Timing ............................... 7-14
Synchronous Mode Interface Timing ................................ 7-18
Synchronous Burst Mode Interface Timing ....................... 7-26
Using External SBSRAM ....................................................... 7-36
SBSRAM Restrictions ........................................................... 7-41
Host Processor Interface ............................................................. 7-42
Acquiring the Bus ................................................................. 7-44
Asynchronous Transfers ......................................................... 7-48
Host Transfer Timing ............................................................ 7-51
Host Interface Deadlock Resolution With SBTS .................... 7-54
Slave Reads and Writes .......................................................... 7-55
IOP Shadow Registers ....................................................... 7-55
Instruction Transfers ......................................................... 7-56
Slave Write Latency .......................................................... 7-56
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Slave Reads ....................................................................... 7-57
Broadcast Writes .................................................................... 7-57
Data Transfers Through the EPBx Buffers .............................. 7-58
DMA Transfers ...................................................................... 7-58
Host Data Packing ................................................................. 7-59
Packing Mode Variations For Host Accesses ........................... 7-61
IOP Register Host Accesses ............................................... 7-62
LINK Port Buffer Access ................................................... 7-63
EPBx Buffer Accesses ........................................................ 7-64
8- to 32-Bit Data Packing .................................................. 7-66
16- to 32-Bit Packing ........................................................ 7-69
48-Bit Instruction Packing ................................................ 7-74
Host Interface Status ............................................................. 7-76
Interprocessor Messages and Vector Interrupts ........................ 7-76
Message Passing (MSGRx) ................................................ 7-77
Host Vector Interrupts (VIRPT) ........................................ 7-78
System Bus Interfacing .......................................................... 7-78
Access to the Processor Bus – Slave Processor ..................... 7-79
Access to the System Bus – Master Processor ...................... 7-79
Processor Core Access to System Bus ................................. 7-82
Deadlock Resolution ......................................................... 7-82
DMA Access to System Bus ............................................... 7-84
Multiprocessing With Local Memory ................................. 7-85
ADSP-21161 to Microprocessor Interface .......................... 7-85
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Multiprocessor (MP) Interface .................................................... 7-87
Multiprocessing System Architectures .................................... 7-90
Data Flow Multiprocessing ............................................... 7-90
Cluster Multiprocessing .................................................... 7-91
Multiprocessor Bus Arbitration .............................................. 7-93
Bus Arbitration Protocol ................................................... 7-95
Bus Arbitration Priority (RPBA) ....................................... 7-98
Bus Mastership Timeout ................................................. 7-101
Priority Access ................................................................ 7-103
Bus Synchronization After Reset .......................................... 7-105
Booting Another processor .................................................. 7-108
Multiprocessor Writes and Reads ......................................... 7-109
Instruction Transfers ....................................................... 7-110
Bus Lock and Semaphores ................................................... 7-110
Multiprocessor Interface Status ....................................... 7-112
SDRAM INTERFACE
SDRAM Pin Connections ............................................................. 8-7
SDRAM Timing Specifications ..................................................... 8-8
SDRAM Control Register (SDCTL) ............................................. 8-9
SDRAM Configuration for Runtime ........................................... 8-10
Setting the Refresh Counter Value (SDRDIV) ....................... 8-13
Setting the SDRAM Clock Enables ........................................ 8-14
Setting the Number of SDRAM Banks (SDBN) ..................... 8-15
Setting the External Memory Bank (SDEMx) ........................ 8-16
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Setting the SDRAM Buffering Option (SDBUF) .................... 8-16
Selecting the CAS Latency Value (SDCL) ............................... 8-17
Selecting the SDRAM Page Size (SDPGS) .............................. 8-18
Setting the SDRAM Power-Up Mode (SDPM) ....................... 8-19
Starting the SDRAM Power-Up Sequence (SDPSS) ................ 8-19
Starting Self-Refresh Mode (SDSRF) ..................................... 8-20
Selecting the Active Command Delay (SDTRAS) ................... 8-20
Selecting the Precharge Delay (SDTRP) ................................. 8-21
Selecting the RAS-to-CAS Delay (SDTRCD) ......................... 8-21
SDRAM Controller Standard Operation ...................................... 8-22
Understanding DAG and DMA Operation ............................. 8-22
Multiprocessing Operation .................................................... 8-24
Accessing SDRAM ................................................................ 8-25
Address Mapping for SDRAM ........................................... 8-27
Understanding DQM Operation ............................................ 8-29
Executing a Parallel Refresh Command During
Host Control ...................................................................... 8-29
Powering Up After Reset ........................................................ 8-30
Entering and Exiting Self-Refresh Mode ................................. 8-31
SDRAM Controller Commands .................................................. 8-31
Bank Activate (ACT) Command ............................................ 8-32
Mode Register Set (MRS) ...................................................... 8-32
Precharge Command (PRE) ................................................... 8-33
Read/Write Command ........................................................... 8-34
Read Commands ............................................................... 8-34
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Write Commands ............................................................. 8-36
DMA Transfers ................................................................. 8-37
Refresh (REF) Command ...................................................... 8-37
Setting the Delay Between Refresh Commands .................. 8-37
Understanding Multiprocessing Operation ........................ 8-38
Self Refresh Command (SREF) .............................................. 8-39
Programming Example .......................................................... 8-40
LINK PORTS
Link Port to Link Buffer Assignment ............................................. 9-3
Link Port DMA Channels ............................................................. 9-4
Link Port Booting ......................................................................... 9-5
Setting Link Port Modes ............................................................... 9-5
Link Port Control Register (LCTL) Bit Descriptions ................ 9-7
Link Data Path and Compatibility Modes ................................ 9-9
Using Link Port Handshake Signals ............................................. 9-10
Using Link Buffers ...................................................................... 9-12
Core Processor Access To Link Buffers ................................... 9-13
Host Processor Access To Link Buffers ................................... 9-14
Using Link Port DMA ................................................................ 9-16
Using Link Port Interrupts .......................................................... 9-17
Link Port Interrupts With DMA Enabled .............................. 9-18
Link Port Interrupts With DMA Disabled ............................. 9-19
Link Port Service Request Interrupts (LSRQ) ......................... 9-19
Detecting Errors on Link Transmissions ...................................... 9-22
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Link Port Programming Examples .......................................... 9-23
Using Token Passing With Link Ports .......................................... 9-27
Designing Link Port Systems ....................................................... 9-30
Terminations for Link Transmission Lines .............................. 9-30
Peripheral I/O Using Link Ports ............................................. 9-31
Data Flow Multiprocessing With Link Ports ........................... 9-33
SERIAL PORTS
Serial Port Pins ........................................................................... 10-3
SPORT Interrupts ...................................................................... 10-7
SPORT Reset .............................................................................. 10-8
SPORT Control Registers and Data Buffers ................................. 10-9
Serial Port Control Registers (SPCTLx) ................................ 10-14
Register Writes and Effect Latency ................................... 10-30
Transmit and Receive Data Buffers ....................................... 10-30
Clock and Frame Sync Frequencies (DIV) ............................ 10-33
Data Word Formats ................................................................... 10-35
Word Length ....................................................................... 10-36
Endian Format .................................................................... 10-36
Data Packing and Unpacking ............................................... 10-37
Data Type ....................................................................... 10-37
Companding ....................................................................... 10-39
Clock Signal Options ................................................................ 10-40
Frame Sync Options .................................................................. 10-41
Framed Versus Unframed ..................................................... 10-41
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CONTENTS
Internal Versus External Frame Syncs ................................... 10-42
Active Low Versus Active High Frame Syncs ........................ 10-43
Sampling Edge for Data and Frame Syncs ............................ 10-43
Early Versus Late Frame Syncs ............................................. 10-44
Data-Independent Transmit Frame Sync .............................. 10-45
SPORT Loopback .................................................................... 10-46
SPORT Operation Modes ......................................................... 10-47
I2S Mode ............................................................................ 10-48
Setting Internal Serial Clock and Frame Sync Rates ......... 10-49
I2S Control Bits ............................................................. 10-49
Setting Word Length (SLEN) .......................................... 10-49
Selecting Transmit Receive Channel Order (L_FIRST) .... 10-49
Selecting the Frame Sync Options (FS_BOTH) ............... 10-50
Enabling SPORT Master Mode (MSTR) ......................... 10-50
Enabling SPORT DMA (SDEN) .................................... 10-51
Multichannel Operation ...................................................... 10-52
Frame Syncs in Multichannel Mode ................................ 10-54
Multichannel Control Bits in SPCTL .............................. 10-55
Channel Selection Registers ............................................ 10-57
Transferring Data to Memory ................................................... 10-58
DMA Block Transfers .......................................................... 10-59
Setting Up DMA on SPORT Channels ........................... 10-60
SPORT DMA Parameter Registers ....................................... 10-61
SPORT DMA Chaining ................................................. 10-65
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Single-Word Transfers .......................................................... 10-65
SPORT Pin/Line Terminations .................................................. 10-66
SPORT Programming Examples ................................................ 10-67
SERIAL PERIPHERAL INTERFACE (SPI)
Functional Description ............................................................... 11-2
SPI Interface Signals ................................................................... 11-3
SPICLK ................................................................................ 11-3
SPIDS ................................................................................... 11-4
FLAG ................................................................................... 11-5
MOSI ................................................................................... 11-6
MISO ................................................................................... 11-6
SPI Interrupts ............................................................................. 11-8
SPI IOP Registers ....................................................................... 11-9
SPI Control Register (SPICTL) .............................................. 11-9
Baud Rate Example ......................................................... 11-14
Seamless Operation ......................................................... 11-15
SPI Status Register (SPISTAT) ............................................. 11-15
SPI Transmit Data Buffer (SPITX) ....................................... 11-20
SPI Receive Data Buffer (SPIRX) ......................................... 11-20
SPI Shift Registers ............................................................... 11-21
SPI Data Word Formats ............................................................ 11-21
SPI Word Packing ............................................................... 11-24
SPI Operation Modes ................................................................ 11-24
Master Mode Operation ...................................................... 11-25
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Interrupt and DMA Driven Transfers .............................. 11-26
Core Driven Transfers ..................................................... 11-26
Automatic Slave Selection ............................................... 11-26
User Controlled Slave Selection ....................................... 11-27
Slave Mode Operation ......................................................... 11-28
Error Signals and Flags ............................................................. 11-29
Multi-Master Error (MME) ................................................. 11-30
Transmission Error (TXE) ................................................... 11-30
Reception Error (RBSY) ...................................................... 11-31
SPI/Link Port DMA ................................................................. 11-32
DMA Operation in SPI Master Mode .................................. 11-32
DMA Operation in Slave Mode ........................................... 11-33
SPI Booting .............................................................................. 11-34
32-Bit SPI Host Boot .......................................................... 11-38
16-Bit SPI Host Boot .......................................................... 11-39
8-Bit SPI Host Boot ............................................................ 11-41
Multiprocessor SPI Port Booting ..................................... 11-42
SPI Programming Example ....................................................... 11-44
JTAG TEST-EMULATION PORT
JTAG Test Access Port ................................................................ 12-3
Instruction Register .................................................................... 12-4
EMUPMD Shift Register ...................................................... 12-5
EMUPX Shift Register .......................................................... 12-6
EMU64PX Shift Register ...................................................... 12-7
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EMUPC Shift Register .......................................................... 12-7
EMUCTL Shift Register ........................................................ 12-8
EMUSTAT Shift Register .................................................... 12-11
BRKSTAT Shift Register ..................................................... 12-12
MEMTST Shift Register ...................................................... 12-13
PSx, DMx, IOx, and EPx (Breakpoint) Registers .................. 12-13
EMUN Register .................................................................. 12-16
EMUCLK and EMUCLK2 Registers ................................... 12-16
EMUIDLE Instruction ........................................................ 12-17
In Circuit Signal Analyzer (ICSA) Function ......................... 12-17
Boundary Register ..................................................................... 12-17
Device Identification Register .................................................... 12-28
Built-In Self-Test Operation (BIST) .......................................... 12-28
Private Instructions ................................................................... 12-28
References ................................................................................. 12-29
SYSTEM DESIGN
Pin Descriptions ......................................................................... 13-2
Input Synchronization Delay ............................................... 13-18
Pin States At Reset ............................................................... 13-19
Pull-Up and Pull-Down Resistors ......................................... 13-22
Clock Derivation ................................................................. 13-24
Timing Specifications ...................................................... 13-25
RESET and CLKIN ............................................................ 13-28
Reset Generators ................................................................. 13-31
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Interrupt and Timer Pins .................................................... 13-33
Core-Based Flag Pins ........................................................... 13-34
Flag Inputs ..................................................................... 13-34
Flag Outputs .................................................................. 13-34
Programmable I/O Flags ..................................................... 13-35
Example #1: Configuring FLGx as Output Flags ............. 13-37
Example #2: Configuring FLGx as Input Flags ................ 13-38
System Design Considerations for Flags ............................... 13-38
Example #3: Programming 2:1 Clock Ratio ..................... 13-40
Example #4: Programming 3:1 Clock Ratio ..................... 13-40
Example #5: Programming 4:1 Clock Ratio ..................... 13-40
JTAG Interface Pins ............................................................ 13-41
Dual-Voltage Power-up Sequencing ........................................... 13-41
PLL Start-Up (Revisions 1.0/1.1) ........................................ 13-44
Power On Reset (POR) Circuit ....................................... 13-44
PLL CLKIN Enable Circuit ............................................ 13-46
PLL Start-Up (Revision 1.2) ................................................ 13-48
Designing For JTAG Emulation ................................................ 13-49
Target Board Connector ...................................................... 13-50
Layout Requirements ................................................................ 13-54
Power Sequence for Emulation .................................................. 13-56
Additional JTAG Emulator References ...................................... 13-56
Pod Specifications ..................................................................... 13-56
JTAG Pod Connector .......................................................... 13-57
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3.3 V Pod Logic .................................................................. 13-58
2.5 V Pod Logic .................................................................. 13-59
Conditioning Input Signals ....................................................... 13-60
Link Port Input Filter Circuits ............................................. 13-60
RESET Input Hysteresis ...................................................... 13-61
Designing For High Frequency Operation ................................. 13-62
Clock Specifications and Jitter ............................................. 13-63
Clock Distribution .............................................................. 13-63
Point-to-Point Connections ................................................. 13-65
Signal Integrity .................................................................... 13-67
Other Recommendations and Suggestions ............................ 13-68
Decoupling Capacitors and Ground Planes .......................... 13-69
Oscilloscope Probes ............................................................. 13-70
Recommended Reading ....................................................... 13-71
Booting Single and Multiple Processors ..................................... 13-71
Multiprocessor Host Booting ............................................... 13-73
Multiprocessor EPROM Booting ......................................... 13-73
Booting From a Single EPROM ...................................... 13-73
Sequential Booting .......................................................... 13-74
Multiprocessor Link Port Booting ........................................ 13-75
Multiprocessor Booting From External Memory ................... 13-75
Data Delays, Latencies, and Throughput ................................... 13-76
Execution Stalls ................................................................... 13-77
DAG Stalls .......................................................................... 13-77
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Memory Stalls ..................................................................... 13-77
IOP Register Stalls .............................................................. 13-78
DMA Stalls ......................................................................... 13-78
Link Port and Serial Port Stalls ............................................ 13-78
REGISTERS
Control and Status System Registers .............................................. A-2
Mode Control 1 Register (MODE1) ........................................ A-3
Mode Mask Register (MMASK) .............................................. A-8
Mode Control 2 Register (MODE2) ...................................... A-10
Arithmetic Status Registers (ASTATx and ASTATy) ............... A-13
Sticky Status Registers (STKYx and STKYy) .......................... A-18
User-Defined Status Registers (USTATx) ............................... A-22
Processing Element Registers ....................................................... A-23
Data File Data Registers (Rx, Fx, Sx) ..................................... A-23
Multiplier Results Registers (MRFx, MRBx) .......................... A-24
Program Memory Bus Exchange Register (PX) ....................... A-25
Program Sequencer Registers ....................................................... A-25
Interrupt Latch Register (IRPTL) .......................................... A-27
Interrupt Mask Register (IMASK) ......................................... A-31
Interrupt Mask Pointer Register (IMASKP) ........................... A-32
Link Port Interrupt Register (LIRPTL) .................................. A-34
Flag Value Register (FLAGS) ................................................. A-37
IOFLAG Value Register ........................................................ A-38
Program Counter Register (PC) ............................................. A-41
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Program Counter Stack Register (PCSTK) ............................ A-44
Program Counter Stack Pointer Register (PCSTKP) .............. A-44
Fetch Address Register (FADDR) .......................................... A-44
Decode Address Register (DADDR) ...................................... A-44
Loop Address Stack Register (LADDR) ................................. A-45
Current Loop Counter Register (CURLCNTR) .................... A-45
Loop Counter Register (LCNTR) ......................................... A-45
Timer Period Register (TPERIOD) ....................................... A-46
Timer Count Register (TCOUNT) ....................................... A-46
Data Address Generator Registers ............................................... A-46
Index Registers (Ix) ............................................................... A-47
Modify Registers (Mx) .......................................................... A-47
Length and Base Registers (Lx,Bx) ........................................ A-47
I/O Processor Registers ............................................................... A-47
System Configuration Register (SYSCON) ............................ A-60
Vector Interrupt Address Register (VIRPT) ........................... A-63
External Memory Waitstate and Access Mode Register
(WAIT) ............................................................................. A-65
System Status Register (SYSTAT) .......................................... A-69
SDRDIV Register (SDRDIV) ............................................... A-72
SDRAM Control Register (SDCTL) ..................................... A-73
External Port DMA Buffer Registers (EPBx) .......................... A-76
Message Registers (MSGRx) ................................................. A-77
PC Shadow Register (PC_SHDW) ........................................ A-77
MODE2 Shadow Register (MODE2_SHDW) ...................... A-78
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CONTENTS
Bus Time-Out Maximum Register (BMAX) ........................... A-79
Bus (Time-Out) Counter Register (BCNT) ........................... A-79
External Port DMA Control Registers (DMACx) ................... A-80
Internal Memory DMA Index Registers (IIx) ......................... A-87
Internal Memory DMA Modifier Registers (IMx) .................. A-87
Internal Memory DMA Count Registers (Cx) ........................ A-87
Chain Pointer For Next DMA TCB Registers (CPx) .............. A-88
General Purpose DMA Registers (GPx) ................................. A-89
External Memory DMA Index Registers (EIEPx) ................... A-89
External Memory DMA Modifier Registers (EMEPx) ............ A-89
External Memory DMA Count Registers (ECEPx) ................. A-90
DMA Channel Status Register (DMASTAT) .......................... A-90
Link Port Buffer Registers (LBUFx) ....................................... A-92
Link Port Buffer Control Register (LCTL) ............................. A-92
Link Port Service Request & Mask Register (LSRQ) ............... A-98
Serial Port Registers ............................................................. A-100
SPORT Serial Control Registers (SPCTLx) ..................... A-100
SPORT Multichannel Control Registers (SPxyMCTL) .... A-109
SPORT Transmit Buffer Registers (TXx) ......................... A-111
SPORT Receive Buffer Registers (RXx) ........................... A-111
SPORT Divisor Registers (DIVx) .................................... A-112
SPORT Count Registers (CNTx) .................................... A-113
SPORT Transmit Select Registers (MT2CSx and
MT3CSx) .................................................................... A-113
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SPORT Transmit Compand Registers (MT2CCSx and
MT3CCSx) ................................................................. A-113
SPORT Receive Select Registers ..................................... A-114
SPORT Receive Compand Registers ............................... A-114
Serial Peripheral Interface Registers ........................................... A-114
SPI Port Status Register ...................................................... A-115
SPI Control Register (SPICTL) ........................................... A-117
SPI Receive Buffer Register (SPIRX) ................................... A-120
SPI Transmit Buffer Register (SPITX) ................................. A-121
Register and Bit #Defines (def21161.h) .................................... A-121
INTERRUPT VECTOR ADDRESSES
NUMERIC FORMATS
IEEE Single-Precision Floating-Point Data ................................... C-1
Extended-Precision Floating-Point ................................................ C-3
Short Word Floating-Point Format ............................................... C-4
Packing for Floating-Point Data ................................................... C-4
Fixed-Point Formats ..................................................................... C-6
GLOSSARY
INDEX
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