Analog Devices ADSP-21160NKB-95, ADSP-21160NCB-TBD Datasheet

PRELIMINARY TECHNICAL DATA

a

Preliminary Technical Data

SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,

Medical, Military, Graphics, Imaging, and
Communication

Super Harvard Architecture—Four Independent Buses

for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O

Backwards-Compatible—Assembly Source Level

Compatible with Code for ADSP-2106x DSPs

Single-Instruction-Multiple-Data (SIMD) Computational

Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File

Integrated Peripherals—Integrated I/O Processor,

4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)

FUNCTIONAL BLOCK DIAGRAM

DSP Microcomputer

ADSP-21160N

KEY FEATURES
95 MHz (10.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD

Operations in Both Computational Units

570 MFLOPS Peak and 380 MFLOPS Sustained

Performance (Based on FIR)

Dual Data Address Generators (DAGs) with Modulo and

Bit-Reverse Addressing

Zero-Overhead Looping and Single-Cycle Loop Setup,

Providing Efficient Program Sequencing

IEEE 1149.1 JTAG Standard Test Access Port and

On-Chip Emulation

400-Ball 27 ⴛ 27 mm Metric PBGA Package

DAG1

8X4X32

BUS

CONNECT

(PX)

MULT

CORE PROCESSOR

DAG2

8X4X32

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

DATA

REGISTER

FILE

(PEX)

16 X 40-BIT

TIMER

BARREL
SHIFTER

ALU

INSTRUCTION

CACHE

32 X 48-BIT

PROGRAM

SEQUENCER

16/32/40/48/64

32/40/64

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

ADDR DATA ADDR

ADDR DATA

32

32

DATA

REGISTER

FILE

BARREL
SHIFTER

ALU

(PEY)

16 X 40-BIT

MULT

DATA

DATA

IOD

64

0
K

C
O
L
B

ADDR

IOA

18

IOP

REGISTERS

(MEMORY
MAPPED)

CONTROL,

STATUS, AND

DATA BUFFERS

1
K

C
O

L
B

CONTROLLER

SERIAL PORTS

I/O PROCESSOR

JTAG

TEST AND

EMULATION

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

HOST PORT

DMA

(2)

LINKPORTS

(6)

6

32

64

4

6

6

60

REV. PrB

This information applies to a product under development. Its characteristics and speci­fications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise agreed to in
writing.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:[phone] www.analog.com
Fax:[phone] ©Analog Devices,Inc., 2002

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)

Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element

Executes the Same Instruction, but Operates on
Different Data

Code Compatibility—at Assembly Level, Uses the

Same Instruction Set as the ADSP-2106x
SHARC DSPs

Parallelism in Buses and Computational Units Allows:

Single-cycle Execution (with or without SIMD) of: A

Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch

Transfers Between Memory and Core at up to Four

32-Bit Floating- or Fixed-Point Words per Cycle

Accelerated FFT Butterfly Computation Through a

Multiply with Add and Subtract

4M Bits On-Chip Dual-Ported SRAM for Independent

Access by Core Processor, Host, and DMA

DMA Controller supports:

14 Zero-Overhead DMA Channels for Transfers Between

ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports

64-Bit Background DMA Transfers at Core Clock Speed,

in Parallel with Full-Speed Processor Execution
665M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit

Microprocessors

4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State

Generation and Page-Mode for Off-Chip Memory

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing

Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of up to Six ADSP-21160Ns plus Host
Six Link Ports for Point-To-Point Connectivity and Array

Multiprocessing

Serial Ports Provide:

Two 47.5M Bits/s Synchronous Serial Ports with

Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM

External Memories
Up to 47.5 MHz Operation

ADSP-21160NApril 2002

GENERAL DESCRIPTION

The ADSP-21160N SHARC DSP is the second iteration
of the ADSP-21160. Built in a 0.18 micron CMOS process,
it offers higher performance and lower power consumption
than its predecessor, the ADSP-21160M. Easing portabil­ity, the ADSP-21160N is application source code
compatible with first generation ADSP-2106x SHARC
DSPs in SISD (Single Instruction, Single Data) mode. To
take advantage of the processor’s SIMD (Single Instruction,
Multiple Data) capability, some code changes are needed.
Like other SHARCs, the ADSP-21160N is a 32-bit
processor that is optimized for high performance DSP appli­cations. The ADSP-21160N includes an 95 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor
with multiprocessing support, and multiple internal buses
to eliminate I/O bottlenecks.

The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa­tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160N can double performance versus the
ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160N has a 10.5 ns instruc­tion cycle time. With its SIMD computational hardware
running at 95 MHz, the ADSP-21160N can perform 570
million math operations per second.

Table 1 shows performance benchmarks for the

ADSP-21160N.

Table 1. ADSP-21160N Benchmarks

Benchmark Algorithm Speed

1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap) 5.25 ns
IIR Filter (per biquad) 21 ns
Matrix Multiply (pipelined)
[3ⴛ3] ⴛ [3ⴛ1]
Matrix Multiply (pipelined)
[4ⴛ4] ⴛ [4ⴛ1]
Divide (y/x) 31.5 ns
Inverse Square Root 47.25 ns
DMA Transfer Rate 665M Bytes/s

These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.

The ADSP-21160N continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M-bit dual
ported SRAM memory, host processor interface, I/O

96 µs

47.25 ns

84 ns

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.

The functional block diagram on page 1 shows a block
diagram of the ADSP-21160N, illustrating the following
architectural features:

• Two processing elements, each made up of an ALU, Mul-

tiplier, Shifter, and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core every core
processor cycle

• Interval timer

• On-Chip SRAM (4M bits)

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six

ADSP-21160N SHARCs

• Host port

• DMA controller

• Serial ports and link ports

• JTAG test access port

Figure 1 shows a typical single-processor system. A multi-

processing system appears in Figure 4.

ADSP-21160

4

3
4

CLKIN
CLK_CFG3–0

EBOOT
LBOOT

IRQ2–0

FLAG3–0
TIMEXP

LXCLK
LXACK
LXDAT7–0

TCLK0
RCLK0
TFS0
RSF0
DT0
DR0

TCLK1
RCLK1
TFS1
RSF1
DT1
DR1

RPBA
ID2–0

RESET JTAG

BMS

CIF

BRST

ADDR31–0
DATA63–0

RDx

WRx

ACK

MS3–0

PAGE

SBTS

CLKOUT

DMAR1–2
DMAG1–2

CS

HBR
HBG

REDY

BR1–6

PA

6

CS

BOOT

EPROM

ADDR

(OPTIONAL)

DATA

ADDR

MEMORY/

DATA

MAPPED

OE

DEVICES

WE

(OPTIONAL)

ACK

L
O
R

T
N
O
C

CS

S
S

A

E

T

R
D
D
A

A
D

DATA

DMA DEVICE

(OPTIONAL)

PROCESSOR

INTERFACE
(OPTIONAL)

ADDR
DATA

HOST

CLOCK

LINK

DEVICES

(6 MAX)

(OPTIONAL)

SERIAL
DEVICE

(OPTIONAL)

SERIAL
DEVICE

(OPTIONAL)

Figure 1. Single-Processor System

ADSP-21160NApril 2002

ADSP-21160N Family Core Architecture

The ADSP-21160N includes the following archi­tectural features of the ADSP-2116x family core. The
ADSP-21160N is code compatible at the assembly level
with the ADSP-2106x and ADSP-21161.

SIMD Computational Engine

The ADSP-21160N contains two computational process­ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational
units. The computational units consist of an arith­metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz­ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera­tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com­putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter­mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21160N features an enhanced Harvard archi­tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc­tions and data (see the functional block diagram on page 1).

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

3REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

With the ADSP-21160N’s separate program and data
memory buses and on-chip instruction cache, the processor
can simultaneously fetch four operands and an instruction
(from the cache), all in a single cycle.

Instruction Cache

The ADSP-21160N includes an on-chip instruction cache
that enables three-bus operation for fetching an instruction
and four data values. The cache is selective—only the
instructions whose fetches conflict with PM bus data
accesses are cached. This cache allows full-speed execution
of core, providing looped operations such as digital filter
multiply- accumulates and FFT butterfly processing.

Data Address Generators with Hardware
Circular Buffers

The ADSP-21160N’s two data address generators (DAGs)
are used for indirect addressing and provide for implement­ing circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data struc­tures required in digital signal processing, and are
commonly used in digital filters and Fourier transforms.
The two DAGs of the ADSP-21160N contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs auto­matically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying imple­mentation. Circular buffers can start and end at any
memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example,
the ADSP-21160N can conditionally execute a multiply, an
add, and subtract, in both processing elements, while
branching, all in a single instruction.

ADSP-21160N Memory and I/O Interface Features

Augmenting the ADSP-2116x family core, the
ADSP-21160N adds the following architectural features:

Dual-Ported On-Chip Memory

The ADSP-21160N contains four megabits of on-chip
SRAM, organized as two blocks of 2M bits each, which can
be configured for different combinations of code and data
storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O proces­sor. The dual-ported memory in combination with three
separate on-chip buses allows two data transfers from the
core and one from I/O processor, in a single cycle. On the
ADSP-21160N, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of
16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four
megabits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the
amount of data that may be stored on-chip. Conversion

ADSP-21160NApril 2002

between the 32-bit floating-point and 16-bit floating-point
formats is done in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data, using the DM
bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and
PM bus in this way, with one dedicated to each memory
block, assures single-cycle execution with two data trans­fers. In this case, the instruction must be available in
the cache.

Off-Chip Memory and Peripherals Interface

The ADSP-21160N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 4G word
off-chip address space is included in the ADSP-21160N’s
unified address space. The separate on-chip buses—for PM
addresses, PM data, DM addresses, DM data, I/O
addresses, and I/O data—are multiplexed at the external
port to create an external system bus with a single 32-bit
address bus and a single 64-bit data bus. The lower 32 bits
of the external data bus connect to even addresses and the
upper 32 bits of the 64 connect to odd addresses. Every
access to external memory is based on an address that
fetches a 32-bit word, and with the 64-bit bus, two address
locations can be accessed at once. When fetching an instruc­tion from external memory, two 32-bit data locations are
being accessed (16 bits are unused). Figure 3 shows the
alignment of various accesses to external memory.

The external port supports asynchronous, synchronous,
and synchronous burst accesses. ZBT synchronous burst
SRAM can be interfaced gluelessly. Addressing of external
memory devices is facilitated by on-chip decoding of
high-order address lines to generate memory bank select
signals. Separate control lines are also generated for simpli­fied addressing of page-mode DRAM. The ADSP-21160N
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold, and
disable time requirements.

DMA Controller

The ADSP-21160N’s on-chip DMA controller allows
zero-overhead data transfers without processor interven­tion. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the
ADSP-21160N’s internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the ADSP-21160N’s internal memory
and its serial ports or link ports. External bus packing to
16-, 32-, 48-, or 64-bit words is performed during DMA
transfers. Fourteen channels of DMA are available on the
ADSP-21160N—six via the link ports, four via the serial
ports, and four via the processor’s external port (for either
host processor, other ADSP-21160Ns, memory or I/O

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Internal
Memory
Space

Multiprocessor
Memory
Space

IOP Reg’s

Long Word

Normal Word

Short Word

Internal
Memory

Space

(ID = 001)

Internal
Memory

Space

(ID = 010)

Internal
Memory

Space

(ID = 011)

Internal
Memory

Space

(ID = 100)

Internal
Memory

Space

(ID = 101)

Internal
Memory

Space

(ID = 110)

Broadcast

Write to
All DSPs
(ID = 111)

0x00 0000
0x02 0000
0x04 0000

0x08 0000

0x10 0000

0x20 0000

0x30 0000

0x40 0000

0x50 0000

0x60 0000

0x70 0000

0x7F FFFF

Bank 0

Bank 1

Bank 2

Bank 3

Nonbanked

0x80 0000

MS

MS

MS

MS

External
Memory
Space

0xFFFF FFFF

0

1

2

3

Figure 2. ADSP-21160N Memory Map

transfers). Programs can be downloaded to the
ADSP-21160N using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-21160N offers powerful features tailored to
multiprocessing DSP systems as shown in Figure 4. The
external port and link ports provide integrated glueless mul­tiprocessing support.

The external port supports a unified address space (see

Figure 2) that allows direct interprocessor accesses of each

ADSP-21160N’s internal memory. Distributed bus arbitra­tion logic is included on -chip for simple, glueless connection
of systems containing up to six ADSP-21160Ns and a host
processor. Master processor changeover incurs only one
cycle of overhead. Bus arbitration is selectable as either fixed
or rotating priority. Bus lock allows indivisible read-mod-

ADSP-21160NApril 2002

DATA63–0

63 55 47 39 31 23 15 7 0

BYTE 0BYTE 7

RDH/WRH

64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS

64-BIT TRANSFER FOR48-BIT INSTRUCTION FETCH

64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION

32-BIT NORMAL WORD (EVEN ADDRESS)

32-BIT NORMAL WORD (ODD ADDRESS)

RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:

32-BIT PACKED

16-BIT PACKED

EPROM

Figure 3. ADSP-21160N External Data Alignment

Options

ify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 380M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ns and can be used
to implement reflective semaphores.

Six link ports provide for a second method of multiprocess­ing communications. Each link port can support
communications to another ADSP-21160N. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.

Link Ports

The ADSP-21160N features six 8-bit link ports that provide
additional I/O capabilities. With the capability of running
at 95 MHz rates, each link port can support 95M bytes/s.
Link port I/O is especially useful for point-to-point inter­processor communication in multiprocessing systems. The
link ports can operate independently and simultaneously.
Link port data is packed into 48- or 32-bit words, and can
be directly read by the core processor or DMA-transferred
to on-chip memory. Each link port has its own double-buff­ered input and output registers. Clock/acknowledge
handshaking controls link port transfers. Transfers are pro­grammable as either transmit or receive.

Serial Ports

The ADSP-21160N features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
each with a maximum data rate of 47.5M bit/s. Independent
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-

RDL/WRL

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

5REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ADS P-21160#6
ADS P-21160#5

RESET

CLOCK

011

010

001

3

3

3

ADS P-21160#4

ADS P-21160#3

CLKIN

RESET

RPBA

ID 2 – 0

BR1–2, BR 4–6

ADS P-21160#2

CLKIN

RESET

RPBA

ID 2 – 0

ADS P-21160#1

CLKIN

RESET

RPBA

ID 2 – 0

ADDR31–0
DAT A63–0

CONTROL

BR3

ADDR31–0
DAT A63–0

CONTROL

BR1,BR3– 6

BR2

ADDR31–0

DAT A63–0

RDx

WRx

ACK

L

MS3 –0

O
R
T
N
O

BMS

C

PAGE

SBTS

CLKOUT

HBR
HBG

REDY

BR2–6

BR1

PA

PA

CS

PA

L

S
S

O

A

E

R

T

R

T

A

D

N

D

D

O

A

C

5

5

L

S
S

O

A

E

R

T

T

R

A

N

D

D

D

O

A

C

ADDR

GLOBAL MEMORY

DATA

AND

OE

PERIPHERAL (OPTIONAL)

WE

ACK

CS

CS

BOOT EPROM( OPTIONAL)

ADDR
DATA

HOSTPROCESSOR
INTERFACE (OPTIONAL)

5

ADDR
DATA

Figure 4. Shared Memory Multiprocessing System

cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit­tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable

ADSP-21160NApril 2002

synchronization and transmit modes as well as optional
µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.

Host Processor Interface

The ADSP-21160N host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160N’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160N,
and can access the DMA channel setup and mailbox regis­ters. Vector interrupt support provides efficient execution
of host commands.

Program Booting

The internal memory of the ADSP-21160N can be booted
at system power-up from an 8-bit EPROM, a host proces­sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.

Phased Locked Loop

The ADSP-21160N uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.

Power Sup plies

The ADSP-21160N has separate power supply connections
for the internal (V

/AGND) power supplies. The internal and analog

(AV

DD

), external (V

DDINT

supplies must meet the 1.9 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.

The PLL Filter Figure 5 on page 7 must be added for each
ADSP-21160N in the system. VDDint is the digital core
supply. It is recommended that the capacitors be connected
directly to AGND using short thick trace. It is recom­mended that the capacitors be placed as close to AVDD and
AGND as possible. The connection from AGND to the
(digital) ground plane should be made after the capacitors.
The use of a thick trace for AGND is reasonable only
because the PLL is a relatively low power circuit - it does
not apply to any other ADSP-21160N GND connection.

), and analog

DDEXT

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

10⍀

V

DDINT

AGND

Figure 5. Analog Power (AVDD) Filter Circuit

Development Tools

0.01␮F0.1␮F

AV

DD

The ADSP-21160N is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and VisualDSP++

1

development envi­ronment. The same emulator hardware that supports other
ADSP-2116x DSPs, also fully emulates the
ADSP-21160N.

The VisualDSP++ project management environment lets
programmers develop and debug an application. This envi­ronment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simula­tor, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. Two key points
for these tools are:

• Compiled ADSP-2116x C/C++ code efficiency—the

compiler has been developed for efficient translation of
C/C++ code to ADSP-2116x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.

• ADSP-2106x family code compatibility—The assembler

has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-2116x.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all

ADSP-21160NApril 2002

of the ADSP-2116x development tools, including the syntax
highlighting in the VisualDSP++ editor. This capability
permits:

• Control how the development tools process inputs and

generate outputs.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21160N processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-2116x processor
family. Hardware tools include ADSP-2116x PC plug-in
cards. Third Party software tools include DSP libraries,
real-time operating systems, and block diagram
design tools.

Designing an Emulator-Compatible DSP Board
(Target)

The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The
emulator uses the TAP to access the internal features of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers.
The DSP must be halted to send data and commands, but
once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on
system timing.

To use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.

Target Board Header

The emulator interface to an Analog Devices’ JTAG DSP
is a 14-pin header, as shown in Figure 6. The customer must
supply this header on the target board in order to commu­nicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on

0.1" ⴛ 0.1" spacing, with a minimum post length of 0.235".
Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the
target board.

1

VisualDSP++ is a registered trademark of Analog Devices, Inc.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

7REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least

0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

12

34

56

78

910

9

11 12

13 14

EMU

GND

TMS

TCK

TRST

TDI

TDO

TOP VIEW

ADSP-21160NApril 2002

12

GND

BTDI

GND

34

56

78

910

9

11 12

13 14

KEY (NO PIN)

BTMS

BTCK

BTRST

TOP VIEW

Figure 7. JTAG Target Board Connector with No Local

Boundary Scan

EMU

GND

TMS

TCK

TRST

TDI

TDO

Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in
Place)

As can be seen in Figure 6, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are option­ally used for board-level (boundary scan) testing.

When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 7. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.

JTAG Emulator Pod Connector

Figure 8 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 9 displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.

Design-for-Emulation Circuit Information

For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website—use site search on

0.64"

0.24"

0.88"

Figure 8. JTAG Pod Connector Dimensions

0.10"

0.15"

Figure 9. JTAG Pod Connector Keep-Out Area

“EE-68” (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.

Additional Information

This data sheet provides a general overview of the
ADSP-21160N architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

8REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

PIN FUNCTION DESCRIPTIONS

ADSP-21160N pin definitions are listed below. Inputs iden­tified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).

Tie or pull unused inputs to VDD or GND, except for the
following:

• ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT

(ID2 –0 = 00x) (NOTE: These pins have a logic-level hold
circuit enabled on the ADSP-21160N DSP with ID2– 0
= 00x)

• PA, ACK, MS3– 0, RDx, WRx, CIF, DMARx, DMAGx

(ID2– 0 = 00x) (NOTE: These pins have a pull-up
enabled on the ADSP-21160N DSP with ID2–0 = 00x)

Table 2. Pin Function Descriptions

Pin Type Function

ADDR31–0 I/O/T External Bus Address. The ADSP-21160N outputs addresses for external memory and

peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ns. The
ADSP-21160N inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s
ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160N with ID2–0 = 00x).

DATA63–0 I/O/T External Bus Data. The ADSP-21160N inputs and outputs data and instructions on

these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only enabled
on the ADSP-21160N with ID2–0 = 00x).

MS3–0

RDL

RDH

WRL

O/T Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-

s p on d i n g b a n ks o f e x t e r na l m e mo r y. M em o r y b an k s i ze m u st b e d e fi n e d in t h e S Y SC O N
control register. The MS3–0 outputs are decoded memory address lines. In asyn­chronous access mode, the MS3–0 outputs transition with the other address outputs.
In synchronous access modes, the MS3–0 outputs assert with the other address lines;
however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted.

MS3–0 has a 20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with

ID2–0 = 00x.

I/O/T Memory Read Low Strobe. RDL is asserted whenever ADSP-21160N reads from the

low word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert RDL for reading from
the low word of ADSP-21160N internal memory. In a multiprocessing system, RDL is

driven by the bus master. RDL has a 20kΩ internal pull-up resistor that is enabled on

the ADSP-21160N with ID2–0 = 00x.

I/O/T Memory Read High Strobe. RDH is asserted whenever ADSP-21160N reads from the

high word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert RDH for reading from
the high word of ADSP-21160N internal memory. In a multiprocessing system, RDH

is driven by the bus master. RDH has a 20kΩ internal pull-up resistor that is enabled

on the ADSP-21160N with ID2–0 = 00x.

I/O/T Memory Write Low Strobe. WRL is asserted when ADSP-21160N writes to the low

word of external memory or inter nal memory of other ADSP-21160Ns. External devices
must assert WRL for writing to ADSP-21160N’s low word of internal memory. In a

multiprocessing system, WRL is driven by the bus master. WRL has a 20kΩ internal

pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (NOTE:

See Link Port Buffer Control Register Bit definitions in
the ADSP-21160 DSP Hardware Reference).

• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI

(NOTE: These pins have a pull-up.)

The following symbols appear in the Type column of

Table 2: A = Asynchronous, G = Ground, I = Input,

O = Output, P = Power Supply, S = Synchronous,
(A/D) = Active Drive, (O/D) = Open Drain, and
T = Three-State (when SBTS is asserted, or when the
ADSP-21160N is a bus slave).

ADSP-21160NApril 2002

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

9REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

WRH I/O/T Memory Write High Strobe. WRH is asserted when ADSP-21160N writes to the high

word of external memory or inter nal memory of other ADSP-21160Ns. External devices
must assert WRH for writing to ADSP-21160N’s high word of internal memory. In a
multiprocessing system, WRH is driven by the bus master. WRH
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

PAGE O/T DRAM Page Boundary. The ADSP-21160N asserts this pin to signal that an external

DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160N’s memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160N with ID2–0 = 00x).

BRST I/O/T Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that

data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160N, ADSP-21160N automatically increments the address
as long as BRS T is asserted . BRST is asser ted after the initial access of a burst transfer.
It is asserted for every cycle after that, except for the last data request cycle (denoted by
RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin
maintains the input at the level it was last driven (only enabled on the ADSP-21160N
with ID2–0 = 00x).

ACK I/O/S Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160N
deasserts ACK as an output to add wait states to a synchronous access of its internal

memory. ACK has a 2kΩ internal pull-up resistor that is enabled on the ADSP-21160N

with ID2–0 = 00x.

SBTS

IRQ2–0

FLAG3–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input,

TIMEXP O Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and

HBR

HBG

CS

I/S Suspend Bus and Three-State. External devices can assert SBTS (low) to place the

external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21160N attempts to access external memory while SBTS is asserted,
the processor will halt and the memory access will not be completed until SBTS is
deasserted. SBTS should only be used to recover from host processor and/or
ADSP-21160N deadlock or used with a DRAM controller.

I/A Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be

either edge-triggered or level-sensitive.

it c a n be tes ted a s a c ond i ti o n. A s an out p ut, it can be used to signal external peripherals.

TCOUNT decrements to zero.

I/A Host Bus Request. Must be asserted by a host processor to request control of the

ADSP-21160N’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-21160N that is bus master will relinquish the bus and assert HBG. To relinquish
the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high
impedance state. HBR has priority over all ADSP-21160N bus requests (BR6–1) in a
multiprocessing system.

I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor

may take control of the external bus. HBG is asserted (held low) by the ADSP-21160N
until HBR is released. In a multiprocessing system, HBG is output by the
ADSP-21160N bus master and is monitored by all others. After HBR is asserted, and
before HBG is given, HBG will float for 1 tCLK (1 CLKIN cycle). To avoid erroneous
grants, HBG should be pulled up with a 20k to 50k ohm external resistor.

I/A Chip Select. Asserted by host processor to select the ADSP-21160N.

ADSP-21160NApril 2002

has a 20kΩ internal

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

10REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

REDY O (O/D) Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add waitstates

to a host access when CS and HBR inputs are asserted.

DMAR1 I/A DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA

services. DMAR1 has a 20kΩ internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

DMAR2 I/A DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA

services. DMAR2 has a 20kΩ internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

ID2–0 I Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used

by ADSP-21160N. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and
so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.

DMAG1 O/T DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

DMAG2 O/T DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

BR6–1

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for

PA

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).

LxDAT7–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down
LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down
LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal

EBOOT I EPROM Boot Select. For a description of how this pin operates, see Table 3. This signal

LBOOT I Link Boot. For a description of how this pin operates, see Table 3. This signal is a system

BMS

I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate

for bus mastership. An ADSP-21160N only drives its own BRx line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ns, the unused BRx pins should be pulled high; the processor’s
own BRx line must not be pulled high or low because it is an output.

multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160N. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160N.

I/O/T Priority Access. Asserting its PA pin allows an ADSP-21160N bus slave to interrupt

background DMA transfers and gain access to the external bus. PA is connected to all
ADSP-21160Ns in the system. If access priority is not required in a system, the PA pin
should be left unconnected. PA has a 20kΩ internal pull-up resistor that is enabled on
the ADSP-21160N with ID2–0 = 00x.

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

is a system configuration selection that should be hardwired.

configuration selection that should be hardwired.

I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and

LBOOT pins; see Table 3. This input is a system configuration selection that should be
hardwired.

ADSP-21160NApril 2002

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

11REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

ADSP-21160NApril 2002

CLKIN I Local Clock In. CLKIN is the ADSP-21160N clock input. The ADSP-21160N external

port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the
CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.

CLK_CFG3–0 I Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal

to n ⴛ CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.

CLKOUT O/T CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can

be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x).

RESET

I/A Processor Reset. Resets the ADSP-21160N to a known state and begins execution at

the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan.

TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ

internal pull-up resistor.

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

20 kΩ internal pull-up resistor.

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A Test Reset (JTAG). Resets the test state machine. TRST must be asser ted (pu lsed low)

after power-up or held low for proper operation of the ADSP-21160N. TRST has a
20 kΩ internal pull-up resistor.

EMU

O (O/D) Emulation Status. Must be connected to the ADSP-21160N emulator target board

connector only. EMU has a 50 kΩ internal pull-up resistor.

CIF O/T Core Instruction Fetch. Signal is active low when an external instruction fetch is

performed. Driven by bus master only. Three-state when host is bus master. CIF has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

V

DDINT

P Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor

(40 pins).
V
AV

DDEXT

DD

P I/O Power Supply. Nominally 3.3 V dc (43 pins).
P Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock

generator). This pin has the same specifications as V

, except that added filtering

DDINT

circuitry is required. For more information, see Power Supplies on page 6.
AGND G Analog Power Supply Return.
GND G Power Supply Return. (82 pins)
NC Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).

Table 3. Boot Mode Selection

EBOOT LBOOT BMS Booting Mode

1 0 Output EPROM (Connect BMS to EPROM chip select.)
0 0 1 (Input) Host Processor
0 1 1 (Input) Link Port
0 0 0 (Input) No Booting. Processor executes from external memory.
0 1 0 (Input) Reserved
1 1 x (Input) Reserved

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

12REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ADSP-21160NApril 2002

ADSP-21160N SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

C Grade K Grade

Signal Parameter

V

DDINT

AV

DD

V

DDEXT

T

CASE

V

IH1

V

IH2

V

IL

1

Specifications subject to change without notice.

2

See Environmental Conditions on page 48 for information on thermal specifications.

3

Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,

ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.

4

Applies to input pins: CLKIN, RESET, TRST.

Internal (Core) Supply Voltage 1.8 2.0 1.8 2.0 V
Analog (PLL) Supply Voltage 1.8 2.0 1.8 2.0 V
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
Case Operating Temperature
High Level Input Voltage3, @ V
High Level Input Voltage4, @ V
Low Level Input Voltage

1

3,4

2

, @ V

=Max 2.2 V

DDEXT

=Max 2.3 V

DDEXT

=Min –0.5 0.8 –0.5 0.8 V

DDEXT

–40 +100 0 85 ºC

+0.5 2.2 V

DDEXT

+0.5 2.3 V

DDEXT

DDEXT

DDEXT

+0.5 V
+0.5 V

UnitMin Max Min Max

ELECTRICAL CHARACTERISTICS

Parameter

V

OH

V

OL

I

IH

I

IL

I

ILPU1

I

ILPU2

I

OZH

I

OZL

I

OZHPD

I

OZLPU1

I

OZLPU2

I

OZHA

I

OZLA

I

DD-INPEAK

I

DD-INHIGH

I

DD-INLOW

I

DD-IDLE

AI

DD

C

IN

1

Specifications subject to change without notice.

1

High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current

2

2

4,5,6

4

Low Level Input Current Pull-Up15@ V
Low Level Input Current Pull-Up26@ V
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Pull-Down
Three-State Leakage Current
Pull-Up1
Three-State Leakage Current
Pull-Up2

10

8

9

Three-State Leakage Current
Three-State Leakage Current
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Idle)
Supply Current (Analog)
Input Capacitance

17,18

12

13

14

15

16

7,8,9,10

7

11

11

C and K Grades

Test Conditions

@ V
@ V
@ V
@ V

@ V
@ V
@ V

@ V

@ V

@ V
@ V
t

CCLK

t

CCLK

t

CCLK

t

CCLK

=Min, IOH=–2.0 mA

DDEXT

=Min, IOL=4.0 mA

DDEXT

=Max, VIN=VDD Max 10 µA

DDEXT

=Max, VIN=0 V 10 µA

DDEXT

=Max, VIN=0 V 250 µA

DDEXT

=Max, VIN=0 V 500 µA

DDEXT

=Max, VIN=VDD Max 10 µA

DDEXT

=Max, VIN=0 V 10 µA

DDEXT

=Max, VIN=V

DDEXT

=Max, VIN=0 V 250 µA

DDEXT

=Max, VIN=0 V 500 µA

DDEXT

=Max, VIN=V

DDEXT

=Max, VIN=0 V 4 mA

DDEXT

=10.5 ns, V
=10.5 ns, V
=10.5 ns, V
=10.5 ns, V

3

2.4 V

3

Max 250 µA

DD

Max 25 µA

DD

=Max 1400 mA

DDINT

=Max 875 mA

DDINT

=Max 625 mA

DDINT

=Max 400 mA

DDINT

0.4 V

UnitMin Max

@AVDD=Max 10 mA
fIN=1 MHz, T

=2.5 V

V

IN

CASE

=25°C,

4.7 pF

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

13REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

2

Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,

ADSP-21160NApril 2002

DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK,
LxACK, BMS, TDO, EMU.

3

See Output Drive Currents on page 46 for typical drive current capabilities.

4

Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.

5

Applies to input pins with internal pull-ups: DR0, DR1.

6

Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.

7

Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.

8

Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.

9

Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.

10

Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.

11

Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.

12

The test program used to measure I

internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 46.

13

I

14

I

15

Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation on page 46.

16

Characterized, but not tested.

17

Applies to all signal pins.

18

Guaranteed, but not tested.

is a composite average based on a range of high activity code. For more information, see Power Dissipation on page 46.

DDINHIGH

is a composite average based on a range of low activity code. For more information, see Power Dissipation on page 46.

DDINLOW

represents worst case processor operation and is not sustainable under normal application conditions. Actual

DD-INPEAK

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

14REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage (V

Analog (PLL) Supply Voltage (A

External (I/O) Supply Voltage (V

Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . –0.5 V to V

)1 . . –0.3 V to +2.3 V

DDINT

) . . . . . –0.3 V to +2.3 V

VDD

) . . . . –0.3 V to +4.6 V

DDEXT

DDEXT

DDEXT

+0.5 V

+0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature under Bias . . . . . . . . . . . . . . .130ºC

Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC

1

Stresses greater than those listed above may cause permanent damage to the devi ce.

These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160N features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor­mance degradation or loss of functionality.

ADSP-21160NApril 2002

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

15REV. PrB

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

Timing Specifications

The ADSP-21160N’s internal clock switches at higher fre­quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).

The ADSP-21160N’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre­quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).

Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:

= (tCK) / CR

• t

CCLK

• t

• t

LCLK

SCLK

= (t

= (t

CCLK

CCLK

) ⴛ LR

) ⴛ SR

Where:

• LCLK = Link Port Clock

• SCLK = Serial Port Clock

• t

= CLKIN Clock Period

CK

• t

= (Processor) Core Clock Period

CCLK

• t

= Link Port Clock Per iod

LCLK

• t

= Serial Port Clock Period

SCLK

• CR = Core/CLKIN Ratio (2, 3, or 4:1,

determined by CLK_CFG3–0 at reset)

• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,

determined by LxCLKD)

• SR = Serial Port/Core Clock Ratio (wide range,

determined by ⴛCLKDIV)

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning­ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con­sequently, it is not meaningful to add parameters to derive
longer times.

See Figure 34 under Test Conditions for voltage reference
levels.

ADSP-21160NApril 2002

Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris­tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris­tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.

During processor reset (RESET
(SRST bit in SYSCON register = 1), de-assertion (MS3-0,
HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and
three-state (FLAG3-0, LxCLK, LxACK, LxDAT7-0,
ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx,
BMS, TDO, EMU, DATA) timings differ. These occur
asynchronously to CLKIN, and may not meet the specifi­cations published in the Timing Requirements and
Switching Characteristics tables. The maximum delay for
de-assertion and three-state is one t
assertion low or setting the SRST bit in SYSCON. During
reset the DSP will not respond to SBTS, HBR and MMS
accesses. HBR asserted before reset will be recognized, but
a HBG will not be returned by the DSP until after reset is
de-asserted and the DSP has completed bus
synchronization.

pin low) or software reset

from RESET pin

CK

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

16REV. PrB