ANALOG DEVICES ADSP-21160 Service Manual

ADSP-21160 SHARC® DSP

Hardware Reference

Revision 3.0, November 2003

Part Number

82-001966-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, SHARC, the SHARC logo, and EZ-ICE are registered trademarks of Analog Devices, Inc.

VisualDSP++ is a trademark of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

INTRODUCTION

Purpose ......................................................................................... 1-1

Audience ...................................................................................... 1-1

Overview – Why Floating-Point DSP? ........................................... 1-2

ADSP-21160 DSP Design Advantages ........................................... 1-2

ADSP-21160 DSP Architecture Overview ..................................... 1-6

Processor Core ......................................................................... 1-7

Processing Elements ............................................................ 1-7

Program Sequence Control .................................................. 1-8

Processor Internal Buses .................................................... 1-11

Processor Peripherals .............................................................. 1-12

Dual-Ported Internal Memory (SRAM) ............................. 1-12

External Port ..................................................................... 1-13

I/O Processor .................................................................... 1-14

JTAG Port ............................................................................. 1-16

Development Tools ..................................................................... 1-16

Differences From Previous SHARC DSPs .................................... 1-19

Processor Core Enhancements ................................................ 1-19

Processor Internal Bus Enhancements ..................................... 1-20

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CONTENTS

Memory Organization Enhancements .................................... 1-20

External Port Enhancements .................................................. 1-21

Host Interface Enhancements ........................................... 1-21

Multiprocessor Interface Enhancements ............................ 1-21

IO Architecture Enhancements .............................................. 1-22

DMA Controller Enhancements ........................................ 1-22

Link Port Enhancements ................................................... 1-22

Instruction Set Enhancements ............................................... 1-22

For Information About Analog Products ...................................... 1-23

For Technical or Customer Support ............................................. 1-24

What’s New in This Manual ....................................................... 1-24

Related Documents .................................................................... 1-24

Conventions ............................................................................... 1-25

PROCESSING ELEMENTS

Overview ...................................................................................... 2-1

Setting Computational Modes ...................................................... 2-2

32-bit (Normal Word) Floating-Point Format .......................... 2-4

40-bit Floating-Point Format ................................................... 2-4

16-bit (Short Word) Floating-Point Format ............................. 2-5

32-Bit Fixed-Point Format ....................................................... 2-5

Rounding Mode ...................................................................... 2-6

Using Computational Status ......................................................... 2-7

Arithmetic Logic Unit (ALU) ........................................................ 2-8

ALU Operation ....................................................................... 2-8

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ALU Saturation ....................................................................... 2-9

ALU Status Flags ................................................................... 2-10

ALU Instruction Summary .................................................... 2-11

Multiply—Accumulator (Multiplier) ........................................... 2-13

Multiplier Operation ............................................................. 2-14

Multiplier (Fixed-Point) Result Register ................................. 2-15

Multiplier Status Flags ........................................................... 2-18

Multiplier Instruction Summary ............................................ 2-19

Barrel-Shifter (Shifter) ................................................................. 2-21

Shifter Operation .................................................................. 2-22

Shifter Status Flags ................................................................ 2-25

Shifter Instruction Summary .................................................. 2-27

Data Register File ........................................................................ 2-28

Alternate (Secondary) Data Registers ........................................... 2-31

Multifunction Computations ...................................................... 2-32

Secondary Processing Element (PEy) ............................................ 2-36

Dual Compute Units Sets ...................................................... 2-38

Dual Register Files ................................................................. 2-39

Dual Alternate Registers ........................................................ 2-40

SIMD (Computational) Operations ....................................... 2-41

SIMD and Status Flags .......................................................... 2-44

PROGRAM SEQUENCER

Overview ...................................................................................... 3-1

Instruction Pipeline ...................................................................... 3-7

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Instruction Cache ......................................................................... 3-9

Using the Cache .................................................................... 3-11

Optimizing Cache Usage ....................................................... 3-12

Branches and Sequencing ............................................................ 3-13

Conditional Branches ............................................................ 3-16

Delayed Branches .................................................................. 3-16

Loops and Sequencing ................................................................ 3-20

Restrictions On Ending Loops ............................................... 3-22

Restrictions On Short Loops ................................................. 3-23

Loop Address Stack ............................................................... 3-28

Loop Counter Stack .............................................................. 3-29

Interrupts and Sequencing .......................................................... 3-33

Sensing Interrupts ................................................................. 3-39

Masking Interrupts ............................................................... 3-40

Latching Interrupts ............................................................... 3-41

Stacking Status During Interrupts .......................................... 3-43

Nesting Interrupts ................................................................. 3-44

Reusing Interrupts ................................................................ 3-46

Interrupting IDLE ................................................................ 3-48

Multiprocessing Interrupts .................................................... 3-48

Timer and Sequencing ................................................................ 3-49

Stacks and Sequencing ................................................................ 3-52

Conditional Sequencing .............................................................. 3-53

SIMD Mode and Sequencing ...................................................... 3-56

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Conditional Compute Operations .......................................... 3-58

Conditional Branches and Loops ........................................... 3-58

Conditional Data Moves ........................................................ 3-58

Case 1:

Complementary Register Pair Data Move ........................ 3-59

Case 2:

Uncomplemented to Complementary Register Move ....... 3-62

Case 3:

Complementary Register => Uncomplimentary

Case 4:

Data Move Involves External Memory or IOP

Memory Space ............................................................... 3-64

Conditional DAG Operations ................................................ 3-65

DATA ADDRESS GENERATORS

Overview ...................................................................................... 4-1

Setting DAG Modes ...................................................................... 4-3

Circular Buffering Mode .......................................................... 4-5

Broadcast Loading Mode ......................................................... 4-5

Alternate (Secondary) DAG Registers ....................................... 4-6

Bit-Reverse Addressing Mode ................................................... 4-8

Using DAG Status ........................................................................ 4-9

DAG Operations ......................................................................... 4-10

Addressing With DAGs ......................................................... 4-10

Addressing Circular Buffers ................................................... 4-12

Modifying DAG Registers ...................................................... 4-17

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CONTENTS

Addressing in SISD and SIMD Modes ................................... 4-18

DAGs, Registers, and Memory .................................................... 4-18

DAG Register-to-Bus Alignment ........................................... 4-19

DAG Register Transfer Restrictions ....................................... 4-21

DAG Instruction Summary ......................................................... 4-22

MEMORY

Overview ...................................................................................... 5-1

Internal Address and Data Buses .............................................. 5-4

Internal Data Bus Exchange .................................................... 5-7

ADSP-21160 DSP Memory Map ................................................ 5-12

Internal Memory ................................................................... 5-14

Multiprocessor Memory ........................................................ 5-16

External Memory .................................................................. 5-19

Shadow Write FIFO .............................................................. 5-21

Memory Organization and Word Size .................................... 5-22

Placing 32-Bit Words and 48-Bit Words ............................ 5-22

Mixing 32-Bit and 48-Bit Words ....................................... 5-23

Restrictions on Mixing 32-Bit and 48-Bit Words ............... 5-24

Setting Data Access Modes .......................................................... 5-27

Using Boot Memory .............................................................. 5-29

Reading from Boot Memory ............................................. 5-30

Writing to Boot Memory .................................................. 5-31

Internal Interrupt Vector Table .............................................. 5-31

Internal Memory Block Data Width ...................................... 5-32

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Memory Bank Size ................................................................ 5-33

External Bus Priority ............................................................. 5-33

Secondary Processor Element (PEy) ........................................ 5-34

Broadcast Register Loads ....................................................... 5-34

Illegal I/O Processor Register Access ....................................... 5-35

Unaligned 64-bit Memory Access ........................................... 5-36

External Bank X Access Mode ................................................ 5-36

External Bank X Waitstates .................................................... 5-37

External (Bank 0) DRAM Page Size ....................................... 5-38

Using Memory Access Status ....................................................... 5-38

Accessing Memory ...................................................................... 5-39

Access Word Size ................................................................... 5-40

Long Word (64-Bit) Accesses ............................................. 5-41

Instruction Word (48-Bit) and Extended Precision

Normal Word (40-Bit) Accesses ...................................... 5-43

Normal Word (32-Bit) Accesses ......................................... 5-43

Short Word (16-Bit) Accesses ............................................ 5-44

SISD, SIMD, and Broadcast Load Modes ............................... 5-44

Single-and Dual-Data Accesses ............................................... 5-45

Data Access Options .............................................................. 5-45

Short Word Addressing of Single Data in SISD Mode ........ 5-45

Short Word Addressing of Single Data in SIMD Mode ....... 5-47

Short Word Addressing of Dual-Data in SISD Mode .......... 5-51

Short Word Addressing of Dual-Data in SIMD Mode ........ 5-51

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32-Bit Normal Word Addressing of Single Data in

SISD Mode ................................................................... 5-55

32-Bit Normal Word Addressing of Single Data in

SIMD Mode .................................................................. 5-55

32-Bit Normal Word Addressing of Dual Data in

SISD Mode ................................................................... 5-57

32-Bit Normal Word Addressing of Dual Data in

SIMD Mode .................................................................. 5-60

Extended Precision Normal Word Addressing of

Single Data .................................................................... 5-62

Extended Precision Normal Word Addressing of

Dual Data in SISD Mode ............................................... 5-62

Extended Precision Normal Word Addressing of

Dual Data in SIMD Mode ............................................. 5-65

Long Word Addressing of Single Data ............................... 5-67

Long Word Addressing of Dual Data in SISD Mode .......... 5-67

Long Word Addressing of Dual Data in SIMD Mode ........ 5-70

Mixed Word Width Addressing of Dual Data in

SISD Mode ................................................................... 5-72

Mixed Word Width Addressing of Dual Data in

SIMD Mode .................................................................. 5-72

Broadcast Load Access ...................................................... 5-75

Arranging Data in Memory ......................................................... 5-75

I/O PROCESSOR

Overview ...................................................................................... 6-1

Setting I/O Processor—EPort Modes .......................................... 6-14

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Boot Memory DMA Mode .................................................... 6-16

External Port Buffer Modes .................................................... 6-17

External Port Channel Priority Modes .................................... 6-19

External Port Channel Transfer Modes ................................... 6-21

External Port Channel Handshake Modes .............................. 6-22

Master Mode .................................................................... 6-25

Paced Master Mode ........................................................... 6-31

Slave Mode ....................................................................... 6-31

Handshake Mode .............................................................. 6-34

External-Handshake Mode ................................................ 6-41

Setting I/O Processor—LPort Modes ........................................... 6-43

Link Port Buffer Modes ......................................................... 6-45

Link Port Channel Priority Modes ......................................... 6-46

Link Port Channel Transfer Modes ......................................... 6-50

Setting I/O Processor—SPort Modes ........................................... 6-51

Serial Port Buffer Modes ........................................................ 6-53

Serial Port Channel Priority Modes ........................................ 6-54

Serial Port Channel Transfer Modes ....................................... 6-54

Using I/O Processor Status .......................................................... 6-55

External Port Status ............................................................... 6-58

Link Port Status .................................................................... 6-62

Serial Port Status ................................................................... 6-65

DMA Controller Operation ........................................................ 6-67

Managing DMA Channel Priority .......................................... 6-68

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Chaining DMA Processes ...................................................... 6-71

Transfer Control Block (TCB) Chain Loading ................... 6-72

Setting Up and Starting The Chain ................................... 6-74

Inserting a TCB in an Active Chain .................................. 6-75

External Port DMA .................................................................... 6-76

Setting up External Port DMA .............................................. 6-76

Bootloading Through The External Port ................................ 6-77

Link Port DMA .......................................................................... 6-82

Setting up Link Port DMA .................................................... 6-82

Using Two-Dimensional Link Port DMA ............................... 6-84

Bootloading Through The Link Port ..................................... 6-89

Serial Port DMA ......................................................................... 6-92

Setting up Serial Port DMA ................................................... 6-92

Using Two-Dimensional Serial Port DMA ............................. 6-94

Optimizing DMA Throughput ................................................... 6-94

Internal Memory DMA ......................................................... 6-94

External Memory DMA ........................................................ 6-95

System-Level Considerations ................................................. 6-98

EXTERNAL PORT

Overview ...................................................................................... 7-1

Setting External Port Modes .......................................................... 7-1

External Memory Interface ........................................................... 7-3

Banked External Memory ...................................................... 7-10

Unbanked External Memory ................................................. 7-10

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Boot Memory ........................................................................ 7-11

Idle Cycle ......................................................................... 7-11

Data Hold Cycle ............................................................... 7-13

Multiprocessor Memory Space Waitstates and

Acknowledge .................................................................. 7-14

DRAM Page Boundary Detection .......................................... 7-15

Timing External Memory Accesses ......................................... 7-18

Asynchronous Mode Interface Timing ............................... 7-19

Asynchronous Mode Read – Bus Master ........................ 7-21

Asynchronous Mode Write – Bus Master ....................... 7-22

Synchronous Mode Interface Timing ................................. 7-23

Synchronous Mode Read – Bus Master .......................... 7-25

Synchronous Write, Zero-Waitstate Mode ...................... 7-28

Synchronous Write, One Waitstate Mode ....................... 7-32

Synchronous Burst Mode Interface Timing ........................ 7-34

Burst Length Determination .......................................... 7-36

Burst Stall Criteria ........................................................ 7-37

Synchronous Burst Reads .............................................. 7-38

Synchronous Burst Writes ............................................. 7-40

Using External SBSRAM ....................................................... 7-44

Executing Instructions From External Memory ...................... 7-49

Host Processor Interface .............................................................. 7-51

Acquiring the Bus .................................................................. 7-54

Asynchronous Transfers ......................................................... 7-58

Asynchronous Transfer Timing .............................................. 7-60

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Synchronous Transfers ........................................................... 7-64

Synchronous Broadcast Writes .......................................... 7-65

Synchronous Burst Read Transfers ..................................... 7-67

Slave Direct Reads and Writes ............................................... 7-68

IOP Shadow Registers ....................................................... 7-68

Instruction Transfers ......................................................... 7-69

Host Direct Writes and Reads ................................................ 7-70

Direct Writes .................................................................... 7-71

Direct Write Latency ........................................................ 7-71

Direct Reads ..................................................................... 7-72

Broadcast Writes ................................................................... 7-73

Shadow Write FIFO .............................................................. 7-73

Data Transfers Through the EPBx Buffers .............................. 7-74

DMA Transfers ..................................................................... 7-75

Host Data Packing ................................................................ 7-75

32-bit Data Packing .......................................................... 7-76

48-Bit Instruction Packing ................................................ 7-79

Host Interface Status ............................................................. 7-81

Interprocessor Messages and Vector Interrupts ....................... 7-81

Message Passing (MSGRx) ................................................ 7-82

Host Vector Interrupts (VIRPT) ....................................... 7-82

System Bus Interfacing .......................................................... 7-83

Access to the DSP Bus—Slave DSP ................................... 7-84

Access to the System Bus—Master DSP ............................. 7-84

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Processor Core Access To System Bus ................................. 7-86

Deadlock Resolution ......................................................... 7-88

DSP DMA Access To System Bus ...................................... 7-91

Multiprocessing with Local Memory .................................. 7-92

DSP To Microprocessor Interface ...................................... 7-95

Multiprocessor (DSPs) Interface .................................................. 7-96

Multiprocessing System Architectures .................................... 7-98

Data Flow Multiprocessing ................................................ 7-99

Cluster Multiprocessing .................................................... 7-99

Multiprocessor Bus Arbitration ............................................ 7-102

Bus Arbitration Protocol ................................................. 7-104

Bus Arbitration Priority (RPBA) ...................................... 7-109

Mastership Timeout Bus ................................................ 7-111

Priority Access ................................................................ 7-112

Bus Synchronization After Reset .......................................... 7-115

Booting Another DSP .......................................................... 7-118

Multiprocessor Direct Writes and Reads ............................... 7-118

IOP Shadow Registers ..................................................... 7-119

Instruction Transfers ....................................................... 7-120

Direct Writes .................................................................. 7-120

Direct Write Latency ....................................................... 7-120

Direct Reads ................................................................... 7-120

Broadcast Writes .................................................................. 7-121

Shadow Write FIFO ............................................................ 7-123

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CONTENTS

Data Transfers Through the EPBx Buffers ............................ 7-123

Bus Lock and Semaphores ................................................... 7-124

Interprocessor Messages and Vector Interrupts ..................... 7-126

Message Passing (MSGRx) .............................................. 7-127

Vector Interrupts (VIRPT) .............................................. 7-127

Multiprocessor Interface Status ....................................... 7-128

LINK PORTS

Overview ...................................................................................... 8-1

Link Port To Link Buffer Assignment ...................................... 8-3

Link Port DMA Channels ....................................................... 8-3

Link Port Booting ................................................................... 8-3

Setting Link Port Modes ............................................................... 8-4

Link Data Path (and Compatibility) Modes ............................. 8-6

Using Link Port Handshake Signals ............................................... 8-7

Using Link Buffers ........................................................................ 8-9

Core Processor Access To Link Buffers ................................... 8-10

Host Processor Access To Link Buffers ................................... 8-10

Using Link Port DMA ................................................................ 8-11

Using Link Port Interrupts .......................................................... 8-11

Link Port Interrupts With DMA Enabled .............................. 8-12

Link Port Interrupts With DMA Disabled ............................. 8-12

Link Port Service Request Interrupts (LSRQ) ......................... 8-13

Detecting Errors On Link Transmissions ..................................... 8-15

Using Token Passing With Link Ports .......................................... 8-16

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Designing Link Port Systems ....................................................... 8-20

Terminations For Link Transmission Lines ............................. 8-20

Peripheral I/O Using Link Ports ............................................. 8-21

Data Flow Multiprocessing With Link Ports ........................... 8-21

SERIAL PORTS

Overview ...................................................................................... 9-1

SPORT Interrupts ................................................................... 9-5

SPORT Reset .......................................................................... 9-5

Setting Serial Port Modes .............................................................. 9-6

Transmit and Receive Control Registers

(STCTL, SRCTL) ................................................................ 9-8

Transmit and Receive Data Buffers (TX, RX) ......................... 9-12

Clock and Frame Sync Frequencies (TDIV, RDIV) ................ 9-14

Data Word Formats ............................................................... 9-17

Word Length .................................................................... 9-17

Endian Format .................................................................. 9-18

Data Packing and Unpacking ............................................ 9-18

Data Type ......................................................................... 9-19

Companding ..................................................................... 9-20

Clock Signal Options ............................................................ 9-21

Frame Sync Options .............................................................. 9-22

Framed Versus Unframed .................................................. 9-22

Internal Versus External Frame Syncs ................................. 9-24

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Active Low Versus Active High Frame Syncs ...................... 9-24

Sampling Edge For Data and Frame Syncs ......................... 9-25

Early Versus Late Frame Syncs .......................................... 9-25

Data-Independent Transmit Frame Sync ........................... 9-27

SPORT Loopback ................................................................. 9-27

Multichannel Operation ........................................................ 9-28

Frame Syncs in Multichannel Mode .................................. 9-30

Multichannel Control Bits in STCTL, SRCTL .................. 9-31

Channel Selection Registers .............................................. 9-32

SPORT Receive Comparison Registers .............................. 9-33

Moving Data Between SPORTS and Memory ............................. 9-36

DMA Block Transfers ............................................................ 9-37

Single-Word Transfers ........................................................... 9-38

SPORT Pin/Line Terminations ................................................... 9-39

JTAG TEST EMULATION PORT

JTAG Test Access Port ................................................................ 10-3

Instruction Register .................................................................... 10-4

EMUPMD Shift Register ...................................................... 10-5

EMUPX Shift Register .......................................................... 10-6

EMU64PX Shift Register ...................................................... 10-7

EMUPC Shift Register .......................................................... 10-7

EMUCTL Shift Register ....................................................... 10-8

EMUSTAT Shift Register .................................................... 10-12

BRKSTAT Shift Register ..................................................... 10-12

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MEMTST Shift Register ...................................................... 10-13

PSx, DMx, IOx, and EPx (Breakpoint) Registers .................. 10-14

EMUN Register .................................................................. 10-16

EMUCLK and EMUCLK2 Registers ................................... 10-17

EMUIDLE Instruction ........................................................ 10-17

In-Circuit Signal Analyzer (ICSA) Function ......................... 10-17

Boundary Register ..................................................................... 10-17

Device Identification Register .................................................... 10-37

Built-in Self-test Operation (BIST) ............................................ 10-37

Private Instructions ................................................................... 10-37

References ................................................................................. 10-38

SYSTEM DESIGN

DSP Pin Descriptions ................................................................. 11-1

Pin States At Reset ............................................................... 11-12

Clock Derivation ................................................................. 11-15

RESET and CLKIN ............................................................ 11-16

Input Synchronization Delay ........................................... 11-17

Interrupt and Timer Pins ..................................................... 11-18

Flag Pins ............................................................................. 11-18

Flag Inputs ..................................................................... 11-19

Flag Outputs ................................................................... 11-19

JTAG Interface Pins ............................................................ 11-20

Dual-Voltage Power-up Sequencing ........................................... 11-21

Designing for JTAG Emulation ................................................. 11-24

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Target Board Connector ...................................................... 11-25

Layout Requirements ................................................................ 11-30

Power Sequence for Emulation .................................................. 11-31

Additional JTAG Emulator References ...................................... 11-31

Pod Specifications ..................................................................... 11-32

DSP JTAG Pod Connector .................................................. 11-32

DSP 3.3V Pod Logic ........................................................... 11-32

DSP 2.5V Pod Logic ........................................................... 11-34

Conditioning Input Signals ....................................................... 11-35

Link Port Input Filter Circuits ............................................. 11-35

RESET Input Hysteresis ...................................................... 11-36

Designing For High Frequency Operation ................................. 11-36

Clock Specifications and Jitter ............................................. 11-38

Clock Distribution .............................................................. 11-38

Point-To-Point Connections ................................................ 11-40

Signal Integrity ................................................................... 11-41

Other Recommendations and Suggestions ............................ 11-44

Decoupling Capacitors and Ground Planes .......................... 11-45

Oscilloscope Probes ............................................................. 11-46

Recommended Reading ....................................................... 11-47

Booting Single and Multiple Processors ..................................... 11-48

Multiprocessor Host Booting ............................................... 11-48

Multiprocessor EPROM Booting ......................................... 11-49

All DSPs Boot in Turn from a Single EPROM ................. 11-49

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One DSP is Booted, which then Boots the Others ........... 11-49

Multiprocessor Link Port Booting ........................................ 11-51

Multiprocessor Booting From External Memory ................... 11-52

REGISTERS

Control and Status System Registers ............................................. A-2

Mode Control 1 Register (MODE1) ....................................... A-2

Mode Mask Register (MMASK) .............................................. A-5

Mode Control 2 Register (MODE2) ....................................... A-6

Arithmetic Status Registers (ASTATx and ASTATy) ................. A-9

Sticky Status Registers (STKYx and STKYy) .......................... A-13

User-Defined Status Registers (USTATx) .............................. A-16

Processing Element Registers ...................................................... A-16

Data File Data Registers (Rx, Fx, Sx) ..................................... A-16

Multiplier Results Registers (MRxF, MRxB) .......................... A-17

Program Memory Bus Exchange Register (PX) ...................... A-17

Program Sequencer Registers ...................................................... A-18

Interrupt Latch Register (IRPTL) ......................................... A-19

Interrupt Mask Register (IMASK) ......................................... A-24

Interrupt Mask Pointer Register (IMASKP) ........................... A-24

Link Port Interrupt Register (LIRPTL) ................................. A-25

Flag Value Register (FLAGS) ................................................ A-28

Program Counter Register (PC) ............................................ A-29

Program Counter Stack Register (PCSTK) ............................ A-30

Program Counter Stack Pointer Register (PCSTKP) .............. A-30

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Fetch Address Register (FADDR) .......................................... A-31

Decode Address Register (DADDR) ...................................... A-31

Loop Address Stack Register (LADDR) .................................. A-31

Current Loop Counter Register (CURLCNTR) ..................... A-32

Loop Counter Register (LCNTR) .......................................... A-32

Timer Period Register (TPERIOD) ....................................... A-32

Timer Count Register (TCOUNT) ....................................... A-32

Data Address Generator Registers ................................................ A-33

Index Registers (Ix) ............................................................... A-33

Modify Registers (Mx) .......................................................... A-33

Length and Base Register (Lx, Bx) ......................................... A-34

I/O Processor Registers ............................................................... A-34

System Configuration Register (SYSCON) ............................ A-36

Vector Interrupt Address Register (VIRPT) ............................ A-48

External Memory Waitstate and Access Mode Register (WAIT) A-49

System Status Register (SYSTAT) .......................................... A-49

External Port DMA Buffer Registers (EPBx) .......................... A-49

Message Registers (MSGRx) .................................................. A-53

PC Shadow Register (PC_SHDW) ........................................ A-53

MODE2 Shadow Register (MODE2_SHDW) ....................... A-53

Bus Timeout Maximum Register (BMAX) ............................. A-54

Bus (Timeout) Counter Register (BCNT) .............................. A-54

Address of Last DRAM Page Register (ELAST) ...................... A-55

External Port DMA Control Registers (DMACx) ................... A-55

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Internal Memory DMA Index Registers (IIx) ......................... A-59

Internal Memory DMA Modifier Registers (IMx) .................. A-60

Internal Memory DMA Count Registers (Cx) ....................... A-60

Chain Pointer For Next DMA TCB Registers (CPx) .............. A-60

General Purpose DMA Registers (GPx, DBx, DAx) ............... A-61

DMA Channel Status Register (DMASTAT) ......................... A-61

External Memory DMA Index Registers (EIx) ....................... A-62

External Memory DMA Modifier Registers (EMx) ................ A-62

External Memory DMA Count Registers (ECx) ..................... A-63

Link Port Buffer Registers (LBUFx) ...................................... A-63

Link Port Buffer Control Registers (LCTLx) ......................... A-63

Link Port Common Control Register (LCOM) ..................... A-66

Link Port Assignment Register (LAR) ................................... A-68

Link Port Service Request and Mask Register (LSRQ) ............ A-69

Link Port Path Registers (LPATHx) ....................................... A-72

Link Port Path Counter Register (LPCNT) ........................... A-72

Link Port Constant Registers (CNSTx) ................................. A-72

SPORT Serial Transmit Control Registers (STCTLx) ............ A-72

SPORT Serial Receive Control Registers (SRCTLx) ............... A-75

SPORT Transmit Buffer Registers (TXx) ............................... A-77

SPORT Receive Buffer Registers (RXx) ................................. A-78

SPORT Transmit Divisor Registers (TDIVx) ......................... A-78

SPORT Transmit Count Registers (TCNTx) ......................... A-78

SPORT Receive Divisor Registers (RDIVx) ........................... A-79

ADSP-21160 SHARC DSP Hardware Reference xxi

CONTENTS

SPORT Receive Count Registers (RCNTx) ............................ A-79

SPORT Transmit Select Registers (MTCSx) ........................... A-79

SPORT Receive Select Registers (MRCSx) ............................. A-80

SPORT Transmit Compand Registers (MTCCSx) .................. A-80

SPORT Receive Compand Register (MRCCSx) ..................... A-80

SPORT Receive Comparison and Mask Registers (KEYWDx and

KEYMASKx) ..................................................................... A-81

SPORT Serial Path Length Registers (SPATHx) ..................... A-81

SPORT Serial Path Counter Registers (SPCNTx) .................. A-82

INTERRUPT VECTOR ADDRESSES

NUMERIC FORMATS

IEEE Single-Precision Floating-Point Data Format ........................ C-1

Extended-Precision Floating-Point Format .................................... C-3

Short Word Floating-Point Format ................................................ C-4

Packing for Floating-Point Data .................................................... C-4

Fixed-Point Formats ..................................................................... C-6

GLOSSARY

INDEX

xxii ADSP-21160 SHARC DSP Hardware Reference

1 INTRODUCTION

Thank you for purchasing Analog Devices SHARC® digital signal proces-

sor (DSP).

Purpose

The ADSP-21160 SHARC DSP Hardware Reference provides architec-

tural information on the ADSP-21160 Super Harvard Architecture

(SHARC) Digital Signal Processor (DSP). The architectural descriptions

cover functional blocks, busses, and ports, including all features and pro-

cesses they support. For programming information, see the ADSP-21160

SHARC DSP Instruction Set Reference.

Audience

DSP system designers and programmers who are familiar with signal pro-

cessing concepts are the primary audience for this manual. This manual

assumes that the audience has a working knowledge of microcomputer

technology and DSP-related mathematics.

DSP system designers and programmers who are unfamiliar with signal

processing can use this manual, but should supplement this manual with

other texts, describing DSP techniques.

ADSP-21160 SHARC DSP Hardware Reference 1-1

Overview – Why Floating-Point DSP?

All readers, particularly system designers, should refer to the DSP’s data sheet for timing, electrical, and package specifications. For additional suggested reading, see “For Information About Analog Products” on

page 1-23.

Overview – Why Floating-Point DSP?

A digital signal processor’s data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and probability of overflow, using a floating-point DSP can ease algorithm and software development. The extent to which this is true depends on the floating-point processor’s architecture. Consistency with IEEE workstation simulations and the elimination of scaling are two clear ease-of-use advantages. High-level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and error handling. The ADSP-21160 is a highly integrated, 32-bit floating-point DSP that provides many of these design advantages.

ADSP-21160 DSP Design Advantages

The ADSP-21160 processor is a high-performance 32-bit DSP for medical imaging, communications, military, audio, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. This DSP builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM, integrated I/O peripherals, and an additional processing element for Single-Instruction-Multiple-Data (SIMD) support.

1-2 ADSP-21160 SHARC DSP Hardware Reference

Introduction

SHARC is an acronym for Super Harvard Architecture. This DSP archi-

tecture balances a high performance processor core with high performance

buses (PM, DM, IO). In the core, every instruction can execute in a single

cycle. The buses and instruction cache provide rapid, unimpeded data

flow to the core to maintain the execution rate.

Figure 1-1 shows a detailed block diagram of the processor, illustrating the

following architectural features:

• Two Processing Elements (PEx and PEy), each containing a 32-Bit IEEE floating-point computation units—multiplier, ALU, Shifter, and data register file

• Program sequencer with related instruction cache, interval timer, and Data Address Generators (DAG1 and DAG2)

• Dual-ported SRAM

• External port for interfacing to off-chip memory, peripherals, hosts, and multiprocessor systems

• Input/Output (IO) processor with integrated DMA controller, serial ports, and link ports for point-to-point multiprocessor communications

• JTAG Test Access Port for emulation

Figure 1-1 also shows the three on-chip buses of the ADSP-21160: the

Program Memory (PM) bus, Data Memory (DM) bus, and Input/Output (IO) bus. The PM bus provides access to either instructions or data. During a single cycle, these buses let the processor access two data operands (one from PM and one from DM), access an instruction (from the cache), and perform a DMA transfer.

ADSP-21160 SHARC DSP Hardware Reference 1-3

ADSP-21160 DSP Design Advantages

The buses connect to the ADSP-21160 DSP’s external port, which provides the processor’s interface to external memory, memory-mapped I/O, a host processor, and additional multiprocessing ADSP-21160 DSPs. The external port performs bus arbitration and supplies control signals to shared, global memory and I/O devices.

CORE PROCESSOR

DAG2

DAG1

8x4x32

BUS

CONNECT

(PX)

DATA

FILE

(PEx)

16 x 40-BIT

MULT

TIMER

PROGRAM

SEQUENCER

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BARREL SHIFTER

ALU

INSTRUCTION

CACHE

32 x 48-BIT

48/64

32/40/64

BARREL SHIFTER

ALU

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/ O PORT

ADDR DATA ADDR

ADDR DATA

DATA

FILE

(PEy)

16 x 40-BIT

MULT

DATA

IOD 64

REGISTERS

MEMORY MAPPED)

(

CONTROL, STATUS, &

DATA BUFFERS

IOP

ADDR

IOA 32

0 K

C O L B

1 K

C O L B

JTAG

TEST &

EMULATION

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

HOST PORT

DMA

CONTROLLER

SERIAL PORTS

(2)

LINK PORTS

(6)

I/O PROCESSOR

Figure 1-1. ADSP-21160 SHARC DSP Block Diagram

Figure 1-2 illustrates a typical single-processor system. The ADSP-21160

DSP includes extensive support for multiprocessor systems as well. For more information, see “Multiprocessor (DSPs) Interface” on page 7-96.

Further, the ADSP-21160 DSP addresses the five central requirements for DSPs:

• Fast, flexible arithmetic computation units

• Unconstrained data flow to and from the computation units

1-4 ADSP-21160 SHARC DSP Hardware Reference

Introduction

ADSP-2116X

CLOCK

LINK

DEVICES

(6 MAX)

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

3 4

CLKIN CLK_CFG3-0 EBOOT LBOOT IRQ2-0 FLAG3-0 TIMEXP

LXCLK LXACK LXDAT7-0

TCLK0 RCLK0 TFS0 RSF0 DT0 DR0

TCLK1 RCLK1 TFS1 RSF1 DT1 DR1

RPBA ID2-0

RESET

BMS

CIF

BRST

ADDR31-0

DATA63-0

RDX

WRX ACK

MS3-0 PAGE

SBTS

CLKOUT DMAR1-2 DMAG1-2

CS HBR HBG

REDY

BR1-6

JTAG

L O R

T N O C

Figure 1-2. ADSP-21160 Processor System

ADDR DATA

OE WE

ACK

S S

D A

DATA

ADDR DATA

BOOT

EPROM

(OPTIONAL)

MEMORY

AND

PERIPHERALS

(OPTIONAL)

DMA DEVICE

(OPTIONAL)

HOST

PROCESSOR

INTERFACE (OPTIONAL)

• Extended precision and dynamic range in the computation units

• Dual address generators with circular buffering support

• Efficient program sequencing

Fast, Flexible Arithmetic. The ADSP-21000 Family processors execute all instructions in a single cycle. They provide both fast cycle times and a complete set of arithmetic operations. The DSP is IEEE floating-point compatible and allows either interrupt on arithmetic exception or latched status exception handling.

ADSP-21160 SHARC DSP Hardware Reference 1-5

ADSP-21160 DSP Architecture Overview

Unconstrained Data Flow. The ADSP-21160 DSP has a Super Harvard Architecture combined with a 10-port data register file. In every cycle, the DSP can write or read two operands to or from the register file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and multiplier. The processor’s 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction.

40-Bit Extended Precision. The DSP handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-complement and unsigned), and extended-precision 40-bit floating-point format. The processors carry extended precision throughout their computation units, limiting intermediate data truncation errors.

Dual Address Generators. The DSP has two data address generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus, bit-reverse, and broadcast operations are supported with no constraints on data buffer placement.

Efficient Program Sequencing. In addition to zero-overhead loops, the DSP supports single-cycle setup and exit for loops. Loops are both nestable (six levels in hardware) and interruptable. The processors support both delayed and non-delayed branches.

ADSP-21160 DSP Architecture Overview

The ADSP-21160 DSP forms a complete system-on-a-chip, integrating a large, high-speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the ADSP-21160 SHARC architecture, which appears in

Figure 1-1 on page 1-4. With each summary, a cross reference points to

the sections where the features are described in greater detail.

1-6 ADSP-21160 SHARC DSP Hardware Reference

+ 802 hidden pages

ANALOG DEVICES ADSP-21160 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

INTRODUCTION

PROCESSING ELEMENTS

PROGRAM SEQUENCER

DATA ADDRESS GENERATORS

MEMORY

I/O PROCESSOR

EXTERNAL PORT

LINK PORTS

SERIAL PORTS

JTAG TEST EMULATION PORT

SYSTEM DESIGN

REGISTERS

INTERRUPT VECTOR ADDRESSES

NUMERIC FORMATS

GLOSSARY

INDEX

1 INTRODUCTION

Purpose

Audience

Overview – Why Floating-Point DSP?

ADSP-21160 DSP Design Advantages

ADSP-21160 DSP Architecture Overview